OKI MSM65522-XXXGS-2K 8-bit microcontroller with a/d converter Datasheet

E2E1015-27-Y4
¡ Semiconductor
MSM65522/65P522
¡ Semiconductor
ThisMSM65522/65P522
version: Jan. 1998
Previous version: Nov. 1996
8-Bit Microcontroller with A/D Converter
GENERAL DESCRIPTION
The MSM65522 is a high-performance 8-bit microcontroller that employs OKI original nX-8/50
CPU core. With a minimum instruction execution time of 400 ns (10MHz clock), the MSM65522
is capable of high-speed processing, and includes 8K bytes of program memory, 384 bytes of
data memory (RAM), timers, serial ports and an A/D converter on chip. Also available is the
MSM65P522, which replaces the on-chip program memory with one-time PROM.
FEATURES
• Operating range
Operating frequency
Operating voltage
Operating temperature
• Memory space
Internal program memory
Internal data memory
• Minimum instruction execution time
• Powerful instruction set
• Abundant addressing modes
• I/O ports
Input only port
• Timers
• Counters
• Serial ports
• A/D converter
• External interrupts
• Interrupt sources
• Package Options
42-pin plastic shrink DIP (SDIP42-P-600-1.78)
: 1 to 10MHz (VDD=4.5 to 5.5V)
1 to 5MHz (VDD=2.7 to 5.5V)
: 2.7 to 5.5V
: – 40 to +85°C
:
:
:
:
8K bytes
384 bytes
400ns @ 10 MHz
81 basic instructions
8/16-bit operation instructions
Bit manipulation instructions
Compound function instructions
: 8-bit ¥ 3
4-bit ¥ 1
: 8-bit ¥ 1
: 8-bit auto-reload timer ¥ 3
(One timer is shared by the baud rate
generator. Combining the 8-bit timers,
it is possible to use the timers as a 16-bit
timer (1 channel).)
Watchdog timer ¥ 1
: Time base counter (14-bit) ¥ 1
: Shift register ¥ 1
Serial port with baud rate generator
(UART/Synchronous) ¥ 1
: 8 bits ¥ 8 channels
: 3
: 11
: (Product name:MSM65522-¥¥¥SS,
MSM65P522-¥¥¥SS)
42-pin plastic DIP (DIP42-P-600-2.54)
: (Product name:MSM65522-¥¥¥RS,
MSM65P522-¥¥¥RS)
44-pin plastic QFP (QFP44-P-910-0.80-2K)
: (Product name:MSM65522-¥¥¥GS-2K,
MSM65P522-¥¥¥GS-2K)
44-pin plastic QFJ (QFJ44-P-S650-1.27)
: (Product name:MSM65522-¥¥¥JS,
MSM65P522-¥¥¥JS)
¥¥¥ indicates the code number.
* Specifications are subject to change without notice.
1/22
CPU CORE
OSC.
CONT.
8
INST.
DEC.
VDD
GND
T
PC
BUS
CONT.
IR
TEST
RAM
(384bytes)
GMAR
ALU
C
8
¡ Semiconductor
OSC0
OSC1
RESET
HSTOP*
BLOCK DIAGRAM
ROM
(8K bytes)
TBC
WDT
8
SIO
AR
BR
PSW
SP
TXD*
RXD*
LMAR
8bit TIMER¥3**
T1OUT*
T0CK*
GATE*
I
8bit SHIFT-REG.
O PORT
INTERRUPT CONT.
AI0*
to
AI7*
PO
P1
P2
P3
P6
SFTO*
SFTI*
SFTCK*
INT0*
INT1*
INT2*
* Indicates the secondary function of the port.
** One of the asterisked items is used in the SIO baud rate generator.
2/22
MSM65522/65P522
8bit ADC
¥8ch
¡ Semiconductor
MSM65522/65P522
PIN CONFIGURATION (TOP VIEW)
P3.0
1
42
VDD
P3.1
2
41
P6.0 / AI0
P3.2
3
40
P6.1 / AI1
P3.3
4
39
P6.2 / AI2
P3.4 / INT2
5
38
P6.3 / AI3
P3.5 / SFT0
6
37
P6.4 / AI4
P3.6 / SFTI
7
36
P6.5 / AI5
P3.7 / SFTCK
8
35
P6.6 / AI6
RESET
9
34
P6.7 / AI7
P2.0 / RXD
10
33
TEST
P2.1 / TXD
11
32
P0.0
P2.2 / INT0
12
31
P0.1
P2.3 / INT1/ GATE
13
30
P0.2
P2.4 / TOCK
14
29
P0.3
P2.5 / HSTOP
15
28
P0.4
P2.6
16
27
P0.5
P2.7 / T1OUT
17
26
P0.6
P1.3
18
25
P0.7
OSC1
19
24
P1.0
OSC0
20
23
P1.1
GND
21
22
P1.2
42-Pin Plastic Shrink DIP
P3.0
1
42
VDD
P3.1
2
41
P6.0 / AI0
P3.2
3
40
P6.1 / AI1
P3.3
4
39
P6.2 / AI2
P3.4 / INT2
5
38
P6.3 / AI3
P3.5 / SFT0
6
37
P6.4 / AI4
P3.6 / SFTI
7
36
P6.5 / AI5
P3.7 / SFTCK
8
35
P6.6 / AI6
RESET
9
34
P6.7 / AI7
P2.0 / RXD
10
33
TEST
P2.1 / TXD
11
32
P0.0
P2.2 / INT0
12
31
P0.1
P2.3 / INT1/ GATE
13
30
P0.2
P2.4 / TOCK
14
29
P0.3
P2.5 / HSTOP
15
28
P0.4
P2.6
16
27
P0.5
P2.7 / T1OUT
17
26
P0.6
P1.3
18
25
P0.7
OSC1
19
24
P1.0
OSC0
20
23
P1.1
GND
21
22
P1.2
42-Pin Plastic DIP
3/22
¡ Semiconductor
MSM65522/65P522
34 P6.3 / AI3
35 P6.2 / AI2
36 P6.1 / AI1
VDD
37 P6.0 / AI0
38
40 P3.0
39 GND
41 P3.1
42 P3.2
44 P3.4 / INT2
43 P3.3
PIN CONFIGURATION (TOP VIEW) (Continued)
1
33
P6.4 / AI4
P3.6 / SFTI
2
32
P6.5 / AI5
P3.7 / SFTCK
3
31
P6.6 / AI6
RESET
4
30
P6.7 / AI7
P2.0 / RXD
5
29
TEST
P2.1 / TXD
6
28
P0.0
P3.5 / SFT0
P2.2 / INT0
7
27
P0.1
P2.3 / INT1/ GATE
8
26
P0.2
P0.7 21
P0.6 22
19
P1.1
P1.0 20
18
P1.2
P1.3
17
P0.5
16
23
NC
11
GND
P2.6
15
P0.4
OSC1 14
P0.3
OSC0
25
24
13
9
10
P2.7 / T1OUT 12
P2.4 / TOCK
P2.5 / HSTOP
NC: No-connection pin
44-Pin Plastic QFP
4/22
¡ Semiconductor
MSM65522/65P522
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
TEST
P6.7 / AI7
P6.6 / AI6
P6.5 / AI5
P6.4 / AI4
PIN CONFIGURATION (TOP VIEW) (Continued)
39 38 37 36 35 34 33 32 31 30 29
P0.6
P6.1 / AI1
42
26
P0.7
P6.0 / AI0
43
25
P1.0
VDD
44
24
P1.1
P3.0
1
23
P1.2
P3.1
2
22
GND
P3.2
3
21
OSC0
P3.3
4
20
OSC1
P3.4 / INT2
5
19
P1.3
NC
6
18
P2.7 / T1OUT
P2.6
P2.5 / HSTOP
P2.4 / TOCK
P2.3 / INT1/ GATE
10 11 12 13 14 15 16 17
P2.1 / TXD
9
P2.2 / INT0
8
P2.0 / RXD
7
RESET
NC
27
P3.7 / SFTCK
28
41
P3.6 / SFTI
40
P3.5 / SFT0
P6.3 / AI3
P6.2 / AI2
NC: No-connection pin
44-Pin Plastic QFJ
5/22
¡ Semiconductor
MSM65522/65P522
PIN DESCRIPTION
Basic Functions
Function
Power
Supply
Symbol
Type
VDD
—
+5V digital power supply (common to analog power supply)
Description
GND
—
0V digital ground (common to analog ground)
OSC0
I
Oscillator input pin: connects to a crystal oscillator (or ceramic resonator)
or external clock. The master clock and external clock are used as the
system clock without frequency division.
Oscillation
OSC1
O
RESET
I
Oscillator input pin: connects to a crystal oscillator (or ceramic resonator).
When an external clock is input to OSC0, leave OSC1 open.
System reset input: when this pin goes low, the internal state of the chip
is initialized and program execution restarts from address 0040H. The
Control
input is pulled up to VDD with an internal pull-up resistor.
TEST
I
P0.0
I/O
Test input pin: connects to ground pin.
8-bit input/output port (Port 0)
I/O
8-bit input/output port (Port 1)
to
P0.7
P1.0
to
P1.3
P2.0
Port
I/O
8-bit input/output port (Port 2): input or output can be selected for each
bit by the port 2 direction register (P2DIR). In addition to their input/
to
output port functions, the pins of port 2 have secondary functions: see
P2.7
the next table.
P3.0
I/O
8-bit input/output port (Port 3): input or output can be selected for each
bit by the port 3 direction register (P3DIR). In addition to their input/
to
output port functions, the pins of port 3 have secondary functions: see
P3.7
the next table.
P6.0/AI0
to
I
8-bit input port (Port 6):
Functions as analog input channel during A/D conversion.
P6.7/AI7
6/22
¡ Semiconductor
MSM65522/65P522
Secondary Functions
Function
Symbol
Type
RXD
I/O
UART: Input pin for a synchronous communication receive data.
Serial
Port
Description
P2.0 secondary functions.
Synchronous: Input/output pin for serial port transmit/receive data.
TXD
O
P2.1 secondary functions.
UART: Input pin for a synchronous communication receive data.
Synchronous: Output pin for serial port synchronizing clock.
INT0
I
Secondary function of P2.2 input pin for external interrupt 0.
The interrupt can be triggered by the rising edge, falling edge, or both
edges of rising or falling.
External
INT1/Gate
I
Secondary function of P2.3 input pin for external interrupt 1.
The interrupt can be triggered by the rising edge, falling edge, or both
interrupt
rising and falling edges. Also used as a gate signal input pin for gating
the counter of timer 0.
INT2
I
Secondary function of P3.4 input pin for external interrupt 2.
The interrupt can be triggered by the rising edge, falling edge, or both
rising and falling edges.
HSTOP
I
Secondary function of P2.0 input pin for hardware stop mode. If this pin goes
low while the HSTP bit in SBYCON is set to 1, the chip enters hard stop
Control
mode. In hardware stop mode the clock stops and the CPU and on-chip
peripheral functions shut down to conserve power.
SFTO
O
P3.5 secondary functions.
SFTI
I
P3.6 secondary functions.
SFTCK
I/O
P3.7 secondary functions.
Shift register data output pin.
Shift
Registers
Shift register data output pin.
Shift register synchronizing clock input/output pin.
In master mode: clock output
In slave mode: clock input
Timer 0
Timer 1
A/D
Converter
T0CK
I
Secondary function of P2.4: external clock input pin for timer 0.
T1OUT
O
Secondary function of P2.7: outputs a waveform with twice the cycle of
AI0
O
the overflow interval of timer 1.
to
Secondary function of P6.0 to P6.7: functions as analog input channel in
A/D conversion.
AI7
7/22
¡ Semiconductor
MSM65522/65P522
MEMORY MAPS
Local Memory Space
1FFH
Page 1
Data Memory
General Memory Space
1FFFH
100H
Program Memory
100H
SFR
80H
Vector Call Table Area
Data Memory
40H
30H
20H
10H
0
Local Register Set 3
Local Register Set 2
Local Register Set 1
Local Register Set 0
Page 0
Internal Memory
80H
40H
20H
0
Program Memory
Interrupt Vector Table Area
Vector Call Table Area
8/22
¡ Semiconductor
MSM65522/65P522
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Condition
Rating
VDD
–0.3 to +7.0
Input Voltage
VI
–0.3 to VDD+0.3
Output Voltage
VO
Analog Input Voltage
VAI
Power Dissipation
PD
Supply Voltage
Storage Temperature
Ta=25°C
–0.3 to VDD+0.3
Unit
V
–0.3 to VDD+0.3
Ta=25°C per package
400
Ta=25°C per one output
50
—
–55 to +150
TSTG
mW
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Supply Voltage
VDD
Analog Input Voltage
VAI
Memory Hold Voltage
VDDMH
Operating Frequency *1
fOSC
External Clock Operating
Frequency
fEXTCLK
Operating Temperature
TOP
Condition
Range
fOSC £ 10 MHz
4.5 to 5.5
fOSC £ 5 MHz
—
2.7 to 5.5
0 to VDD
fOSC=0 Hz
2.0 to 5.5
VDD=4.5 to 5.5
1 to 10
VDD=2.7 to 4.5
1 to 5
VDD=4.5 to 5.5
0 to 10
VDD=2.7 to 4.5
—
0 to 5
–40 to +85
Unit
V
MHz
MHz
°C
*1 This is due to the standard of a crystal oscillator or resonator.
Ta=–40 to +85°C
fOSC, fEXTCLK (MHz)
10
8
6
5
4
2
1
2
3
2.7
4
5
5.5
6
* Operating Frequency is more than 1MHz.
VDD (V)
Figure 1. Supply Voltage vs. Operating frequency
9/22
¡ Semiconductor
MSM65522/65P522
ELECTRICAL CHARACTERISTICS
DC Characteristics 1 (VDD=4.5 to 5.5V, 5V Version)
(GND=0V, Ta=–40 to +85°C)
Parameter
Schmitt Trigger Circuit
Input Voltage
Symbol
Condition
VT–
*1
VT+
—
VT
Min.
Typ.
Max.
0.3VDD
—
—
—
—
0.7VDD
—
1.0
—
"H" Input Voltage 1
*2
VIH1
—
0.3VDD+0.7
—
VDD+0.3
"H" Input Voltage 2
*3
VIH2
—
0.7VDD
—
VDD+0.3
"L" Input Voltage
*4
"H" Output Voltage 2
"L" Output Voltage 1
VIL
—
–0.3
—
0.3VDD-0.3
VOH
IOH=–400mA
VDD–0.4V
—
—
Unit
V
VOL
IOL=1.6mA
—
—
0.4
Input Leakage Current 1
*5
ILI1
VI=VDD/0V
—
—
±1
Input Leakage Current 2
*6
ILI2
VI=VDD/0V
—
—
±10
Pull-up Resistor
*7
RRST
VI=0V
30
50
80
CI
f=1MHz, Ta=25°C
—
5
—
pF
IDDS
5V, Stop mode
—
2
50
mA
IDD
fOSC=10MHz, 5V, no load
—
25
35
mA
Input Capacitance
Current Consumption
Current Consumption
*1
*2
*3
*4
*5
*6
*7
*8
*8
mA
KW
P0 to P3 (Includes secondary function inputs)
P6
OSC0 and RESET
P6, OSC0, RESET
P6
Excludes P6. RESET sets to VDD and TEST sets to 0V
RESET
The ports set for input mode are V DD or 0V, the ports except these are no load and A/D
converter is not active.
10/22
¡ Semiconductor
MSM65522/65P522
DC Characteristics 2 (2.7 to 4.5V, 3V Version)
(GND=0V, Ta=–40 to +85°C)
Parameter
Symbol
Condition
VT–
Schmitt Trigger Circuit
*1
Input Voltage
VT+
—
VT
Min.
Typ.
Max.
0.3VDD
—
—
—
—
0.7VDD
—
0.5
—
"H" Input Voltage
*2
VIH1
—
0.3VDD+0.7
—
VDD+0.3
"H" Input Voltage
*3
VIH2
—
0.7VDD+0.3
—
VDD+0.3
"L" Input Voltage
*4
VIL
—
–0.3
—
0.3VDD–0.3
VOH
IOH=–20mA
VDD–0.1
—
—
"H" Output Voltage
"L" Output Voltage
Unit
V
VOL
IOL=20mA
—
—
0.1
Input Leakage Current 1
*5
ILI1
VI=VDD/0V
—
—
±1
Input Leakage Current 1
*6
ILI1
VI=VDD/0V
—
—
±1
Pull-up Resistor
*7
RRST
VI=0V
30
50
80
KW
CI
f=1MHz, Ta=25°C
—
5
—
pF
IDDS
3V, stop mode
1
—
25
mA
IDD
5MHz, 3V, no load
10
6
15
mA
Input Capacitance
*8
Current Consumption
Current Consumption
*1
*2
*3
*4
*5
*6
*7
*8
mA
P0 to P3 (Includes secondary function inputs)
P6
OSC0 and RESET
P6, OSC0, RESET
P6
Excludes P6. RESET sets to VDD and TEST sets to 0V.
RESET
The ports except these are no load, and A/D converter active.
AC Characteristics
CPU control (OSC0 Clock)
(VDD=2.7 to 5.5 V, GND=0V, Ta=–40 to +85°C)
Parameter
Symbol
Clock Period
Condition
tC
Max.
100
—
"L" Clock Pulse Width
tCLW
45
—
"H" Clock Pulse Width
tCHW
45
—
tC
200
—
90
—
90
—
Clock Period
"L" Clock Pulse Width
tCLW
"H" Clock Pulse Width
tCHW
VDD=4.5 to 5.5 V
Min.
VDD=2.7 to 4.5 V
Unit
ns
CPU control (OSC0 Clock)
tC
tCHW
OSC0
tCLW
11/22
¡ Semiconductor
MSM65522/65P522
10MHz
50
Max.
IDD (mA)
40
30
Typ.
20
10
2
3
4
5
VDD (V)
6
6MHz
50
IDD (mA)
40
Max.
30
20
Typ.
10
2
3
4
5
VDD (V)
6
2MHz
50
IDD (mA)
40
30
20
Max.
10
Typ.
2
3
4
5
VDD (V)
6
Ta=–40 to +85°C, no load
Figure 2. Voltage vs. Current
12/22
¡ Semiconductor
MSM65522/65P522
• CPU control
(VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C)
Parameter
Symbol
Condition
Min.
Max.
Unit
RESET Pulse Width *1
tRESW1
—
20
—
ns
RESET Pulse Width *2
tRESW2
—
*3
—
—
*1 Excluding power ON, stop mode and hard stop mode.
*2 In power ON, stop mode and hard stop mode.
*3 Oscillation stabilization time depends on resonator.
RESET Pulse Width
tRESW1, 2
RESET
• Peripheral control 1
(VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C)
Parameter
Symbol
OSC
Clock Period
tC
EXI
External Interrupt Pulse
Width
tEXIW
tT0CW
T0
External Clock Pulse
Width
GATE Pulse Width
tT0GW
Condition
Min.
Max.
VDD=4.5 to 5.5V
100
—
VDD=2.7 to 4.5V
200
—
4 tC
—
Unit
ns
—
4 tC
—
1 tTOCLK *1
—
*1 tT0CLK : Timer 0 count clock period selected by T0CON.
13/22
¡ Semiconductor
MSM65522/65P522
1) OSC0
tC
OSC0
tCLW
2) EXI Pulse Width
tEXIW
INT0-2
3) T0
tT0CW
T0CK
tT0GW
GATE
14/22
¡ Semiconductor
MSM65522/65P522
• Peripheral control 2
(VDD=AVDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C)
Parameter
OSC
SFT
Symbol
Condition
Min.
Max.
VDD=4.5 to 5.5V
100
—
VDD=2.7 to 4.5V
200
—
Clock Period
tC
SFTCK Period
tSFC
8 tC
—
SFTCK "L" Pulse Width
tSFCLW
4 tC–20
—
SFTCK "H" Pulse Width
tSFCHW
4 tC–20
—
SFTO Setup Time
tSFOS
tSFCLW–100
—
SFTO Hold Time
tSFOH
tSFCHW–100
—
SFTI Setup Time
tSFIS
100
—
SFTI Hold Time
tSFIH
100
—
Synchronous Clock Period
CL=100pF
tSIC
8 tC
—
tSICLW
4 tC–20
—
tSICHW
4 tC–20
—
tSIOS
6 tC–100
—
tSIOH
2 tC–100
—
Input Data Setup Time
tSIIS
tC+tCLW+100
—
Input Data Hold Time
tSIIH
0
—
Synchronous Clock "L"
Pulse Width
SIO
(Clock Synchronous Clock "H"
Synchro- Pulse Width
nous Output Data Setup Time
Mode)
Output Data Hold Time
Unit
ns
15/22
¡ Semiconductor
MSM65522/65P522
1) SFT
tSFC
tSFCLW
tSFCHW
tSFOS
tSFOH
tSFIS
tSFIH
SFTCK
SFTO
SFTI
2) SIO
(Clock Synchronous Mode)
tSIC
tSICLW
tSICHW
tSIOS
tSIOH
tSIIS
tSIIH
TXD
RXD (transmission)
RXD (reception)
16/22
¡ Semiconductor
MSM65522/65P522
A/D Converter Characteristics
(VDD=4.5 to 5.5V/2.7 to 4.5V, GND=0V, Ta=-40 to +85°C)
Parameter
Symbol
Resolution
n
Absolute Error
EL
Condition
See the recommended circuit (Fig. 3).
Analog input source impedance
RI£5kW
Min.
Typ.
Max.
Unit
—
8
—
bit
—
—
+1.5/+2
LSB
–1.5/–2
—
—
±0.5/±1
LSB
EZS
—
—
+1.5/+2
LSB
Full Scale Error
EFS
—
—
–1.5/–2
LSB
Crosstalk
ECT
See the measuring circuit (Fig. 4).
—
—
±0.5/±1
LSB
tCONV
fOSC=10 MHz / 5 MHz
—
16/32
—
ms/CH
Differential Linearity Error
ED
Zero Point Error
Conversion time *
*
14.8/2.96ms/CH for the one time conversion follows setting the GO bit.
Definitions of Terms
(1)
Resolution
The minimum distinguishable analog value. For 8 bits, 28=256, i.e. (VRH–VRL) ÷ 256.
(2)
Linearity Error
The variance between the ideal conversion characteristics as an 8-bit A/D converter and
actual conversion characteristics (does not include quantatized error).
The ideal conversion characteristics refer to steps of the voltage between VRH and VRL
into 256 intervals.
(3)
Differential Linearity Error
Indicates the smoothness of the conversion. The width of analog input voltage
corresponding to the change by one bit of digital output is 1 LSB = (VRH-VRL) ÷ 256
ideally. The variance between this ideal bit size and bit size at arbitrary point in the
conversion range.
(4)
Zero Scale Error
The variance between the ideal conversion characteristics at the switching point of digital
outputs "000H to 001H" and actual conversion characteristics.
(5)
Full Scale Error
The variance between the ideal conversion characteristics at the switching point of digital
outputs "0FEH to 0FFH" and actual conversion characteristics.
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¡ Semiconductor
MSM65522/65P522
VDD
VDD
+
MSM65522
R1
–
Analog Voltage
Input
0.1
mF
47
mF
AI0 to 7
+
0V
GND
0.1
mF
RI (Analog input source impedance)£5kW
Figure 3. Recommended Circuit
–
Analog Voltage
Input
5kW
AI0
+
AI1
0.1
mF
Crosstalk is defined
as the difference of
A/D conversion result
between supplying
the same voltage to AI0
to AI7 and supplying
voltage shown in this
diagram.
AI7
VREF or AGND
Figure 4. Crosstalk Measuring Circuit
18/22
¡ Semiconductor
MSM65522/65P522
PACKAGE DIMENSIONS
(Unit : mm)
SDIP42-P-600-1.78
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
4.52 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
19/22
¡ Semiconductor
MSM65522/65P522
(Unit : mm)
DIP42-P-600-2.54
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
6.20 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
20/22
¡ Semiconductor
MSM65522/65P522
(Unit : mm)
QFP44-P-910-0.80-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Epoxy resin
42 alloy
Solder plating
5 mm or more
Package weight (g)
0.41 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
21/22
¡ Semiconductor
MSM65522/65P522
(Unit : mm)
QFJ44-P-S650-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
Cu alloy
Solder plating
5 mm or more
2.00 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
22/22
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