OKI MSM51V4222C-40RA 262,263-word ã 4-bit field memory Datasheet

FEDS51V4222C-03
1Semiconductor
MSM51V4222C
This version: Oct. 2000
Previous version: Feb. 2000
262,263-Word × 4-Bit Field Memory
GENERAL DESCRIPTION
The OKI MSM51V4222C is a high performance 1-Mbit, 256 K × 4-bit, Field Memory. It is designed for highspeed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media
systems. It is a FRAM for wide or low end use as general commodity TVs and VTRs, exclusively. The
MSM51V4222C is not designed for the other use or high end use in medical systems, professional graphics
systems which require long term picture, and data storage systems and others. The 1-Mbit capacity fits one field of
a conventional NTSC TV screen and cascaded directly without any delay devices among the MSM51V4222C.
(Cascading of MSM51V4222C provides larger storage depth or a longer delay).
Each of the 4-bit planes has separate serial write and read ports. These employ independent control clocks to
support asynchronous read and write operations. Different clock rates are also supported that allow alternate data
rates between write and read data streams.
The MSM51V4222C provides high speed FIFO, First-In First-Out, operation without external refreshing: it
refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable refresh free serial access operation,
so that the serial read and/or write control clock can be halted high or low for any duration as long as the power is
on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic.
The MSM51V4222C’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set
by reset timing. The delay length, number of read delay clocks between write and read, is determined by externally
controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 × 4-bit enable high speed first-bitaccess with no clock delay just after the write or read reset timings.
The MSM51V4222C is similar in operation and functionality to OKI 2-Mbit Field Memory MSM51V8222A.
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MSM51V4222C
FEATURES
•
•
•
•
Single power supply: 3.3 V ± 0.3 V
512 Rows × 512 Column × 4 bits
Fast FIFO (First-in First-out) operation
High speed asynchronous serial access
Read/Write cycle time
30 ns/40 ns
Access time
30 ns/35 ns
• Functional compatibility with OKI MSM51V8222A
• Self refresh (No refresh control is required)
• Package options:
16-pin 300 mil plastic DIP
(DIP16-P-300-2.54)
26/20-pin 300 mil plastic SOJ
(SOJ26/20-P-300-1.27)
20-pin 400 mil plastic ZIP
(ZIP20-P-400-1.27)
(Product: MSM51V4222C-xxRA)
(Product: MSM51V4222C-xxJA)
(Product: MSM51V4222C-xxRD)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Cycle Time (Min.)
MSM51V4222C-30RA
Family
30 ns
30 ns
MSM51V4222C-40RA
35 ns
40 ns
MSM51V4222C-30JA
30 ns
30 ns
MSM51V4222C-40JA
35 ns
40 ns
MSM51V4222C-30RD
30 ns
30 ns
MSM51V4222C-40RD
35 ns
40 ns
Package
300 mil 16-pin DIP
300 mil 26/20-pin SOJ
400 mil 20-pin ZIP
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FEDS51V4222C-03
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MSM51V4222C
PIN CONFIGURATION (TOP VIEW)
WE 1
RSTW 2
SWCK 3
16 VCC
15 RE
WE 1
26 VCC
RSTW 2
25 RE
SWCK 3
24 RSTR
DIN0 4
23 SRCK
14 RSTR
22 NC
NC 5
DIN0 4
13 SRCK
SRCK
1
RE
3
WE 5
SWCK 7
9
DIN1 5
12 DOUT0
NC 9
DIN1 10
18 NC
NC
17 DOUT0
NC 11
DIN2 6
11 DOUT1
DIN2 11
16 DOUT1
DIN3 7
10 DOUT2
DIN3 12
VSS 13
15 DOUT2
VSS 8
9 DOUT3
14 DOUT3
26/20-Pin Plastic SOJ
16-Pin Plastic DIP
DIN1 13
DIN3 15
DOUT3 17
DOUT1 19
2 RSTR
4 VCC
6 RSTW
8 DIN0
NO LEAD
12 NC
14 DIN2
16 VSS
18 DOUT2
20 DOUT0
20-Pin Plastic ZIP
Pin Name
Function
SWCK
Serial Write Clock
SRCK
Serial Read Clock
WE
Write Enable
RE
Read Enable
RSTW
Write Reset Clock
RSTR
Read Reset Clock
DIN0 to 3
DOUT0 to 3
Data Input
Data Output
VCC
Power Supply (3.3 V)
VSS
Ground (0 V)
NC
No Connection
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MSM51V4222C
BLOCK DIAGRAM
DOUT (× 4)
Data-Out
Buffer (× 4)
RE
RSTR
SRCK
Serial Read Controller
512-Word Serial Read Register (× 4)
Read Line Buffer Read Line Buffer
Low-Half (× 4)
High-Half (× 4)
256 (× 4)
120-Word
Sub-Register (× 4)
120-Word
Sub-Register (× 4)
256 (× 4)
256K (× 4)
Memory
Array
X
Decoder
256 (× 4)
256 (× 4)
Read/Write
and Refresh
Controller
Clock
Oscillator
Write Line Buffer Write Line Buffer
Low-Half (× 4)
High-Half (× 4)
512-Word Serial Write Register (× 4)
Data-In
Buffer (× 4)
DIN (× 4)
VBB
Generator
Serial Write Controller
WE
RSTW
SWCK
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MSM51V4222C
OPERATION
Write Operation
The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is accomplished by
cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW.
Each write operation, which begins after RSTW, must contain at least 130 active write cycles, i.e. SWCK cycles
while WE is high. To transfer the last data to the DRAM array, which at that time is stored in the serial data
registers attached to the DRAM array, an RSTW operation is required after the last SWCK cycle.
Write Reset: RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address counters to zero. RSTW
setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely
controlled by the SWCK rising edge after the high level of RSTW, the states of WE are ignored in the write reset
cycle.
Before RSTW may be brought high again for a further reset operation, it must be low for at least two SWCK
cycles.
Data Inputs: DIN0 to 3
Write Clock: SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer.
Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.
Write Enable: WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the
input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high)
restrictions, because the MSM51V4222C is in fully static operation as long as the power is on. Note that WE setup
and hold times are referenced to the rising edge of SWCK.
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MSM51V4222C
Read Operation
The read operation is controlled by three clocks, SRCK, RSTR, and RE. Read operation is accomplished by
cycling SRCK, and holding RE high after the read address pointer reset operation or RSTR.
Each read operation, which begins after RSTR, must contain at least 130 active read cycles, i.e. SRCK cycles while
RE is high.
Read Reset: RSTR
The first positive transition of SRCK after RSTR becomes high resets the read address counters to zero. RSTR
setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled
by the SRCK rising edge after the high level of RSTR, the states of RE are ignored in the read reset cycle.
Before RSTR may be brought high again for a further reset operation, it must be low for at least two SRCK cycles.
Data Out: DOUT0 to 3
Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read
operation. The SRCK input increments the internal read address pointer when RE is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of
SRCK. There are no output valid time restriction on MSM51V4222C.
Read Enable: RE
The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the
rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE
setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK
clock.
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MSM51V4222C
Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 100 µs after VCC has stabilized to a
value within the range of recommended operating conditions. After this 100 µs stabilization interval, the following
initialization sequence must be performed.
Because the read and write address counters are not valid after power-up, a minimum of 130 dummy write
operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW
operation and an RSTR operation, to properly initialize the write and the read address pointer. Dummy write
cycles/RSTW and dummy read cycles/RSTR may occur simultaneously.
If these dummy read and write operations start while VCC and/or the substrate voltage has not stabilized, it is
necessary to perform an RSTR operation plus a minimum of 130 SRCK cycles plus another RSTR operation, and
an RSTW operation plus a minimum of 130 SRCK cycles plus another RSTW operation to properly initialize read
and write address pointers
Old/New Data Access
There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from memory.
If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the
next RSTW operation), then the data just written will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the second field of
data for as many as 119 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 119
SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device
assures that the first field will still be read out. The first field of data that is read out while the second field of data
is written is called “old data”.
In order to read out “new data”, i.e., the second field written in, the delay between an RSTW operation and an
RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR operations is more than
120 but less than 600 cycles, then the data read out will be undetermined. It may be “old data” or “new” data, or a
combination of old and new data. Such a timing should be avoided.
Cascade Operation
The MSM51V4222C is designed to allow easy cascading of multiple memory devices. This provides higher
storage depth, or a longer delay than can be achieved with only one memory device.
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MSM51V4222C
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Input Output Voltage
VT
at Ta = 25°C, VSS
–1.0 to 4.6
V
Output Current
IOS
Ta = 25°C
50
mA
Power Dissipation
PD
Ta = 25°C
1
W
Operating Temperature
Topr
—
0 to 70
°C
Storage Temperature
Tstg
—
–55 to 150
°C
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supply Voltage
VCC
3.0
3.3
3.6
V
Power Supply Voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.4
VCC
VCC + 0.3
V
Input Low Voltage
VIL
–0.3
0
0.8
V
DC Characteristics
Parameter
Symbol
Condition
Min.
Max.
Unit
Input Leakage Current
ILI
Output Leakage Current
ILO
0 < VI < VCC, Other Pins Tested at V = 0 V
–10
10
µA
0 < VO < VCC
–10
10
µA
Output “H” Level Voltage
VOH
IOH = –1 mA
2.4
—
V
Output “L” Level Voltage
VOL
Operating Current
ICC1
IOL = 2 mA
—
0.4
V
Minimum Cycle Time, Output Open
—
30
mA
Standby Current
ICC2
Input Pin = VIH/VIL
—
3
mA
Capacitance
(Ta = 25°C, f = 1 MHz)
Symbol
Max.
Unit
Input Capacitance (DIN, SWCK, SRCK, RSTW, RSTR, WE, RE)
Parameter
CI
7
pF
Output Capacitance (DOUT)
CO
7
pF
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MSM51V4222C
AC Characteristics
(VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C)
Parameter
Access Time from SRCK
Symbol
MSM51V4222C-30
MSM51V4222C-40
Min.
Max.
Min.
Max.
Unit
tAC
—
30
—
35
ns
DOUT Hold Time from SRCK
tDDCK
6
—
6
—
ns
DOUT Enable Time from SRCK
tDECK
6
30
6
35
ns
DOUT Hold Time from RE
tDDRE
9
—
9
—
ns
SWCK “H” Pulse Width
tWSWH
12
—
17
—
ns
SWCK “L” Pulse Width
tWSWL
12
—
17
—
ns
Input Data Setup Time
tDS
3
—
5
—
ns
Input Data Hold Time
tDH
6
—
6
—
ns
WE Enable Setup Time
tWENS
0
—
0
—
ns
WE Enable Hold Time
tWENH
5
—
5
—
ns
WE Disable Setup Time
tWDSS
0
—
0
—
ns
WE Disable Hold Time
tWDSH
5
—
5
—
ns
WE “H” Pulse Width
tWWEH
5
—
10
—
ns
WE “L” Pulse Width
tWWEL
5
—
10
—
ns
RSTW Setup Time
tRSTWS
0
—
0
—
ns
RSTW Hold Time
tRSTWH
10
—
10
—
ns
SRCK “H” Pulse Width
tWSRH
12
—
17
—
ns
SRCK “L” Pulse Width
tWSRL
12
—
17
—
ns
RE Enable Setup Time
tRENS
0
—
0
—
ns
RE Enable Hold Time
tRENH
5
—
5
—
ns
RE Disable Setup Time
tRDSS
0
—
0
—
ns
RE Disable Hold Time
tRDSH
5
—
5
—
ns
RE “H” Pulse Width
tWREH
5
—
10
—
ns
RE “L” Pulse Width
tWREL
5
—
10
—
ns
RSTR Setup Time
tRSTRS
0
—
0
—
ns
RSTR Hold Time
tRSTRH
10
—
10
—
ns
SWCK Cycle Time
tSWC
30
—
40
—
ns
SRCK Cycle Time
tSRC
30
—
40
—
ns
tT
3
30
3
30
ns
Transition Time (Rise and Fall)
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MSM51V4222C
Notes: 1. Input signal reference levels for the parameter measurement are VIH = 3.0 V and VIL = 0 V. The
transition time tT is defined to be a transition time that signal transfers between VIH = 3.0 V and
VIL = 0 V.
2. AC measurements assume tT = 3 ns.
3. Read address must have more than a 600 address delay than write address in every cycle
when asynchronous read/write is performed.
4. Read must have more than a 600 address delay than write in order to read the data written in
a current series of write cycles which has been started at last write reset cycle: this is called
“new data read”.
When read has less than a 119 address delay than write, the read data are the data written in
a previous series of write cycles which had been written before at last write reset cycle: this is
called “old data read”.
5. When the read address delay is between more than 120 and less than 599, read data will be
undetermined. However, normal write is achieved in this address condition.
6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF.
Output reference levels are VOH = 2.0 V and VOL = 0.8 V.
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MSM51V4222C
TIMING WAVEFORM
Write Cycle Timing (Write Reset)
n Cycle
0 Cycle
SWCK
tRSTWH
tRSTWS
tT
DIN
–VIH
–VIL
tWSWH tWSWL
–VIH
–VIL
tSWC
RSTW
tDS
2 Cycle
1 Cycle
tDH
n–1
n
0
1
2
–VIH
–VIL
–VIH
–VIL
WE
Write Cycle Timing (Write Enable)
n Cycle
Disable Cycle
tWENH
tWDSH
Disable Cycle
n + 1 Cycle
tWDSS
tWENS
–VIH
–VIL
SWCK
–VIH
–VIL
WE
tWWEH
tWWEL
DIN
RSTW
n–1
n
n+1
–VIH
–VIL
–VIH
–VIL
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MSM51V4222C
Read Cycle Timing (Read Reset)
0 Cycle
n Cycle
2 Cycle
1 Cycle
–VIH
–VIL
SRCK
tRSTRS
tT
tWSRH
tRSTRH
tSRC
RSTR
–VIH
–VIL
tDDCK
tAC
DOUT
tWSRL
n–1
n
0
1
2
–VOH
–VOL
–VIH
–VIL
RE
Read Cycle Timing (Read Enable)
n Cycle
Disable Cycle
Disable Cycle
n + 1 Cycle
–VIH
–VIL
SRCK
tRDSH
tRENH
tRDSS
tRENS
–VIH
–VIL
RE
tWREL
tDDRE
DOUT
RSTR
n–1
n
tWREH
tDECK
Hi-Z
n+1
–VOH
–VOL
–VIH
–VIL
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MSM51V4222C
PACKAGE DIMENSIONS
(Unit: mm)
DIP16-P-300-2.54
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.99 TYP.
2/Dec. 11, 1996
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MSM51V4222C
(Unit: mm)
SOJ26/20-P-300-1.27
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.80 TYP.
5/Dec. 5, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
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MSM51V4222C
(Unit: mm)
ZIP20-P-400-1.27
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
1.50 TYP.
3/Dec. 5, 1996
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MSM51V4222C
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2000 Oki Electric Industry Co., Ltd.
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