MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
DESCRIPTION
The M65817AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal
to high precise switching-pulse digital output without analog signal.The M65817AFP has built-in 24bit sampling rate converter and
digital-gain-controller.
The M65817AFP enables to realize high precise ( X`tal oscillation precision) full digital amplifier systems combining with power
driver IC.
FEATURES
• Built-in 24bit Sampling Rate Converter.
Input Signal Sampling Rate
from 32KHz to 192KHz(24bit Maximum).
4 kinds of Digital Input Format.
• Built-in L/R Independent Digital Gain Control.
• Built-in Soft Mute Function with Exponential Approximate-Curve.
• Correspondence for SACD signal (64Fs 1bit,Fs=44.1KHz).
• Output from Sampling Rate Converter.
• 3.3V and 5.0V Power Supply Operation at Output Clock, Input Data, and Control Signal Port
MAIN SPECIFICATION
• Master Clock
Primary Clock: 256Fs/512Fs Secondary Clock: 1024Fs/512Fs
• Input Signal Format:
MSB First Right Justified(16/20/24bit),MSB First Left Justified(24bit)
LSB First Right Justified(24bit),I2S(24bit)
• Input Signal Sampling Rate from 32kHz to 192kHz.
• 8Fs Input Mode:Correspondence for External Digital Filter,Rate Converter Outputs.
• Gain Control Function:
+30dB to -∞dB(0.1dB Step until -96dB, -136dB Minimum)
• Third Order ∆Σ(16Fs:6bit/5bit)
• Sampling Rate Converter Output :Left MSB First /LRch Independent/32BCK
APPLICATION
DVD Receiver, AV Amplifier
RECOMMENDED OPERATING CONDITIONS
Logic Block:3.3V±10%,PWM Buffer Block :5.0V±10%
SYSTEM BLOCK DIAGRAM)
M65817AFP
External
Input
24bit
CD
DVD Audio
etc.
LRCK
BCK
DATA
256fsi
/512fsi
SACD
DSD
Sampling
Rate
Converter
32kHz
to
192kHz
Level
Control
∆Σ
MCU I/F
LC
Filter
Stream
Power
Driver
LC
Filter
PWM
+30dB
to
-∞
Clock
DSD
Interface
Stream
Power
Driver
Clock
1024fs/512fs
* "S-Master" is the digital amplifier technology developed by Sony Corporation. "S-Master" is a trademark of Sony Corporation.
MITSUBISHI
ELECTRIC
1
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
PIN CONFIGURATION
(3.3V system)
(5V system)
(3.3V/5V system)
P
G
M
U
T
E
N
S
P
M
U
T
E
S
C
D
T
S
C
S
H
I
F
T
S
C
L
A
T
C
H
M
O
D
E
2
M
O
D
E
1
D
V
d
d
M
C
K
S
E
L
D
V
s
s
X
V
s
s
X
V
s
s
X
f
s
o
I
N
X
V
d
d
V
s
s
L
V
s
s
L
1
+
40 39 3837 3635 34 33 3231 3029 2827 2625
INIT
SYNC
DATA
BCK
LRCK
FsiI
DSD128Fs
DSD64Fs
DSDR
DSDL
DSDCKSEL1
DSDCKSEL2
DSDCKIO
TEST1
TEST2
CKCTL1
CKCTL2
BFVdd
EXIOSEL
EXDATAL
EXDATAR
EXBCK
EXWCK
XfsiIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OUTL1+
VddL1+
VddL1OUTL1VssL1VssL2OUTL2VddL2VddL2+
OUTL2+
VssL2+
VddL
VddR
VssR1+
OUTR1+
VddR1+
VddR1OUTR1VssR1VssR2OUTR2VddR2VddR2+
OUTR2+
(5V system)
(5V system)
65 66 6768 6970 71 72 7374 7576 7778 7980
C C C B D T O S F F D X X X V V
K K K F V E F F s s V O f O s s
O O O V s S L L o o d V s V s s
U U U s s T F A C I d d o s R R
T T T s
3 L G K
2
d O s
1 2 3
A
O
+
U
G
T
(3.3V/5V system)
(3.3V system) (5V system)
MITSUBISHI
ELECTRIC
2
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
BLOCK DIAGRAM
EXDATAL 60
EXDATAR 61
EXBCK 62
E
X
I
O
S
E
L
X
f
F s
s i
i I
I N
S
Y
N
C
59
46 64
42 56 57 32 74 73 65 66 67
S>>P
C
K
C
T
L
1
C
K
C
T
L
2
M
C
K
S
E
L
F C C C
s K K K
F o O O O
s C U U U
o K T T T
I O 1 2 3
Clock
Generator
Primary
Clock
Generator
DSD128Fs 47
DSD64Fs 48
DSDR 49
S>>P
Sampling
Rate
Converter
Gain
Control
X
f
s
o
I
N
O
F
L S
F F
L L
A A
G G
77
28
71 72
24
21
18
15
Secondary
EXWBCK 63
DATA 43
BCK 44
LRCK 45
X
f
s
o
O
U
T
Noise
Shaper
(∆Σ)
OUTL1+
OUTL1OUTL2OUTL2+
PWM
10 OUTR1+
7 OUTR14 OUTR21 OUTR2+
Down Sampling
Filter
Serial
Control
DSDL 50
51 52 53
D
S
D
C
L
S
E
L
1
D
S
D
C
L
S
E
L
2
D
S
D
C
K
I
O
38 37 36
S
C
D
T
S
C
S
H
I
F
T
S
C
L
A
T
C
H
INIT/MUTE
35 34
M
O
D
E
1
M
O
D
E
2
MITSUBISHI
ELECTRIC
41
39
40
54 55
70
I
N
I
T
N
S
P
M
U
T
E
P
G
M
U
T
E
T
E
S
T
1
T
E
S
T
2
T
E
S
T
3
3
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Min.
Typ.
Max
Unit
PWMVdd
XVdd, XOVdd, and Vdd (PWM).
-0.3
-
6.0
V
6.0
V
Supply Voltage
BFVdd
-0.3
-
DVdd
-0.3
-
4.2
V
Input Voltage Range
Vi (5.0V)
-0.3
-
Vdd+0.3V
V
Vi (3.3V)
-0.3
-
Vdd+0.3V
Power Dissipation
Pd
Storage Temperature
Tstg
Ta=60ºC
V
mW
600
-40
-
125
ºC
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
Conditions
Min.
Typ.
Max
Unit
PWMVdd
5V XVdd, XOVdd, and Vdd (PWM).
4.5
5.0
5.5
V
BFVdd
5V function
4.5
5.0
5.5
V
3.3V function
V
3.0
3.3
3.6
DVdd
3.0
3.3
3.6
V
Operating Temperature
Ta
-10
-
60
ºC
Operating Frequency
XFsoIN
XFsiIN
16
-
50
8
-
25
MHz
MHz
ELECTRICAL CHARACTERISTICS
(Ta=25ºC,PWMVdd=5V, DVdd=3.3V: Unless otherwise specified.)
Parameter
Symbol
Conditions
Min.
Typ.
Max
Unit
H Level Input Voltage
VIH5
BFVdd=4.5~5.5V
0.75Vdd
-
-
V
VIH3
BFVdd=3.0~3.6V
0.75Vdd
-
-
V
VIL5
BFVdd=4.5~5.5V
-
-
0.25Vdd
V
VIL3
BFVdd=3.0~3.6V
-
-
0.25Vdd
V
-
-
10
µA
L Level Input Voltage
Input Leak Current
Ileak
DSD128Fs
DSD64Fs
VOH5
BFVdd=4.5~5.5V IOH5=-2.0mA
Vdd-0.5
-
-
V
VOH3
BFVdd=3.0~3.6V IOH3=-1.5mA
Vdd-0.5
-
-
V
VOH5
BFVdd=4.5~5.5V IOH5=-4.0mA
Vdd-0.5
-
-
V
CKOUT3
VOH3
BFVdd=3.0~3.6V IOH3=-3.0mA
Vdd-0.5
-
-
V
XfsoOUT
VOH5
BFVdd=4.5~5.5V IOH5=-2.0mA
Vdd-0.5
-
-
V
VOH3
BFVdd=3.0~3.6V IOH3=-2.0mA
Vdd-0.5
-
-
V
VOL5
BFVdd=4.5~5.5V IOH5=2.0mA
-
-
0.5
V
VOL3
BFVdd=3.0~3.6V IOH3=1.5mA
-
-
0.5
V
VOL5
BFVdd=4.5~5.5V IOH5=4.0mA
-
-
0.5
V
CKOUT3
VOL3
BFVdd=3.0~3.6V IOH3=3.0mA
-
-
0.5
V
XfsoOUT
VOL5
BFVdd=4.5~5.5V IOH5=2.0mA
-
-
0.5
V
VOL3
BFVdd=3.0~3.6V IOH3=2.0mA
-
-
0.5
V
Idd
BFVdd=5V
EXDATAL
EXDATAR
EXBCK
H Level
EXWCK
Output Voltage
CKOUT1
CKOUT2
OFLFAG
SFLAG
FsoCKO
DSD128Fs
DSD64Fs
EXDATAL
EXDATAR
EXBCK
L Level
EXWCK
Output Voltage
CKOUT1
CKOUT2
OFLFAG
SFLAG
FsoCKO
Power Supply Current
MITSUBISHI
ELECTRIC
33
mA
4
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
Characteristics Evaluation Circuit
OUTL1+
OUTL1OUTL2OUTL2+
DATA 43
BCK 44
LRCK 45
+
24
21
18
15
+
+
-
+
-
M65817AFP
OUTR1+
OUTR1OUTR2OUTR2+
+
10
7
4
1
+
+
-
+
-
Reference Characteristic
S/N
103dB(typ)
THD+N
0.0015%(typ)
Conditions
•Input:1kHz sine wave •Fs:Primary, Secondary 48kHz
•AC dithering E
•DC dithering:0.1%
•Gain Data Setting:(Index)10000b/(Mantissa)10000000b
•THD+N:Filter 20kHz LPF S/N:Filter 22kHz LPF+JIS-A
MITSUBISHI
ELECTRIC
5
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
PIN DESCRIPTION
Pin No.
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
OUTR2+
VddR2+
VddR2OUTR2VssR2VssR1OUTR1VddR1VddR1+
OUTR1+
VssR1+
VddR
VddL
VssL2+
OUTL2+
VddL2+
VddL2OUTL2VssL2VssL1OUTL1VddL1VddL1+
OUTL1+
VssL1+
VssL
XVdd
XfsoIN
XVss
XVss
DVss
MCKSEL
DVdd
MODE1
MODE2
SCLATCH
SCSHIFT
SCDT
NSPMUTE
PGMUTE
Description
Input
Type
O Rch PWM2(+) Output
-
I/O
-
-
Power Supply for Rch PWM2(-) (5V)
-
-
-
5V
GND for Rch PWM2(-)
-
-
GND for Rch PWM1(-)
-
-
O Rch PWM1 (-) Output
Signal Level
5V
Power Supply for Rch PWM2(+) (5V)
O Rch PWM2 (-) Output
-
5V
Power Supply for Rch PWM1(-) (5V)
-
-
-
Power Supply for Rch PWM1(+) (5V)
-
-
-
O Rch PWM1 (+) Output
-
5V
GND for Rch PWM1(+)
-
-
-
Power Supply for Rch PWM (5V)
-
-
-
Power Supply for Lch PWM (5V)
-
-
-
GND for Lch PWM2(+)
-
-
-
O Lch PWM2 (+) Output
-
5V
Power Supply for Lch PWM2(+) (5V)
-
-
Power Supply for Lch PWM2(-) (5V)
-
-
O Lch PWM2 (-) Output
-
5V
GND for Lch PWM2(-)
-
-
GND for Lch PWM1(-)
-
-
O Lch PWM1 (-) Output
-
5V
Power Supply for Lch PWM1(-) (5V)
-
-
-
Power Supply for Lch PWM1(+) (5V)
-
-
-
O Lch PWM1 (+) Output
-
GND for Lch PWM1(+)
-
5V
-
-
GND for Lch PWM
-
-
-
Power Supply for Master Clock Buffer
-
-
-
Normal
-
5V
GND for Master Clock Buffer
-
-
-
GND for Master Clock Buffer
-
-
-
GND for Digital Block
-
-
-
Normal
-
3.3V
I Secondary Master Clock Input:1024Fso/512Fso
I Secondary Master Clock Selection; L:1024Fso,
H:512Fso
Power Supply for Digital Block (3.3V)
I
I
I
I
I
I
I
Output Current
5V/3.3V
-
-
-
Schmitt
-
5V/3.3V
Input Mode Selection 2
Schmitt
-
5V/3.3V
Serial Control•Latch Signal Input
Schmitt
-
5V/3.3V
Serial Control•Shift Clock Input
Schmitt
-
5V/3.3V
Serial Control•Data Input
Schmitt
-
5V/3.3V
PWM Duty 50% Mute (L :Active)
Schmitt
-
5V/3.3V
PWM G-MUTE(L :Active)
Schmitt
-
5V/3.3V
Input Mode Selection 1
MITSUBISHI
ELECTRIC
6
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
Pin No.
Name
I/O
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
INIT
SYNC
DATA
BCK
LRCK
FsiI
DSD128Fs
DSD64Fs
DSDR
DSDL
DSDCKSEL1
DSDCKSEL2
DSDCKIO
TEST1
TEST2
CKCTL1
CKCTL2
BFVdd
EXIOSEL
EXDATAL
EXDATAR
EXBCK
EXWCK
XfsiIN
CKOUT1
CKOUT2
CKOUT3
BFVss
DVss
TEST3
OFLFLAG
SFLAG
FsoCKO
FsoI
DVdd
XOVdd
XfsoOUT
XOVss
VssR
VssR2+
I
I
I
I
I
I
I/O
I/O
I
I
I
I
I
I
I
I
I
Description
Initialize Input(Power Supply Reset): ; L:Reset, H:Release
I
O
O
O
I
Output Current
5V/3.3V
Signal Level
Schmitt
-
5V/3.3V
Synchronous Set of System Clock (at Rising Edge)
Schmitt
-
5V/3.3V
DATA Input (CD/MD / DVD audio mode)
Normal
-
5V/3.3V
BCK Input (CD/MD / DVD audio mode)
Schmitt
-
5V/3.3V
LRCK Input (CD/MD / DVD audio mode)
Schmitt
-
5V/3.3V
Primary Fsi Clock Input (SACD mode)
Schmitt
-
5V/3.3V
SACD Interface Clock(128Fs)
Schmitt
2mA/1.5mA
5V/3.3V
SACD Interface Clock(64Fs)
Schmitt
2mA/1.5mA
5V/3.3V
SACD Rch Data Input
Normal
-
5V/3.3V
SACD Lch Data Input
Normal
-
5V/3.3V
SACD Interface Selection 1
Normal
-
5V/3.3V
SACD Interface Selection 2
Normal
-
5V/3.3V
I/O Selection for SACD(64Fs,128Fs)Clock L:input,H:output
Normal
-
5V/3.3V
TEST1 must be connected to GND.
Normal
-
5V/3.3V
TEST2 must be connected to GND.
Normal
-
5V/3.3V
fso System Clock(CKOUT1,2,3) Output Selection 1
Normal
-
5V/3.3V
fso System Clock(CKOUT1,2,3) Output Selection 2
Normal
-
5V/3.3V
-
-
-
8Fs Data Input/Output Selection L:Input H:Output
Normal
-
5V/3.3V
8Fs Data Lch
Normal
2mA/1.5mA
5V/3.3V
8Fs Data Rch
Normal
2mA/1.5mA
5V/3.3V
BCK for 8fs Data (32BCK=1WCK)
Schmitt
2mA/1.5mA
5V/3.3V
Word Clock for 8fs Data (1WCK=32BCK)
Schmitt
2mA/1.5mA
5V/3.3V
Primary Master Clock Input (256fsi/512fsi/256fso/512fso)
Normal
-
5V/3.3V
fso System Clock Output 1
-
4mA/3mA
5V/3.3V
fso System Clock Output 2
-
4mA/3mA
5V/3.3V
fso System Clock Output 3
-
4mA/3mA
5V/3.3V
GND for Digital Block Input/Output Buffer
-
-
-
GND for Digital Block
-
-
-
Normal
-
3.3V
Overflow Detector Flag of Digital Operation (H :Active)
-
2mA
3.3V
Asynchronous Flag (H :Active)
-
2mA
3.3V
Secondary Fso Clock Output
-
4mA
3.3V
3.3V
Power Supply for Input/Output (3.3V/5V)Buffer
I
I/O
I/O
I/O
I/O
I
O
O
O
Input
Type
TEST3 must be connected to GND.
Secondary Fso Clock Input
Schmitt
-
Power Supply for Digital Block(3.3V)
-
-
-
Power Supply for Secondary Master Clock Buffer(5V)
-
-
-
O Buffered Output of Secondary Master Clock (1024/512fso)
-
2mA
5V
GND for Secondary Master Clock Buffer(1024/512fso)
-
-
-
GND for Rch PWM
-
-
-
GND for Rch PWM2(+)
-
-
-
MITSUBISHI
ELECTRIC
7
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
EXPLANATION OF OPERATION
1. Pin Setting.
34 35
1-1. MODE1, MODE2
The states of MODE1 and MODE2 pins select input signal mode.
MODE1 and MODE2 are control pins for input signal mode (Normal/SACD/External Rate Converter 8fs Input).
These are selectable as follows.
Pin
34
Name Mode
MOD
35
SACD-fsi
SACD-fso
L
L
H
H
L
H
L
H
Normal
MOD
External Rate Converter 8fs
♦Normal mode
The Normal is data input mode from CD,MD,DVD etc.
Input pins are DATA, BCK and LRCK .
♦External Rate Converter 8fs mode
The External Rate Converter 8fs is data input mode from external source without using Rate Converter
Block. Input pins are EXBCK, EXWCK, EXDATAL and EXDATAR .
♦SACD-fsi mode
The SACD-fsi is data input mode on SACD format with synchronized primary clock.
Input pins are DSDL, DSDR, DSD128Fs and DSD64Fs .
♦SACD-fso mode
The SACD-fso is data input mode on SACD format with synchronized secondary clock.
Input pins are DSDL, DSDR, DSD128Fs and DSD64Fs .
* primary clock:
This clock means input side clock system of rate converter.
secondary clock: This clock means output side clock system of rate converter. This clock makes to
operate after Rate Converter Block( Gain Control Block, ∆Σ Block and PWM Block).
1-2. SCDT,SCSHIFT,SCLATCH
38 37
36
SCDT,SCSHIFT, and SCLATCH are input pins for setting M65817AFP's operation.
Input format of SCDT, SCSHIFT and SCLATCH is shown below.
♦Input format of SCDT, SCSHIFT and SCLATCH .
bit1
SCDT
24
20
15
10
5
1
SCSHIFT
SCLATCH
♦Description of Operation Mode
Operating Mode are classified in four and assigned by bit1and bit2. These four functions are shown below.
(bit1 and bit2) = :
(L and L) Gain Control Mode:
Gain control.
(bit1 and bit2) = :
(L and H) System1 Mode:
Primary block initialization, etc.
(bit1 and bit2) = :
(H and L) System2 Mode:
Secondary block initialization, etc.
(bit1 and bit2) = :
(H and H) Test Mode( setting prohibition )
These four detail functions are shown in Page17.
MITSUBISHI
ELECTRIC
8
.
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
1-3. DATA,BCK,LRCK
43
44
45
DATA, BCK and LRCK are input pins under condition of ` Normal ` mode.
Input formats are supported by following 4 ways, and are set by Serial Control, "System1 Mode,
bit3 and bit4". Input data length are selectable in a case of "MSB First Right Justified"
(Serial Control "System1 Mode,bit5 and bit6").
Input formats are shown in following figures.
♦Input Formats of DATA, BCK and LRCK
1/fs, 1/2fs, 1/4fs
MSB first left justified
(24bit)
Left
LRCK
Right
BCK
MSB
LSB
MSB
DATA
(24bit)
24cycle
24cycle
1/fs, 1/2fs, 1/4fs
MSB first right justified
(16bit, 20bit, 24bit)
LSB
Right
Left
LRCK
BCK
16 cycle
16 cycle
MSB
LSB
20 cycle
20 cycle
LSB
MSB
DATA
(24bit)
LSB
MSB
24 cycle
24 cycle
1/fs, 1/2fs, 1/4fs
LSB first right justified
(24bit)
MSB
LSB
DATA
(20bit)
LSB
MSB
LSB
MSB
DATA
(16bit)
Left
LRCK
Right
BCK
LSB
LSB
MSB
DATA
(24bit)
MSB
24 cycle
24 cycle
1/fs, 1/2fs, 1/4fs
I2S(24bit)
Left
LRCK
Right
BCK
1 BCK
1 BCK
MSB
DATA
(24bit)
LSB
24 cycle
MITSUBISHI
ELECTRIC
MSB
LSB
24 cycle
9
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
62
1-4. EXBCK,EXWCK,EXDATAL,EXDATAR,EXIOSEL
63
60
61
59
These are Input pins on "External sampling rate converter 8fs mode". In case of no usage ,
from 59 pin to 63 pin should be tied to "low" .
But when EXIOSEL is set the condition to "H" on no usage mode,
EXDATAL,EXDATAR are changed to output terminals for sampling rate converter.
This function‘s detail explanation is shown in Page14 .
1-5. DSDL,DSDR,DSD128Fs,DSD64Fs,DSDCKSEL1,DSDCKSEL2,DSDCKIO
50
49
47 48
51
52
53
These are Input pins used on SACD-fsi Mode or SACD-fso Mode.
In case of no usage,from 47 pin to 53 pin should be tied to "low".
This function‘s detail explanation is shown in Page15 .
1-6. MCKCEL,XfsoIN,XfsoOUT
32
XfsoIN pin is secondary master clock input.
28
77
MCKSEL
L
H
The state of MCKSEL pin selects secondary master clock.
XfsoIN
1024fs
512fs
XfsoOUT pin is buffered-output from XfsoIN pin's input clock.
1-7. XfsiIN
64
XfsiIN pin is primary master clock input.
Frequency of primary master clock must be selected by the serial control "System2 Mode,bit3".
The state of IMCKSEL pin selects primary master clock.
1-8. CKCTL1,CKCTL2,CKOUT1,CKOUT2,CKOUT3
XfsiIN
512fs
256fs
bit3(IMCKSEL)
H
L
56
57
65
66
67
CKOUT1, CKOUT2 and CKOUT3 pins are divided-clock output from secondary clock.
At power on, these frequency is free-running.
The states of CKCTL1 and CKCTL2 pins selects clock frequency of CKOUT1,CKOUT2 and CKOUT3 pins.
The setting table of CKCTL1 and CKCTL2 pins is shown below.
CKCTL1
L
L
H
H
CKCTL2 CKOUT1 CKOUT2 CKOUT3
L
L
L
L
H
256Fso
16Fso
8Fso
L
512Fso
256Fso
16Fso
H
512Fso
256Fso
8Fso
1-9. FsoCKO
73
FsoCKO is clock output pin of 1Fs frequency. The output is divided-clock of XfsoIN, and frequency is
free-running at power on. FsoCKO pin's clock is utilized for a synchronization in case that have used
plural M65817AFP,take a synchronization between M65817AFP and other external devices.
Detail explanation is shown in next paragraph, "SYNC ".
MITSUBISHI
ELECTRIC
10
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
1-10. SYNC,FsoI,FsiI,SFLAG
42
74
46
72
SYNC pin is input for resynchronization. Fsol and Fsil pins are clock input for synchronized operation.
SFLAG pin is output for Asynchronous Flag. It is necessary of synchronized operation between M65817AFP
and other input-source-devices. Therefore the M65817AFP is operated by the synchronized clocks,Fsol(1fs),
Fsil(1fs),and LRCK(1/2/4fs).The M65817AFP detects rise edge of these synchronized-clocks in normal operation,
and the M65817AFP does a treatment of resynchronization in case that the cycle has changed. In addition,
the M65817AFP re-synchronizes for a synchronized clock, in case that the M65817AFP detects SYNC pin's
rise edge ,too. This rise edge detective function is effective for stable operation in case of power-on and change
of input source, this 'SYNC' function is able to do at Serial Control(System2 mode, bit6:Page17 in detail),too.
For a period of resynchronization, SFLAG pin output "H" and output signal is muted ,The synchronization
clock is differed by input signal mode.
These relations are shown in following table.
Input Signal Mode
Normal
External Rate Converter 8fs
SACD-fsi
SACD-fso
`Synchronization detection` clock
Primary Side
Secondary Side
FsoI
LRCK
FsoI
FsiI
FsoI
FsoI
In case of using Multiplex(for multi channel application) and Single(for 2ch application) , detail explanation is
shown below.(Input signal mode is "Normal")
♦Normal Mode (34 pin="L",35 pin="L")
Multiplex use
The primary clock must be entered into each LRCK pins of M65817AFP, therefore primary clock side of
plural M65817AFP is done with synchronization.
The secondary clock must be generated from arbitrary one master-M65817AFP`s FsoCKO pin and
be entered each FsoI pins of slave-M65817AFP(inclusive master-M65817AFP) with synchronization.
Single use
The primary clock must be entered into LRCK pin of M65817AFP, therefore primary clock side of
M65817AFP is done with synchronization.
The secondary clock can be entered from FsoCKO pin into FsoI pin with synchronization.
As the other way, the secondary clock may not be entered into FsoI pin,
however in this case, the ASYNCEN2 register flag in System Control must be set
`disable`, secondary-asynchronous-detection.
Under `Normal` mode, M65817AFP always treats synchronous detection between LRCK pin's clock
and primary clock in M65817AFP.This detection has a priority rather than Serial Control:ASYNCEN1,
therefore the synchronous detection does as ` forced-enable`, regardless of ASYNCEN value.
LRCK(Primary Side)
Master
LRCK
FsoCKO(Secondary Side)
FsoI
FsiI
Slave
LRCK
FsoI
FsiI
LRCK(Primary Side)
Slave
LRCK
FsiI
FsoI
LRCK
FsiI
FsoI
Multiplex use ( 6ch )
Single use ( 2ch )
*Refer to Page14 and Page15 about circuit examples in case that input signal modes
are `External Rate Converter 8fs`, `SACD-fsi`, and `SACD-fso`.
MITSUBISHI
ELECTRIC
11
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
1-11. OFLFLAG
71
OFLFLAG pin is output for the 'over flow flag' in the operation. OFLFLAG pin outputs "H" level by detection of
over flow from Gain Control Block and others. The "H" level width is over 0.6msec, so detection result is held.
1-12. NSPMUTE
39
NSPMUTE pin is input to make for PWM output to 50% duty mute.
"L": PWM output 50% duty Mute. '"H": Mute release.
1-13. PGMUTE
40
PGMUTE pin is input to make PWM output to absolute zero mute.
"L": PWM output mute.
OUTL1 (+), OUTL2 (+), OUTR1 (+), OUTR2 (+) : "L" fixed
OUTL1 (-), OUTL2 (-), OUTR1 (-), OUTR2 (-)
: "H" fixed
"H": MUTE release.
1-14. INIT
41
INIT pin is input for reset to all the function of M65817AFP.
"L" level : (1). Clear of data memory. (2). Initialization of Serial Control. (3). PWM output Duty 50 %.
"L" period needs more than 5 msec.
"H" level : usual operation.
"L">"H" rise edge: Resynchronization treatment, which is same at SYNC function.
1-15. TEST1,TEST2,TEST3
TEST1,TEST2, and TEST3 pins are test input for factory shipping test of M65817AFP.
TEST1,TEST2, and TEST3 pins must be tied to "L" level on usual operation.
1-16. Power Supply and GND
Power supply and GND routes have 5 isolated lines.
(1) VddL1+, VssL1+, VddL1-, VssL1-, VddL2+, VssL2+, VddL2,-, VssL2 - ,VddR1+, VssR1+,
VddR1-, VssR1-, VddR2+, VssR2+, VddR2, -, VssR2 - ,VssL, VddL, VssR, VddR
These pins are Power supply and GND for PWM output buffer block.
Power Supply voltage must be fixed at 5.0V.
27
(2) XVdd, XVss(29pin) ,XVss(30pin)
29
30
These pins are Power supply and GND for XfsoIN clock input block.
Power Supply voltage must be fixed at 5.0V.
(3) XOVdd, XOVss
76
78
These pins are Power supply and GND for XfsoOUT clock output block.
Power Supply voltage must be fixed at 5.0V.
33 31 75 69
(4) DVdd, DVss
These pins are Power supply and GND for digital block and fixed input/output
buffer only for 3.3V (32,70-74 pins).Power Supply voltage must be fixed at 3.3V
58
(5) BFVdd, BFVss
68
These pins are Power supply and GND for input/output buffer (3.3V/5V ). In a case that BFVdd pin
is applied at 5.0V, input/output voltage level of 34-67pins becomes 5.0V signal level. In another case
that BFVdd pin is supplied at 3.3V, input/output pins (34-67 pins) becomes 3.3V signal level.
MITSUBISHI
ELECTRIC
12
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
1-17. OUTL1+,OUTL1-,OUTL2+,OUTL2-,OUTR1+,OUTR1-,OUTR2+,OUTR2OUTL1+,OUTL1-,OUTL2+,OUTL2-,OUTR1+,OUTR1-,OUTR2+ and OUTR2- pins are pulse output
converted ∆∑ output signal to PWM data.
These pins are connected to external Power Driver ICs.
MITSUBISHI
ELECTRIC
13
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
2. Setting on `External Rate Converter 8fs` Mode
2-1. EXBCK,EXWCK,EXDATAL,EXDATAR,EXIOSEL
EXDATAL and EXDATARare data input pins under condition of `External Sampling Rate Converter 8fs` mode.
EXDATAL and EXDATAR are changed to output pins for Sampling Rate Converter except condition of `External
Rate Converter 8fs` mode and EXIOSEL ="H".
In case of un-using `External sampling rate converter 8fs` mode, EXIOSEL="L" and EXBCK, EXWCK, EXDATAL
and EXDATAR must be tied to low position.
EXDATAL, EXDATAR, EXBCK and EXWCK pin's input/output format is following figure.
Input Signal Mode
EIOSEL
EXWCK,EXBCK,EXDATAL,EXDATAR
input/ output
L
input
H
input
L
input
H
output
`External Rate
Converter 8fs` mode
(MODE1,2=L,H)
Except `External Rate
Converter 8fs` mode
(Except MODE1,2=L,H)
•EXDATAL,EXDATAR,EXBCK and EXWCK input/output format
EXWCK
8fso
EXBCK
256fso
MSB
23 22 21 20
EXDATAL
/EXDATAR
9 8 7
LSB
1 0
MSB first left justified (24bit)
2-2. SYNC,Fsol,Fsil,SFLAG
Multiplex and Single use
The primary clock side is not operated with synchronization, because internal Sampling Rate Converter is not used.
Under `External Rate Converter 8fs` mode, the primary clock side asynchronous detection operates as `forced-disable`.
The secondary clock side is operated with synchronization by FsoCKO pin.
Then, M65817AFP needs that rising edge of FsoCKO connected from M65817AFP to external sampling rate converter
and rising edge of EXWCK connected from external rate converter to M65817AFP are in synchronized phase.
Master
FsoCKO(Secondary Side)
LRCK
FsoI
Fsil
LRCK
Slave
LRCK FsoI
Fsil
FSoCKO
FsoI
Fsil
Slave
LRCK
Fsol
Fsil
Multiplex use ( 6ch )
Single use ( 2ch )
MITSUBISHI
ELECTRIC
14
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
3. Setting on `SACD` Mode
3-1. DSDL,DSDR,DSD128Fs,DSD64Fs,DSDCKSEL1,DSDCKSEL2,DSDCKIO
DSDL and DSDR are data input pins under `SACD-fsi` or `SACD-fso` mode.
Under `SACD-fsi ` mode, SACD data must be synchronized for primary clock.
Under `SACD-fso ` mode, SACD data must be synchronized for secondary clock.
DSDCKIO pin selects pin-type of DSD128Fs and DSD64Fs pins as input or output clock for data fetch.
The states of DSDCKSEL1 and DSDCKDEL2 pins select 4 "SACD" operating mode.
The relations of DSDCKSEL1, DSDCKSEL2 pins and SACD input format mode setting are following figures.
DSDCKSEL1
L
L
H
H
DSDCKSEL2
L
H
L
H
SACD operating timing mode
mode1
mode2
mode3
mode4
Setting of DSDCKIO is following table.
DSDCKIO
L
H
Selection of DSD64fs and DSD128fs I/O
Input
Output
SACD operating mode
♦mode1
DSDL/R (input data)
DSD128fs
DSD64fs
D0
DSD64fs
D1
XD1
D2
XD2
D3
XD3
128fs
64fs
♦mode2
DSDL/R (input data)
DSD128fs
XD0
D0
XD0
D1
XD1
D2
XD2
D3
XD3
XD0
D1
XD1
D2
XD2
D3
XD3
128fs
64fs
♦mode3
DSDL/R (input data)
D0
128fs
DSD128fs
64fs
DSD64fs
♦mode4
DSDL/R (input data)
D0
D1
D2
D3
DSD128fs
64fs
DSD64fs
* D0:Positive phase data,
XD0:Negative phase data (reversal)
Positive phase data are fetched at the timing of "O" marks in upper figure.
MITSUBISHI
ELECTRIC
15
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
3-2. SYNC,FsoI,FsiI,SFLAG
♦SACD-fsi Mode
Multiplex Use
In the primary clock side,M65817AFP are operated with synchronization by FsiI pin's clock. In secondary clock side,
M65817AFP must be generated from arbitrary one master-M65817AFP's FsoCKO pin and be entered each FsoI pins
of slave-M65817AFP(inclusive master) with synchronization.
Additionally, the master-M65817AFPoutputs clock from DSD64fs and DSD128fs pins( DSDCKIO ="H"), and these
clock are entered DSD64fs and DSD128fs pins ( DSDCKIO="L") of slave-M65817AFP.
By these conditions, multiple M65817AFP are operated with synchronization each other for SACD input.
Single Use
The primary clock must be entered to FsiI pin, and the secondary clock must be entered to FsoI pin. In the other way,
the primary and secondary clocks can not be entered at FsiI and FsoI pins, however in this case, the asynchronousdetection register flags (ASYNCEN1 and ASYNCEN2 in System Control ) must be `disable`.
Master
FsoCKO(Secondary Side)
LRCK
FsiI(Primary)
Fsil
FsoI
DSD128fs/DSD64fs
Slave
LRCK
FsoI
LRCK FsoI
Fsil
Fsil FsoCKO DSD128fs/DSD64fs
Slave
LRCK
Fsol
Fsil
♦SACD-fso Mode
Multiplex use ( 6ch )
Multiplex use ( 6ch )
Single use ( 2ch )
The primary clock side is not done with synchronization, because internal Sampling Rate Converter is not used. In
`SACD-fso` mode, the primary side asynchronous detection operates as forced-`disable`. The secondary clock must
be generated from arbitrary one master-M65817AFP's FsoCKO pin and be entered each FsoI pins of slaveM65817AFP(inclusive master) with synchronization. Additionally, the master-M65817AFP outputs clock wave from
DSD64fs and DSD128fs pins (in this condition, DSDCKIO pin's input level of master-M65817AFP must be "H"), and
these clock are entered DSD64fs and DSD128fs pins of slave-M65817AFP(in this condition, DSDCKIO pin's input
level of slave-M65817AFP must be “L”). By these conditions, plural M65817AFP are operated with synchronization
each other for SACD input.
Single Case (2ch)
The primary clock side is not operated with synchronization, because internal Sampling Rate Converter is not used.
In `SACD-fso` mode, the primary side asynchronous detection operates as forced-`disable`. The secondary clock
can be input at FsoI pin. As the another way, the secondary clock can not be entered at FsoI pin, however in this
case, the asynchronous-detection flag register (ASYNCEN2 in System Control) must be `disable`.
Master
FsoCKO(Secondary Side)
LRCK
FsoI
Fsil
DSD128fs/DSD64fs
LRCK FsoI
Slave
LRCK
FsoI
Fsil
DSD128fs/DSD64fs
Fsil
Slave
LRCK
Fsol
Fsil
Multiplex use ( 6ch )
Single use ( 2ch )
MITSUBISHI
ELECTRIC
16
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
SERIAL CONTROL
1. Gain Control Mode
No setting bits means "Don't care".
bit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Flag Name
MODE1
MODE2
TEST1
TEST2
NSLMT1
NSLMT2
GCONT1
GCONT2
GAIN0
GAIN1
GAIN2
GAIN3
GAIN4
GAIN5
GAIN6
GAIN7
GAIN8
GAIN9
GAIN10
GAIN11
GAIN12
Functional Explanation
H
L
Mode Setting 1
"L" fixed
Mode Setting 2
"L" fixed
Test Mode 1
"L" fixed
Test Mode 2
"L" fixed
Output Limit 1
Refer to Table 1-1.
Output Limit 1
Channel selection for Gain Control Block 1 L/R independence
L/R common
Channel selection for Gain Control Block 2
Lch
Rch
Gain Data
Gain Data
Gain Data
Gain Data
Gain Data
Gain Data
Gain Data
Gain Data
Gain Data
Gain Data
Gain Data
Gain Data
Gain Data
Index (MSB)
Index
Index
Index
Index (LSB)
Mantissa (MSB)
Mantissa
Mantissa
Mantissa
Mantissa
Mantissa
Mantissa
Mantissa (LSB)
INIT
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
•Output Limit (bit5,bit6:NSLMT1 , NSLMT2)
The M65817AFP has Over Flow Limit function.
Over Flow Limit detects of input signal level and limits gain level.
Limit value is set by Gain Control Mode :bit5,bit6 ” NSLMT1,NSLMT2” and System2 Mode:bit17"NSOBIT".
•The limit value setting of Gain control block and PWM output.
Table (1-1a). Limit Value [ In Case of 6bit mode, system2 mode bit17(NSOBIT)="L" ]
Gain Block
±0.9375
±0.90625
±0.875
±0.84375
NSLMT1 NSLMT2
L
L
H
L
L
H
H
H
PWM Output(Limit Value from DS Block )
63 values (±31)
61 values (±30)
59 values (±29)
57 values (±28)
Table (1-1b). Limit Value [ In Case of 5bit mode system 2 mode bit17(NSOBIT)="H" ]
NSLMT1 NSLMT2
L
L
H
L
L
H
H
H
Limit Value of Gain
±0.90625
±0.875
±0.84375
±0.8125
PWM Output Value(Limit Value from ∆Σ Block )
31 values (±15)
31 values (±15)
29 values (±14)
29 values (±14)
•Channel Selection for Gain Control Block (bit7,bit8:GCONT1, GCONT2 )
These bits select L/R common or L/Rch independence operation.
GCONT1:"L"…L/Rch common(INIT),"H"…L/Rch independence.
GCONT2:"L"…Rch only,
"H"…Lch only.
Bit8 is effective only the case of `bit7 = "H"`.
MITSUBISHI
ELECTRIC
17
MITSUBISHI ICs (SOUND PROCESSOR)
M65817AFP
Digital Amplifier Processor of S-Master* Technology
• The index and Mantissa part of Gain Data. (bit12 -bit24,:GAIN0 -GAIN12)
The Gain value is set from bit12 to bit24.
Index part: bit12 (MSB) -bit16(LSB)
Mantissa part: bit17 (MSB) -bit24 (LSB)
The Gain Data is assigned 13bits, composed of Index part 5bits and of Mantissa part 8bits,
The range of Index parts is following statements.
Index part: 10100b(16.0) - 10000b(1.0) - 00000b( 2-16 )
The range of mantissa part is following as statement.
Index part; 10100b -00001b: Mantissa part; 11111111b -10000000b (128 step/1 Index).
Index part;00000b:
Mantissa part; 11111111b -00000000b (256 step).
Initial value :Index part: 10000b
Mantissa part:10000000b
infinity zero:Index part: 00000b
Mantissa part:00000000b
For instance 10000b (1.0) / 10000000b (0.5) means 0.5 (0dB).
# Notice of GAIN value Setting continuously
In the case of GAIN value Setting continuously, for example of Setting L/Rch independently, please take
the interval time (pulse interval time of SCLATCH signal) more than 1/fsc.For example, in the case of
fso=48kHz, please take the interval time more than 21µsec.
• The Gain Data and Audio Output Level.
Table (6-1-2). The Gain Data and Output Level
The Gain Data
Polarity
10100/11111111
|
10001/10000000
|
10000/10000000
01111/11111111
|
00000/10000000
|
00000/00000001
00000/00000000
+
Absolute Output
15.937
|
1.
|
0.
0.49804687
|
0.5*2-16
|
0.00390625*2-16
infinity zero
Output Level
+30.069dB
|
+6.021dB
|
0dB
–0.0340dB
|
–96.330dB
|
–138.474dB
–∞ dB
• Calculation method of Gain value.
The way to calculation of Gain value from Gain Data is following equation.
Gain value = 20log [ 2
(Index data(decimal value)-16)
X
Mantissa data(decimal value)
128
MITSUBISHI
ELECTRIC
]
dB
18
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
♦Soft Mute.
The Soft Mute function is executed by setting of Gain Data as 00000/00000000b
( "/" :means dividing point between index part and mantissa part).
The release from Soft Mute function must be executed by setting the gain data before soft mute.
The Soft Mute function and release from Soft Mute function don't have linear curve but
have characteristics of approximate exponential curve.
Output amplitude
16
0.5
T = xxxx/Fs(sec)
0
t
T
T
00000/00000000b setting
10000/10000000b setting
Characteristics of Soft Mute function
♦Operating time of Soft Mute
Total steps from MAX value(10100b/11111111b) to MIN value(00000b/00000000b) are
(128steps/1index) × (20 indexes(10100b-10000b)) + 256steps =2816steps.
The transition term of up and down depend on 2fso clock.
Therefore, in case of fso=48kHz, T=1/2fso=10.416µsec/step, transition term are following.
From MAX value (10100b/11111111b) to MIN value (00000b/00000000b) : 2816T=29.333msec.
From 0dB value(10100b/11111111b) to MIN value(00000b/00000000b) : 2304T=24.000msec.
6dB transition term (when over 00000b/10000000b(=-96dB) values): 128T=1.333msec.
♦Soft Attenuate.
Transition from older Gain Attenuation to newer Gain Attenuation always operates with Soft Mute function.
For example, in case of Gain1 > GAIN3 > GAIN2, transition process is shown below.
First, GAIN1 is operated, then second, GAIN2 is operated.
In case that GAIN2 is operated faster than GAIN1of transition completion("A" situation in figure),
GAIN1 is ignored and data approaches at GAIN2 .
Further, GAIN3 is operated faster than GAIN2 of transition completion("B" or "C" situation in figure),
GAIN2 is ignored and data approaches at GAIN3 .
Gain
1.0
A
(GAIN1)
B
(GAIN3)
0
C
-1.0
(GAIN2)
t
Soft Attenuate
MITSUBISHI
ELECTRIC
19
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
2. System1 Mode (Primary side).
bit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Flag Name
MODE1
MODE2
IFMT0
IFMT1
IBIT0
IBIT1
ISF0
ISF1
EMPFS1
EMPFS2
DF1IMUTE
DF2IMUTE
ASYNCEN1
Functional Explanation
Mode Setting 1
Mode Setting 2
H
L
"L" fixed
"H" fixed
Input Format Selection
Refer to Table 2-1.
Setting for Input Word Length
Refer to Table 2-2.
Input Sampling Rate Selection
Refer to Table 2-3.
Fs selection for De-emphasis Filter
Refer to Table 2-4.
Zero Mute of DATA input
Zero Mute at rate converter input
Active
Active
Asynchronous Detection Flag for Primary Side
Non-active
Non-active
don't care
don't care
don't care
enable
disable
INIT
L
L
L
L
L
L
L
L
L
L
L
Table 2-1. Input Format
bit
3
4
Flag Name
IFMT0
IFMT1
MSB First Left
Justified
L
L
MSB First Right
Justified
H
L
LSB First Right
Justified
L
H
I2S
H
H
Table 2-2. Setting for Input Data Word Length
bit
Flag Name
16bit
20bit
24bit Don't use
5
IBIT0
L
L
H
H
6
IBIT1
L
H
L
H
Table 2-3. Input Sampling Rate Selection (Fs:32k-48kHz, 2Fs:64k-96kHz, and 4Fs:128k-192kHz)
bit
7
8
Flag Name
ISF0
ISF1
Fs
L
L
2Fs
H
L
4Fs
L
H
Don`t use
H
H
Table 2-4. Fs Selection for De-emphasis filter (De-emphasis is "ON" except for bit9=L and bit10=L)
bit
9
10
Flag Name
EMPFS1
EMPFS2
32.0K
H
H
44.1K
L
H
48.0K
H
L
OFF
L
L
MITSUBISHI
ELECTRIC
20
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
♦Input Format Selection (bit3,bit4:IFMT0,IFMT1).
Input Format Selection function is effective only condition of `Normal` mode.
Otherwise, Input Format Selection function is ineffective under conditions of `External Rate Converter 8fs `
and `SACD` modes(Interlocked with MODE1 and MODE2 pins).
Detail setting of `External Rate Converter 8fs` and `SACD` modes are shown in Page14 and Page15 .
♦Setting of Input Word Length (bit5,bit6:IBIT0,IBIT1).
Refer to Table 2-2.
Setting of Input Data Word Length is effective only MSB First Right Justified.
♦Input Sampling Rate Selection (bit7,bit8:ISF0,ISF1).
Refer to Table 2-3.
♦Fs Selection for De-emphasis Filter on/off (bit9, bit10 : EMPFS1, EMPFS2).
Refer to Table 2-4.
(bit9,bit10):
(L,L)…
De-emphasis Filter is "off".
except (L,L)…De-emphasis Filter on (Fs setting).
♦Zero Mute at data input (bit11: DF1IMUTE).
DF1IMUTE : "L"…Mute release.
"H"…Mute.
The input data from DATA pin in normal mode is muted in this setting.
♦Zero Mute at Sampling Rate Converter Input (bit12: DF2IMUTE).
DF2IMUTE : "L"…Mute release.
"H"…Mute.
DF2IMUTE is effective for rate converter input data.
DF2IMUTE executes zero mute of input data from DATA pin under condition of `Normal` mode and
from DSDL /DSDR pins under condition of `SACD-fsi` mode.
♦"Enable" of Primary Side Asynchronous Detection Flag (bit16: ASYNCEN1).
Bit16 controls "enable"/"disable" of primary-side-asynchronous-detection-circuit.
ASYNCEN1 : "L"…disable.
"H"…enable.
Under condition of ASYNCEN1="L", primary side asynchronous detection is ineffective whether the clock is
not inputted to FsiI pin, thereby M65817AFP does not operate function under asynchronization, for instance mute
operation. However, Primary Side Asynchronous Detection is effective only condition of `SACD-Fsi ` mode.
MITSUBISHI
ELECTRIC
21
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
3. System2 Mode (Secondary side).
bit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Flag name
Functional Explanation
MODE1
Mode setting1
MODE2
Mode setting2
IMCKSEL
Input Master Clock Selection
DSDFCO0
Filter Coefficient of Down Sampling
DSDFCO1
SYNC
Resynchronization
XFsoOEN
XfsoOUT pin output "enable"
ASYNCEN2 Asyncronous Detection Flag for secondary Side
CHSEL
L / R inversion of PWM output
DRPOL
∆Σ Block: Rch Input Phase
SRCRST
Sampling Rate Converter Reset
GIMUTE
NSPMUTE
PGMUTE
NSSPEED
NSOBIT
DCDRPOL
DCDSEL0
DSDSEL1
ACDRPOL
ACDSEL0
ACDSEL1
ACDSEL2
Table 3-1
bit
4
5
bit
19
20
bit
22
23
24
"L" fixed
256Fs
512Fs
Refer to Table 6-3-1.
Zero Mute at Gain Control Input Clock
Duty 50 percent Mute of PWM Output
G_MUTE of PWM Output Data
∆Σ Block: Operation Speed
∆Σ Block: Setting of Output Bit Number
∆Σ Block: Rch Phase of DC dithering
∆Σ Block: DC dithering Selection
Refer to 6-3-2
∆Σ Block: Rch Phase of AC dithering
Negative-phase
∆Σ Block: AC dithering selection
Positive-phase
Refer to 6-3-3
INIT
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Setting of Down Sampling Filter Coefficient
ROM1 ROM2 ROM3 ROM4
L
H
L
H
L
L
H
H
DC dithering Selection at ∆Σ Block
Flag Name
DCDSEL0
DCDSEL1
Table 3-3
L
L->H : Resynchronization.
disable
enable
enable
disable
active
non-active
Negative-phase
Positive-phase
Active
Non-active
don't care
Active
Non-active
Active
Non-active
Active
Non-active
"L" fixed
5 bits (31 value)
6 bits (63 value)
Negative-phase
Positive-phase
Flag Name
DSDFCO0
DSDFCO1
Table 3-2
H
"H" fixed
Non-dithering
L
L
DC dithering
H
L
DC dithering
L
H
DC
H
H
AC dithering Selection at ∆Σ Block
Flag Name
ACDSEL0
ACDSEL1
ACDSEL2
Non-dithering
don't care
L
L
AC dithering A
L
H
L
AC dithering C
L
L
H
AC dithering E
L
H
H
•Input Master Clock Selection (bit3:IMCKSEL).
"L":256Fs
"H":512Fs
•Selection of of Down Sampling Filter Coefficient for SACD input (bi4,bit5: DSDFCO0,DSDFCO1) .
Refer to Table 6-3-1.
•Resynchronization (bit6: SYNC).
Resynchronization function is same at SYNC pin's function. Refer to Operation Explanation, Chapter 5-1.10 .
Resynchronization process starts by SYNC rise edge,
therefore SYNC level must be fixed to "L"just before SYNC operation .
•"Enable" of XfsoOUT pin Output(bit7: XfsoOEN).
"L": Clock Output (enable), "H": L fixed (disable)
MITSUBISHI
ELECTRIC
22
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
•Flag to "Enable" Asynchronous Detection for Secondary Block (bit8: ASYNCEN2).
ASYNCEN2 :
"L"…disable.
"H"…enable.
Under condition of ASYNCEN2="L", secondary side asynchronous detection is ineffective whether FsiI Clock is not
inputted, there by M65817AFP does not operate function under asynchronous position, for instance mute operation.
•PWM Output Pins L/R Reverse.(bit9: CHSEL).
"L": L/R no reverse, "H": L/R reverse.
•∆Σ: Rch Input Phase (bit10: DRPOL).
"L": Positive Phase(Through).
"H": This setting makes ∆Σ Rch input in reverse, further makes PWM block input phase reverse,
ultimately phase becomes Positive Phase(Input pin and output pin's phase is same).
•Rate Converter Block Reset (Initialize function) (bit11: SRCRST).
SRCRST: "L"…normal operation .
"H”>>"L" edge…Reset(initialize function).
•Zero Mute of Gain Control Input (bit13: GIMUTE).
GIMUTE: "L"…Mute release,
"H"…Mute.
•Duty 50% Mute of PWM Output (bit14: NSPMUTE).
NSPMUTE: "L"…Mute release.
"H"…PWM output duty 50 % mute.
This function is able to do NSPMUTE pin (39 pin), too. (This Mute function can be set either NSPMUTE register
or NSPMUTE pin.)
•PWM Output Data G_MUTE. (bit15: PGMUTE).
Under condition of G_MUTE flag ="H", each PWM outputs are fixed below.
OUTL1+ and OUTR1+ = "L", OUTL2+ and OUTR2+ = "L”
OUTL1- and OUTR1- = "H", OUTL2- and OUTR2- = "H"
"L"…Mute release, "H"…Mute.
PGMUTE function exists at PGMUTE pin (39 pin), too(PGMUTE function and PGMUTE pin are same function.
This Mute function can be set either NSPMUTE function or NSPMUTE pin.)
•∆Σ Block : Operation RATE (bit16: NSSPEED).
NSSPEED: "L” fixed
NSSPEED function becomes 16Fs fixed.
• ∆Σ Block : Output Bit Number Setting (bit17: NSOBIT).
Bit17 selects bit numbers of ∆Σ Block .
NSOBIT: "L"…6bits(63 values).
"H"…5bits(31values).
(At MCKSEL="H", bit numbers of ∆Σ Block become 5bits(31values) fixed.
•∆Σ Block: DC dithering Rch Phase (bit18: DCDRPOL).
DCDRPOL: "L"…In phase (toward the left channel).
"H"…Out of phase.
•∆Σ Block: DC dithering Selection (bit19,bit20: DCDSEL0,DCDSEL1).
Refer to Table 3-2.
•∆Σ Block: AC dithering Rch Phase (bit21: ACDRPOL).
ACDRPOL: "L"…In phase (toward the left channel).
"H"…Out of phase.
•∆Σ Block: AC dithering Selection (bit22,bit23,bit24: ACDSEL0,ACDSEL1,ACDSEL2).
Refer to Table 3-3.
MITSUBISHI
ELECTRIC
23
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
TIMING CHARACTERISTIC
1. AC Characteristics Lists.
(Ta=25ºC, PWM Vdd=5V, DVdd=3.3V)
Parameter
XfsoIN duty ratio
XfsiIN duty ratio
SCSHIFT pulse time
SCDT setup time
SCDT hold time
SCLATCH pulse width
SCLATCH setup time
SCLATCH hold time
BCK pulse width
DATA setup time
DATA hold time
LRCK setup time
LRCK hold time
EXBCK pulse time
EXWCK setup time
EXWCK hold time
EXDATA L / R setup time
EXDATA L / R hold time
EXDATA L / R output delay time
EXWCK output delay time
DSD128fs pulse width
DSD64fs pulse width
DSD L / R setup time
DSD L / R hold time
SYNC pulse width
Symbol
duty(XfsoIN)
duty(XfsiIN)
tw(SCSHIFT)
tsu(SCDT)
th(SCDT)
tw(SCLATCH)
tsu(SCLATCH)
th(SCLATCH)
tw(BCK)
tsu(DATA)
th(DATA)
tsu(LRCK)
th(LRCK)
tw(EXBCK)
tsu(EXWCK)
th(EXWCK)
tsu(EXDATA)
th(EXDATA)
tpd(EXDATA)
tpd(EXWCK)
tw(DSDCK)
tw(DSDCK)
tsu(DATA)
th(DATA)
tw(SYNC)
Conditions
512fs
256fs
Min.
Typ.
Max.
40
30
40
160
80
80
160
160
160
35
20
20
20
20
35
20
20
20
20
50
50
50
60
70
60
1.0
1.0
Output load capacity 10 [pF]
Output load capacity 10 [pF]
mode 1, 2, 3 and 4
mode 1, 2, 3 and 4
MITSUBISHI
ELECTRIC
70
140
40
40
160
Unit
%
%
%
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
24
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
2. AC Characteristics Timing Chart.
(1) XfsoIN, XfsiIN Duty Ratio
twhl
twh
twl
duty (XfsoIN,XfiIN) =
twh
twhl
(2) SCSHIFT, SCDT, SCLATCH input timing
tw(SCSHIFT)
tw(SCSHIFT)
SCSHIFT
th(SCDT)
tsu(SCDT)
SCDT
tw(SCLATCH)
SCLATCH
tsu(SCLATCH)
th(SCLATCH)
(3) BCK, DATA, and LRCK Input timing
tw(BCK)
tw(BCK)
BCK
th(DATA)
DATA
th(LRCK)
tsu(DATA)
tsu(LRCK)
LRCK
(4) EXBCK, EXDATAL, EXDATAR, EXWCK input timing
tw(EXBCK)
tw(EXBCK)
EXBCK
th(EXDATA)
tsu(EXDATA)
EXDATAL
EXDATAR
th(EXWCK)
tsu(EXWCK)
EXWCK
(5) EXBCK, EXDATAL, EXDATAR, EXWCK output timing
tw(EXBCK)
tw(EXBCK)
EXBCK
EXDATAL
EXDATAR
tpd(EXDATA)
tpd(EXWCK)
EXWCK
MITSUBISHI
ELECTRIC
25
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
(6) DSD64fs, DSD128fs, DSDL, DSDR input timing
♦mode1
tw(DSDCK)
tw(DSDCK)
DSD128fs
th(DATA)
tsu(DATA)
DSDL
DSDR
♦mode2
tw(DSDCK)
tw(DSDCK)
DSD64fs
th(DATA)
tsu(DATA)
DSDL
DSDR
♦mode3
tw(DSDCK)
tw(DSDCK)
DSD128fs
th(DATA)
tsu(DATA)
DSDL
DSDR
♦mode4
tw(DSDCK)
tw(DSDCK)
th(DATA)
tsu(DATA)
DSD64fs
DSDL
DSDR
(7) SYNC input timing
tw(SYNC)
SYNC
MITSUBISHI
ELECTRIC
26
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
DETAILED DIAGRAM OF PACKAGE OUTLINE
MMP
80P6N-A
EIAJ Package Code
QFP80-P-1420-0.80
Plastic 80pin 145 20mm body QFP
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
65
b2
80
ME
HD
D
1
64
I2
24
Symbol
HE
E
Recommended Mount Pad
41
25
A
40
c
A2
L1
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
y
b
x
M
A1
F
e
L
Detail F
MITSUBISHI
ELECTRIC
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
3.05
–
–
0.1
0.2
0
2.8
–
–
0.3
0.35
0.45
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
0.8
–
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
–
–
0.2
0.1
–
–
0°
10°
–
0.5
–
–
1.3
–
–
14.6
–
–
20.6
–
–
27
MITSUBISHI SOUND PROCESSOR ICs
M65817AFP
Digital Amplifier Processor of S-Master* Technology
Keep safety first in your circuit designs!
lMitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more
reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may
lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your
circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
lThese materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
lMitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s
rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application
examples contained in these materials.
lAll information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are subject to
change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric
Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or
errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means,
including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
lWhen using any or all of the information contained in these materials, including product data, diagrams, charts,
programs, and algorithms, please be sure to evaluate all information as a total system before making a final
decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no
responsibility for any damage, liability or other loss resulting from the information contained herein.
lMitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system
that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular,
medical, aerospace, nuclear, or undersea repeater use.
lThe prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in
part these materials.
lIf these products or technologies are subject to the Japanese export control restrictions, they must be exported
under a license from the Japanese government and cannot be imported into a country other than the approved
destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of
destination is prohibited.
lPlease contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor
for further details on these materials or the products contained therein.
MITSUBISHI
ELECTRIC
28