HD74LS192 Synchronous Up / Down Decade Counter (dual clock lines) REJ03D0454–0200 Rev.2.00 Feb.18.2005 Synchronous operation is provided by having all flip-flops clocked simultaneously so that the output change coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is high. This counter is fully programmable; that is, each output may be preset to either level by desired data at the data inputs while the load inputs is low. The output will change to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements. This reduces the number of clock drivers, etc., required for long words. This counter was designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up-and downcounting functions. The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count up input when an overflow condition exists. The counters can be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of .the succeeding counter. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS192P DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74LS192FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Rev.2.00, Feb.18.2005, page 1 of 10 HD74LS192 Pin Arrangement Data B Input 1 QB 2 QB QA 3 QA Count Down Count Up QC 6 QC QD 7 QD GND 8 16 VCC A 15 Data A Clear 14 Clear 4 Count Borrow Down 13 Borrow 5 Count Up Carry 12 Carry Load 11 Load C 10 Data C 9 Data D B Outputs Inputs Inputs Outputs Outputs D (Top view) Rev.2.00, Feb.18.2005, page 2 of 10 Inputs HD74LS192 Block Diagram Borrow Output Carry Output Data Input A QA Down Count Output QA T QA Up Count Data Input B QB Output QB T QB Data Input C QC Output QC T QC Data Input D Clear QD Output QD T QD Load Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC 7 V Input voltage VIN 7 V PT 400 mW Tstg –65 to +150 °C Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Rev.2.00, Feb.18.2005, page 3 of 10 HD74LS192 Recommended Operating Conditions Item Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Operating temperature Topr –20 25 75 °C Clock frequency ƒclock 0 — 25 MHz tw 20 — — ns tsu (CLR) 40 — — ns Setup time tsu 20 — — ns Hold time th 3 — — ns Supply voltage Output current Pulse width Setup time (Clear) Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V II — — — — — — — — — — 0.4 0.5 20 –0.4 0.1 µA mA mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V IOS –20 — –100 mA VCC = 5.25 V ICC VIK — — 19 — 34 –1.5 mA V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Output voltage VOL Input current Short-circuit output current Supply current** Input clamp voltage IIH IIL V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA Notes: * VCC = 5 V, Ta = 25°C ** ICC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol ƒmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Rev.2.00, Feb.18.2005, page 4 of 10 Inputs Outputs Count-up Carry Count-down Borrow Either Count Q Load Q Clear Q min. 25 — — — — — — — typ. 32 17 18 16 15 27 30 24 max. — 26 24 24 24 38 47 40 — — 25 23 40 35 Unit MHz Condition ns ns ns ns ns CL = 15 pF, RL = 2 kΩ HD74LS192 Count Sequence Clear Load A Data Inputs B C D Count Up Count Down QA QB QC QD Carry Borrow Sequence Illustrated 8 0 7 Clear Preset Rev.2.00, Feb.18.2005, page 5 of 10 9 0 1 Count Up 2 1 0 9 8 Count Down 7 HD74LS192 Testing Method Test Circuit VCC Output 4.5V RL Load circuit 1 Borrow CL Up Output Down See Waveforms Input P.G. Zout = 50Ω Carry A Same as Load Circuit 1. Output B QA C Same as Load Circuit 1. Output D QB Same as Load Circuit 1. Output Load Clear QC Same as Load Circuit 1. Output QD Notes: Same as Load Circuit 1. 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Testing Table Item From input to output ƒmax tPLH tPHL Up Count Down Count Load→Q Clear→Q CLR GND GND GND GND GND IN Load 4.5V 4.5V 4.5V 4.5V IN IN* Up IN 4.5V IN 4.5V GND GND Inputs Down A 4.5V GND IN GND 4.5V GND IN GND GND IN GND 4.5V B GND GND GND GND IN 4.5V C GND GND GND GND IN 4.5V D GND GND GND GND IN 4.5V Note: *. For initialized Item From input to output ƒmax tPLH tPHL Up Count Down Count Load→Q Clear→Q Rev.2.00, Feb.18.2005, page 6 of 10 Outputs QA QB QC QD Carry Borrow OUT OUT OUT OUT OUT — OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT — OUT — — — OUT — OUT — — HD74LS192 Waveforms 1 ƒmax, tPLH, tPHL, (Count Up) tTLH Count Up 10% tTHL 90% 90% 1.3V 1.3V 10% tw (H) tw (L) tPLH QA (Measure at tn + 1) 3V 1.3V 1.3V 0V tPHL (Measure at tn + 2) VOH 1.3V tPHL (Measure at tn + 4) QB tPLH (Measure at tn + 2) VOL VOH 1.3V 1.3V VOL Outputs QC tPHL (Measure at tn + 8) 1.3V tPLH (Measure at tn + 4) tPHL (Measure at tn + 10) tPLH (Measure at tn + 8) VOH 1.3V VOL QD 1.3V VOH 1.3V VOL (Measure before 1 clock of tn + 10) tPHL tPLH (Measure at tn + 10) VOH Carry 1.3V 1.3V VOL Notes: 1. Input pulse; tTLH, tTHL ≤ 7 ns, PRR = 500 kHz (Data input). PRR = 1 MHz (except data input) Duty cycle = 50% 2. for ƒmax tTLH, tTHL ≤ 2.5 ns. 3. tn is reference bit time when all outputs are low. Rev.2.00, Feb.18.2005, page 7 of 10 HD74LS192 Waveforms 2 ƒmax, tPLH, tPHL, (Count Down) tTLH tTHL tw (H) tw (L) 3V Count Down 90% 90% 1.3V 1.3V 1.3V 1.3V 1.3V 0V 10% 10% tPLH (Measure (Measure at tn + 1) tPHL at tn + 0) VOH QA 1.3V 1.3V 1.3V VOL tPHL (Measure at tn + 4) tPLH (Measure at tn + 2) QB 1.3V VOH 1.3V VOL tPHL (Measure at tn + 6) Outputs tPLH (Measure at tn + 2) QC 1.3V tPHL (Measure at tn + 2) 1.3V VOH VOL tPLH (Measure at tn + 0) VOH QD 1.3V 1.3V VOL t (Measure before 1 clock of tn + 0) PHL tPLH (Measure at tn + 0) VOH Borrow 1.3V 1.3V VOL Notes: 1. for ƒmax tTLH , tTHL ≤ 2.5 ns. 2. tn is reference bit time when all outputs are high. Rev.2.00, Feb.18.2005, page 8 of 10 HD74LS192 Waveforms 3 tPLH, tPHL, (Load, Clear→Q) tTLH tTHL 3V Clear 10% 90% 90% 1.3V 1.3V 10% 0V tTLH tw (CLR) ≥ 20ns Data Inputs (A to D) tTHL 3V 10% 90% 1.3V 90% 1.3V tsu th 10% tsu tTHL 90% 1.3V Load tPHL 0V 3V 90% 1.3V 10% 10% tTLH tPLH 1.3V 1.3V 0V tPHL VOH Q 1.3V 1.3V 1.3V VOL Note: Input pulse: tTLH ≤ 7 ns, tTHL ≤ 7 ns Rev.2.00, Feb.18.2005, page 9 of 10 HD74LS192 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.2.00, Feb.18.2005, page 10 of 10 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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