APW8703/6/7 High-Performance, High-Current DrMOS Power Module Features General Description • 4.5V ~ 5.5V Input Range for VCC & PVCC • 4.5V ~ 25V Input Range for VIN • Power-On-Reset Monitoring on VCC Pin • APW8703-Up to 10A (peak), 8A (continuous) output The APW8703/6/7 integrates a high-side N-channel MOSFET and a low-side N-channel MOSFET with adaptive dead-time control. The APW8703/6/7 have a built-in tri-state PWM input function which can support a number of PWM controllers. When the PWM input signal stays tri- current scale • APW8706-Up to 8A (peak), 6A (continuous) output state, the tri-state function shuts off the high-side MOSFET and turns on the low-side MOSFET without consider ZC current scale • APW8707-Up to 25A (peak), 13A (continuous) function. The device is also equipped with Power-OnReset(POR) and enable control functions into a single output current scale • Adjustable Over-Current Protection Threshold • Up to 1.5MHz PWM operation • Built-in Tri-State PWM input Function • Built in EN Timing Control function • Build in N-CH MOSFET for high side, N-CH MOSFET package and accurate current limit. The device over-current protection monitors the output current by using the voltage drop across the RDS(ON) of low-side MOSFET, eliminating the need for a current sensing resistor that features high efficiency and low cost. The POR circuit with hysteresis monitors VCC supply voltage to start up/shut- for low side • Skip Mode Operation • down the IC at power-on/off. The APW8703/6/7 also can be enabled or disabled by other power system. Pulling Over-Temperature Protection the EN pin high or low will turn on or shut off the device. • TQFN 4x4-23P package and TQFN 5x5-30 packages • Applications Lead Free and Green Devices Available (RoHS Compliant) • • Desktops • Severs • Portable/Notebook Regulators Graphics Cards Simplified Application Circuit VCC C VCC 1uF VIN VCC VIN PVCC CIN APW8703 APW8706 APW8707 VCC L VOUT LX PWM CONTROLLER PWM COUT EN AGND PGND ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 1 www.anpec.com.tw APW8703/6/7 Ordering and Marking Information Package Code APW8703 APW8706 APW8707 QB : TQFN 4x4-23 QB : TQFN 5x5-30 Operating Ambient Temperature Range I : -40 to 85oC Assembly Material Handling Code Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device Temperature Range Package Code APW8703 QB: APW8703 XXXXX X - Date Code APW8706 QB: APW8706 XXXXX X - Date Code APW8707 QB: APW8707 XXXXX X - Date Code Note:ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). 26 LX 27 LX PGND 28 LX NC AGND 29 BOOT VCC 19 PGND 30 25 24 23 18 LX 20 BST 21 PVCC 22 VIN 23 VCC Pin Configuration OCSET 1 OCSET 1 17 LX 25 24 OCB 2 OCB 2 16 LX EN 3 AGND 4 SMOD 4 14 PGND SMOD 5 AGND 5 13 PGND PWM 6 12 PGND LX 21 LX 33 AGND EN 3 15 PGND VIN 22 LX 31 20 LX 19 PGND LX 18 PGND 17 PGND 32 PWM 6 16 PGND VIN 12 13 14 PGND 11 PGND 10 PGND 9 VIN = Exposed and Thermal Pad 8 VIN (TOP VIEW) VIN LX 11 15 PGND VIN TQFN 4x4-23 LX 10 VIN 9 VIN 8 NC 7 NC 7 TQFN5x5-30 (TOP VIEW) APW8703/6 = Exposed and Thermal Pad APW8707 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 2 www.anpec.com.tw APW8703/6/7 Absolute Maximum Ratings (Note 1) Symbol VCC & VPVCC VIN Parameter VCC & PVCC to GND Voltage VIN to PGND Voltage LX to PGND Voltage VLX >20ns Pulse Width <20ns Pulse Width VBST V BST-V LX Other Pins BST to GND Voltage BST to LX Voltage EN,SMOD, OCSET and PWM to AGND Voltage AGND to PGND Voltage Rating Unit -0.3 ~ 7 V -0.3 ~ 30 V -0.3 ~ 30 V -5 ~ 38 -0.3 ~ 37 V -0.3 ~ 7 V -0.3 ~ VCC+0.3 V -0.3 ~0.3 V TJ Junction Temperature 150 o TSTG Storage Temperature -65 ~ 150 o TSDR Maximum Lead Soldering Temperature(10 Seconds) 300 o C C C Note1: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Junction-to-Ambient Resistance in free air Typical Value (Note 2) TQFN4x4-23 50 TQFN5x5-30 25 Unit o C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol V CC&PVCC V IN Pa ra mete r Range Unit V CC an d P VCC to A GND Voltage 4.5 ~ 5.5 V V IN to P GND Voltage 4 .5 ~ 2 5 V APW8 703 8 A APW8 706 6 A APW8 707 13 A APW8 703 10 A APW8 706 8 A Ma ximum Continu ous Output Cu rrent I OUT Ma ximum Pe ak O utp ut Curr ent APW8 707 F PWM TA TJ 25 A P WM O peratio n Freq uency 0.1 ~ 1.5 MHz A mbien t Tem perature -4 0 ~ 85 o - 40 ~ 125 o Ju nction Tempe rature C C Note 3: Refer to the typical application circuit. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 3 www.anpec.com.tw APW8703/6/7 Electrical Characteristics Unless otherwise specified, these specifications apply over VCC = VPVCC = VEN = 5V, VIN =12V and TA = 25oC. Pa ramete r AP W8703 /6 /7 Test Conditions Min Typ Ma x Unit - 90 120 uA - 60 90 uA - - 1.0 uA VCC Rising PO R Thresold 3 .7 4.0 4.3 V VCC POR Hyster esis 50 1 00 150 mV APW870 3 - 25 - APW870 6 - 30 - APW870 7 - 9.7 - APW870 3 - 7 - SUPPLY CURRE NT I VCC VCC Su pply Current EN = High , PWM = High, SMOD=L EN = High , PWM = Low, SMOD=L EN = L ow POWER- ON-RESET(POR) POWER STAGE R ON_H RON_ L I LX Hig h-side swi tch on resistance L ow-side swi tch on resista nce APW870 6 - 12 5.2 - mΩ mΩ APW870 7 - L X Leakag e Cu rrent V IN = V CC = LX = 25V, EN = GND -1 - 1 uA VIN Pin L eakage Curre nt EN = L ow, V IN=25V - - 1 uA BOOT Pin Curre nt V BOOT-PGND=30V, VLX=25V - - 1 uA V LX - P GND -5 - 5 mV 9 10 11 µA mV ZERO CURRENT DETECT VZC Zer o Cu rrent De te ct Over-Curre nt Protec tion(OCP) I OCSET OCSET Cu rrent Sour ce VOCP OCP Thre sh old - 1 90 - OCB Output Low Vo lta ge Sink Curr ent=5m A - 0.5 0.7 V OCB Leakag e Cu rrent V OC B=5V - - 1 uA OCB g o l ow - 0.6 - ms - 1 45 - o o tD(OCB) OCB De glitch TIm e Over-Tem perature Prot ection (OTP) TOTR OTP Rising Thresh old OTP Hyster esi s C - 45 - C V PWM Risin g 3 .6 3.9 4.1 V V PWM Falling 1 1.2 1.4 V PWM INPUT PIN V PWM VTRI PWM Inpu t Log ic Thresho ld Tri-state Inpu t Rising Log ic Threshol d V PWM Risin g 1 .0 1.3 1.6 V hysteresis 14 0 2 80 420 mV V PWM Falling 3 .4 3.7 4.0 V VTRI Tri-state Inpu t Fallin g L ogic Th resh old hysteresis 85 1 70 255 mV I PWM PWM P in input cu rrent Source/ Sink , VPWM = 0V to 5V -1 - 1 uA Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 4 www.anpec.com.tw APW8703/6/7 Electrical Characteristics Unless otherwise specified, these specifications apply over VDD=5V. Typical values are at TA=25oC. APW8 703/6/7 Parame ter Test Conditions EN INPUT AND SMO D Input EN/SMOD Input Logic High EN/SMOD Input Logic Low EN/SMOD Input Cu rrent V EN = 5V or VSMOD=5 V Unit Min Typ Ma x 2.0 - - V - - 0 .8 V -1 - 1 uA GATE DRIVE R TIM INGS (re fer t o Figure 1 and Table 1 ) t PDLU PW M to Hig h sid e Gate PW M H to L to GH H to L (Note4 ) - 18 - ns tPDL L PW M to Low sid e Gate PW M L to H to GL H to L (Note4 ) - 25 - ns tPD HU LS to HS Gate Deadtime G L H to L to GH L to H (No te 4) - 20 - ns t PDHL HS to LS Gate Deadtime G H H to L to GL L to H (No te 4) - 20 - ns Note4: Not tested in production. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 5 www.anpec.com.tw APW8703/6/7 PWM Operation Characteristics Tri-state Band PWM GH GL t PDLL tPDHU t PDHL t PDHU t PDHL t PDLL t PDLU tPDLU Figure 1 : Timing chart Table 1 : Truth table EN L H H H H H SMO D X L L X H H PWM X H L Tri-sta te H L Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 GH L H L L H L GL L L Skip mode H L H 6 www.anpec.com.tw APW8703/6/7 Pin Descriptions PIN NUMBER FUNCTION NAME APW8703/6 APW8707 1 1 OCSET 2 2 OCB 3 3 EN 4 5 SMOD Skip Mode Input. Pull SMOD high to enter diode emulation or skip mode. 5 4,29,31 AGND Signal Ground for The IC. All voltage levels are measured with respect to this pin. Tie this pin to the ground island/plane through the lowest impedance connection available. 6 6 PWM PWM Drive Logic Input. 7 7,28 NC No Connection. 8,9,22,24 8,9,10,11,32 VIN Supply Voltage Input Pin for Power Stage. 10,11,16,17, 20,21,22,23, 18,25 24,25,33 LX Junction Point of The High-side and Low-side MOSFET. Connect the output LC filter for PWM output voltage. 12,13,14,15, 12,13,14,15, 16,17,18,19, 19 26 PGND 20 27 BST 21 - PVCC 23 30 VCC Over-Current Setting Input. Connect a resistor to GND to set the OCP trip level. Fault Indication Pin. This pin goes low when a OCP condition is detected after a 1ms deglitch time. Enable Pin. Logic high enables the device. Logic low disables the device. The pin is not floating. Power ground. High-Side Gate Driver Power Input Pin. Connect a 0.1uF capacitor from BST to LX. Supply Voltage Input Pin for Low Side Gate Driver. Supply voltage Input Pin for Control Circuitry. Decoupling at least 1uF of a MLCC capacitor from the VCC pin to the AGND pin. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 7 www.anpec.com.tw APW8703/6/7 Block Diagram VCC PVCC (For APW8703/06) Power - On Reset BST VIN EN GH VCC PWM Controller Shoot Through Control Tri -State Input Circuit GH LX PVCC GL GL OCSET 10uA Zero Crossing Detect OCP + 115mV PGND LX + + LX Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 OCB SMOD 8 AGND www.anpec.com.tw APW8703/6/7 Typical Application Circuit VCC (Note5) C VCC 1uF R OCB 50kΩ VIN VCC VIN PVCC BST OCB VCC SMOD PWM CONTROLLER APW8703(Note6) APW8706(Note6) LX APW8707 C IN C BST 0.1u F L VOUT PWM COUT EN OCSET AGND PGND R OCSET Note 5: VCC voltage rail must be SYNC with PWM controller VCC voltage level. Note 6: PVCC pin is only for APW8703/06 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 9 www.anpec.com.tw APW8703/6/7 Function Description voltage on the VCC pin if at least one of the enable pins is set high. When the VCC supply voltage exceeds the The current limit circuit employs a "valley" current-sensing algorithm (See Figure 2). The APW8703/6/7 use the low-side MOSFET’s RDS(ON) of the synchronous rectifier as a current-sensing element. If the magnitude of the current-sense signal at LX pin is above the current-limit threshold, the PWM is not allowed to initiate a new cycle. The current-limit threshold is given by: rising POR threshold, the POR enables the device. The POR circuit has a hysteresis and a deglitch feature so ILIMIT=(190mV-ROCSET*10uA)/RON_L VCC Power-On-Reset (POR) A Power-On-Reset (POR) function is designed to prevent wrong logic controls when the VCC voltage is low. The POR function continually monitors the bias supply that it will typically ignore undershoot transients on the VCC pin. The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the sense resistance, inductor value, and input voltage. Enable Control Pulling the VEN above 2V will enable the driver output, and pulling VEN below 0.8V will disable the driver output. IPEAK INDUCTOR CURRENT If enable function is not used, connect EN to VCC for normal operation. PWM Control The PWM pin has three states. If the pin is gave high level state, the internal pre-driver output of high-side (GH) goes high and internal pre-driver output of low-side (GL) goes low. If the pin is gave low level state, the GH goes low and GL goes high. If the pin is gave tri-state level, the GH goes low and GL goes High. Please refer to Table 1. IOUT ILIMIT 0 SMOD APW8703/6/7 can be operated in the skip mode using ΔI Time Figure 2. Current Limit algorithm SMOD pin. When SMOD is low, the IC will enter the skip mode. In Skip mode if the PWM is low and the ZC is Over-Temperature Protection (OTP) When the junction temperature increases above the ris- detected, the GL will be pulled low, and low-side MOSFET will be off. It is useful if the converter has to operation in ing threshold temperature TOTR, the IC will enter the over temperature protection state that suspends the PWM, skip mode to improve efficiency at light load. When SMOD is high, the converter will operate in force PWM mode. which forces the UG and LG gate drivers output low. The thermal sensor allows the converters to start a start-up Over-current Protection (OCP) The over-current protection function protects the switch- process and regulate the output voltage again after the junction temperature cools by 45oC. The OTP designed ing converter to against over-current or short-circuit conditions. The IC senses the inductor current by detect- with a 45oC hysteresis lowers the average TJ during continuous thermal overload conditions, which increases life- ing the drain to source voltage of low-side MOSFET during it’s on-state. When the inductor current is over the time of the APW8703/6/7. internal OCP trip point, the both of gate drivers will be latched off. The APW8703/6/7 provide an open-drain output to indi- OCB Output cate that a fault has occurred. When current-limit occurs for a deglitch time of tD(OCB), the OCB goes low. Since the OCB pin is an open-drain output, connecting a resistor to a pull high voltage is necessary. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 10 www.anpec.com.tw APW8703/6/7 Layout Consideration For all switching power supplies, the layout is an important step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. The input capacitors should be placed close to the VIN pin, and the ground terminals of input capacitors and output capacitors should be close PGND pin. 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the LX pin to minimize the noise coupling into other circuits. 3. The traces of PWM signal from the PWM controller to the PWM pin of APW8703/6/7 should be short to eliminate the parasitical capacitance; the parasitical capacitance will cause an invalid PWM signal. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 11 www.anpec.com.tw APW8703/6/7 Package Information TQFN4x4-23 D b E A Pin 1 A1 A3 E1 NX aaa C L K E2 e Pin 1 Corner D1 D2 TQFN4x4-23 S Y M B O L A MIN. MAX. MIN. MAX. 0.70 0.80 0.028 0.032 A1 0.00 0.05 0.000 0.002 A3 MILLIMETERS 0.20 REF b 0.20 0.30 INCHES 0.008 REF 0.008 0.012 D 3.90 4.10 0.154 0.161 D1 2.58 2.78 0.102 0.109 D2 E 2.95 3.15 0.116 0.124 3.90 4.10 0.154 0.161 E1 1.24 1.44 0.049 0.057 E2 0.85 1.05 0.033 0.041 e L 0.50 BSC 0.35 0.45 0.020 BSC 0.014 0.018 K 0.20 0.008 aaa 0.08 0.003 Note : 1. Follow from JEDEC MO-229 WCCD-3. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 12 www.anpec.com.tw APW8703/6/7 Package Information TQFN5x5-30 A b E D Pin 1 K1 D1 A1 D2 A3 NX E1 aaa C E2 K1 Pin 1 Corner K L e D3 S Y M B O L A A1 TQFN5*5-30 MILLIMETERS INCHES MIN. MAX. MIN. MAX. 0.70 0.80 0.028 0.031 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.20 0.30 0.008 0.012 D 4.90 5.10 0.193 0.201 D1 2.12 2.32 0.083 0.091 D2 0.97 1.17 0.038 0.046 D3 3.56 3.76 0.140 0.148 E 4.90 5.10 0.193 0.201 E1 1.29 1.49 0.051 0.059 2.00 0.071 0.079 0.45 0.014 E2 1.80 e 0.50 BSC L 0.35 K 0.20 0.020 BSC 0.018 0.008 K1 0.37 REF 0.015 REF aaa 0.08 0.003 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 13 www.anpec.com.tw APW8703/6/7 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Applicat ion TQ FN4x 4 Applicat ion TQFN 5x5 A H 330.0±2.00 5 0 MIN. P0 P1 T1 12.4+2.00 -0.00 C 13.0+0.50 -0.20 P2 D0 4.00±0.10 8.00 ±0 .10 2.00 ±0 .05 1 .5 +0.10 -0.00 A H 330.0±2.00 5 0 MIN. T1 12.4+2.00 -0.00 C 13.0+0.50 -0.20 d D W E1 F 1.5 MIN. 20.2 MIN. 1 2.0±0.30 1.75 ±0 .1 0 5.50±0.10 D1 T A0 B0 K0 1.5 MIN. 0 .6 +0.00 -0 .40 4 .3 0±0.20 4.3 0±0.20 1.00±0.20 d D W E1 F 1.5 MIN. 20.2 MIN. 1 2.0±0.30 1.75 ±0 .1 0 5 .5 ±0 .10 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.10 1 .5 +0.10 -0.00 1.5 MIN. 0.6+0 .00 -0.40 5 .3 5±0.20 5.3 5±0.20 1.00±0.20 (mm) Devices Per Unit Pa ckage Type Unit Q uantit y TQFN4x4 Tape & Reel 300 0 TQ FN5x 5 Tape & Reel 250 0 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 14 www.anpec.com.tw APW8703/6/7 Taping Direction Information TQFN4x4-23 USER DIRECTION OF FEED TQFN5x5-30 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 15 www.anpec.com.tw APW8703/6/7 Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 16 www.anpec.com.tw APW8703/6/7 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 17 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW8703/6/7 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan, 2016 18 www.anpec.com.tw