CXA2055P Preamplifier for High Resolution Computer Display Description The CXA2055P is a bipolar IC developed for high resolution computer displays. Features • Built-in wide band amplifier (130 MHz/–3 dB typ.@4 Vp-p) • Input dynamic range : 1.0 Vp-p (typ.) • R, G and B in a single package • I2C bus control Contrast control Subcontrast control Brightness control OSD contrast control Power save function Input clamp pulse polarity selection Output composite sync polarity selection 5-channel, 8-bit D/A Blanking level control • Built-in sync separator (G channel only) • Built-in blanking mixing function • Built-in OSD mixing function • Built-in ABL function • Video interval detection function 28 pin DIP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC 14 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1794 mW (when mounted on a 11.5 cm × 12.0 cm substrate) Operating Conditions Recommended supply voltage VCC1 VCC2 12±0.5 5±0.25 V V 1 SDA VDET/COFF-RGB 28 2 SCL Applications High resolution computer displays DA/CSYNC/ABL 27 3 COFF-R 4 Structure Bipolar silicon monolithic IC R-S/H 26 COFF-G R-OUT 25 5 COFF-B GND-R 24 6 RIN G-S/H 23 7 VCC2 G-OUT 22 8 GIN GND-G 21 9 SYNC CON VCC1 20 10 BIN B-S/H 19 11 CLP B-OUT 18 12 OSD-R GND-B 17 13 OSD-G BLK 16 14 OSD-B YS 15 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E96Z18-TE CXA2055P SDA 1 D/A CONVERTER I2C BUS DECODER SCL BLANKING VDET LEVEL CUTOFF (R) CUTOFF (G) CUTOFF (B) 2 To each MODE switch COFF-R CUTOFF (RGB) CONTRAST SUB CONTRAST (R) SUB CONTRAST (G) SUB CONTRAST (B) OSD GAIN BRIGHTNESS (R) BRIGHTNESS (G) BRIGHTNESS (B) 3 28 VDET /COFF-RGB 27 DA /CSYNC /ABL 26 R-S/H 25 R-OUT 24 GND-R 23 G-S/H 22 G-OUT 21 GND-G 20 VCC1 19 B-S/H 18 B-OUT 17 GND-B 16 BLK 15 YS PINSW1 PINSW LOGIC PINSW0, 2 BRIGHTNESS (R, G, B) Rch COFF-G 4 SUB CONTRAST ABL (27PIN) CONTRAST COFF-B GAIN CONTROL DATA 5 GAIN CONTROL AMP RIN 6 BRIGHTNESS BLANKING BLANKING BUFFER AMP BLANKING PULSE OSD YS GENERATOR OSD GAIN OSD PULSE (12PIN) OSD LOGIC YS PULSE (15PIN) VCC2 7 5V GIN SYNC CON VDET, SYNC SEP 8 VDET LEVEL VDET COMPARATOR SYNC COMPARATOR SYNC POL 9 12V Gch BIN 10 Same as R channel CLP POL CLP 11 Bch OSD-R 12 to OSD LOGIC Same as R channel OSD-G 13 to OSD LOGIC OSD-B 14 to OSD LOGIC to OSD LOGIC —2— CXA2055P Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description VCC2 50µA 5k 4k 1 SDA — 1 10k 10k 7.5k I2C bus address and data input. 15k 7.5k GND VCC2 50µA 5k 4k 2 SCL — 2 10k 10k I2C bus clock signal input. 15k 10k GND 3 VCC2 COFF-R 100 D/A converter outputs. The variable range is 1 to 4 V. Use as cut-off control voltages is recommended. 60k 4 COFF-G — 3 4 50k 5 100 5 COFF-B 6 RIN 8 GIN GND VCC1 VCC2 — 6 1k 124 1k 5k 2k 8 2k 10 50µA 10 1mA BIN 1k R, G and B inputs. When clamped, the input voltage black level is approximately 3.2 V. Connect 0.1 µF or more in series as a clamp capacitor. GND 7 VCC2 5V 5 V power supply. —3— CXA2055P Pin No. Symbol Pin voltage Equivalent circuit Description VCC2 24k 9 70k 9 SYNC CON 10k 50µA 50µA Sync signal separation circuit block during sync-on-video signal input. Connect a sampleand-hold capacitor. 1k GND VCC1 22µA 30k 11 CLP — 11 1.3V Clamp pulse input. The polarity can be switched via the I2C bus. The threshold level is approximately 1.3 V. GND 12 VCC1 OSDR 150µA 13 OSDG — 124 12 1.25V 13 R, G and B OSD pulse inputs. The threshold level is approximately 1 V. 14 14 OSDB GND VCC1 150µA 15 YS — 124 15 1.25V OSD-BLK pulse input. The threshold level is approximately 1.7 V. GND VCC1 49k 16 BLK — BLK pulse input. The threshold level is approximately 1.5 V. 124 16 100µA GND —4— 1.5V CXA2055P Pin No. Symbol 17 GND-B 21 GND-G 24 GND-R 18 B-OUT 22 G-OUT Pin voltage Equivalent circuit Description 0V R, G and B independent GND. VCC1 18 — 200 R, G and B outputs. 22 25 25 R-OUT 19 B-S/H GND 1k 1k VCC1 1k 1k 23 G-S/H 19 — 23 Connection for external sampleand-hold capacitor (0.1 µF). 26 26 2.5V 225µA R-S/H GND 21 VCC1 12 V 12 V power supply. VCC2 5k 27 DA /CSYNC /ABL 100 100 4k 1V 50k 27 100k 7.4k GND VCC2 100 28 VDET /COF-RGB 5k — 28 100 100 GND —5— General-purpose D/A converter output. Composite sync output. TTL drive is possible. VL=0.5 V or less, VH=4.0 V or more RGB output amplitude gain compensation input. (common for all three channels) Function switching is performed via the I2C bus. Video signal detection output. VL=0.5 V or less, VH=4.0 V or more General-purpose D/A converter output. The variable range is 1 to 4 V. Function switching is performed via the I2C bus. CXA2055P Electrical Characteristics Measurement Circuit 1 SDA VDET/COFF-RGB 28 Video detector output DAC4 output 2 SCL Composite sync output DAC5 output I2C bus control DA/CSYNC/ABL 27 S2 3 COFF-R DAC1 output ABL input R-S/H 26 0.1µ DAC2 output 4 COFF-G R-OUT 25 5 COFF-B GND-R 24 Rch OUT DAC3 output 75 0.1µ 6 RIN G-S/H 23 0.1µ 0.1µ 5V 7 VCC2 G-OUT 22 8 GIN GND-G 21 10µ 0.1µ 75 0.01µ 9 SYNC CON VCC1 20 Gch OUT 12V 10µ 75 0.1µ 0.1µ 10 BIN B-S/H 19 0.1µ S1 11 CLP B-OUT 18 12 OSD-R GND-B 17 13 OSD-G BLK 16 14 OSD-B YS 15 —6— Bch OUT CXA2055P Electrical Characteristics Measurement Circuit (For AC Measurement) 1 SDA VDET/COFF-RGB 28 Video detector output DAC4 output DAC5 output 2 SCL Composite sync outpt ABL input I2C bus control DAC1 output DA/CSYNC/ABL 27 3 COFF-R R-S/H 26 4 COFF-G R-OUT 25 5 COFF-B GND-R 24 DAC2 output Rch OUT DAC3 output 50 0.1µ 6 RIN 5k 5V G-S/H 23 7 VCC2 G-OUT 22 8 GIN GND-G 21 10µ 50 Gch OUT 0.1µ 0.1µ 5k 9 SYNC CON VCC1 20 12V 10µ 0.01µ 50 0.1µ 10 BIN B-S/H 19 11 CLP B-OUT 18 12 OSD-R GND-B 17 13 OSD-G BLK 16 14 OSD-B YS 15 0.1µ 5k —7— Bch OUT CXA2055P Electrical Characteristics No. 1 Measurement item Current consumption Ta=25 °C VCC1=12 V VCC2=5 V Symbol ICC1 (12 V) Measurement contents S1 : GND, S2 : OFF Input signal : none ICC2 (5 V) Min. Typ. Max. Unit — 82 115 mA — 40 55 mA — –3.0 — dB 16.0 16.5 — dB 10.5 13.5 — dB Input continuous 1 MHz and 130 MHz sine waves at 0.7 Vp-p. Measure the output amplitude gain difference at this time. 2 Frequency response ( Gain difference [dB] =20log VOUT 130M VOUT 1M f 130 MHz ) RGB input signal (RGB input pins) 0.7Vp-p 0.35V CLP potential (approximately 3.2 V) GND S1 : Pulse, S2 : OFF Measure the output signal amplitude VOUT when a 0.7 Vp-p video signal is input. Calculate the contrast gain from this VOUT. 3 Contrast control CONTMAX [dB] =20log VOUT ( 0.7 CONTMAX ) RGB input signal 0.7Vp-p Either with or without sync-on-green (sync signal) S1 : Pulse, S2 : OFF Measure the variable width of the output signal amplitude VOUT when a 0.7 Vp-p video signal is input. Gain difference [dB]= 4 Subcontrast gain SUBgain CONTMAX [dB] –20log (V OUTSUBmin 0.7 RGB output signal SUBmax SUBmin Either with or without sync-on-green (sync signal) —8— ) CXA2055P No. Measurement item Symbol Measurement contents Min. Typ. Max. 3.4 3.7 — Unit S1 : Pulse, S2 : OFF BRTmax 5 CLP pulse width: 350 ns Measure the black level of the RGB output signal. RGB output signal Brightness control V BRTmin Black level — 0.5 0.7 0.9 1 1.2 Vp-p 200 — — nsec 4.0 5.0 — dB 1.7 1.9 — GND Either with or without sync-on-green (sync signal) S1 : Pulse, S2 : OFF 6 Input dynamic range Drang Measure the level at which the output gain can be secured when the input video signal level is varied. S1 : Pulse, S2 : OFF Measure the clamp pulse width over which the black level of the output signal VOUT 7 Minimum clamp pulse width does not change. CLPmin Video input Pulse width CLP pulse S1 : Pulse, S2 : OFF Measure the variable width of the output signal VOUT when a 0.7 Vp-p video signal is input. 8 OSD control range OSDcont Gain difference [dB] =20log ( OSDmax OSDmin ) OSD interval RGB output signal OSDmax OSDmin S1 : Pulse, S2 : OFF Measure the BLK level of the output signal BLKmax 9 when a 5.0 Vp-p BLK signal is input RGB output signal BLK control V BLKmin — VBLK GND —9— 0.1 0.4 CXA2055P (I2C BUS Logic System) No. Item Symbol Min. Typ. Max. Unit 1 High level input voltage VIH 3.0 — 5.0 V 2 Low level input voltage VIL 0 — 1.5 V 3 Low level output voltage SDA, during current inflow of 3 mA VOL 0 — 0.4 V 4 Maximum clock frequency fSCL 0 — 100 kHz 5 Minimum waiting time for data change tBUF 4.7 — — µs 6 Minimum waiting time for data transfer start tHD ; STA 4.0 — — µs 7 Low level clock pulse width tLOW 4.7 — — µs 8 High level clock pulse width tHIGH 4.0 — — µs 9 Minimum waiting time for start preparation tSU ; STA 4.7 — — µs 10 Minimum data hold time tHD ; DAT 5 — — µs 11 Minimum data preparation time tSU ; DAT 250 — — ns 12 Rise time tR — — 1000 ns 13 Fall time tF — — 300 ns 14 Minimum waiting time for stop preparation tSU ; STO 4.0 — — µs I2C BUS Control Signal 1 SDA tBUF tR 2 tF tHD;STA SCL P S tLOW tHD;STA tHD;DAT tHIGH tSU;DAT —10— tSU;STA Sr tSU;STO P CXA2055P 1. Application The CXA2055P is a preamplifier for computer displays, and combines three R, G and B channels into a single package. All controls such as the contrast and black level for each channel are performed via I2C bus control. 1) I2C bus Two wires (SDA, SCL) provide control over start, stop, data transfer, synchronization and collision avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR format. The bus signal configuration is as follows. SDA D A T A A MSB LSB D A MSB T A LSB SCL S P 1 2 3 4 5 6 7 8 9 1 2 3 9 START STOP S : Start condition; SDA is set at “low” when SCL is “high”. P : Stop condition; SDA is set at “high” when SCL is “high”. A : Acknowledge; Signal sent from the slave. Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave ∗1 IC receives data at the rising edge of SCL and the master ∗2 IC changes data at the falling edge of SCL. The actual data format is as follows. S Slave address 40H A Subaddress ∗∗H A DATA0 A DATA1 A DATA2 A P Slave address configuration BIT8 BIT7 BIT6 BIT5 BIT4 Slave address BIT3 BIT2 BIT1 R/W The slave address is an address unique to each IC, and is assigned according to the IC functions. The upper 7 of the 8 bits are the unique address and the final bit is the R/W bit. The R/W bit indicates read ∗3 when 1 and write ∗4 when 0. 40H is allotted as the slave address for the CXA2055P. (This is write only and there is no read mode.) The subaddress is the assigned address within the IC, and is used for the various IC adjustments. The subaddress is sent just once following the slave address, and is automatically incremented thereafter until a stop condition is sent. ∗1 Slave : An IC that is placed under the control of the master. In a normal system, all devices excluding the central microcomputer are slaves. ∗2 Master : A central microcomputer or other controlling IC. ∗3 Read : Mode where data is read from master to slave. ∗4 Write : Mode where data is written from master to slave. —11— CXA2055P 2) Register map • Slave address : 40H • “∗” indicates undefined. • Values inside parentheses ( ) are the initial setting values (during power-on reset) (undetermined when not indicated) Slave address configuration BIT8 0 BIT7 1 SUB ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH BIT6 0 BIT5 0 BIT7 BIT6 ∗ ∗ BLK (0) MODE BRT SW (0) ∗ SYNC POL (0) ∗ ∗ BIT4 0 BIT5 BIT3 0 BIT2 0 BIT1 R/W BIT4 BIT3 CONTRAST SUB CONTRAST R SUB CONTRAST G SUB CONTRAST B OSD GAIN BRIGHTNESS R (DA) BRIGHTNESS G BRIGHTNESS B CUT OFF RGB CUT OFF R CUT OFF G CUT OFF B BIT2 BIT1 BIT0 BRT MODE (2) BLANKING LEVEL (0) VDET POWER MODE (0) SAVE (0) ∗ ∗ —12— ∗ CLP (0) D/A TEST (0) PINSW2 (0) VDET LEVEL PINSW1 (0) PINSW0 (0) CXA2055P 3) Description of registers (Numbers inside parentheses ( ) indicate the number of bits.) CONTRAST (8) : Adjusts the R, G and B-OUT (Pins 25, 22 and 18) output amplitude gain commonly for all three channels. SUB CONTRAST (8) : Adjusts the R, G and B-OUT (Pins 25, 22 and 18) output amplitude gain independently for each channel. OSD GAIN (4) : Adjusts the OSD R, G and B (Pins 12, 13 and 14) OSD interval output signal gain commonly for all three channels. BRTMODE (2) : This register changes the output dynamic range. The 2H setting is recommended. 0H : Output dynamic range 0.5 V to 4.5 V 1H : Output dynamic range 0.5 V to 5.5 V 2H : Output dynamic range 1.0 V to 6.5 V (recommended) 3H : Output dynamic range 2.0 V to 7.5 V BRIGHTNESS (8) : Controls the output black level potential. (Three-channel independent and common control can be selected by BRTSW. During three-channel common mode, control is performed by the G channel.) CUT OFF (8) : This is a general-purpose DAC. Use as a cut-off control is recommended. BLK MODE (1) : Switches the blanking level mode 0H : BLK LEVEL=fixed 1H : BLK LEVEL=variable BLANKING LEVEL (6) : Sets the blanking level when BLK MODE is set to 1H. BRTSW (1) : Switches the brightness control between three-channel independent and three-channel common control. When using three-channel common mode, the BRIGHTNESS G channel is valid. 0H : Three-channel independent mode 1H : Three-channel common mode SYNC POL (1) : Switches the sync separator output polarity during sync-on-green input. 0H : Positive polarity 1H : Negative polarity VDET MODE (1) : Switches the video signal detection mode. 0H : B channel only is detected 1H : Signal obtained by adding R, G and B signals is detected POWER SAVE (1) : Power save mode selector switch. 0H : Power save not performed 1H : Power save performed —13— CXA2055P CLP (1) : Selects the input clamp pulse polarity. 0H : Positive polarity input 1H : Negative polarity input VDET LEVEL (2) : Threshold level selector switch for video interval detection. The threshold level changes as follows. (An input pulse width of as narrow as 10 ns can be detected.) When VDET MOD=0H When VDET MOD=1H 0H : 300 mV or more 0H : Undetectable 1H : Undetectable 1H : Undetectable 2H : Undetectable 2H : 300 mV or more 3H : Undetectable 3H : 600 mV or more Note) The threshold level when VDET MOD=1H is the total of the three channel inputs. D/A TEST (1) : DA TEST switch for IC measurement. Set to 0H. PINSW : Switches the Pins 27 and 28 functions. (“∗” indicates don’t care.) 2 0 1 0 1 ∗ ∗ PINSW 1 0 0 1 1 0 1 0 0 0 0 0 1 1 Pin 28 output Pin 27 output DA (COFF_RGB) DA (COFF_RGB) VDET VDET DA (COFF_RGB) VDET C-SYNC ABL (CONTRAST) C-SYNC ABL (CONTRAST) DA (BRIGHTNESS) DA (BRIGHTNESS) Note) When the Pin 27 output is set to DA (BRIGHTNESS), BRIGHTNESS is forcibly set to the three-channel common mode. —14— CXA2055P 2. Blanking addition function The output is blanked while the BLK pin (Pin 16) is high level. The BLK pin threshold level is approximately 1.5 V. 3. OSD addition function and OSD contrast control OSD can be added to the video signal while the OSD-R, G and B pins (Pins 12, 13 and 14) are high level. OSD blanking is added when any of these three channels is high level. OSD blanking is also added to all three channels while the YS pin (Pin 15) is high level. See the following logic. Ys Circuit (R, G, B) YS PULSE 1 : Active 0 : Passive from 15pin OSD PULSE (R) OSD Circuit (R) 1 : Active 0 : Passive from 12pin OSD PULSE (G) OSD Circuit (G) from 13pin 1 : Active 0 : Passive OSD PULSE (B) OSD Circuit (B) from 14pin 1 : Active 0 : Passive 4. CONTRAST function The CONTRAST function performs gain control for the R, G and B-OUT output amplitudes. 5. ABL function ABL control can be performed by Pin 27 by setting PINSW. The variable range is approximately 13.7 dB. See the characteristics diagrams hereafter for the control characteristics. —15— CXA2055P I/O Signal Example 0.7Vp-p (typ) Video In Clamp DC voltage Approximately 3.2 V GND tCLP ≥ 200nsec Clp Pulse Blanking Pulse Ys Pulse OSD Pulse Video Out C-Sync Out Vdet Out —16— CXA2055P Application Circuit DAC1 output DAC2 output DAC3 output Video detector output DAC4 output 1 SDA VDET/COFF-RGB 28 I2C bus control 2 SCL Composite sync output ABL input (0V to 4V) DAC5 output DA/CSYNC/ABL 27 3 COFF-R R-S/H 26 0.1µ Rch DISPLAY POWER AMP 4 COFF-G R-OUT 25 5 COFF-B GND-R 24 Rch to CRT cathode 0.1µ 6 RIN Rch video input G-S/H 23 0.1µ 75Ω 0.1µ 5V 7 VCC2 G-OUT 22 8 GIN GND-G 21 Gch to CRT cathode 10µ 0.1µ Gch DISPLAY POWER AMP Gch video input 75Ω 0.1µ 9 SYNC CON 12V VCC1 20 10µ 0.1µ Bch video input 0.1µ 10 BIN B-S/H 19 75Ω 0.1µ 11 CLP B-OUT 18 Rch OSD input 12 OSD-R GND-B 17 Gch OSD input 13 OSD-G BLK 16 Bch OSD input 14 OSD-B YS 15 Clamp pulse input Bch DISPLAY POWER AMP Bch to CRT cathode BLANKING pulse input YS input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —17— CXA2055P Notes on Board Pattern and Layout 1. When not using the OSD, YS or BLK pins, connect these pins to GND. 2. Care should be taken for the following items regarding the output signals from R, G and BOUT. 1) Connect these signal lines so that they are high impedance to external circuits. 2) Do not allow current to flow into the IC side. 3) Arrange the signal lines so that the distance to the power amplifier is as short as possible. 3. The VCC1 and VCC2 decoupling capacitors should consist of ceramic capacitors and electrolytic capacitors connected in parallel, and should be connected as close to the IC as possible. 4. The R, G and BIN clamp capacitors should be located as close to the IC as possible. 5. The sample-and-hold capacitors connected to the R, G and B-S/H pins should be connected as close to the IC as possible. 6. The output signals from COFF-R, G and B should be arranged so that capacitance of 20 pF or more is not applied to the pins or the pattern. —18— CXA2055P Contrast control characteristics, subcontrast control characteristics Input amplitude 700mVp-p ABL characteristics mVp-p mVp-p 5000 5000 4500 4500 4000 4000 3500 Output amplitude Output amplitude Subcontrast Control=FFH 3000 2500 2000 1500 3500 3000 2500 2000 1500 Subcontrast Control=7FH 1000 1000 500 500 Subcontrast Control=00H 0 0 32 64 V 0 96 128 160 192 224 0 1 2 BUS DATA 4 5 Control voltage Brightness control characteristics BLK control characteristics V mV 4.000 2000 3.500 1800 1600 3.000 Output BLK level Output black level 3 2.500 2.000 1.500 1.000 1400 1200 1000 800 600 400 0.500 200 0.000 0 32 64 0 96 128 160 192 224 0 BUS DATA mVp-p 6000 5500 5000 Subcontrast Control=FFH 4500 OSD interval output amplitude 4000 3500 3000 Subcontrast Control=7FH 2000 1500 1000 Subcontrast Control=00H 500 0 0 2 4 6 8 10 16 24 32 40 BUS DATA OSD control characteristics 2500 8 12 14 BUS DATA —19— 48 56 CXA2055P Unit : mm + 0.1 0.05 0.25 – 28PIN DIP (PLASTIC) + 0.4 37.8 – 0.1 1 + 0.3 13.0 – 0.1 15 15.24 28 0° to 15° 14 0.5 ± 0.1 1.2 ± 0.15 Two kinds of package surface: 1.All mat surface type. 2.Center part is mirror surface. + 0.4 4.6 – 0.1 0.5 MIN 2.54 3.0 MIN Package Outline PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE DIP-28P-03 LEAD TREATMENT SOLDER PLATING EIAJ CODE DIP028-P-0600 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 4.2g JEDEC CODE —20—