CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Features Functional Description ■ Supports bus operation up to 250 MHz The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F SRAM[1] integrates 512 K × 36/1 M × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth expansion chip enables (CE2 and CE3 [2]), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ■ Depth expansion without wait state ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 2.6 ns (for 250 MHz device) ■ Provides high performance 3-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium Interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed writes ■ Asynchronous output enable ■ CY7C1386D/CY7C1387D available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. CY7C1386F/CY7C1387F available in Pb-free and non Pb-free 119-ball BGA package ■ IEEE 1149.1 JTAG-compatible boundary scan ■ ZZ sleep mode option Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle.This part supports byte write operations (see on page 4 and Truth Table on page 11 for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F operates from a +3.3 V core power supply while all outputs operate with a +3.3 V or +2.5 V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum access time Description 2.6 3.0 3.4 ns Maximum operating current 350 300 275 mA Maximum CMOS standby current 70 70 70 mA Notes 1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com. 2. CE3 and CE2 are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in Single Chip Enable. Cypress Semiconductor Corporation Document Number: 38-05545 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 12, 2011 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Logic Block Diagram – CY7C1386D/CY7C1386F [3] (512 K × 36) ADDRESS REGISTER A0,A1,A 2 A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP BW D DQ D, DQP D BYTE WRITE REGISTER DQ D, DQP D BYTE WRITE DRIVER BW C DQ c ,DQP C BYTE WRITE REGISTER DQ c ,DQP C BYTE WRITE DRIVER DQ B ,DQP B BYTE WRITE REGISTER DQ B ,DQP B BYTE WRITE DRIVER BW B GW CE 1 CE 2 CE 3 OE ENABLE REGISTER ZZ SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQP A DQP B DQP C DQP D E DQ A, DQP A BYTE WRITE DRIVER DQ A, DQP A BYTE WRITE REGISTER BW A BWE MEMORY ARRAY INPUT REGISTERS PIPELINED ENABLE CONTROL Logic Block Diagram – CY7C1387D/CY7C1387F [3] (1 M × 18) A0, A1, A ADDRESS REGISTER 2 MODE ADV CLK A [1:0] Q1 BURST COUNTER AND CLR Q0 ADSC ADSP BW B BW A BWE CE 1 CE 2 CE 3 DQ B , DQP B BYTE DQ B, DQP B BYTE WRITE REGISTER DQ A, DQP A BYTE DQ A , DQP BYTE WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQ s, DQP A DQP B E INPUT REGISTERS OE SLEEP CONTROL Note 3. CY7C1386F and CY7C1387F have only 1 Chip Enable (CE1). Document Number: 38-05545 Rev. *H Page 2 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 7 Functional Overview ........................................................ 8 Single Read Accesses ................................................ 8 Single Write Accesses Initiated by ADSP ................... 9 Single Write Accesses Initiated by ADSC ................... 9 Burst Sequences ......................................................... 9 Sleep Mode ................................................................. 9 Interleaved Burst Address Table (MODE = Floating or VDD) ............................................... 10 Linear Burst Address Table (MODE = GND) ............. 10 ZZ Mode Electrical Characteristics ............................ 10 Truth Table ...................................................................... 11 Truth Table for Read/Write ............................................ 12 Truth Table for Read/Write ............................................ 12 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13 Disabling the JTAG Feature ...................................... 13 Test Access Port (TAP) ............................................. 13 PERFORMING A TAP RESET .................................. 13 TAP REGISTERS ...................................................... 13 TAP Instruction Set ................................................... 13 TAP Controller State Diagram ....................................... 15 TAP Controller Block Diagram ...................................... 15 TAP Timing Diagram ...................................................... 15 TAP AC Switching Characteristics ............................... 16 3.3 V TAP AC Test Conditions ....................................... 17 3.3 V TAP AC Output Load Equivalent ......................... 17 2.5 V TAP AC Test Conditions ....................................... 17 Document Number: 38-05545 Rev. *H 2.5 V TAP AC Output Load Equivalent ......................... 17 TAP DC Electrical Characteristics and Operating Conditions ..................................................... 17 Identification Register Definitions ................................ 18 Scan Register Sizes ....................................................... 18 Identification Codes ....................................................... 18 Boundary Scan Order .................................................... 19 Boundary Scan Order .................................................... 20 Maximum Ratings ........................................................... 21 Operating Range ............................................................. 21 Electrical Characteristics ............................................... 21 Capacitance .................................................................... 22 Thermal Resistance ........................................................ 22 AC Test Loads and Waveforms ..................................... 23 Switching Characteristics .............................................. 24 Switching Waveforms .................................................... 25 Ordering Information ...................................................... 29 Ordering Code Definitions ......................................... 29 Package Diagrams .......................................................... 30 Acronyms ........................................................................ 33 Document Conventions ................................................. 33 Units of Measure ....................................................... 33 Document History Page ................................................. 34 Sales, Solutions, and Legal Information ...................... 36 Worldwide Sales and Design Support ....................... 36 Products .................................................................... 36 PSoC Solutions ......................................................... 36 Page 3 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Configurations NC NC NC CY7C1387D (1 M × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC/72M NC/36M VSS VDD A A A A A A A A A DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CY7C1386D (512 K × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC/72M NC/36M VSS VDD A A A A A A A A A DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 1. 100-pin TQFP (3 Chip Enable) Document Number: 38-05545 Rev. *H A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC Page 4 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Configurations (continued) Figure 2. 119-ball BGA (1 Chip Enable) CY7C1386F (512 K × 36) A 1 VDDQ 2 A 3 A ADSP 4 5 A 6 A 7 VDDQ B C NC/288M NC/144M A A A A ADSC VDD A A A A NC/576M NC/1G D E DQC DQC DQPC DQC VSS VSS NC CE1 VSS VSS DQPB DQB DQB DQB F VDDQ DQC VSS OE VSS DQB VDDQ G H J K DQC DQC VDDQ DQD DQC DQC VDD DQD BWC VSS NC VSS ADV BWB VSS NC VSS DQB DQB VDD DQA DQB DQB VDDQ DQA BWA VSS DQA DQA DQA VDDQ GW VDD CLK L DQD DQD M VDDQ DQD BWD VSS N DQD DQD VSS BWE A1 NC VSS DQA DQA P DQD DQPD VSS A0 VSS DQPA DQA R NC A MODE VDD NC A NC T U NC VDDQ NC/72M TMS A TDI A TCK A TDO NC/36M NC ZZ VDDQ CY7C1387F (1 M × 18) 1 2 3 4 5 6 7 A VDDQ A ADSP A A VDDQ B NC/288M A A A A A NC/576M C NC/144M A A ADSC VDD A A NC/1G D DQB NC VSS NC VSS DQPA NC E NC DQB VSS CE1 VSS NC DQA OE ADV VSS DQA VDDQ GW VDD NC VSS NC NC DQA VDD DQA NC VDDQ F VDDQ NC VSS G H J NC DQB VDDQ DQB NC VDD BWB VSS NC K NC DQB VSS CLK VSS NC DQA L M DQB VDDQ NC DQB NC VSS NC DQA NC NC VDDQ N DQB NC VSS BWE A1 BWA VSS VSS DQA NC P NC DQPB VSS A0 VSS NC DQA R T U NC NC/72M VDDQ A A TMS MODE A TDI VDD NC/36M TCK NC A TDO A A NC NC ZZ VDDQ Document Number: 38-05545 Rev. *H Page 5 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Configurations (continued) Figure 3. 165-ball FBGA (3 Chip Enable) CY7C1386D (512 K × 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/288M A CE1 BWC BWB CE3 BWE ADSC ADV A NC R NC/144M A CE2 BWD BWA CLK NC/512M VDDQ VSS VSS VSS VSS VDDQ VDDQ VSS VDD OE VSS VDD A NC DQC GW VSS VSS ADSP DQPC DQC VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC NC DQD DQC VDDQ VDDQ NC VDDQ VDD VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQB VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS DQB NC DQA DQB DQB ZZ DQA DQC NC DQD DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC/72M A A TDI A1 TDO A A A A MODE NC/36M A A TMS A0 TCK A A A A 8 9 10 11 A CY7C1387D (1 M × 18) 1 2 A B C D E F G H J K L M N P NC/288M A 3 4 5 6 NC CE3 A CE1 CE2 BWB NC/144M NC BWA NC NC NC DQB VDDQ VDDQ VSS VDD NC DQB VDDQ NC NC NC DQB DQB DQB NC NC VDDQ VDDQ NC VDDQ DQB NC R 7 CLK BWE GW ADSC OE ADV ADSP A VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ NC/1G NC DQPA DQA VDD VSS VSS VSS VDD VDDQ NC DQA VDD VSS VDD VDD VDD VDDQ VDDQ NC VDDQ NC VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS ‘VSS NC NC DQA DQA DQA ZZ NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC A NC/576M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB DQPB NC NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC NC NC/72M A A TDI A1 TDO A A A A MODE NC/36M A A TMS A0 TCK A A A A Document Number: 38-05545 Rev. *H Page 6 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Definitions Name A0, A1, A I/O Description InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK [4] Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1: A0 are fed to the two-bit counter. BWA, BWB, InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled BWC, BWD Synchronous on the rising edge of CLK. GW InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write Synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE). BWE InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted Synchronous LOW to conduct a byte write. CLK InputClock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 [4] Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 [4] InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 [4] Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. CE3 [4] InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 [4] Synchronous and CE2 to select or deselect the device. Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. OE InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, Asynchronous the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tristated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it Synchronous automatically increments the address in a burst cycle. ADSP InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputZZ sleep input, active HIGH. When asserted HIGH places the device in a non-time critical sleep Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW. ZZ pin has an internal pull down. DQs, DQPX I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tristate condition. VDD Power Supply Power supply inputs to the core of the device. VSS Ground Ground for the core of the device. VSSQ I/O Ground Ground for the I/O circuitry. VDDQ I/O Power Supply Power supply for the I/O circuitry. Note 4. CE3 and CE2 are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in Single Chip Enable. Document Number: 38-05545 Rev. *H Page 7 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Definitions (continued) Name I/O Description MODE InputStatic Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not used, this pin must be disconnected. This pin is not available on TQFP packages. output Synchronous TDI JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. input Synchronous TMS JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. input Synchronous Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be connected to VSS. This pin is not available on TQFP packages. TCK JTAGClock NC – No Connects. Not internally connected to the die. NC/(36 M, 72 M, 144 M, 288 M, 576 M, 1 G) – These pins are not connected. They are used for expansion up to 36 M, 72 M, 144 M, 288 M, 576 M, and 1G densities. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium® and i486 processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tristated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a double cycle deselect part. After the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output tristates immediately after the next clock rise. Synchronous chip selects CE1, CE2, CE3 [5] and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Note 5. CE3 and CE2 are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in Single Chip Enable. Document Number: 38-05545 Rev. *H Page 8 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, the write operation is controlled by BWE and BWX signals. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F provides byte write capability that is described in the write cycle description table. Asserting the byte write enable input (BWE) with the selected byte write input, selectively writes to the desired bytes. Bytes not selected during a byte write operation remains unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. This tristates the output drivers. As a safety precaution, DQ are automatically tristated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory Document Number: 38-05545 Rev. *H core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation remains unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. This tristates the output drivers. As a safety precaution, DQX are automatically tristated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Page 9 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Linear Burst Address Table (MODE = GND) Fourth Address A1: A0 11 10 01 00 First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ Active to sleep current ZZ Inactive to exit sleep current Document Number: 38-05545 Rev. *H Test Conditions ZZ > VDD– 0.2 V ZZ > VDD – 0.2 V ZZ < 0.2 V This parameter is sampled This parameter is sampled Min – – 2tCYC – 0 Max 80 2tCYC – 2tCYC – Unit mA ns ns ns ns Page 10 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Truth Table The Truth Table for CY7C1386D, CY7C1386F, CY7C1387D, and CY7C1387F follow.[6, 7, 8, 9, 10] Operation Add. Used CE1 CE2 CE3 ADSP ADSC ADV WRITE X L X L X OE CLK DQ X X L–H Tristate Deselect cycle, power-down None H Deselect cycle, power-down None L L X L L X X X X L–H Tristate Deselect cycle, power-down None L X H L L X X X X L–H Tristate Deselect cycle, power-down None L L X L H L X X X L–H Tristate Deselect cycle, power-down None L X H L H L X X X L–H Tristate None X X X H X X X X X X Tristate External L H L L L X X X L L–H Q Sleep mode, power-down Read cycle, begin burst X ZZ Read cycle, begin burst External L H L L L X X X H L–H Tristate Write cycle, begin burst External L H L L H L X L X L–H D Read cycle, begin burst External L H L L H L X H L L–H Q Read cycle, begin burst External L H L L H L X H H L–H Tristate Read cycle, continue burst Next X X X L H H L H L L–H Q Read cycle, continue burst Next X X X L H H L H H L–H Tristate Read cycle, continue burst Next H X X L X H L H L L–H Q Read cycle, continue burst Next H X X L X H L H H L–H Tristate Write cycle, continue burst Next X X X L H H L L X L–H D Write cycle, continue burst Next H X X L X H L L X L–H D Read cycle, suspend burst Current X X X L H H H H L L–H Q Read cycle, suspend burst Current X X X L H H H H H L–H Tristate Read cycle, suspend burst Current H X X L X H H H L L–H Q Read cycle, suspend burst Current H X X L X H H H H L–H Tristate Write cycle, suspend burst Current X X X L H H H L X L–H D Write cycle, suspend burst Current H X X L X H H L X L–H D Notes 6. X = Do not care, H = Logic HIGH, L = Logic LOW. 7. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H. 8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 9. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for the remainder of the write cycle. 10. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 38-05545 Rev. *H Page 11 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Truth Table for Read/Write The Truth Table for Read/Write for CY7C1386D and CY7C1386F follows.[11, 12] Function (CY7C1386D/CY7C1386F) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write byte A – (DQA and DQPA) H L H H H L Write byte B – (DQB and DQPB) H L H H L H Write bytes B, A H L H H L L Write byte C – (DQC and DQPC) H L H L H H Write bytes C, A H L H L H L Write bytes C, B H L H L L H Write bytes C, B, A H L H L L L Write byte D – (DQD and DQPD) H L L H H H Write bytes D, A H L L H H L Write bytes D, B H L L H L H Write bytes D, B, A H L L H L L Write bytes D, C H L L L H H Write bytes D, C, A H L L L H L Write bytes D, C, B H L L L L H Write all bytes H L L L L L Write all bytes L X X X X X Truth Table for Read/Write The Truth Table for Read/Write for CY7C1387D and CY7C1387F follows.[11, 12] Function (CY7C1387D/CY7C1387F) GW BWE BWB BWA Read H H X X Read H L H H Write byte A – (DQA and DQPA) H L H L Write byte B – (DQB and DQPB) H L L H Write all bytes H L L L Write all bytes L X X X Notes 11. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 12. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid appropriate write is done based on which byte write is active. Document Number: 38-05545 Rev. *H Page 12 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO can be left unconnected. Upon power-up, the device comes up in a reset state which does not interfere with the operation of the device. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test Data-Out (TDO) The TDO output ball is used to serially clock data out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 15. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The boundary scan order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor specific 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions on page 18. TAP Instruction Set Performing a TAP Reset Overview A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and may be performed while the SRAM is operating. Eight different instructions are possible with the three bit instruction register. All combinations are listed in Identification Codes on page 18. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below. At power-up, the TAP is reset internally to ensure that TDO comes up in a high Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the Document Number: 38-05545 Rev. *H Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute Page 13 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F the instruction after it is shifted in, the TAP controller needs to be moved into the Update-IR state. still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. EXTEST After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the Shift-DR controller state. IDCODE The IDCODE instruction causes a vendor specific 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. The SAMPLE Z command places all SRAM outputs into a high Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. As there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is Document Number: 38-05545 Rev. *H PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required; that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST Output Bus Tristate IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The boundary scan register has a special bit located at bit #85 (for 119-ball BGA package) or bit #89 (for 165-ball FBGA package). When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a high Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 14 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F TAP Controller State Diagram 1 TAP Controller Block Diagram TEST-LOGIC RESET 0 0 0 RUN-TEST/ IDLE Bypass Register 1 SELECT DR-SCAN 1 0 1 1 SELECT IR-SCAN 2 1 0 0 1 CAPTURE-DR TDI CAPTURE-IR 0 Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 0 SHIFT-DR 0 S election Circuitr y TDO Identification Register SHIFT-IR 0 x . . . . . 2 1 0 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR 1 0 0 TCK 1 0 EXIT2-DR TAP CONTROLLER TMS EXIT2-IR 1 1 UPDATE-DR 1 Boundary Scan Register 1 UPDATE-IR 1 0 0 The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK. TAP Timing Diagram 1 2 Test Clock (TCK) 3 t t TH t TMSS t TMSH t TDIS t TDIH TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE Document Number: 38-05545 Rev. *H UNDEFINED Page 15 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F TAP AC Switching Characteristics Over the Operating Range Parameter [13, 14] Clock tTCYC tTF tTH tTL Output Times tTDOV tTDOX Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Description Min Max Unit TCK clock cycle time TCK clock frequency TCK clock HIGH time TCK clock LOW time 50 – 20 20 – 20 – – ns MHz ns ns TCK clock LOW to TDO valid TCK Clock LOW to TDO invalid – 0 10 – ns ns TMS setup to TCK clock rise TDI setup to TCK clock rise Capture setup to TCK rise 5 5 5 – – – ns ns ns TMS hold after TCK clock rise TDI hold after clock rise Capture hold after clock rise 5 5 5 – – – ns ns ns Notes 13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 14. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document Number: 38-05545 Rev. *H Page 16 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................VSS to 3.3 V Input pulse levels .............................................. .VSS to 2.5 V Input rise and fall times ...................................................1 ns Input rise and fall time ....................................................1 ns Input timing reference levels ......................................... 1.5 V Input timing reference levels ....................................... 1.25 V Output reference levels ................................................ 1.5 V Output reference levels .............................................. 1.25 V Test load termination supply voltage ............................ 1.5 V Test load termination supply voltage .......................... 1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.5V 1.25V 50Ω 50Ω TDO Z O= 50 Ω TDO 20pF Z O= 50 Ω 20pF TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted) Parameter[15] VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH voltage Output HIGH voltage Output LOW voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input load current Test Conditions Min Max Unit IOH = –4.0 mA, VDDQ = 3.3 V 2.4 – V IOH = –1.0 mA, VDDQ = 2.5 V 2.0 – V IOH = –100 µA VDDQ = 3.3 V 2.9 – V VDDQ = 2.5 V 2.1 – V IOL = 8.0 mA, VDDQ = 3.3 V – 0.4 V IOL = 8.0 mA, VDDQ = 2.5 V – 0.4 V IOL = 100 µA VDDQ = 3.3 V – 0.2 V VDDQ = 2.5 V – 0.2 V VDDQ = 3.3 V 2.0 VDD + 0.3 V VDDQ = 2.5 V 1.7 VDD + 0.3 V VDDQ = 3.3 V –0.5 0.7 V VDDQ = 2.5 V –0.3 0.7 V –5 5 µA GND < VIN < VDDQ Note 15. All voltages referenced to VSS (GND). Document Number: 38-05545 Rev. *H Page 17 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Identification Register Definitions CY7C1386D/CY7C1386F CY7C1387D/CY7C1387F (512 K × 36) (1 M × 18) Instruction Field Revision Number (31:29) Description 000 000 01011 01011 Reserved for internal use. Device Width (23:18) 119-ball BGA 101110 101110 Defines the memory type and architecture. Device Width (23:18) 165-ball FBGA 000110 000110 Defines the memory type and architecture. Cypress Device ID (17:12) 100101 010101 Defines the width and density. 00000110100 00000110100 1 1 Device Depth (28:24) [16] Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) Describes the version number Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Bit Size (× 18) Bit Size (× 36) Instruction Register Name 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 85 85 Boundary Scan Order (165-ball FBGA package) 89 89 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. RESERVED 011 Do Not Use. This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use. This instruction is reserved for future use. RESERVED 110 Do Not Use. This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note 16. Bit #24 is 1 in the register definitions for both 2.5 V and 3.3 V versions of this device. Document Number: 38-05545 Rev. *H Page 18 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Boundary Scan Order 119-ball BGA [17, 18] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # 1 H4 T4 23 2 24 3 T5 25 4 T6 26 5 R5 27 G6 49 6 L5 28 E6 50 7 R6 29 D6 51 8 U6 30 C7 52 9 R7 31 B7 53 10 T7 32 C6 54 Ball ID F6 45 G4 67 L1 E7 46 A4 68 M2 D7 47 G3 69 N1 H7 48 C3 70 P1 B2 71 K1 B3 72 L2 A3 73 C2 74 N2 P2 A2 75 R3 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82 L4 17 N6 39 B4 61 D1 83 N4 18 L6 40 F4 62 E2 84 P4 19 K7 41 M4 63 G2 85 Internal 20 J5 42 A5 64 H1 21 H6 43 K4 65 J3 22 G7 44 E4 66 2K Notes 17. Balls that are NC (No Connect) are preset LOW. 18. Bit#85 is preset HIGH. Document Number: 38-05545 Rev. *H Page 19 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Boundary Scan Order 165-ball BGA [19, 20] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 C2 84 R4 25 F11 55 B1 85 P4 26 E11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1 88 R6 29 F10 59 E1 89 Internal 30 E10 60 F1 Notes 19. Balls that are NC (No Connect) are preset LOW. 20. Bit#89 is preset HIGH. Document Number: 38-05545 Rev. *H Page 20 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ................................... –55 °C to +125 °C Operating Range Ambient Temperature Commercial 0 °C to +70 °C Industrial –40 °C to +85 °C Range VDD VDDQ 3.3 V– 5% / +10% 2.5 V – 5% to VDD Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD DC voltage applied to outputs in tristate ...........................................–0.5 V to VDDQ + 0.5 V DC input voltage ................................. –0.5 V to VDD + 0.5 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Neutron Soft Error Immunity Parameter Description Test Conditions Typ Max* Unit LSBU Logical single-bit upsets 25 °C 361 394 FIT/ Mb LMBU Logical multi-bit upsets 25 °C 0 0.01 FIT/ Mb Single event latch-up 85 °C 0 0.1 FIT/ Dev Latch-up current .................................................... > 200 mA SEL * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates” Electrical Characteristics Over the Operating Range Parameter [21, 22] Description VDD Power supply voltage VDDQ I/O supply voltage VOH VOL VIH VIL IX for 3.3 V I/O for 2.5 V I/O Output HIGH voltage for 3.3 V I/O, IOH = –4.0 mA for 2.5 V I/O, IOH = –1.0 mA Output LOW voltage for 3.3 V I/O, IOL = 8.0 mA for 2.5 V I/O, IOL = 1.0 mA Input HIGH voltage [21] for 3.3 V I/O for 2.5 V I/O Input LOW voltage [21] for 3.3 V I/O for 2.5 V I/O Input leakage current except ZZ GND VI VDDQ and MODE Input current of MODE Input current of ZZ IOZ Test Conditions Output leakage current Input = VSS Input = VDD Input = VSS Input = VDD GND VI VDDQ, Output Disabled Min 3.135 3.135 2.375 2.4 2.0 – – 2.0 1.7 –0.3 –0.3 –5 –30 – –5 – –5 Max Unit 3.6 V VDD V 2.625 V – V – V 0.4 V 0.4 V VDD + 0.3 V V VDD + 0.3 V V 0.8 V 0.7 V 5 µA – 5 – 30 5 µA µA µA µA µA Notes 21. Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 22. TPower-up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 38-05545 Rev. *H Page 21 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Electrical Characteristics (continued) Over the Operating Range Parameter [21, 22] Description IDD VDD operating supply current Test Conditions VDD = Max., 4 ns cycle, 250 MHz IOUT = 0 mA, 5 ns cycle, 200 MHz f = fMAX = 1/tCYC 6 ns cycle, 167 MHz VDD = Max, 4 ns cycle, 250 MHz device deselected, 5 ns cycle, 200 MHz VIN VIH or VIN VIL 6 ns cycle, 167 MHz f=f = 1/t Min – – – – – – Max 350 300 275 160 150 140 Unit mA mA mA mA mA mA ISB1 Automatic CE power-down current—TTL inputs ISB2 Automatic CE power-down current—CMOS inputs VDD = Max, device deselected, VIN 0.3 V or VIN > VDDQ – 0.3 V, f=0 All speeds – 70 mA ISB3 Automatic CE power-down current—CMOS inputs 4 ns cycle, 250 MHz 5 ns cycle, 200 MHz 6 ns cycle, 167 MHz – – – 135 130 125 mA mA mA ISB4 Automatic CE power-down current—TTL inputs VDD = Max, device deselected, or VIN 0.3 V or VIN > VDDQ – 0.3 V f = fMAX = 1/tCYC VDD = Max, device deselected, VIN VIH or VIN VIL, f=0 All speeds – 80 mA MAX CYC Capacitance Parameter[23] Description CIN Input capacitance CCLK Clock input capacitance CIO I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V 100-pin TQFP 119-ball BGA 165-ball FBGA Unit Max Max Max 5 8 9 pF 5 8 9 pF 5 8 9 pF Thermal Resistance Parameter[23] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 100-pin TQFP 119-ball BGA 165-ball FBGA Unit Package Package Package 28.66 23.8 20.7 °C/W 4.08 6.2 4.0 °C/W Note 23. Tested initially and after any design or process change that may affect these parameters. Document Number: 38-05545 Rev. *H Page 22 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3 V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 351 VT = 1.5 V INCLUDING JIG AND SCOPE (a) 2.5 V I/O Test Load OUTPUT RL = 50 Z0 = 50 Document Number: 38-05545 Rev. *H INCLUDING JIG AND SCOPE 1 ns 1 ns (c) ALL INPUT PULSES VDDQ GND 5 pF R = 1538 (b) 90% 10% 90% (b) VT = 1.25 V (a) 10% R = 1667 2.5 V OUTPUT ALL INPUT PULSES VDDQ 10% 90% 10% 90% 1 ns 1 ns (c) Page 23 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Switching Characteristics Over the Operating Range Parameter [24, 25] tPOWER -250 Description VDD(Typical) to the first access [26] -200 -167 Unit Min Max Min Max Min Max 1 – 1 – 1 – ms Clock tCYC Clock cycle time 4.0 – 5.0 – 6.0 – ns tCH Clock HIGH 1.7 – 2.0 – 2.2 – ns tCL Clock LOW 1.7 – 2.0 – 2.2 – ns Output Times tCO Data output valid after CLK rise – 2.6 – 3.0 – 3.4 ns tDOH Data output hold after CLK rise 1.0 – 1.3 – 1.3 – ns 1.0 – 1.3 – 1.3 – ns – 2.6 – 3.0 – 3.4 ns – 2.6 – 3.0 – 3.4 ns 0 – 0 – 0 – ns – 2.6 – 3.0 – 3.4 ns tCLZ Clock to low Z [27, 28, 29] [27, 28, 29] tCHZ Clock to high Z tOEV OE LOW to output valid tOELZ tOEHZ OE LOW to output low Z [27, 28, 29] OE HIGH to output high Z [27, 28, 29] Setup Times tAS Address setup before CLK rise 1.2 – 1.4 – 1.5 – ns tADS ADSC, ADSP setup before CLK rise 1.2 – 1.4 – 1.5 – ns tADVS ADV setup before CLK rise 1.2 – 1.4 – 1.5 – ns tWES GW, BWE, BWX setup before CLK rise 1.2 – 1.4 – 1.5 – ns tDS Data input setup before CLK rise 1.2 – 1.4 – 1.5 – ns tCES Chip enable setup before CLK rise 1.2 – 1.4 – 1.5 – ns tAH Address hold after CLK rise 0.3 – 0.4 – 0.5 – ns tADH ADSP, ADSC hold after CLK rise 0.3 – 0.4 – 0.5 – ns tADVH ADV hold after CLK rise 0.3 – 0.4 – 0.5 – ns tWEH GW, BWE, BWX hold after CLK rise 0.3 – 0.4 – 0.5 – ns tDH Data input hold after CLK rise 0.3 – 0.4 – 0.5 – ns tCEH Chip enable hold after CLK rise 0.3 – 0.4 – 0.5 – ns Hold Times Notes 24. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 25. Test conditions shown in (a) of Figure 4 on page 23 unless otherwise noted. 26. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 27. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of Figure 4 on page 23. Transition is measured ±200 mV from steady-state voltage. 28. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 29. This parameter is sampled and not 100% tested. Document Number: 38-05545 Rev. *H Page 24 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Switching Waveforms Figure 5. Read Cycle Timing [30] tCYC CLK tCH t ADS tCL tADH ADSP t ADS tADH ADSC t AS ADDRESS tAH A1 A2 t WES GW, BWE,BW A3 Burst continued with new base address tWEH X t CES Deselect cycle tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data Out (DQ) High-Z CLZ t OEHZ Q(A1) t OEV t CO t OELZ t DOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) t CO Single READ BURST READ DON’T CARE Burst wraps around to its initial state UNDEFINED Note 30. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWX LOW. Document Number: 38-05545 Rev. *H Page 25 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Switching Waveforms (continued) Figure 6. Write Cycle Timing [31] t CYC CLK tCH t ADS tCL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW X t WES tWEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t OEHZ DS t DH D(A1) D(A2) D(A2 + 1) D(A2 + 3) D(A3) D(A3 + 1) Data Out (Q) BURST READ BURST WRITE Single WRITE DON’T CARE Extended BURST WRITE UNDEFINED Note 31. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWX LOW. Document Number: 38-05545 Rev. *H Page 26 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Switching Waveforms (continued) Figure 7. Read/Write Cycle Timing [32, 33, 34] t CYC CLK tCL tCH t ADS tADH t AS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 t WES tWEH BWE, BW X t CES tCEH CE ADV OE t DS tCO Data In (D) t OELZ High-Z tOEHZ tCLZ Data Out (Q) tDH High-Z Q(A1) Q(A2) Back-to-Back READs D(A5) D(A3) Q(A4) DON’T CARE Q(A4+3) BURST READ Single WRITE D(A6) Back-to-Back WRITEs UNDEFINED Notes 32. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWX LOW. 33. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC. 34. GW is HIGH. Document Number: 38-05545 Rev. *H Page 27 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Switching Waveforms (continued) Figure 8. ZZ Mode Timing [35, 36] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 35. Device must be deselected when entering ZZ sleep mode. See cycle descriptions table for all possible signal conditions to deselect the device. 36. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05545 Rev. *H Page 28 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Ordering Information The table below contains only the parts that are currently available. If you do not see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 167 Ordering Code CY7C1386D-167AXC Package Diagram Part and Package Type Operating Range 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial CY7C1387D-167AXC 200 CY7C1386D-200AXC Ordering Code Definitions CY 7 C 13XX D - XXX A X C Temperature Range: C = Commercial = 0 C to +70 C X = Pb-free; X Absent = Leaded Package Type: A = 100-pin TQFP Speed Grade: XXX = 167 MHz / 200 MHz Process Technology 90 nm 13XX = 1386 or 1387 1386 = DCD, 512 K × 36 (18 Mb) 1387 = DCD, 1 M × 18 (18 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05545 Rev. *H Page 29 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Package Diagrams Figure 10: 100-pin TQFP (14 × 20 × 1.4 mm) A100RA, 51-85050 51-85050 *D Document Number: 38-05545 Rev. *H Page 30 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Package Diagrams (continued) Figure 9. 119-ball PBGA (14 × 22 × 2.4 mm) BG119, 51-85115 51-85115 *C Document Number: 38-05545 Rev. *H Page 31 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Package Diagrams (continued) Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter), 51-85180 51-85180 *C Document Number: 38-05545 Rev. *H Page 32 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Acronyms Acronym Document Conventions Description Units of Measure BGA ball grid array CE chip enable °C degree Celsius CMOS complementary metal oxide semiconductor k kilo ohms FBGA fine-pitch ball grid array MHz Mega Hertz I/O input/output µA micro Amperes JTAG Joint Test Action Group µs micro seconds LMBU logical multiple-bit upsets mA milli Amperes LSB least significant bit mV milli Volts LSBU logical single-bit upsets mm milli meter MSB most significant bit ms milli seconds OE output enable ns nano seconds SEL single event latch-up ohms SRAM static random access memory % percent TAP test access port pF pico Farad TCK test clock ps pico seconds TDI test data-in V Volts TDO test data-out W Watts TMS test mode select TQFP thin quad flat pack TTL transistor-transistor logic Document Number: 38-05545 Rev. *H Symbol Unit of Measure Page 33 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document History Page Document Title: CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F, 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Document Number: 38-05545 Revision ECN Orig. of Change Submission Date Description of Change ** 254550 RKF See ECN New data sheet *A 288531 SYT See ECN Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for non-compliance with 1149.1 Removed 225 MHz Speed Bin Added Pb-free information for 100-pin TQFP, 119 BGA and 165 FBGA Packages. Added comment of ‘Pb-free BG packages availability’ below the Ordering Information *B 326078 PCI See ECN Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added description on EXTEST Output Bus Tristate Changed description on the Tap Instruction Set Overview and Extest Changed Device Width (23:18) for 119-BGA from 000110 to 101110 Added separate row for 165 -FBGA Device Width (23:18) Changed JA and JC for TQFP Package from 31 and 6 C/W to 28.66 and 4.08 C/W respectively Changed JA and JC for BGA Package from 45 and 7 C/W to 23.8 and 6.2 C/W respectively Changed JA and JC for FBGA Package from 46 and 3 C/W to 20.7 and 4.0 C/W respectively Modified VOL, VOH test conditions Removed comment of ‘Pb-free BG packages availability’ below the Ordering Information Updated Ordering Information Table *C 418125 NXR See ECN Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed the description of IX from Input Load Current to Input Leakage Current on page# 18. Changed the IX current values of MODE on page # 18 from –5 A and 30 A to –30 A and 5 A. Changed the IX current values of ZZ on page # 18 from –30 A and 5 A to –5 A and 30 A. Changed VIH < VDD to VIH < VDDon page # 18. Replaced Package Name column with Package Diagram in the Ordering Information table. Updated Ordering Information Table. *D 475009 VKN See ECN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. *E 793579 VKN See ECN Added Part numbers CY7C1386F and CY7C1387F Added footnote# 3 regarding Chip Enable Updated Ordering Information table *F 2756940 VKN 08/27/2009 *G 3006369 NJY 08/12/10 Document Number: 38-05545 Rev. *H Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Template update. Added Ordering Code Definitions. Added Acronyms. Page 34 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document History Page (continued) Document Title: CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F, 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Document Number: 38-05545 Revision ECN Orig. of Change Submission Date *H 3309506 OSN 07/12/2011 Document Number: 38-05545 Rev. *H Description of Change Updated Package Diagrams. Added Units of Measure. Updated in new template. Page 35 of 36 [+] Feedback CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05545 Rev. *H Revised July 12, 2011 Page 36 of 36 Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback