TI MSP430F2419TPN Mixed signal microcontroller Datasheet

MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
D
D
D
D
D
D
D
D
D
D
D
Low Supply Voltage Range, 1.8 V to 3.6 V
Ultra-Low Power Consumption:
- Active Mode: 365 µA at 1 MHz, 2.2 V
- Standby Mode (VLO): 0.5 µA
- Off Mode (RAM Retention): 0.1 µA
Wake-Up From Standby Mode in Less
Than 1 µs
16-Bit RISC Architecture,
62.5-ns Instruction Cycle Time
Three-Channel Internal DMA
12-Bit Analog-to-Digital (A/D) Converter
With Internal Reference, Sample-and-Hold,
and Autoscan Feature
Dual 12-Bit Digital-to-Analog (D/A)
Converters With Synchronization
16-Bit Timer_A With Three
Capture/Compare Registers
16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
On-Chip Comparator
Four Universal Serial Communication
Interfaces (USCIs)
- USCI_A0 and USCI_A1
- Enhanced UART Supporting
Auto-Baudrate Detection
- IrDA Encoder and Decoder
- Synchronous SPI
- USCI_B0 and USCI_B1
- I2Ct
- Synchronous SPI
D
D
D
D
D
D
D
†
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
Brownout Detector
Bootstrap Loader
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Family Members† Include:
- MSP430F2416
92KB+256B Flash Memory, 4KB RAM
- MSP430F2417
92KB+256B Flash Memory, 8KB RAM
- MSP430F2418
116KB+256B Flash Memory, 8KB RAM
- MSP430F2419
120KB+256B Flash Memory, 4KB RAM
- MSP430F2616
92KB+256B Flash Memory, 4KB RAM
- MSP430F2617
92KB+256B Flash Memory, 8KB RAM
- MSP430F2618
116KB+256B Flash Memory, 8KB RAM
- MSP430F2619
120KB+256B Flash Memory, 4KB RAM
Available in 80-Pin Quad Flat Pack (QFP),
64-Pin QFP, and 113-Pin Ball Grid Array
(BGA) (See Available Options)
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide,
Literature Number SLAU144
The MSP430F241x devices are identical to the MSP430F261x
devices, with the exception that the DAC12 modules and the DMA
controller are not implemented.
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The calibrated digitally controlled oscillator (DCO) allows wake-up from low-power modes to active
mode in less than 1 µs.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a registered trademark of Philips Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright  2009, Texas Instruments Incorporated
1
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
description (continued)
The MSP430F261x/241x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit
A/D converter, a comparator, dual 12-bit D/A converters, four universal serial communication interface (USCI)
modules, DMA, and up to 64 I/O pins. The MSP430F241x devices are identical to the MSP430F261x devices,
with the exception that the DAC12 and the DMA modules are not implemented.
Typical applications include sensor systems, industrial control applications, hand-held meters, etc.
TA
--40°C to 105°C
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC 113-PIN BGA (ZQW) PLASTIC 80-PIN LQFP (PN) PLASTIC 64-PIN LQFP (PM)
MSP430F2416TZQW
MSP430F2416TPN
MSP430F2416TPM
MSP430F2417TZQW
MSP430F2417TPN
MSP430F2417TPM
MSP430F2418TZQW
MSP430F2418TPN
MSP430F2418TPM
MSP430F2419TZQW
MSP430F2419TPN
MSP430F2419TPM
MSP430F2616TZQW
MSP430F2616TPN
MSP430F2616TPM
MSP430F2617TZQW
MSP430F2617TPN
MSP430F2617TPM
MSP430F2618TZQW
MSP430F2618TPN
MSP430F2618TPM
MSP430F2619TZQW
MSP430F2619TPN
MSP430F2619TPM
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy-to-use development tools. Recommended hardware options include:
D Debugging and Programming Interface
-- MSP-FET430UIF (USB)
-- MSP-FET430PIF (Parallel Port)
D Debugging and Programming Interface with Target Board
-- MSP-FET430U64
-- MSP-FET430U80
D Standalone Target Board
-- MSP-TS430PM64
D Production Programmer
-- MSP-GANG430
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
P7.7
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P8.7/XT2IN
P8.6/XT2OUT
pin designation, MSP430F241x, 80-pin PN package
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
1
60
P7.6
P6.3/A3
P6.4/A4
2
3
59
58
P7.5
P7.4
P6.5/A5
4
57
P7.3
P6.6/A6
P6.7/A7/SVSIN
5
6
56
55
P7.2
P7.1
VREF+
XIN
7
8
54
53
P7.0
DVSS2
XOUT
9
52
DVCC2
51
50
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
80-pin
PN PACKAGE
(TOP VIEW)
VeREF+
VREF-/VeREF-
10
11
P1.0/TACLK/CAOUT
P1.1/TA0
12
13
49
48
P5.5/SMCLK
P5.4/MCLK
P1.2/TA1
14
47
P5.3/UCB1CLK/UCA1STE
P1.3/TA2
P1.4/SMCLK
15
16
46
45
P5.2/UCB1SOMI/UCB1SCL
P5.1/UCB1SIMO/UCB1SDA
P1.5/TA0
17
44
P5.0/UCB1STE/UCA1CLK
P1.6/TA1
P1.7/TA2
18
19
43
42
P4.7/TBCLK
P4.6/TB6
P2.0/ACLK/CA2
20
41
P4.5/TB5
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
pin designation, MSP430F241x, 64-pin PM package
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DVCC1
1
48
P5.4/MCLK
P6.3/A3
P6.4/A4
2
3
47
46
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P6.5/A5
P6.6/A6
4
5
45
44
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P6.7/A7/SVSIN
6
43
P4.7/TBCLK
VREF+
XIN
7
8
42
41
P4.6/TB6
P4.5/TB5
XOUT
VeREF+
9
10
40
39
P4.4/TB4
P4.3/TB3
VREF-/VeREFP1.0/TACLK/CAOUT
11
12
38
37
P4.2/TB2
P4.1/TB1
P1.1/TA0
P1.2/TA1
13
14
36
35
P4.0/TB0
P3.7/UCA1RXD/UCA1SOMI
P1.3/TA2
P1.4/SMCLK
15
16
34
33
P3.6/UCA1TXD/UCA1SIMO
P3.5/UCA0RXD/UCA0SOMI
64-pin
PM PACKAGE
(TOP VIEW)
4
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/CA6
P2.7/TA0/CA7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
P7.7
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P8.7/XT2IN
P8.6/XT2OUT
pin designation, MSP430F261x, 80-pin PN package
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
1
60
P7.6
P6.3/A3
2
59
P7.5
P6.4/A4
P6.5/A5/DAC1
3
4
58
57
P7.4
P7.3
P6.6/A6/DAC0
5
56
P7.2
P6.7/A7/DAC1/SVSIN
VREF+
6
7
55
54
P7.1
P7.0
XIN
8
53
DVSS2
XOUT
VeREF+/DAC0
9
10
52
51
DVCC2
P5.7/TBOUTH/SVSOUT
80-pin
PN PACKAGE
(TOP VIEW)
VREF-/VeREF-
11
50
P5.6/ACLK
P1.0/TACLK/CAOUT
P1.1/TA0
12
13
49
48
P5.5/SMCLK
P5.4/MCLK
P1.2/TA1
14
47
P5.3/UCB1CLK/UCA1STE
P1.3/TA2
P1.4/SMCLK
15
16
46
45
P5.2/UCB1SOMI/UCB1SCL
P5.1/UCB1SIMO/UCB1SDA
P1.5/TA0
17
44
P5.0/UCB1STE/UCA1CLK
P1.6/TA1
P1.7/TA2
18
19
43
42
P4.7/TBCLK
P4.6/TB6
P2.0/ACLK/CA2
20
41
P4.5/TB5
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/DMAE0/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
P5.5/SMCLK
P5.6/ACLK
XT2OUT
P5.7/TBOUTH/SVSOUT
TDO/TDI
XT2IN
TDI/TCLK
TMS
RST/NMI
TCK
P6.0/A0
P6.1/A1
P6.2/A2
AVSS
DVSS1
AVCC
pin designation, MSP430F261x, 64-pin PM package
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DVCC1
P6.3/A3
P6.4/A4
1
2
3
48
47
46
P5.4/MCLK
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P6.5/A5/DAC1
P6.6/A6/DAC0
4
5
45
44
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P6.7/A7/DAC1/SVSIN
VREF+
XIN
6
7
8
43
42
41
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
40
39
P4.4/TB4
P4.3/TB3
64-pin
PM PACKAGE
(TOP VIEW)
XOUT
VeREF+/DAC0
9
10
VREF-/VeREFP1.0/TACLK/CAOUT
P1.1/TA0
11
12
13
38
37
36
P4.2/TB2
P4.1/TB1
P4.0/TB0
P1.2/TA1
P1.3/TA2
14
15
35
34
P3.7/UCA1RXD/UCA1SOMI
P3.6/UCA1TXD/UCA1SIMO
P1.4/SMCLK
16
33
P3.5/UCA0RXD/UCA0SOMI
6
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.2/UCB0SOMI/UCB0SCL
P3.1/UCB0SIMO/UCB0SDA
P3.0/UCB0STE/UCA0CLK
P2.7/TA0/CA7
P2.5/ROSC/CA5
P2.6/ADC12CLK/DMAE0/CA6
P2.4/CA1/TA2
P2.3/CA0/TA1
P2.2/CAOUT/TA0/CA4
P2.1/TAINCLK/CA3
P2.0/ACLK/CA2
P1.7/TA2
P1.6/TA1
P1.5/TA0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
pin designation, 113-pin ZQW package
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C11
C12
D1
D2
D4
D5
D6
D7
D8
D9
D11
D12
E1
E2
E4
E5
E6
E7
E8
E9
E11
E12
F1
F2
F4
F5
F8
F9
F11
F12
G1
G2
G4
G5
G8
G9
G11
G12
H1
H2
H4
H5
H6
H7
H8
H9
H11
H12
J1
J2
J4
J5
J6
J7
J8
J9
J11
J12
K1
K2
K11
K12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
Note: For terminal assignments, see the MSP430F261x Terminal Functions table.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
functional block diagram, MSP430F241x, 80-pin PN package
XIN/
XT2IN
XOUT/
XT2OUT
2
2
DVCC1/2
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
DVSS1/2
Flash
RAM
120kB
116kB
92kB
92kB
4kB
8kB
8kB
4kB
AVCC
AVSS
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
Ports
P1/P2
ADC12
12-Bit
Ports
P3/P4
P5/P6
2x8 I/O
Interrupt
capability
8
Channels
P7.x/P8.x
2x8/
1x16
Ports
P7/P8
2x8/1x16
I/O
4x8 I/O
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
Timer_B7
Watchdog
WDT+
MPY,
MPYS,
MAC,
MACS
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
functional block diagram,
MSP430F241x, 64-pin PM package
XIN/ XOUT/
XT2IN XT2OUT
2
2
DVCC
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
DVSS
Flash
RAM
120kB
116kB
92kB
92kB
4kB
8kB
8kB
4kB
AVCC
AVSS
Ports
P1/P2
ADC12
12-Bit
2x8 I/O
Interrupt
capability
8
Channels
Ports
P3/P4
P5/P6
USCI A0
UART/
LIN,
IrDA, SPI
4x8 I/O
USCI B0
SPI, I2C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
Timer_B7
Watchdog
WDT+
15-Bit
RST/NMI
8
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
functional block diagram,
XIN/
XT2IN
XOUT/
XT2OUT
2
2
DVCC1/2
ACLK
Oscillators
Basic Clock SMCLK
System+
Flash
120kB
116kB
92kB
92kB
56kB
MCLK
16MHz
CPU
1MB
incl. 16
Registers
MSP430F261x, 80-pin PN package
DVSS1/2
AVCC
RAM
4kB
8kB
8kB
4kB
4kB
ADC12
12-Bit
8
Channels
AVSS
DAC12
12-Bit
2
Channels
Voltage
Out
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
Ports
P1/P2
Ports
P3/P4
P5/P6
2x8 I/O
Interrupt
capability
4x8 I/O
P7.x/P8.x
2x8/
1x16
Ports
P7/P8
2x8/1x16
I/O
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
MAB
MDB
Brownout
Protection
Emulation
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
DMA
Controller
3
Channels
Timer_B7
Watchdog
WDT+
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
functional block diagram,
XIN/
XT2IN
MSP430F261x, 64-pin PM package
XOUT/
XT2OUT
2
2
DVCC
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
Flash
120kB
116kB
92kB
92kB
56kB
DVSS
AVCC
RAM
4kB
8kB
8kB
4kB
4kB
ADC12
12-Bit
8
Channels
AVSS
DAC12
12-Bit
2
Channels
Voltage
Out
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
Ports
P1/P2
2x8 I/O
Interrupt
capability
Ports
P3/P4
P5/P6
USCI A0
UART/
LIN,
IrDA, SPI
4x8 I/O
USCI B0
SPI, I2C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
DMA
Controller
3
Channels
Timer_B7
Watchdog
WDT+
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Terminal Functions
TERMINAL
64
PIN
NO.
80
PIN
113
PIN
AVCC
64
80
A2
AVSS
62
78
DVCC1
DVSS1
DVCC2
DVSS2
P1.0/TACLK/
CAOUT
1
63
1
79
52
53
B2,
B3
A1
A3
F12
E12
12
12
G2
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input/Comparator_A output
P1.1/TA0
13
13
H1
I/O
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK/CA2
P2.1/TAINCLK/
CA3
P2.2/CAOUT/
TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
14
15
16
17
18
19
20
14
15
16
17
18
19
20
H2
J1
J2
K1
K2
L1
M1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL
transmit
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
General-purpose digital I/O pin/SMCLK signal output
General-purpose digital I/O pin/Timer_A, compare: Out0 output
General-purpose digital I/O pin/Timer_A, compare: Out1 output
General-purpose digital I/O pin/Timer_A, compare: Out2 output
General-purpose digital I/O pin/ACLK output/Comparator_A input
21
21
M2
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
22
22
M3
I/O
23
24
23
24
L3
L4
I/O
I/O
P2.5/Rosc/CA5
25
25
M4
I/O
P2.6/ADC12CLK/ 26
26
DMAE0†/CA6
P2.7/TA0/CA7
27
27
P3.0/UCB0STE/
28
28
UCA0CLK
P3.1/UCB0SIMO/ 29
29
UCB0SDA
P3.2/UCB0SOMI/ 30
30
UCB0SCL
P3.3/UCB0CLK/
31
31
UCA0STE
P3.4/UCA0TXD/
32
32
UCA0SIMO
P3.5/UCA0RXD/
33
33
UCA0SOMI
† MSP430F261x devices only
J4
I/O
L5
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL
receive/Comparator_A input
General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
General-purpose digital I/O pin/input for external resistor defining the DCO nominal
frequency/Comparator_A input
General-purpose digital I/O pin/conversion clock – 12-bit ADC/DMA channel 0 external
trigger/Comparator_A input
General-purpose digital I/O pin/Timer_A, compare: Out0 output/Comparator_A input
M5
I/O
General-purpose digital I/O pin/USCI B0 slave transmit enable/USCI A0 clock input/output
L6
I/O
M6
I/O
General-purpose digital I/O pin/USCI B0 slave in/master out in SPI mode, SDA I 2C data in
I2C mode
General-purpose digital I/O pin/USCI B0 slave out/master in in SPI mode, SCL I 2C clock
in I2C mode
L7
I/O
General-purpose digital I/O/USCI B0 clock input/output, USCI A0 slave transmit enable
M7
I/O
L8
I/O
General-purpose digital I/O pin/USCIA transmit data output in UART mode, slave data
in/master out in SPI mode
General-purpose digital I/O pin/USCI A0 receive data input in UART mode, slave data
out/master in in SPI mode
NAME
10
I/O
DESCRIPTION
Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and
DAC12.
Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and
DAC12.
Digital supply voltage, positive terminal. Supplies all digital parts.
Digital supply voltage, negative terminal. Supplies all digital parts.
Digital supply voltage, positive terminal. Supplies all digital parts.
Digital supply voltage, negative terminal. Supplies all digital parts.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Terminal Functions (Continued)
TERMINAL
NAME
P3.6/UCA1TXD/
UCA1SIMO
P3.7/UCA1RXD/
UCA1SOMI
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK
P5.0/UCB1STE/
UCA1CLK
P5.1/UCB1SIMO/
UCB1SDA
P5.2/UCB1SOMI/
UCB1SCL
P5.3/UCB1CLK/
UCA1STE
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/
SVSOUT
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
P6.5/A5/DAC1†
64
PIN
NO.
80
PIN
113
PIN
34
34
35
I/O
DESCRIPTION
M8
I/O
35
L9
I/O
36
37
38
39
40
41
42
43
36
37
38
39
40
41
42
43
M9
J9
M10
L10
M11
M12
L12
K11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O pin/USCI A1 transmit data output in UART mode, slave data
in/master out in SPI mode
General-purpose digital I/O pin/USCIA1 receive data input in UART mode, slave data
out/master in in SPI mode
General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output
General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output
General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output
General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output
General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output
General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output
General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output
General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
44
44
K12
I/O
General-purpose digital I/O pin/USCI B1 slave transmit enable/USCI A1 clock input/output
45
45
J11
I/O
46
46
J12
I/O
General-purpose digital I/O pin/USCI B1slave in/master out in SPI mode, SDA I 2C data in
I2C mode
General-purpose digital I/O pin/USCI B1slave out/master in in SPI mode, SCL I 2C clock in
I2C mode
47
47
H11
I/O
General-purpose digital I/O/USCI B1 clock input/output, USCI A1 slave transmit enable
48
49
50
48
49
50
H12
G11
G12
I/O
I/O
I/O
51
51
F11
I/O
59
60
61
2
3
75
76
77
2
3
I/O
I/O
I/O
I/O
I/O
4
4
D4
A4
B4
B1
C1
C2
C3
D1
General-purpose digital I/O pin/main system clock MCLK output
General-purpose digital I/O pin/submain system clock SMCLK output
General-purpose digital I/O pin/auxiliary clock ACLK output
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance Timer_B TB0 to TB6/SVS comparator output
General-purpose digital I/O pin/analog input A0 – 12-bit ADC
General-purpose digital I/O pin/analog input A1 – 12-bit ADC
General-purpose digital I/O pin/analog input A2 – 12-bit ADC
General-purpose digital I/O pin/analog input A3 – 12-bit ADC
General-purpose digital I/O pin/analog input A4 – 12-bit ADC
I/O
General-purpose digital I/O pin/analog input A5 – 12-bit ADC/DAC12.1 output
I/O
General-purpose digital I/O pin/analog input A6 – 12-bit ADC/DAC12.0 output
D2
I/O
General-purpose digital I/O pin/analog input a7 – 12-bit ADC/DAC12.1 output/SVS input
E11
D12
D11
C12
C11
B12
A12
A11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
P6.6/A6/DAC0†
5
5
P6.7/A7/DAC1†/
6
6
SVSIN
P7.0
54
P7.1
55
P7.2
56
P7.3
57
P7.4
58
P7.5
59
P7.6
60
P7.7
61
† MSP430F261x devices only
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Terminal Functions (Continued)
TERMINAL
NAME
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6/XT2OUT
64
PIN
NO.
80
PIN
62
63
64
65
66
67
68
113
PIN
B10
A10
D9
A9
B9
B8
A8
69
A7
I/O
DESCRIPTION
I/O
I/O
I/O
I/O
I/O
I/O
O
XT2OUT
XT2IN
52
53
RST/NMI
58
74
B5
I
TCK
57
73
A5
I
TDI/TCLK
TDO/TDI
TMS
VeREF+/DAC0†
VREF+
55
54
56
10
7
71
70
72
10
7
A6
B7
B6
F2
E2
I
I/O
I
I
O
VREF--/VeREF--
11
11
G1
I
XIN
XOUT
8
9
8
9
I
O
Reserved
-
-
E1
F1
L2, E4
F4, G4
H4, D5
E5, F5
G5, H5
J5, D6
E6, H6
J6, D7
E7, H7
J7, D8
E8, F8
G8, H8
J8, E9
F9, G9
H9, B11
L11
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin/Output terminal of crystal oscillator XT2
General-purpose digital I/O pin/Input port for crystal oscillator XT2. Only standard
crystals can be connected.
Output terminal of crystal oscillator XT2
Input port for crystal oscillator XT2
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in flash
devices).
Test clock (JTAG). TCKis theclock inputport fordevice programmingtest andbootstrap
loader start.
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
Test data output port. TDO/TDI data output or programming data input terminal.
Test mode select. TMS is used as an input port for device programming and test.
Input for an external reference voltage/DAC12.0 output
Output of positive terminal of the reference voltage in the ADC12
Negative terminal for the reference voltage for both sources, the internal reference
voltage, or an external applied reference voltage
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
Output port for crystal oscillator XT1. Standard or watch crystals can be connected.
NA
Reserved pins. Connection to D/AVSS recommended.
P8.7/XT2IN
† MSP430F261x devices only
12
I
O
I
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g., ADD R4,R5
e.g., CALL R8
e.g., JNE
R4 + R5 - - - > R5
PC - - >(TOS), R8-- - > PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D
SYNTAX
Register
D D
MOV Rs,Rd
Indexed
D D
MOV X(Rn),Y(Rm)
Symbolic (PC relative) D D
MOV EDE,TONI
Absolute
D D MOV &MEM,&TCDAT
Indirect
D
MOV @Rn,Y(Rm)
Indirect
D
MOV @Rn+,Rm
autoincrement
Immediate
D
MOV #X,TONI
NOTE: S = source
D = destination
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OPERATION
R10 - - > R11
M(2+R5)-- - > M(6+R6)
M(EDE) - - > M(TONI)
M(MEM) - - > M(TCDAT)
M(R10) - - > M(Tab+R6)
M(R10) - - > R11
R10 + 2-- - > R10
#45 - - > M(TONI)
13
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
-- All clocks are active.
D Low-power mode 0 (LPM0)
-- CPU is disabled.
-- ACLK and SMCLK remain active. MCLK is disabled.
D Low-power mode 1 (LPM1)
-- CPU is disabled.
-- ACLK and SMCLK remain active. MCLK is disabled.
-- DCO’s dc generator is disabled if DCO not used in active mode.
D Low-power mode 2 (LPM2)
-- CPU is disabled.
-- MCLK and SMCLK are disabled.
-- DCO’s dc generator remains enabled.
-- ACLK remains active.
D Low-power mode 3 (LPM3)
-- CPU is disabled.
-- MCLK and SMCLK are disabled.
-- DCO’s dc generator is disabled.
-- ACLK remains active.
D Low-power mode 4 (LPM4)
-- CPU is disabled.
-- ACLK is disabled.
-- MCLK and SMCLK are disabled.
-- DCO’s dc generator is disabled.
-- Crystal oscillator is stopped.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0x0FFFF to 0x0FFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset
vector (0x0FFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU enters LPM4 after power-up.
INTERRUPT SOURCE
Power-up
External Reset
Watchdog
Violation
PC out of range (see Note 1)
NMI
Oscillator Fault
Flash memory access violation
Flash Key
Timer_B7
Timer_B7
Comparator_A+
Watchdog timer+
Timer_A3
Timer_A3
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
ADC12
I/O port P2 (eight flags)
I/O port P1 (eight flags)
USCI_A0/USCI_B1 receive
USCI_B1 I2C status
USCI_A1/USCI_B1 transmit
USCI_B1 I2C receive/transmit
DMA
DAC12
INTERRUPT FLAG
PORIFG
WDTIFG
RSTIFG
KEYV (see Note 2)
SYSTEM INTERRUPT
WORD ADDRESS PRIORITY
Reset
0x0FFFE
31, highest
NMIIFG
OFIFG
ACCVIFG (see Notes 2 and 6)
TBCCR0 CCIFG
(see Note 3)
TBCCR1 to TBCCR6 CCIFGs, TBIFG
(see Notes 2 and 3)
CAIFG
WDTIFG
TACCR0 CCIFG (see Note 3)
TACCR1 CCIFG
TACCR2 CCIFG
TAIFG (see Notes 2 and 3)
UCA0RXIFG, UCB0RXIFG
(see Notes 2 and 4)
UCA0TXIFG, UCB0TXIFG
(see Note 2 and 5)
ADC12IFG (see Notes 2 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0x0FFFC
30
Maskable
0x0FFFA
29
Maskable
0x0FFF8
28
Maskable
Maskable
Maskable
0x0FFF6
0x0FFF4
0x0FFF2
27
26
25
Maskable
0x0FFF0
24
Maskable
0x0FFEE
23
Maskable
0x0FFEC
22
Maskable
P2IFG.0 to P2IFG.7 (see Notes 2 and 3)
P1IFG.0 to P1IFG.7 (see Notes 2 and 3)
UCA1RXIFG, UCB1RXIFG
(see Notes 2 and 4)
UCA1TXIFG, UCB1TXIFG
(see Notes 2 and 5)
DMA0IFG, DMA1IFG, DMA2IFG
(see Notes 2 and 3)
DAC12_0IFG, DAC12_1IFG
(see Notes 2 and 3)
Maskable
Maskable
0x0FFEA
0x0FFE8
0x0FFE6
0x0FFE4
21
20
19
18
Maskable
0x0FFE2
17
Maskable
0x0FFE0
16
Maskable
0x0FFDE
15
Maskable
0x0FFDC
14
0x0FFDA to
13 to 0,
0
Reserved (see Notes 7 and 8)
Reserved
0 0FFC0
0x0FFC0
l
lowest
t
NOTES: 1. A reset isexecuted ifthe CPUtries tofetch instructionsfrom withinthe moduleregister memoryaddress range(0x00000 to0x001FF)
or from within unused address ranges.
2. Multiple source flags.
3. Interrupt flags are located in the module.
4. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
5. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
6. (Non)maskable: The individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot.
7. The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY).
A 0x0AA55 at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
8. The interrupt vectors at addresses 0x0FFDA to 0x0FFC0 are not used in this device and can be used for regular program code if
necessary.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
special function registers
Most interrupt enable bits are collected in the lowest address space. Special-function register bits not allocated
to a functional purpose are not physically present in the device. This arrangement provides simple software
access.
interrupt enable 1 and 2
Address
00h
WDTIE
OFIE
NMIIE
ACCVIE
Address
01h
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
16
7
6
5
ACCVIE
rw-- 0
4
NMIIE
rw-- 0
3
2
1
OFIE
rw-- 0
0
WDTIE
rw-- 0
Interrupt Enable Register 1
Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as general-purpose timer.
Oscillator fault interrupt enable
Nonmaskable interrupt enable
Flash memory access violation interrupt enable
7
6
5
4
3
2
1
0
UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw-- 0
rw-- 0
rw-- 0
rw-- 0
Interrupt Enable Register 2
USCI_A0 receive interrupt enable
USCI_A0 transmit interrupt enable
USCI_B0 receive interrupt enable
USCI_B0 transmit interrupt enable
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
interrupt flag register 1 and 2
Address
02h
7
WDTIFG
6
5
4
NMIIFG
rw-- 0
3
RSTIFG
rw-- (0)
2
PORIFG
rw-- (1)
1
OFIFG
rw-- 1
0
WDTIFG
rw-- (0)
Interrupt Flag Register 1
NMIIFG
Set on watchdog timer overflow or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault7
Power-on interrupt flag. Set on VCC power up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset
on VCC power up.
Set via RST/NMI pin
Address
7
OFIFG
PORIFG
RSTIFG
6
5
4
03h
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
L eg e n d
rw :
rw -0 ,1 :
rw -(0 ,1 )
3
UCB0TX
IFG
rw-- 1
2
UCB0RX
IFG
rw-- 0
1
UCA0TX
IFG
rw-- 1
0
UCA0RX
IFG
rw-- 0
Interrupt Flag Register 2
USCI_A0 receive interrupt flag
USCI_A0 transmit interrupt flag
USCI_B0 receive interrupt flag
USCI_B0 transmit interrupt flag
B it ca n b e rea d a n d w ritten .
B it ca n b e rea d a n d w ritten . It is R e s et o r S e t b y P U C .
B it ca n b e rea d a n d w ritten . It is R e s et o r S e t b y P O R .
S F R b it is n o t p re s en t in d e vice .
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17
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
memory organization
Memory
Main: interrupt vector
Main: code memory
RAM (total)
Size
Flash
Flash
Size
Extended
Size
Mirrored
Size
Information memory
Boot memory
RAM (mirrored at
0x18FF to 0x01100)
Peripherals
Memory
Main: interrupt vector
Main: code memory
RAM (total)
Size
Flash
Size
ROM
Size
16-bit
8-bit
8-bit SFR
Size
Flash
Flash
Size
Extended
Size
Mirrored
Size
Information memory
Boot memory
RAM (mirrored at
0x18FF to 0x01100)
Peripherals
MSP430F2416
MSP430F2616
MSP430F2417
MSP430F2617
92KB
0x0FFFF - 0x0FFC0
0x18FFF - 0x02100
4kB
0x020FF - 0x01100
2kB
0x020FF - 0x01900
2kB
0x018FF - 0x01100
256 Byte
0x010FF - 0x01000
1KB
0x00FFF - 0x00C00
2KB
0x009FF - 0x00200
0x001FF - 0x00100
0x000FF - 0x00010
0x0000F - 0x00000
92KB
0x0FFFF - 0x0FFC0
0x19FFF - 0x03100
8kB
0x030FF - 0x01100
6kB
0x030FF - 0x01900
2kB
0x018FF - 0x01100
256 Byte
0x010FF - 0x01000
1KB
0x00FFF - 0x00C00
2KB
0x009FF - 0x00200
0x001FF - 0x00100
0x000FF - 0x00010
0x0000F - 0x00000
MSP430F2618
MSP430F2418
MSP430F2619
MSP430F2419
116KB
0x0FFFF - 0x0FFC0
0x1FFFF - 0x03100
8kB
0x030FF - 0x01100
6kB
0x030FF - 0x01900
2kB
0x018FF - 0x01100
256 Byte
0x010FF - 0x01000
1KB
0x00FFF - 0x00C00
2KB
0x009FF - 0x00200
0x001FF - 0x00100
0x000FF - 0x00010
0x0000F - 0x00000
Size
Flash
Size
ROM
Size
16-bit
8-bit
8-bit SFR
120KB
0x0FFFF - 0x0FFC0
0x1FFFF - 0x02100
4kB
0x020FF - 0x01100
2kB
0x020FF - 0x01900
2kB
0x018FF - 0x01100
256 Byte
0x010FF - 0x01000
1KB
0x00FFF - 0x00C00
2KB
0x009FF - 0x00200
0x001FF - 0x00100
0x000FF - 0x00010
0x0000F - 0x00000
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by a user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.
BSL FUNCTION
Data Transmit
Data Receive
18
PM, PN PACKAGE PINS
13 - P1.1
22 - P2.2
ZQW PACKAGE PINS
H1 - P1.1
M3 - P2.2
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MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset, segment A is protected against programming or erasing.
It can be unlocked, but care should be taken not to erase this segment if the calibration data is required.
D Flash content integrity check with marginal read modes
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide, literature number
SLAU144.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430x241x and MSP43x261x family of devices is supported by the basic clock
module that includes support for a 32768-Hz watch crystal oscillator, an internal very low-power low-frequency
oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the
following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or a very
low-power LF oscillator
D Main clock (MCLK), the system clock used by the CPU
D Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
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19
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
calibration data stored in information memory segment A
Calibration data is stored for the DCO and for the ADC12. It is organized in a tag-length-value (TLV) structure.
NAME
TAG_DCO_30
TAG_ADC12_1
TAG_EMPTY
ADDRESS
0x10F6
0x10DA
-
LABEL
CAL_ADC_25T85
CAL_ADC_25T30
CAL_ADC_25VREF_FACTOR
CAL_ADC_15T85
CAL_ADC_15T30
CAL_ADC_15VREF_FACTOR
CAL_ADC_OFFSET
CAL_ADC_GAIN_FACTOR
CAL_BC1_1MHZ
CAL_DCO_1MHZ
CAL_BC1_8MHZ
CAL_DCO_8MHZ
CAL_BC1_12MHZ
CAL_DCO_12MHZ
CAL_BC1_16MHZ
CAL_DCO_16MHZ
TAGS USED BY THE TLV STRUCTURE
VALUE
DESCRIPTION
0x01 DCO frequency calibration at VCC = 3 V and TA = 25°C at calibration
0x08 ADC12_1 calibration tag
0xFE Identifier for empty memory areas
LABELS USED BY THE ADC CALIBRATION STRUCTURE
CONDITION AT CALIBRATION / DESCRIPTION
INCHx = 0x1010; REF2_5 = 1, TA = 85°C
INCHx = 0x1010; REF2_5 = 1, TA = 30°C
REF2_5 = 1, TA = 30°C
INCHx = 0x1010; REF2_5 = 0, TA = 85°C
INCHx = 0x1010; REF2_5 = 0, TA = 30°C
REF2_5 = 0, TA = 30°C
External VREF = 1.5 V, fADC12CLK = 5 MHz
External VREF = 1.5 V, fADC12CLK = 5 MHz
-
SIZE
word
word
word
word
word
word
word
word
byte
byte
byte
byte
byte
byte
byte
byte
ADDRESS OFFSET
0x000E
0x000C
0x000A
0x0008
0x0006
0x0004
0x0002
0x0000
0x0007
0x0006
0x0005
0x0004
0x0003
0x0002
0x0001
0x0000
brownout, supply voltage supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports
both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM) (the
device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not changed until
VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are up to eight 8-bit I/O ports implemented—ports P1 through P8:
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all eight bits of ports P1 and P2.
D Read/write access to port-control registers is supported by all instructions.
D Each I/O has an individually programmable pullup/pulldown resistor.
D Ports P7/P8 can be accessed word-wise.
20
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MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
watchdog timer+ (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16,
16×8, 8×16, and 8×8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
universal serial communication interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin) or I2C, and asynchronous combination protocols such as
UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
The USCI A module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, and IrDA.
The USCI B module provides support for SPI (3 pin or 4 pin) and I2C.
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21
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
INPUT PIN
NUMBER
(ZQW)
G2 - P1.0
M2 - P2.1
H1 - P1.1
M3 - P2.2
H2 - P1.2
J1 - P1.3
22
INPUT PIN
NUMBER
(PM, PN)
12 - P1.0
21 - P2.1
13 - P1.1
22 - P2.2
14 - P1.2
15 - P1.3
DEVICE
INPUT
SIGNAL
TACLK
ACLK
SMCLK
TAINCLK
TA0
TA0
DVSS
DVCC
TA1
CAOUT
(internal)
DVSS
DVCC
TA2
ACLK
(internal)
DVSS
DVCC
TIMER_A3 SIGNAL CONNECTIONS
MODULE
INPUT NAME
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
VCC
CCI1A
CCI1B
GND
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
CCR1
TA0
TA1
CCI2A
CCI2B
GND
VCC
CCR2
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TA2
OUTPUT PIN OUTPUT PIN
NUMBER
NUMBER
(PM, PN)
(ZQW)
13 - P1.1
17 - P1.5
27 - P2.7
H1 - P1.1
K1 - P1.5
L5 - P2.7
14 - P1.2
H2 - P1.2
18 - P1.6
K2 - P1.6
23 - P2.3
L3 - P2.3
ADC12 (internal)
DAC12_0 (internal)
DAC12_1 (internal)
15 - P1.3
J1 - P1.3
19 - P1.7
L1 - P1.7
24 - P2.4
L4 - P2.4
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
INPUT PIN
NUMBER
(ZQW)
K11 - P4.7
INPUT PIN
NUMBER
(PM, PN)
43 - P4.7
K11 - P4.7
M9 - P4.0
M9-- P4.0
43 - P4.7
36 - P4.0
36 - P4.0
J9 - P4.1
J9 - P4.1
37 - P4.1
37 - P4.1
M10 - P4.2
M10 - P4.2
38 - P4.2
38 - P4.2
L10 - P4.3
L10 - P4.3
39 - P4.3
39 - P4.3
M11 - P4.4
M11 - P4.4
40 - P4.4
40 - P4.4
M12 - P4.5
M12 - P4.5
41 - P4.5
41 - P4.5
L12 - P4.6
42 - P4.6
TIMER_B3/B7 SIGNAL CONNECTIONS†
DEVICE
MODULE
MODULE
MODULE
INPUT
OUTPUT
INPUT NAME
BLOCK
SIGNAL
SIGNAL
TBCLK
ACLK
SMCLK
TBCLK
TB0
TB0
DVSS
DVCC
TB1
TB1
DVSS
DVCC
TB2
TB2
DVSS
DVCC
TB3
TB3
DVSS
DVCC
TB4
TB4
DVSS
DVCC
TB5
TB5
DVSS
DVCC
TB6
ACLK
(internal)
DVSS
DVCC
TBCLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
VCC
CCI1A
CCI1B
GND
VCC
CCI2A
CCI2B
GND
VCC
CCI3A
CCI3B
GND
VCC
CCI4A
CCI4B
GND
VCC
CCI5A
CCI5B
GND
VCC
CCI6A
CCI6B
GND
VCC
Timer
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OUTPUT PIN OUTPUT PIN
NUMBER
NUMBER
(PM, PN)
(ZQW)
NA
TB0
TB1
TB2
36 - P4.0
M9 - P4.0
ADC12 (internal)
37 - P4.1
J9 - P4.1
ADC12 (internal)
38 - P4.2
M10 - P4.2
DAC_0(internal)
DAC_1(internal)
39 - P4.3
L10 - P4.3
40 - P4.4
M11 - P4.4
41 - P4.5
M12 - P4.5
42 - P4.6
L12 - P4.6
TB3
TB4
TB5
TB6
23
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage-output digital-to-analog converter (DAC). The DAC12 may be
used in 8-bit or 12-bit mode and may be used in conjunction with the DMA controller. When multiple DAC12
modules are present, they may be grouped together for synchronous operation.
24
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MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
peripheral file map
PERIPHERAL FILE MAP
DMA channel 2 transfer size
DMA channel 2 destination address
DMA channel 2 source address
DMA channel 2 control
DMA channel 1 transfer size
DMA channel 1 destination address
DMA channel 1 source address
DMA channel 1 control
DMA channel 0 transfer size
DMA channel 0 destination address
DMA channel 0 source address
DMA channel 0 control
DMA module interrupt vector word
DMA module control 1
DMA module control 0
DAC12†
DAC12_1 data
DAC12_1 control
DAC12_0 data
DAC12_0 control
ADC12
Interrupt-vector-word register
Inerrupt-enable register
Inerrupt-flag register
Control register 1
Control register 0
Conversion memory 15
Conversion memory 14
Conversion memory 13
Conversion memory 12
Conversion memory 11
Conversion memory 10
Conversion memory 9
Conversion memory 8
Conversion memory 7
Conversion memory 6
Conversion memory 5
Conversion memory 4
Conversion memory 3
Conversion memory 2
Conversion memory 1
Conversion memory 0
† MSP430F261x devices only
DMA†
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DMA2SZ
DMA2DA
DMA2SA
DMA2CTL
DMA1SZ
DMA1DA
DMA1SA
DMA1CTL
DMA0SZ
DMA0DA
DMA0SA
DMA0CTL
DMAIV
DMACTL1
DMACTL0
DAC12_1DAT
DAC12_1CTL
DAC12_0DAT
DAC12_0CTL
ADC12IV
ADC12IE
ADC12IFG
ADC12CTL1
ADC12CTL0
ADC12MEM15
ADC12MEM14
ADC12MEM13
ADC12MEM12
ADC12MEM11
ADC12MEM10
ADC12MEM9
ADC12MEM8
ADC12MEM7
ADC12MEM6
ADC12MEM5
ADC12MEM4
ADC12MEM3
ADC12MEM2
ADC12MEM1
ADC12MEM0
0x01F2
0x01EE
0x01EA
0x01E8
0x01E6
0x01E2
0x01DE
0x01DC
0x01DA
0x01D6
0x01D2
0x01D0
0x0126
0x0124
0x0122
0x01CA
0x01C2
0x01C8
0x01C0
0x01A8
0x01A6
0x01A4
0x01A2
0x01A0
0x015E
0x015C
0x015A
0x0158
0x0156
0x0154
0x0152
0x0150
0x014E
0x014C
0x014A
0x0148
0x0146
0x0144
0x0142
0x0140
25
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
ADC12
(continued)
Timer_B7
_
Timer_A3
_
26
PERIPHERAL FILE MAP (CONTINUED)
ADC memory-control register15
ADC memory-control register14
ADC memory-control register13
ADC memory-control register12
ADC memory-control register11
ADC memory-control register10
ADC memory-control register9
ADC memory-control register8
ADC memory-control register7
ADC memory-control register6
ADC memory-control register5
ADC memory-control register4
ADC memory-control register3
ADC memory-control register2
ADC memory-control register1
ADC memory-control register0
Capture/compare register 6
Capture/compare register 5
Capture/compare register 4
Capture/compare register 3
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_B register
Capture/compare control 6
Capture/compare control 5
Capture/compare control 4
Capture/compare control 3
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_B control
Timer_B interrupt vector
Capture/compare register 2
Capture/compare register 1
Capture/compare register 0
Timer_A register
Reserved
Reserved
Reserved
Reserved
Capture/compare control 2
Capture/compare control 1
Capture/compare control 0
Timer_A control
Timer_A interrupt vector
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ADC12MCTL15
ADC12MCTL14
ADC12MCTL13
ADC12MCTL12
ADC12MCTL11
ADC12MCTL10
ADC12MCTL9
ADC12MCTL8
ADC12MCTL7
ADC12MCTL6
ADC12MCTL5
ADC12MCTL4
ADC12MCTL3
ADC12MCTL2
ADC12MCTL1
ADC12MCTL0
TBCCR6
TBCCR5
TBCCR4
TBCCR3
TBCCR2
TBCCR1
TBCCR0
TBR
TBCCTL6
TBCCTL5
TBCCTL4
TBCCTL3
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
TBIV
TACCR2
TACCR1
TACCR0
TAR
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
0x008F
0x008E
0x008D
0x008C
0x008B
0x008A
0x0089
0x0088
0x0087
0x0086
0x0085
0x0084
0x0083
0x0082
0x0081
0x0080
0x019E
0x019C
0x019A
0x0198
0x0196
0x0194
0x0192
0x0190
0x018E
0x018C
0x018A
0x0188
0x0186
0x0184
0x0182
0x0180
0x011E
0x0176
0x0174
0x0172
0x0170
0x016E
0x016C
0x016A
0x0168
0x0166
0x0164
0x0162
0x0160
0x012E
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Hardware
Multiplier
Flash
Watchdog
USCI A0/B0
/
USCI A1/B1
/
PERIPHERAL FILE MAP (CONTINUED)
Sum extend
Result high word
Result low word
Second operand
Multiply signed +accumulate/operand1
Multiply+accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
Flash control 4
Flash control 3
Flash control 2
Flash control 1
Watchdog Timer control
USCI A0 auto baud rate control
USCI A0 transmit buffer
USCI A0 receive buffer
USCI A0 status
USCI A0 modulation control
USCI A0 baud rate control 1
USCI A0 baud rate control 0
USCI A0 control 1
USCI A0 control 0
USCI A0 IrDA receive control
USCI A0 IrDA transmit control
USCI B0 transmit buffer
USCI B0 receive buffer
USCI B0 status
USCI B0 I2C Interrupt enable
USCI B0 baud rate control 1
USCI B0 baud rate control 0
USCI B0 control 1
USCI B0 control 0
USCI B0 I2C slave address
USCI B0 I2C own address
USCI A1 auto baud rate control
USCI A1 transmit buffer
USCI A1 receive buffer
USCI A1 status
USCI A1 modulation control
USCI A1 baud rate control 1
USCI A1 baud rate control 0
USCI A1 control 1
USCI A1 control 0
USCI A1 IrDA receive control
USCI A1 IrDA transmit control
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SUMEXT
RESHI
RESLO
OP2
MACS
MAC
MPYS
MPY
FCTL4
FCTL3
FCTL2
FCTL1
WDTCTL
UCA0ABCTL
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCLT
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0CIE
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
UCB0OA
UCA1ABCTL
UCA1TXBUF
UCA1RXBUF
UCA1STAT
UCA1MCTL
UCA1BR1
UCA1BR0
UCA1CTL1
UCA1CTL0
UCA1IRRCTL
UCA1IRTCLT
0x013E
0x013C
0x013A
0x0138
0x0136
0x0134
0x0132
0x0130
0x01BE
0x012C
0x012A
0x0128
0x0120
0x005D
0x0067
0x0066
0x0065
0x0064
0x0063
0x0062
0x0061
0x0060
0x005F
0x005E
0x006F
0x006E
0x006D
0x006C
0x006B
0x006A
0x0069
0x0068
0x011A
0x0118
0x00CD
0x00D7
0x00D6
0x00D5
0x00D4
0x00D3
0x00D2
0x00D1
0x00D0
0x00CF
0x00CE
27
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
USCI A1/B1
/
(continued)
PERIPHERAL FILE MAP (CONTINUED)
USCI B1 transmit buffer
USCI B1 receive buffer
USCI B1 status
USCI B1 I2C Interrupt enable
USCI B1 baud rate control 1
USCI B1 baud rate control 0
USCI B1 control 1
USCI B1 control 0
USCI B1 I2C slave address
USCI B1 I2C own address
USCI A1/B1 interrupt enable
USCI A1/B1 interrupt flag
Comparator_A+
p
_
Comparator_A port disable
Comparator_A control2
Comparator_A control1
Basic Clock
Basic clock system control3
Basic clock system control2
Basic clock system control1
DCO clock frequency control
Brownout, SVS
SVS control register (reset by brownout signal)
Port PA†
Port PA resistor enable
Port PA selection
Port PA direction
Port PA output
Port PA input
Port P8†
Port P8 resistor enable
Port P8 selection
Port P8 direction
Port P8 output
Port P8 input
Port P7†
Port P7 resistor enable
Port P7 selection
Port P7 direction
Port P7 output
Port P7 input
Port P6
Port P6 resistor enable
Port P6 selection
Port P6 direction
Port P6 output
Port P6 input
Port P5
Port P5 resistor enable
Port P5 selection
Port P5 direction
Port P5 output
Port P5 input
† 80-pin PN and 113-pin ZQW devices only
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UCB1TXBUF
UCB1RXBUF
UCB1STAT
UCB1CIE
UCB1BR1
UCB1BR0
UCB1CTL1
UCB1CTL0
UCB1SA
UCB1OA
UC1IE
UC1IFG
CAPD
CACTL2
CACTL1
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
SVSCTL
PAREN
PASEL
PADIR
PAOUT
PAIN
P8REN
P8SEL
P8DIR
P8OUT
P8IN
P7REN
P7SEL
P7DIR
P7OUT
P7IN
P6REN
P6SEL
P6DIR
P6OUT
P6IN
P5REN
P5SEL
P5DIR
P5OUT
P5IN
0x00DF
0x00DE
0x00DD
0x00DC
0x00DB
0x00DA
0x00D9
0x00D8
0x017E
0x017C
0x0006
0x0007
0x005B
0x005A
0x0059
0x0053
0x0058
0x0057
0x0056
0x0055
0x0014
0x003E
0x003C
0x003A
0x0038
0x0015
0x003F
0x003D
0x003B
0x0039
0x0014
0x003E
0x003C
0x003A
0x0038
0x0013
0x0037
0x0036
0x0035
0x0034
0x0012
0x0033
0x0032
0x0031
0x0030
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P4
Port P3
Port P2
Port P1
Special
p
Functions
PERIPHERAL FILE MAP (CONTINUED)
Port P4 selection
Port P4 resistor enable
Port P4 direction
Port P4 output
Port P4 input
Port P3 resistor enable
Port P3 selection
Port P3 direction
Port P3 output
Port P3 input
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P4SEL
P4REN
P4DIR
P4OUT
P4IN
P3REN
P3SEL
P3DIR
P3OUT
P3IN
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
IFG2
IFG1
IE2
IE1
0x001F
0x0011
0x001E
0x001D
0x001C
0x0010
0x001B
0x001A
0x0019
0x0018
0x002F
0x002E
0x002D
0x002C
0x002B
0x002A
0x0029
0x0028
0x0027
0x0026
0x0025
0x0024
0x0023
0x0022
0x0021
0x0020
0x0003
0x0002
0x0001
0x0000
29
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
absolute maximum ratings (see Note 1)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature: Unprogrammed device (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C
Programmed device (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 105°C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification, with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
PARAMETER
Supply voltage during program execution, VCC
Supply voltage during flash memory programming, V CC
Supply voltage, VSS
MIN
MAX UNIT
AVCC = DVCC = VCC (see Note 1)
1.8
3.6
V
AVCC = DVCC = VCC (see Note 1)
2.2
3.6
V
AVSS = DVSS = VSS
0.0
0.0
V
I version
- 40
85
Operating free-air
free air temperature,
temperature TA
°C
T version
- 40
105
VCC = 1.8 V,
dc
4.15
Duty cycle = 50% ± 10%
VCC = 2.7 V,
Processor frequency fSYSYTEM (maximum MCLK frequency)
dc
12 MHz
Duty cycle = 50% ± 10%
(see Notes 2 and 3 and Figure
g 1)
VCC ≥ 3.3 V,
dc
16
Duty cycle = 50% ± 10%
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AV CC and DVCC can
be tolerated during power-up.
2. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
3. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend:
16 MHz
z
H
M
- 12 MHz
yc
ne
uq
er
F 7.5 MHz
m
tes
yS
4.15 MHz
Supply voltage range
during flash memory
programming
Supply voltage range
during program execution
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage - V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V CC of 2.2 V.
Figure 1. Operating Area
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current into VCC excluding external current (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN TYP MAX UNIT
fDCO = fMCLK = fSMCLK = 1 MHz,
- 40_C to 85_C
365 395
fACLK = 32768 Hz,
Hz
22V
2.2
executes from flash,
105_C
375 420
mode (AM) Program
IAM, 1MHz Active
µA
BCSCTL1
=
CALBC1_1MHZ,
CALBC1
1MHZ
current (1 MHz)
- 40_C to 85_C
515 560
DCOCTL = CALDCO_1MHZ,
_
3V
CPUOFF = 0,
0 SCG0 = 0,
0 SCG1 = 0,
0
105_C
525 595
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 1 MHz,
- 40_C to 85_C
330 370
fACLK = 32768 Hz,
Hz
22V
2.2
executes in RAM,
105_C
340 390
mode (AM) Program
IAM, 1MHz Active
µA
BCSCTL1
=
CALBC1_1MHZ,
CALBC1
1MHZ
current (1 MHz)
- 40_C to 85_C
460 495
DCOCTL = CALDCO_1MHZ,
_
3V
CPUOFF = 0,
0 SCG0 = 0,
0 SCG1 = 0,
0
105_C
470 520
OSCOFF = 0
fMCLK = fSMCLK =
- 40_C to 85_C
2.1
9
fACLK = 32768 Hz/8 = 4096 Hz,
22V
2.2
fDCO = 0 Hz,
105_C
15
31
Active mode (AM) Program executes in flash,
IAM, 4kHz
µA
current (4 kHz)
SELMx = 11, SELS = 1,
40
_C to 85_C
3
11
DIVMx = DIVSx = DIVAx = 11,
3V
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
105_C
19
32
OSCOFF = 0
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100 kHz,
- 40_C to 85_C
67
86
22V
2.2
fACLK = 0 Hz,
Hz
105_C
80
99
mode (AM) Program executes in flash,
IAM,100kHz Active
µA
current (100 kHz) RSELx = 0, DCOx = 0,
- 40_C to 85_C
84 107
CPUOFF = 0,
0 SCG0 = 0,
0 SCG1 = 0,
0
3V
105_C
99 128
OSCOFF = 1
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a micro crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
31
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
typical characteristics - active mode supply current (into DV + AV )
CC
CC
7.0
10.0
fDCO = 16 MHz
9.0
A
m
-t
ne
rr
uC
ed
o
M
ev
it
cA
8.0
6.0
A
m 5.0
-t
ne
rr
uC 4.0
ed
o 3.0
M
ev
it
cA 2.0
fDCO = 12 MHz
7.0
6.0
5.0
fDCO = 8 MHz
4.0
3.0
2.0
1.0
fDCO = 1 MHz
1.0
0.0
1.5
2.0
2.5
3.0
3.5
CC - Supply Voltage - V
4.0
0.0
0.0
V
Figure 2. Active Mode Current vs VCC, TA = 25°C
32
TA = 85 °C
TA = 25 °C
VCC = 3 V
TA = 85 °C
TA = 25 °C
VCC = 2.2 V
4.0
8.0
12.0
fDCO - DCO Frequency - MHz
16.0
Figure 3. Active Mode Current vs DCO Frequency
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low-power mode supply current into VCC excluding external current (see Notes 1 and 2)
PARAMETER
ILPM0, 1MHz
ILPM0,
100kHz
ILPM2
ILPM3,LFXT1
ILPM3,VLO
NOTES: 1.
2.
3.
4.
TEST CONDITIONS
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
MHz
Low-power mode 0 fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
(LPM0) current,
current
DCOCTL = CALDCO_1MHZ,
_
see Note 3
CPUOFF = 1,
1 SCG0 = 0,
0 SCG1 = 0,
0
OSCOFF = 0
fMCLK = 0MHz,
kHz
DCO(0, 0) ≈ 100 kHz,
Low-power mode 0 ffSMCLK= =0 fHz,
ACLK
(LPM0) current,
current
RSELx = 0, DCOx = 0,
see Note 3
CPUOFF = 1,
1 SCG0 = 0,
0 SCG1 = 0,
0
OSCOFF = 1
fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz,
fACLK = 32768 Hz,
Hz
Low-power mode 2 BCSCTL1
=
CALBC1_1MHZ,
(LPM2) current,
current
DCOCTL = CALDCO_1MHZ,
see Note 4
CPUOFF = 1,
1 SCG0 = 0,
0 SCG1 = 1,
1
OSCOFF = 0
TA
- 40_C to 85_C
105_C
- 40_C to 85_C
VCC
22V
2.2
MIN
TYP
68
MAX UNIT
83
83
98
87
105
µA
3V
105_C
100 125
- 40_C to 85_C
37
49
22V
2.2
105_C
50
62
µA
- 40_C to 85_C
40
55
3V
105_C
57
73
- 40_C to 85_C
23
33
22V
2.2
105_C
35
46
µA
- 40_C to 85_C
25
36
3V
105_C
40
55
- 40°C
0.8
1.2
25°C
1
1.3
22V
2.2
85°C
4.6
7
= fSMCLK = 0 MHz,
MHz
Low-power mode 3 ffDCO ==fMCLK
105
°
C
14
24
ACLK 32768 Hz,
µA
(LPM3) current,
current
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
- 40°C
0.9
1.3
see Note 4
OSCOFF = 0
25°C
1.1
1.5
3V
85°C
5.5
8
105°C
17
30
- 40°C
0.4
1.0
25°C
0.5
1.0
22V
2.2
85°C
4.3
6.5
fDCO = fMCLK = fSMCLK = 0 MHz,
MHz
105°C
14
24
Low-power mode 3 fACLK from internal LF oscillator (VLO),
µA
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
((LPM3)) current,
- 40°C
0.6
1.2
see Note
Nt 4
OSCOFF = 0
25°C
0.6
1.2
3V
85°C
5
7.5
105°C
16.5 29.5
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The currents are characterized with a micro crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Current for Brownout and WDT+ is included. The WDT+ is clocked by SMCLK.
Current for Brownout and WDT+ is included. The WDT+ is clocked by ACLK.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
33
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low-power mode supply current into VCC excluding external current (see Notes 1 and 2) (continued)
TA
VCC MIN TYP MAX UNIT
- 40°C
0.1
0.5
Low-power mode 4 fDCO = fMCLK = fSMCLK = 0 MHz,
MHz
25
°
C
0.1
0.5
(LPM4) current,
fACLK = 0 Hz,
ILPM4
2
2.2
2
V
see Note 3
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
85°C
4
6 µA
OSCOFF = 1
105°C
13
23
- 40°C
0.2
0.5
Low-power mode 4 fDCO = fMCLK = fSMCLK = 0 MHz,
MHz
25
°
C
0.2
0.5
(LPM4) current,
fACLK = 0 Hz,
ILPM4
3
V
see Note 3
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
85°C
4.7
7 µA
OSCOFF = 1
105°C
14
24
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a micro crystal CC4V-- T1A SMD crystalwith aload capacitanceof 9pF. Theinternal andexternal
load capacitance is chosen to closely match the required 9 pF.
3. Current for Brownout included.
PARAMETER
TEST CONDITIONS
typical characteristics - LPM4 current
Au
-t
ne
rr
uc
ed
o
m
re
w
op
w
oL
4
M
PL
I
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
Vcc = 3.6 V
7.0
Vcc = 3.0 V
6.0
5.0
Vcc = 2.2 V
4.0
3.0
2.0
1.0
Vcc = 1.8 V
0.0
- 40.0 - 20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
TA - Temperature - °C
Figure 4. ILPM4 - LPM4 Current vs Temperature
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Schmitt-trigger inputs - ports P1 through P8, RST/NMI, JTAG, XIN, and XT2IN (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
V
Positive-going
Positive
going input threshold voltage
2.2 V
3V
V
Negative-going
Negative
going input threshold voltage
V
Input voltage hysteresis (V
2.2 V
3V
2.2 V
3V
IT+
IT--
hys
R
Pull
IT+
-V )
IT--
Pullup: V = V ,
Pulldown: V = V
V = V or V
Pullup/pulldown resistor
IN
SS
IN
C
Input capacitance
NOTE 1: XIN and XT2IN in bypass mode only.
I
IN
SS
CC
MIN
TYP
0.45 VCC
CC
V
CC
35
5
CC
UNIT
CC
1.0
1.35
0.25 V
0.55
0.75
0.2
0.3
20
MAX
0.75 V
1.65
2.25
0.55 V
1.2
1.65
1.0
1.0
50
V
V
kΩ
pF
inputs -- ports P1 and P2
PARAMETER
TEST CONDITIONS
VCC
MIN MAX UNIT
Port
P1,
P2:
P1.x
to
P2.x,
external
trigger
pulse
width
to
t
External interrupt timing
2.2 V/3 V
20
ns
set the interrupt flag (see Note 1)
NOTE 1: The external signal sets the interrupt flag every time the minimum t parameters are met. It may be set with trigger signals shorter
than t .
int
(int)
(int)
leakage current -- ports P1 through P8 (see Note 1 and 2)
PARAMETER
TEST CONDITIONS
VCC
MIN MAX UNIT
I
High-impedance leakage current
see Notes 1 and 2
2.2 V/3 V
±50
nA
NOTES: 1. The leakage current is measured with V or V applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor isdisabled.
lkg (Px.x)
SS
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
35
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
standard inputs -- RST/NMI
VIL
VIH
PARAMETER
Low-level input voltage
High-level input voltage
TEST CONDITIONS
VCC
2.2 V/3 V
2.2 V/3 V
MIN
VSS
0.8×VCC
MAX
VSS+0.6
VCC
UNIT
V
V
outputs -- ports P1 through P8
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
IOH(max) = - 1.5 mA (see Note 1)
VCC - 0.25
VCC
22V
2.2
IOH(max) = - 6 mA (see Note 2)
VCC - 0.6
VCC
VOH
High level output voltage
High-level
V
IOH(max) = - 1.5 mA (see Note 1)
VCC - 0.25
VCC
3V
IOH(max) = - 6 mA (see Note 2)
VCC - 0.6
VCC
IOL(max) = 1.5 mA (see Note 1)
VSS VSS+0.25
22V
2.2
IOL(max) = 6 mA (see Note 2)
VSS VSS+0.6
VOL
Low level output voltage
Low-level
V
VSS VSS+0.25
IOL(max) = 1.5 mA (see Note 1)
3V
IOL(max) = 6 mA (see Note 2)
VSS VSS+0.6
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
voltage drop specified.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
voltage drop specified.
output frequency -- ports P1 through P8
PARAMETER
Port output frequency
with load
TEST CONDITIONS
VCC
MIN TYP
MAX UNIT
2.2 V
DC
10
P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ
fPx.y
MHz
(see Notes 1 and 2)
3.0 V
DC
12
2.2 V
DC
12
P2.0/ACLK/CA2, P1.4/SMCLK, CL = 20 pF
fPort_CLK Clock output frequency (see Note 2)
MHz
3.3 V
DC
16
P5.6/ACLK, CL = 20 pF, LF mode
30
50
70
P5.6/ACLK, CL = 20 pF, XT1 mode
40
50
60
%
P5.4/MCLK, CL = 20 pF, XT1 mode
40
60
Duty cycle of output
t(Xdc)
frequency
q
y
P5.4/MCLK, CL = 20 pF, DCO
50% - 15 ns
50 50% + 15 ns
P1.4/SMCLK, CL = 20 pF, XT2 mode
40
60
%
P1.4/SMCLK, CL = 20 pF, DCO
50% - 15 ns
50% + 15 ns
NOTES: 1. A resistive divider with 2 times 0.5 k Ω between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% V CC at the specified toggle frequency.
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
of one pin
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
of one pin
25.0
A
m
-t
ne20.0
rr
uC
tu
tpu15.0
O
le
ve
L- 10.0
w
oL
la
ci
py 5.0
-T
L
IO
CC = 2.2 V
V
A
m
-t
ne
rr
uC
tu
pt
u
O
le
ve
Lw
oL
la
ci
py
T
L
IO
A = 25°C
T
P4.5
A = 85°C
T
0.0
50.0
CC = 3 V
V
A = 25°C
P4.5
T
40.0
A = 85°C
T
30.0
20.0
10.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
OL
VOL -- Low-Level Output Voltage -- V
V
1.0
0.0
A
m
-t
ne --5.0
rr
uC
tu
tpu --10.0
O
le
ve
Lhg --15.0
iH
la
ci
py --20.0
T
H
IO
3.0
3.5
0.0
P4.5
A = 85°C
T
A = 25°C
T
--25.0
0.5
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
of one pin
A
m
-t
ne --10.0
rr
uC
tu
pt
u --20.0
O
le
ve
Lhg --30.0
iH
la
ci
py --40.0
T
H
IO
CC = 2.2 V
V
0.0
2.0
Figure 6
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
of one pin
1.5
-- Low-Level Output Voltage -- V
1.0
1.5
2.0
OH -- High-Level Output Voltage -- V
2.5
CC = 3 V
V
P4.5
A = 85°C
T
A = 25°C
T
--50.0
0.0
0.5
V
Figure 7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1.0
1.5
2.0
2.5
3.0
3.5
OH -- High-Level Output Voltage -- V
V
Figure 8
37
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX UNIT
VCC(start) Operating voltage
dVCC/dt ± 3 V/s
0.7 ¢ V(B_IT--)
V
V(B_IT--)
Negative going VCC reset threshold voltage
dVCC/dt ± 3 V/s
1.71
V
Vhys(B_IT--) VCC reset threshold hysteresis
dVCC/dt ± 3 V/s
70 130 210 mV
td(BOR)
BOR reset release delay time
2000
µs
treset
Pulse length at RST/NMI pin to accept a reset
2.2 V / 3 V
2
µs
NOTES: 1. The current consumption of the brownout module is included in the I CC current consumption data. The voltage level
V(B_IT--) + Vhys(B_IT--) is ≤ 1.8 V.
2. During power up, the CPU begins code execution following a period of t d(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default DCO
settings must not be changed until VCC ≥ VCC(MIN), where VCC(min) is the minimum supply voltage for the desired operating
frequency.
VCC
Vhys(B_IT-)
V(B_IT-)
VCC(Start)
1
0
td(BOR)
Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- POR/brownout reset (BOR)
V
CC
2
CC
V
t
pw
3 V
= 3 V
Typical Conditions
V
)
p
o
r
d
(
C
C
V
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
pw -- Pulse Width -- µs
t
1 ns
pw -- Pulse Width -- µs
t
Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
V
CC
2
t
pw
3 V
CC = 3 V
V
V
)
p
o
r
d
(
C
C
V
1.5
Typical Conditions
1
V
CC(drop)
0.5
f
t = t
0
0.001
1
1000
pw -- Pulse Width -- µs
t
r
tr
f
tpw -- Pulse Width -- µs
t
Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
39
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
SVS (supply voltage supervisor/monitor)
PARAMETER
t
TEST CONDITIONS
dV /dt > 30 V/ms (see Figure 12)
dV /dt ≤ 30 V/ms
SVSON, switch from VLD = 0 to VLD ≠ 0, V = 3 V
VLD ≠ 0
VLD ≠ 0, V /dt ≤ 3 V/s (see Figure 12)
MIN
5
CC
(SVSR)
S S
t
t
V
d(SVSon)
settle
(SVSstart)
V
hys(SVS IT--)
hys(SVS_IT-
CC
20
CC
‡
CC
V /dt ≤ 3 V/s (see Figure 12)
CC
V /dt ≤ 3 V/s (see Figure 12),
External voltage applied on A7
CC
V
TYP
V /dt ≤ 3 V/s (see Figure 12 and Figure 13)
CC
(SVS IT -))
(SVS_IT-
V /dt ≤ 3 V/s (see Figure 12 and Figure 13),
External voltage applied on A7
CC
VLD = 1
VLD = 2 to 14
V
70
(SVS_IT--)
1.55
120
×
V
MAX UNIT
150
µs
2000
150 µs
12 µs
1.7 V
210 mV
0.016
×
V
20
mV
(SVS_IT--)
0.004
VLD = 15
4.4
VLD = 1
VLD = 2
VLD = 3
VLD = 4
VLD = 5
VLD = 6
VLD = 7
VLD = 8
VLD = 9
VLD = 10
VLD = 11
VLD = 12
VLD = 13
VLD = 14
1.8
1.94
2.05
2.14
2.24
2.33
2.46
2.58
2.69
2.83
2.94
3.11
3.24
3.43
1.9
2.1
2.2
2.3
2.4
2.5
2.65
2.8
2.9
3.05
3.2
3.35
3.5
3.7
2.05
2.25
2.37
2.48
2.6
2.71
2.86
3
3.13
3.29
3.42
3.61
3.76
3.99
VLD = 15
1.1
1.2
1.3
†
V
†
†
†
I
VLD ≠ 0, V = 2.2 V/3 V
10
15 µA
(see Note 1)
The recommended operating voltage range is limited to 3.6 V.
t
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value between
2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the I current consumption data.
CC(SVS)
CC
†
‡
settle
CC
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
typical characteristics
Software sets VLD >0:
SVS is active
AVCC
V(SVS_IT-- )
V(SVSstart)
V(B_IT-- )
VCC(start)
Vhys(SVS_IT-- )
V
hys(B_IT-- )
Brownout
Region
Brownout
Region
Brownout
1
0
SVS out
1
t d(BOR)
0
Set POR
1
SVS Circuit is Active From VLD > to V
CC
td(SVSon)
< V(
td(BOR)
B_IT--)
td(SVSR)
undefined
0
Figure 12. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
2
V)n
i
m
(C
VC
Rectangular Drop
1.5
VCC(min)
Triangular Drop
1
VCC
3V
0.5
0
t pw
1
10
100
t - Pulse Width - µs
pw
1 ns
1 ns
t pw
1000
VCC(min)
t =t
f
r
t
t
t - Pulse Width - µs
f
r
CC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)
Figure 13. V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
41
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D DCO control bits DCOx have a step size as defined by parameter SDCO.
D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency f
to:
DCO(RSEL,DCO)
f
average
is used for the remaining cycles. The frequency is an average equal
×f
= MOD × 32
f
×f
+(32−MOD) × f
DCO(RSEL,DCO)
DCO(RSEL,DCO)
DCO frequency
PARAMETER
V
CC
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
S
DCO(0,0)
DCO(0,3)
DCO(1,3)
DCO(2,3)
DCO(3,3)
DCO(4,3)
DCO(5,3)
DCO(6,3)
DCO(7,3)
DCO(8,3)
DCO(9,3)
DCO(10,3)
DCO(11,3)
DCO(12,3)
DCO(13,3)
DCO(14,3)
DCO(15,3)
DCO(15,7)
RSEL
S
Duty cycle
DCO
42
TEST CONDITIONS
RSELx < 14
RSELx = 14
Supply voltage
RSELx = 15
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0
DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0
DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0
DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0
DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0
DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0
DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0
Frequency step between S = f
/f
range RSEL and RSEL+1
Frequency step between S = f
/f
tap DCO and DCO+1
Measured at P1.4/SMCLK
RSEL
DCO
DCO(RSEL+1,DCO)
DCO(RSEL,DCO+1)
+
DCO(RSEL,DCO
DCO(RSEL,DCO)
DCO(RSEL,DCO)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1)
+
DCO(RSEL,DCO
VCC
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
3V
3V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
1)
MIN
1.8
2.2
3.0
0.06
0.07
0.10
0.14
0.20
0.28
0.39
0.54
0.80
1.10
1.60
2.50
3.00
4.30
6.00
8.60
12.0
16.0
TYP
MAX UNIT
3.6
3.6
3.6
0.14
0.17
0.20
0.28
0.40
0.54
0.77
1.06
1.50
2.10
3.00
4.30
5.50
7.30
9.60
13.9
18.5
26.0
1.55
V
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ratio
1.05 1.08 1.12 ratio
40 50 60 %
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance at calibration
PARAMETER
Frequency tolerance at calibration
fCAL(1MHz)
1-MHz calibration value
fCAL(8MHz)
8-MHz calibration value
fCAL(12MHz) 12-MHz calibration value
fCAL(16MHz) 16-MHz calibration value
TEST CONDITIONS
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
TA
25°C
VCC
3V
MIN
-1
25°C
3V
0.990
1 1.010 MHz
25°C
3V
7.920
8 8.080 MHz
25°C
3V
11.88
12 12.12 MHz
25°C
3V
15.84
16 16.16 MHz
VCC
3V
3V
3V
3V
2.2 V
3V
3.6 V
2.2 V
3V
3.6 V
2.2 V
3V
3.6 V
3V
3.6 V
MIN
- 2.5
- 2.5
- 2.5
- 3.0
0.970
0.975
0.970
7.760
7.800
7.600
11.64
11.64
11.64
15.52
calibrated DCO frequencies - tolerance over temperature 0°C to 85°C
PARAMETER
1-MHz tolerance over temperature
8-MHz tolerance over temperature
12-MHz tolerance over temperature
16-MHz tolerance over temperature
TEST CONDITIONS
TA
0°C to 85°C
0°C to 85°C
0°C to 85°C
0°C to 85°C
fCAL(1MHz)
11-MHz
MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
0°C to 85°C
fCAL(8MHz)
88-MHz
MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
CALBC1 8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
0°C to 85°C
fCAL(12MHz) 12
12-MHz
MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
CALBC1 12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
0°C to 85°C
fCAL(16MHz) 16-MHz
16 MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
CALDCO 16MHZ
Gating time: 2 ms
0°C to 85°C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15.00
TYP
±0.2
TYP
±0.5
±1.0
±1.0
±2.0
1
1
1
8
8
8
12
12
12
16
16
MAX UNIT
+1 %
MAX
+2.5
+2.5
+2.5
+3.0
1.030
1.025
1.030
8.400
8.200
8.240
12.36
12.36
12.36
16.48
16.48
UNIT
%
%
%
%
MHz
MHz
MHz
MHz
43
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
CC
TA
25°C
25°C
25°C
25°C
VCC
1.8 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3.0 V to 3.6 V
MIN
-3
-3
-3
-6
25°C
1.8 V to 3.6 V
0.970
1 1.030 MHz
25°C
1.8 V to 3.6 V
7.760
8 8.240 MHz
25°C
2.2 V to 3.6 V
11.64
12 12.36 MHz
25°C
3.0 V to 3.6 V
15.00
16 16.48 MHz
TA
VCC
- 40°C to 105°C 1.8 V to 3.6 V
- 40°C to 105°C 1.8 V to 3.6 V
- 40°C to 105°C 2.2 V to 3.6 V
- 40°C to 105°C 3 V to 3.6 V
MIN
-5
-5
-5
-6
- 40°C to 105°C 1.8 V to 3.6 V
0.950
1 1.050 MHz
- 40°C to 105°C 1.8 V to 3.6 V
7.600
8 8.400 MHz
- 40°C to 105°C 2.2 V to 3.6 V
11.40
12 12.60 MHz
- 40°C to 105°C
15.00
16 17.00 MHz
calibrated DCO frequencies -- tolerance over supply voltage V
PARAMETER
1-MHz tolerance over VCC
8-MHz tolerance over VCC
12-MHz tolerance over VCC
16-MHz tolerance over VCC
fCAL(1MHz)
1-MHz calibration value
fCAL(8MHz)
8-MHz calibration value
fCAL(12MHz) 12-MHz calibration value
fCAL(16MHz) 16-MHz calibration value
TEST CONDITIONS
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
TYP
±2
±2
±2
±2
MAX UNIT
+3 %
+3 %
+3 %
+3 %
calibrated DCO frequencies -- overall tolerance
PARAMETER
1-MHz tolerance overall
8-MHz tolerance overall
12-MHz tolerance overall
16-MHz tolerance overall
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
44
TEST CONDITIONS
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
BCSCTL1 = CALBC1_8MHZ,
8-MHz calibration value DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
BCSCTL1 =
12-MHz calibration value CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
BCSCTL1 =
16-MHz calibration value CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
1-MHz calibration value
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3 V to 3.6 V
TYP
±2
±2
±2
±3
MAX UNIT
+5 %
+5 %
+5 %
+6 %
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- calibrated 1-MHz DCO frequency
1.02
1.01
z
H
M
y
c
n
e
u
q
e
r
F
A = 105 °C
T
A = 85 °C
1.00
T
A = 25 °C
T
0.99
A = --40 °C
T
0.98
1.5
2.0
2.5
3.0
3.5
4.0
VCC -- Supply Voltage -- V
Figure 14. Calibrated 1-MHz Frequency vs VCC
typical characteristics -- calibrated 8-MHz DCO frequency
8.20
A = 105 °C
T
8.15
8.10
z
H
M
y
c
n
e
u
q
e
r
F
8.05
A = 85 °C
T
A = 25 °C
T
8.00
7.95
A = --40 °C
T
7.90
7.85
7.80
1.5
2.0
2.5
CC
V
3.0
3.5
4.0
-- Supply Voltage -- V
Figure 15. Calibrated 8-MHz Frequency vs VCC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
45
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- calibrated 12-MHz DCO frequency
12.2
12.1
A = --40 °C
T
z
H
M
y
c
n
e
u
q
e
r
A = 25 °C
T
12.0
A = 85 °C
T
11.9
F
A = 105 °C
T
11.8
11.7
1.5
2.0
2.5
3.0
3.5
4.0
VCC -- Supply Voltage -- V
Figure 16. Calibrated 12-MHz Frequency vs VCC
typical characteristics -- calibrated 16-MHz DCO frequency
16.1
16.0
A = --40 °C
T
z
H
M
y
c
n
e
u
q
e
r
F
15.9
A = 25 °C
T
A = 85 °C
T
15.8
A = 105 °C
T
15.7
15.6
1.5
2.0
2.5
CC
V
3.0
3.5
4.0
-- Supply Voltage -- V
Figure 17. Calibrated 16-MHz Frequency vs VCC
46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from low-power modes (LPM3/LPM4)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX UNIT
BCSCTL1= CALBC1_1MHZ,
2.2 V/3 V
2
DCOCTL = CALDCO_1MHZ
BCSCTL1= CALBC1_8MHZ,
2.2 V/3 V
1.5
DCO clock wake
wake-up
up time from LPM3/4 DCOCTL = CALDCO_8MHZ
t
µs
(see Note 1)
BCSCTL1= CALBC1_12MHZ,
2.2
V/3
V
1
DCOCTL = CALDCO_12MHZ
BCSCTL1= CALBC1_16MHZ,
3V
1
DCOCTL = CALDCO_16MHZ
CPU wake-up time from LPM3/4
1/f
+
t
(see Note 2)
t
NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
DCO,LPM3/4
MCLK
CPU,LPM3/4
Clock,LPM3/4
typical characteristics - DCO clock wake-up time from LPM3/4
10.00
su
e
im
T
ek
a
W 1.00
O
CD
0.10
0.10
RSELx = 0 to 11
RSELx = 12 to 15
1.00
10.00
DCO Frequency - MHz
Figure 18. Clock Wake-Up Time From LPM3 vs DCO Frequency
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
47
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
OSC (see Note 1)
DCO with external resistor R
PARAMETER
fDCO,ROSC
TEST CONDITIONS
DCO output frequency with ROSC DCOR = 1,
1 RSELx = 4,
4 DCOx = 3,
3 MODx = 0,
0 TA = 25°C
Dt
Temperature drift
DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0
DV
Drift with VCC
DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0
NOTE 1: ROSC = 100 kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and T K = ±50ppm/°C.
OSC
VCC
2.2 V
3V
2.2 V/3 V
2.2 V/3 V
TYP UNIT
1.8
MHz
1.95
±0.1 %/°C
10 %/V
typical characteristics -- DCO with external resistor R
10.00
z
H
M
y
c
n
e
u
q
e
r
F
O
C
D
10.00
z
H
M
-
1.00
y
c
n
e
u
q
e
r
F
0.10
RSELx = 4
O
C
D
y
c
n
e
u
q
e
r
F
O
C
D
RSELx = 4
0.01
10.00
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
- 50.0 - 25.0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
1.5
ROSC = 100k
ROSC = 270k
ROSC = 1M
0.0 25.0 50.0 75.0 100.0
TA - Temperature - °C
Figure 21. DCO Frequency vs Temperature,
VCC = 3.0 V
48
0.10
0.01
10.00
100.00
1000.00
10000.00
ROSC - External Resistor - kOhm
Figure 19. DCO Frequency vs ROSC,
VCC = 2.2 V, TA = 25°C
z
H
M
-
1.00
100.00
1000.00
10000.00
ROSC - External Resistor - kOhm
Figure 20. DCO Frequency vs ROSC,
VCC = 3.0 V, TA = 25°C
z
H
M
y
c
n
e
u
q
e
r
F
O
C
D
ROSC = 100k
ROSC = 270k
ROSC = 1M
2.5
3.0
3.5
VCC - Supply Voltage - V
Figure 22. DCO Frequency vs VCC,
TA = 25°C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2.0
4.0
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
TEST CONDITIONS
LFXT1 oscillator crystal XTS = 0, LFXT1Sx = 0 or 1
f
frequency, LF mode 0/1
LFXT1 oscillator logic
level square wave input XTS = 0, LFXT1Sx = 3, XCAPx = 0
f
frequency, LF mode
XTS = 0, LFXT1Sx = 0,
f
= 32768 kHz,
Oscillation allowance for C = 6 pF
OA
LF crystals
XTS = 0, LFXT1Sx = 0;
f
= 32768 kHz, C = 12 pF
XTS = 0, XCAPx = 0
Integrated effective load XTS = 0, XCAPx = 1
capacitance LF mode
capacitance,
C
XTS = 0, XCAPx = 2
(see Note 1)
XTS = 0, XCAPx = 3
XTS = 0, Measured at P1.4/ACLK,
Duty cycle LF mode
f
= 32768 Hz
Oscillator fault
XTS = 0, LFXT1Sx = 3, XCAPx = 0
frequency, LF mode
f
(see Note 2)
(see Note 3)
VCC
LFXT1,LF
1.8 V to 3.6 V
LFXT1,LF,logic
1.8 V to 3.6 V
MIN
10000
32768
Hz
50000
500
200
L,eff
1
5.5
8.5
11
L,eff
LFXT1,LF
Hz
kΩ
L,eff
LFXT1,LF
Fault,LF
MAX UNIT
32768
LFXT1,LF
LF
TYP
2.2 V/3 V
30
2.2 V/3 V
10
50
pF
70
%
10000
Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces under or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
5. Applies only if using an external logic-level clock source. Not applicable when using a crystal or resonator.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
49
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
internal very low power, low frequency oscillator (VLO)
PARAMETER
fVLO
VLO frequency
TEST CONDITIONS
TA
- 40°C to 85°C
105°C
VCC
2 2 V/3 V
2.2
MIN
4
TYP
12
VLO frequency
See Note 1
2.2 V/3 V
0.5
temperature drift
frequency supply See Note 2
dfVLO/dVCC VLO
25°C
1.8V - 3.6V
4
voltage drift
NOTES: 1. Calculated using the box method:
I version: (MAX(-- 40_C to 85_C) - MIN(-- 40_C to 85_C))/MIN(-- 40_C to 85_C)/(85_C - (-- 40_C))
T version: (MAX(-- 40_C to 105_C) - MIN(-- 40_C to 105_C))/MIN(-- 40_C to 105_C)/(105_C - (-- 40_C))
2. Calculated using the box method: (MAX(1.8 V to 3.6V) - MIN(1.8V to 3.6V))/MIN(1.8 V to 3.6V)/(3.6 V - 1.8 V)
dfVLO/dT
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MAX UNIT
20
kHz
22
%/°C
%/V
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, high frequency modes (see Note 5)
f
LFXT1,HF0
f
LFXT1,HF1
f
LFXT1,HF2
f
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX UNIT
LFXT1 oscillator crystal frequency, XTS = 1, LFXT1Sx = 0, XCAPx = 0 1.8 V to 3.6 V
0.4
1 MHz
HF mode 0
LFXT1 oscillator crystal frequency, XTS = 1, LFXT1Sx = 1, XCAPx = 0 1.8 V to 3.6 V
1
4 MHz
HF mode 1
1.8 V to 3.6 V
2
10
LFXT1 oscillator
ill t crystal
t l frequency,
f
2.2
V
to
3.6
V
2
12 MHz
XTS
=
1,
LFXT1Sx
=
2,
XCAPx
=
0
HF mode 2
3 V to 3.6 V
2
16
1.8 V to 3.6 V
0.4
10
LFXT1 oscillator logic level
0.4
12 MHz
square-wave
square
wave input frequency,
XTS = 1, LFXT1Sx = 3, XCAPx = 0 2.2 V to 3.6 V
HF mode
3 V to 3.6 V
0.4
16
XTS = 1, XCAPx = 0,
LFXT1Sx = 0, f
= 1 MHz,
2700
C = 15 pF
XTS = 1, XCAPx = 0,
Oscillation allowance for HF
LFXT1Sx = 1, f
= 4 MHz,
800
Ω
crystals
C = 15 pF
(see Figure 23 and Figure 24)
XTS = 1, XCAPx = 0,
LFXT1Sx = 2, f
= 16 MHz,
300
C = 15 pF
Integrated effective load
capacitance, HF mode
XTS = 1, XCAPx = 0 (see Note 2)
1
pF
(see Note 1)
XTS = 1, XCAPx = 0,
Measured at P1.4/ACLK,
2.2 V/3 V
40
50
60
f
= 10 MHz
HF mode
%
XTS = 1, XCAPx = 0,
Measured at P1.4/ACLK,
2.2 V/3 V
40
50
60
f
= 16 MHz
Oscillator fault frequency, HF mode XTS = 1, LFXT1Sx = 3, XCAPx = 0 2.2 V/3 V
30
300 kHz
(see Note 4)
(see Note 3)
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Measured with logic level input frequency but also applies to operation with crystals.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces under or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
LFXT1,HF,logic
LFXT1,HF
,logic
LFXT1,HF
L,eff
OA
LFXT1,HF
HF
L,eff
LFXT1,HF
L,eff
C
L,eff
Duty cycle
LFXT1,HF
LFXT1,HF
f
Fault,HF
NOTES: 1.
2.
3.
4.
5.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
51
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics - LFXT1 oscillator in HF mode (XTS = 1)
100000.00
s
m
h 10000.00
O
ec
na
w
ol 1000.00
A
no
it
lai
cs 100.00
O
LFXT1Sx = 2
LFXT1Sx =0
LFXT1Sx = 1
10.00
0.10
1.00
10.00
100.00
Crystal Frequency -- MHz
Figure 23. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
Au
tn
er
ru
C
lyp
pu
Sr
ot
al
ic
s
O
TX
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
LFXT1Sx = 2
LFXT1Sx = 1
LFXT1Sx = 0
0
4
8
12
16
Crystal Frequency - MHz
20
Figure 24. XT Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, XT2 (see Note 5)
f
PARAMETER
XT2 oscillator crystal frequency,
mode 0
XT2 oscillator crystal frequency,
mode 1
f
XT2 oscillator
ill t crystal
t l frequency,
f
mode 2
XT2Sx = 2
f
XT2 oscillator
ill t logic
l i level
l l
square-wave input frequency
XT2Sx = 3
Oscillation allowance
(see Figure 23 and Figure 24)
XT2Sx = 0, f = 1 MHz,
C = 15 pF
XT2Sx = 1, f = 4 MHz,
C = 15 pF
XT2Sx = 2, f
= 16 MHz,
C = 15 pF
f
XT2
XT2
XT2
XT2
TEST CONDITIONS
VCC
MIN
XT2Sx = 0
1.8 V to 3.6 V
0.4
1 MHz
XT2Sx = 1
1.8 V to 3.6 V
1
4 MHz
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
2
2
2
0.4
0.4
0.4
10
12 MHz
16
10
12 MHz
16
XT2
2700
XT2
800
XT1,HF
300
L,eff
OA
L,eff
L,eff
Integrated effective load
capacitance, HF mode
(see Note 1)
C
L,eff
Duty cycle
See Note 2
Measured at P1.4/SMCLK,
f = 10 MHz
Measured at P1.4/SMCLK,
f = 16 MHz
XT2
XT2
f
Fault
NOTES: 1.
2.
3.
4.
5.
TYP
MAX UNIT
Ω
1
2 2 V/3 V
2.2
pF
40
50
60
40
50
60
%
Oscillator fault frequency, HF mode XT2Sx = 3, (see Note 3)
2.2 V/3 V
30
300 kHz
(see Note 4)
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Measured with logic level input frequency but also applies to operation with crystals.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces under or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
53
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- XT2 oscillator
100000.00
s
m
h 10000.00
O
ec
na
w
ol 1000.00
A
no
it
lai
cs 100.00
O
XT2Sx = 2
XT2Sx = 1
XT2Sx = 0
10.00
0.10
1.00
10.00
100.00
Crystal Frequency -- MHz
Figure 25. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
Au
tn
er
ru
C
lyp
pu
Sr
ot
al
ic
s
O
TX
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
XT2Sx = 2
XT2Sx = 1
XT2Sx = 0
0
4
8
12
16
Crystal Frequency - MHz
20
Figure 26. XT2 Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
54
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
ffTA
Timer A clock frequency
Timer_A
tTA,cap
Timer_A, capture timing
Timer_B
PARAMETER
fTB
Timer B clock frequency
Timer_B
tTB,cap
Timer_B, capture timing
TEST CONDITIONS
Internal: SMCLK, ACLK,
External: TACLK,
TACLK INCLK,
INCLK
Duty cycle = 50% ±10%
TA0, TA1, TA2
VCC
2.2 V
3.3 V
2.2 V/3 V
MIN
TEST CONDITIONS
Internal: SMCLK, ACLK,
External: TBCLK,
TBCLK
Duty cycle = 50% ±10%
TB0, TB1, TB2
VCC
2.2 V
MIN
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3.3 V
2.2 V/3 V
20
20
MAX UNIT
10
MHz
16
ns
MAX UNIT
10
MHz
16
ns
55
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
fUSCI
TEST CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
USCI input clock frequency
VCC
MIN
TYP
MAX UNIT
fSYSTEM MHz
BITCLK clock frequency
2.2 V /3 V
1 MHz
(equals baud rate in MBaud)
2.2 V
50 150 600 ns
UART receive deglitch time
tτ
(see Note 1)
3V
50 100 600 ns
NOTE 1: Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
fBITCLK
USCI (SPI master mode) (see Figure 27 and Figure 28)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
TEST CONDITIONS
SMCLK, ACLK
Duty cycle = 50% ± 10%
VCC
MIN
fSYSTEM MHz
2.2 V
3V
2.2 V
3V
2.2 V
3V
UCLK edge to SIMO valid;
CL = 20 pF
110
75
0
0
NOTE 1: fUCxCLK = 2t 1 with tLOፒHI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
LOፒHI
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
USCI (SPI slave mode) (see Figure 29 and Figure 30)
tSTE,DIS
PARAMETER
STE lead time,
STE low to clock
STE lag time,
Last clock to STE high
STE access time,
STE low to SOMI data out
STE disable time,
STE high to SOMI high impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
tSTE,LEAD
tSTE,LAG
tSTE,ACC
TEST CONDITIONS
VCC
MIN
TYP
2.2 V/3 V
2.2 V/3 V
UCLK edge to SOMI valid;
CL = 20 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ns
ns
30
20
ns
MAX UNIT
50
ns
10
ns
2.2 V/3 V
50
ns
2.2 V/3 V
50
ns
2.2 V
3V
2.2 V
3V
2.2 V
3V
20
15
10
10
NOTE 1: fUCxCLK = 2t 1 with tLOፒHI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
LOፒHI
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
56
MAX UNIT
ns
ns
75
50
110
75
ns
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
1/fUCxCLK
UCLK
CKPL=0
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 27. SPI Master Mode, CKPH = 0
1/fUCxCLK
UCLK
CKPL=0
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 28. SPI Master Mode, CKPH = 1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
57
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 29. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
SOMI
Figure 30. SPI Slave Mode, CKPH = 1
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
tSTE,DIS
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 31)
PARAMETER
TEST CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) Start
tSU,STA
Setup time for a repeated Start
tHD,DAT
tSU,DAT
tSU,STO
Data hold time
Data setup time
Setup time for Stop
tSP
Pulse width of spikes suppressed by input filter
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
VCC
MIN
TYP
MAX UNIT
fSYSTEM MHz
2.2 V/3 V
2 2 V/3 V
2.2
2 2 V/3 V
2.2
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V
3V
0
4.0
0.6
4.7
0.6
0
250
4.0
50
50
400
kHz
µs
µs
150
100
600
600
ns
ns
µs
ns
tSU,STA tHD,STA
SDA
1/fSCL
tSP
SCL
tHD,DAT
tSU,DAT
tSU,STO
Figure 31. I2C Mode Timing
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
59
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Comparator_A+ (see Note 1)
PARAMETER
I(DD)
TEST CONDITIONS
CAON = 1,
1 CARSEL = 0,
0 CAREF = 0
VCC
2.2 V
3V
2.2 V
3V
2.2 V/3 V
MIN
TYP
25
45
30
45
MAX UNIT
40
µA
60
50
µA
71
VCC - 1
V
CAON = 1, CARSEL = 0,
CAREF = 1/2/3,
1/2/3 no load at P2.3/CA0/TA1
P2 3/CA0/TA1
and P2.4/CA1/TA2
V(IC)
Common-mode input voltage
CAON =1
0
PCA0 = 1, CARSEL = 1, CAREF = 1,
Voltage at 0.25 V CC node no load at P2.3/CA0/TA1 and
V(Ref025)
2.2 V/3 V
0.23 0.24
0.25
P2.4/CA1/TA2
VCC
Voltage at 0.5V CC node PCA0 = 1, CARSEL = 1, CAREF = 2,
no load at P2.3/CA0/TA1 and
V(Ref050)
2.2 V/3 V
0.47 0.48
0.5
VCC
P2.4/CA1/TA2
PCA0 = 1, CARSEL = 1, CAREF = 3,
2.2 V
390 480
540
V(RefVT)
See Figure 35 and Figure 36
mV
no load at P2.3/CA0/TA1
P2 3/CA0/TA1 and
3V
400 490
550
P2.4/CA1/TA2, TA = 85°C
V(offset)
Offset voltage
See Note 2
2.2 V/3 V
- 30
30 mV
Vhys
Input hysteresis
CAON=1
2.2 V/3 V
0
0.7
1.4 mV
2.2 V
80 165
300
TA = 25°C, Overdrive 10 mV,
ns
Without
filter:
CAF
=
0
3V
70 120
240
time, low-to-high
low to high and
t(response) Response
high-to-low
g
(see Note 3)
2.2 V
1.4
1.9
2.8
TA = 25°C, Overdrive 10 mV,
µs
With filter: CAF = 1
3V
0.9
1.5
2.2
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to I lkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
3. The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step, with Comparator_A+ already enabled
(CAON = 1). If CAON is set at the same time, a settling time of up to 300 ns is added to the response time.
I(Refladder/Refdiode)
60
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MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
0 V VCC
0 1
CAF
CAON
To Internal
Modules
Low Pass Filter
+
_
V+
V--
0
0
1
1
CAOUT
Set CAIFG
Flag
τ≈
2.0 µs
Figure 32. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V--
400 mV
t(response)
V+
Figure 33. Overdrive Definition
CA0
CASHORT
CA1
1
VIN
+
-
Comparator_A+
CASHORT = 1
IOUT = 10µA
Figure 34. Comparator_A+ Short Resistance Test Condition
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
61
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics - Comparator A+
650
650
V 600
m
tsl
oV
ec 550
ne
re
fe
R 500
-)
TV
FE
R
V( 450
400
- 45
VCC = 2.2 V
VCC = 3 V
V 600
m
slt
oV
ec 550
ne
re
fe
R- 500
)T
VF
ER
V( 450
Typical
- 25
-5
15
35
55
75
TA - Free-Air Temperature - °C
95
Figure 35. V(RefVT) vs Temperature, VCC = 3 V
400
- 45
Typical
- 25
-5
15
35
55
75
TA - Free-Air Temperature - °C
Figure 36. V(RefVT) vs Temperature, VCC = 2.2 V
100.00
Ω
k
ec
na
ts 10.00
is
eR
tr
oh
S
VCC = 2.2V
VCC = 3.0V
VCC = 1.8V
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
1.0
VIN/VCC - Normalized Input Voltage - V/V
Figure 37. Short Resistance vs VIN/VCC
62
95
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit ADC power supply and input range conditions (see Note 1)
PARAMETER
AVCC
Analog supply voltage
V(P6.x/Ax)
Analog input voltage
(see Note 2)
IADC12
Operating supply current
into AVCC terminal
(see Note 3)
TEST CONDITIONS
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
All P6.0/A0 to P6.7/A7 terminals.
Analog inputs selected in ADC12MCTLx register
and P6Sel.x = 1, 0 ≤ x ≤ 7,
V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC)
fADC12CLK = 5 MHz, ADC12ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
VCC
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
VAVCC
V
2.2 V
0.65
0.8
3V
0.8
1.0
mA
fADC12CLK = 5 MHz, ADC12ON = 0,
3V
0.5
0.7
REFON = 1, REF2_5V = 1
IREF+
2.2 V
0.5
0.7 mAA
fADC12CLK = 5 MHz, ADC12ON = 0,
REFON = 1, REF2_5V = 0
3V
0.5
0.7
Only
one
terminal
can
be
selected
at
one
time,
CI †
Input capacitance
2.2 V
40
pF
P6.x/Ax
RI†
Input MUX ON resistance 0 V ≤ VAx ≤ VAVCC
3V
2000
Ω
† Limits verified by design
NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range V R+ to VR-- for valid conversion results.
3. The internal reference supply current is not included in current consumption parameter I ADC12.
4. The internal reference current is supplied via terminal AV CC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Operating
p
g supply
pp y current
i t AVCC terminal
into
t i l
(see Note 4)
12-bit ADC external reference (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
MIN MAX UNIT
Positive
external
VeREF+
1.4 VAVCC
V
reference voltage input VeREF+ > VREF--/VeREF-- (see Note 2)
Negative external
VREF-- /VeREF-0
1.2
V
reference voltage input VeREF+ > VREF--/VeREF-- (see Note 3)
external
(VeREF+ - VREF--/VeREF--) Differential
1.4 VAVCC
V
reference voltage input VeREF+ > VREF--/VeREF-- (see Note 4)
IVeREF+
Static input current
0V ≤VeREF+ ≤ VAVCC
2.2 V/3 V
±1
µA
IVREF--/VeREF-Static input current
0V ≤ VeREF-- ≤ VAVCC
2.2 V/3 V
±1
µA
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C i, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
63
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit ADC built-in reference
PARAMETER
VREF+
Positive built-in
reference voltage
output
AVCC(min)
AVCC minimum
voltage, positive
built-in
built in reference
active
IVREF+
IL(VREF)+ †
IDL(VREF) +‡
CVREF+
TREF+†
TEST CONDITIONS
REF2_5V = 1 (2.5 V)
IVREF+max ≤ IVREF+≤ IVREF+min
REF2_5V = 0 (1.5 V)
IVREF+max ≤ IVREF+≤ IVREF+min
REF2_5V = 0,
IVREF+max ≤ IVREF+≤ IVREF+min
REF2_5V = 1,
- 0.5mA ≤ IVREF+≤ IVREF+min
REF2_5V = 1,
- 1mA ≤ IVREF+≤ IVREF+min
Load current out of
VREF+ terminal
IVREF+ = 500 µA +/-- 100 µA
Analog input voltage ~0.75
0 75 V,
V
Load-current
REF2_5V = 0
regulation VREF+
regulation,
IVREF+ = 500 µA ± 100 µA
terminal
Analog input voltage ~1.25 V,
REF2_5V = 1
Load current
IVREF+ = 100 µA → 900 µA,
regulation VREF+
CVREF+= 5 µFF, at ~0.5
0 5 VREF+,
Error of conversion result ≤ 1 LSB
terminal
Capacitance at pin REFON =1,
VREF+ (see Note 1) 0 mA ≤ IVREF+ ≤ IVREF+max
Temperature
IVREF+ is a constant in the range
coefficient of
of
0 mA ≤ IVREF+ ≤ 1 mA
built-in reference
VCC
3V
2.2 V/3 V
2.2 V/3 V
TA
- 40°C to 85°C
105°C
- 40°C to 85°C
105°C
MIN
2.4
2.37
1.44
1.42
TYP
2.5
2.5
1.5
1.5
MAX
2.6
2.64
1.56
1.57
UNIT
V
2.2
2.8
V
2.9
2.2 V
3V
2.2 V
0.01
0.01
- 0.5
-1
±2
3V
±2
3V
±2
3V
20
2.2 V/3 V
2.2 V/3 V
5
10
mA
LSB
ns
µF
±100
ppm/°C
Settle time of
internal reference I
VREF+ = 0.5 mA, CVREF+ = 10 µF,
voltage (see
17 ms
tREFON†
V
Figure 38 and Note REF+ = 1.5 V, VAVCC = 2.2 V
2)
† Limits characterized
‡ Limits verified by design
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests use
two capacitors between pins VREF+ and AVSS and VREF--/VeREF-- and AVSS: 10 µF tantalum and 100 nF ceramic.
2. The condition is that the error in a conversion started after t REFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
64
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MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics - ADC12
CVREF+
100 µF
tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in µF
10 µF
1 µF
0
1 ms
10 ms
100 ms
tREFON
Figure 38. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
65
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
From
Power
Supply
+
10 µ F 100 nF
+
10 µ F 100 nF
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
+
-
Apply
External
Reference
10 µ F 100 nF
+
10 µ F 100 nF
DVCC
DVSS
AVCC
MSP430F261x
AVSS MSP430F241x
VREF+ or VeREF+
VREF - /VeREF--
Figure 39. Supply Voltage and Reference Voltage Design VREF-- /VeREF-- External Supply
From
Power
Supply
+
10 µ F 100 nF
+
-
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
Reference Is Internally
Switched to AVSS
10 µ F 100 nF
+
-
10 µ F 100 nF
DVCC
DVSS
AVCC
MSP430F261x
AVSS MSP430F241x
VREF+ or VeREF+
VREF-- /VeREF--
Figure 40. Supply Voltage and Reference Voltage Design VREF-- /VeREF-- = AVSS, Internally Connected
66
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit ADC timing parameters
PARAMETER
fADC12CLK
fADC12OSC Internal ADC12 oscillator
tCONVERT
Conversion time
tADC12ON‡
Turn-on settling time of
the ADC
tSample‡
Sampling time
† Limits characterized
‡ Limits verified by design
TEST CONDITIONS
VCC
For specified performance of ADC12
2.2V/3 V
linearity parameters
ADC12DIV = 0,
2.2 V/ 3 V
fADC12CLK = fADC12OSC
CVREF+ ≥ 5 µF, Internal oscillator,
2.2 V/ 3 V
fADC12OSC = 3.7 MHz to 6.3 MHz
External fADC12CLK from ACLK, MCLK
or SMCLK, ADC12SSEL ≠ 0
MIN
TYP
MAX
UNIT
0.45
5
6.3
MHz
3.7
5
6.3
MHz
2.06
3.51
13 × ADC12DIV
× 1/fADC12CLK
See Note 1
RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
τ = [RS + RI] x CI;(see Note 2)
100
3V
2.2 V
1220
1400
µs
ns
ns
NOTES: 1. The condition is that the error in a conversion started after t ADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC linearity parameters
PARAMETER
EI
ED
EO
EG
ET
TEST CONDITIONS
1.4 V ≤ (VeREF+ - VREF--/VeREF--) min ≤ 1.6 V
Integral linearity error
1.6 V < (VeREF+ - VREF--/VeREF--) min ≤ VAVCC
(V
VREF--/VeREF--)min ≤ (VeREF+ - VREF--/VeREF--),
Differential linearity error C eREF+ =- 10
µF (tantalum) and 100 nF (ceramic)
VREF+
(VeREF+ - VREF--/VeREF--)min ≤ (VeREF+ - VREF--/VeREF--),
Internal impedance of source RS < 100 Ω,
Offset error
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
(VeREF+ - VREF--/VeREF--)min ≤ (VeREF+ - VREF--/VeREF--),
Gain error
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
(VeREF+ - VREF--/VeREF--)min ≤ (VeREF+ - VREF--/VeREF--),
Total unadjusted error
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCC
MIN TYP
2 2 V/3 V
2.2
2.2 V/3 V
MAX
±2
±1.7
UNIT
±1
LSB
LSB
2.2 V/3 V
±2
±4
LSB
2.2 V/3 V
±1.1
±2
LSB
2.2 V/3 V
±2
±5
LSB
67
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC temperature sensor and built-in VMID
ISENSOR
PARAMETER
Operating supply current into
AVCC terminal (see Note 1)
VSENSOR†
See Note 2
TCSENSOR†
TEST CONDITIONS
REFON = 0, INCH = 0Ah,
ADC12ON = 1, TA = 25_C
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
ADC12ON = 1,
1 INCH = 0Ah
tSENSOR(sample)†
Sample time required if channel
10 is selected (see Note 3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at channel 11
ADC12ON = 1,
1 INCH = 0Bh
(see Note 4)
VMID
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID is ~0.5 x VAVCC
VCC
2.2 V
3V
2.2 V
3V
2.2 V
3V
2.2 V
3V
2.2 V
3V
2.2 V
3V
2.2 V
3V
MIN
30
30
TYP
40
60
986
986
3.55
3.55
MAX UNIT
120
µA
160
mV
mV/°C
µs
NA
NA
1.1 1.1±0.04
1.5 1.50±0.04
µA
V
1400
Sample time required if channel ADC12ON = 1, INCH = 0Bh,
ns
Error of conversion result ≤ 1 LSB
11 is selected (see Note 5)
1220
† Limits characterized
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1) or if (ADC12ON = 1, INCH = 0Ah and sample signal
is high). When REFON = 1, ISENSOR is already included in IREF+.
2. The temperature sensor offset can be as much as ±20_C. A single-point calibration is recommended to minimize the offset error
of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 k Ω. The sample time required includes the sensor-on time t SENSOR(on).
4. No additional current is needed. The VMID is used during sampling.
5. The on time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
tVMID(sample)
68
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MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit DAC supply specifications
PARAMETER
TEST CONDITIONS
VCC
TA
MIN TYP MAX UNIT
AVCC = DVCC,
AVCC Analog supply voltage
2.20
3.60 V
AVSS = DVSS = 0 V
- 40°C to 85°C
50 110
DAC12AMPx = 2, DAC12IR = 0,
2 2V/3V
2.2V/3V
DAC12_xDAT = 0x0800
105°C
69 150
DAC12AMPx = 2, DAC12IR = 1,
2.2V/3V
50 130
DAC12_xDAT = x00800 ,
VeREF+ = VREF+ = AVCC
Supply current,
IDD
µA
single DAC channel
DAC12AMPx = 5, DAC12IR = 1,
(see Notes 1 and 2)
2.2V/3V
200 440
DAC12_xDAT = 0x0800,
VeREF+ = VREF+ = AVCC
DAC12AMPx = 7, DAC12IR = 1,
2.2V/3V
700 1500
DAC12_xDAT = 0x0800,
VeREF+ = VREF+ = AVCC
DAC12_xDAT = 800h, VREF = 1.5 V,
2.2V
Power-supply
∆AVCC = 100mV
PSRR rejection ratio
70
dB
DAC12_xDAT = 800h, VREF = 1.5 V or 2.5 V,
(see Notes 3 and 4)
3V
∆AVCC = 100mV
NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20 × log{∆AVCC/∆VDAC12_xOUT}
4. VREF is applied externally. The internal reference is not used.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
69
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC linearity specifications (see Figure 41)
PARAMETER
Resolution
INL
Integral nonlinearity (see Note 1)
DNL
Differential nonlinearity
(see Note 1)
Offset voltage without calibration
(see Notes 1 and 2)
EO
Offset voltage with calibration
(see Notes 1 and 2)
dE(O)/dT
Offset error temperature
coefficient (see Note 1)
EG
Gain error (see Note 1)
dE(G)/dT
Gain temperature
coefficient (see Note 1)
TEST CONDITIONS
12-bit monotonic
VREF = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
VREF = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
VREF = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
VREF = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
VREF = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
VREF = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
VREF = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
VREF = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
VCC
MIN
12
TYP
MAX
UNIT
bits
±22.00
±88.00
LSB
±00.44
±11.00
LSB
2.2 V
3V
2.2 V
3V
2.2 V
±21
3V
mV
2.2 V
±22.55
3V
2.2 V/3 V
VREF = 1.5 V
VREF = 2.5 V
30
2.2 V
3V
V/C
µ
33.50
50 % FSR
±
2.2 V/3 V
10
ppm of
FSR/°C
DAC12AMPx = 2
100
DAC12AMPx = 3, 5
32 ms
2.2 V/3 V
DAC12AMPx = 4, 6, 7
6
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first-order equation: y = a + b × x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset calibration is triggered setting bit DAC12CALON.
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx={0,1}.TheDAC12moduleshouldbeconfiguredpriortoinitiatingcalibration.Portactivityduringcalibrationmayaffect
accuracy and is not recommended.
tOffset_Cal
Offset Cal
Time for
Ti
f offset
ff t calibration
lib ti
(see Note 3)
DAC Output
DAC VOUT
VR+
RLoad =
AV CC
2
CLoad = 100pF
Offset Error
Positive
Negative
Ideal transfer
function
Gain Error
DAC Code
Figure 41. Linearity Test Load Conditions and Gain/Offset Definition
70
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics - 12-bit DAC, linearity specifications
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
4
B
S
L
r
o
r
r
E
y
t
i
r
a
e
n
il
n
o
N
l
a
r
g
e
t
In
L
N
I
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
-1
-2
-3
-4
0
L
N
D
1024
1536
2048
2560
DAC12_xDAT - Digital Code
3072
3584
4095
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
2.0
B
S
L
r
o
r
r
E
y
t
i
r
a
e
n
il
n
o
N
l
a
it
n
e
r
e
f
f
i
D
-
512
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
- 0.5
- 1.0
- 1.5
- 2.0
0
512
1024
1536
2048
2560
DAC12_xDAT - Digital Code
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3072
3584
4095
71
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC output specifications
PARAMETER
VO
Output voltage range
(see Note 1 and Figure 44)
CL(DAC12)
Max DAC12 load
capacitance
IL(DAC12)
Max DAC12 load current
TEST CONDITIONS
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh,
DAC12IR = 1, DAC12AMPx = 7
RLoad= 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
RLoad= 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR =
1, DAC12AMPx = 7
VCC
MIN
MAX UNIT
0
0.005
AVCC - 0.05
AVCC
2 2 V/3 V
2.2
V
0
0.1
AVCC - 0.13
AVCC
2.2 V/3 V
2.2V
3V
- 0.5
- 1.0
RLoad= 3 kΩ, VO/P(DAC12) = 0 V,
DAC12AMPx = 7, DAC12_xDAT = 0h
RLoad= 3 kΩ, VO/P(DAC12) = AVCC,
DAC12AMPx
= 7,
Output
resistance
RO/P(DAC12) (see Figure 44)
2.2 V/3 V
DAC12_xDAT = 0FFFh
RLoad= 3 kΩ,
0.3 V < VO/P(DAC12) < AVCC - 0.3 V,
DAC12AMPx = 7
NOTE 1: Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
Max
RLoad
ILoad
AV CC
DAC12
2
O/P(DAC12_x) CLoad= 100pF
Min
0.3
Figure 44. DAC12_x Output Resistance Tests
72
TYP
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
100
pF
+0.5
+1.0
mA
150
250
150
250
1
4
Ω
AV CC - 0.3V VOUT
AV CC
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC reference input specifications
PARAMETER
Reference input voltage
range
Ve
REF+
Ri
Ri
,
(VREF+)
(VeREF+)
NOTES: 1.
2.
3.
4.
5.
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DAC12IR = 0, (see Notes 1 and 2)
AV /3 AV +0.2
2 2 V/3 V
2.2
V
AVcc AVcc+0.2
DAC12IR = 1, (see Notes 3 and 4)
DAC12_0 IR = DAC12_1 IR = 0
20
MΩ
DAC12_0 IR = 1, DAC12_1 IR = 0
40
48
56
Reference input
p
DAC12_0 IR = 0, DAC12_1 IR = 1
2.2 V/3 V
resistance
it
kΩ
DAC12_0 IR = DAC12_1 IR = 1
DAC12_0 SREFx = DAC12_1 SREFx
20
24
28
(see Note 5)
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV ).
The maximum voltage applied at reference input voltage terminal Ve
= [AV - V ] / [3*(1 + E )].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV ).
The maximum voltage applied at reference input voltage terminal Ve
= [AV - V ] / (1 + E ).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
CC
CC
CC
REF+
CC
E(O)
REF+
CC
E(O)
G
CC
G
12-bit DAC dynamic specifications, Vref = VCC, DAC12IR = 1 (see Figure 45 and Figure 46)
PARAMETER
TEST CONDITIONS
DAC12_xDAT
_
= 800h,, DAC12AMPx = 0 → {2, 3, 4}
Error < ±0.5 LSB DAC12AMPx = 0 → {5, 6}
t
DAC12 on-time
(see Note 1 and
DAC12AMPx = 0 → 7
Figure 45)
DAC12AMPx = 2
S ttli time,
Settling
ti
DAC12 DAT =
DAC12_xDAT
DAC12AMPx = 3, 5
t
full scale
80h→ F7Fh→ 80h
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
DAC12 xDAT =
DAC12_xDAT
S ttli time,
Settling
ti
3F8h→ 408h→ 3F8h DAC12AMPx = 3, 5
t
code to code
BF8h→ C08h→ BF8h DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
DAC12
DAT =
DAC12_xDAT
DAC12AMPx = 3, 5
SR
Slew rate
80h→ F7Fh→ 80h
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
Glit h energy,
Glitch
DAC12 DAT =
DAC12_xDAT
DAC12AMPx = 3, 5
full scale
80h→ F7Fh→ 80h
DAC12AMPx = 4, 6, 7
NOTES: 1. R and C are connected to AV (not AV /2) in Figure 45.
2. Slew rate applies to output voltage steps ≥ 200 mV.
V(O)
ON
VCC
2.2 V/3
/ V
S(FS)
2.2 V/3 V
S(C-C)
2.2 V/3 V
Load
Load
SS
DAC Output
ILoad
RO/P(DAC12.x)
MIN
2.2 V/3 V
0.05
0.35
1.5
2.2 V/3 V
TYP
60
15
6
100
40
15
5
2
1
0.12
0.7
2.7
600
150
30
MAX
120
30
12
200
80
30
UNIT
µs
µs
µs
V/µs
nV-ss
nV
CC
VOUT
RLoad = 3 kΩ
Conversion 1
Glitch
Energy
Conversion 2
+/-- 1/2 LSB
AV CC
2
+/-- 1/2 LSB
CLoad = 100pF
tsettleLH
Figure 45. Settling Time and Glitch Energy Testing
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Conversion 3
tsettleHL
73
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
VOUT
Conversion 1
Conversion 2
90%
Conversion 3
90%
10%
10%
tSRLH
tSRHL
Figure 46. Slew Rate Testing
12-bit DAC, dynamic specifications (continued) (TA = 25°C, unless otherwise noted)
PARAMETER
BW--3dB
TEST CONDITIONS
3-dB bandwidth,
VDC = 1.5 V, VAC = 0.1 VPP
(see Figure 47)
Channel to channel crosstalk
Channel-to-channel
(see Note 1 and Figure 48)
NOTE 1: RLOAD = 3 kΩ, CLOAD = 100 pF
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h<-- >F7Fh, RLoad = 3 kΩ,
fDAC12_1OUT = 10 kHz, Duty cycle = 50%
DAC12_0DAT = 80h<-- >F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No load,
fDAC12_0OUT = 10 kHz, Duty cycle = 50%
Ve REF+
DAC12_x
AC
DC
ILoad
DACx
VCC
MIN
TYP
MAX UNIT
40
180
2.2 V/3 V
kHz
550
- 80
2 2 V/3 V
2.2
dB
- 80
RLoad = 3 kΩ
AV CC
2
CLoad = 100pF
Figure 47. Test Conditions for 3-dB Bandwidth Specification
DAC12_0
RLoad
AV CC
2
DAC0
CLoad= 100pF
VREF+
e
ILoad
DAC12_1
ILoad
DAC1
DAC12_xDAT 080h
V OUT
4
080h
V DAC12_yOUT
RLoad
AV CC
2
V DAC12_xOUT
CLoad= 100pF
Figure 48. Crosstalk Test Conditions
7
7F7h
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
fToggle
7F7h
080h
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Program and erase supply voltage
2.2
3.6
V
Flash Timing Generator frequency
257
476 kHz
Supply current from DVCC during program
2.2 V/ 3.6 V
3
5 mA
Supply current from DVCC during erase
2.2 V/ 3.6 V
3
7 mA
Cumulative program time
See Note 1
2.2 V/ 3.6 V
10 ms
Cumulative mass erase time
2.2 V/ 3.6 V
20
ms
Program/Erase endurance
104
105
cycles
tRetention
Data retention duration
TJ = 25°C
100
years
tWord
Word or byte program time
See Note 2
35
tFTG
tBlock, 0
Block program time for first byte or word
See Note 2
30
tFTG
tBlock, 1-63
Block program time for each additional byte or word See Note 2
21
tFTG
tBlock, End
Block program end-sequence wait time
See Note 2
6
tFTG
tMass Erase
Mass erase time
See Note 2
10593
tFTG
tSeg Erase
Segment erase time
See Note 2
4819
tFTG
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (t FTG = 1/fFTG).
VCC(PGM/ERASE)
fFTG
IPGM
IERASE
tCPT
tCMErase
RAM
PARAMETER
TEST CONDITIONS
MIN MAX UNIT
VRAMh
See Note 1
CPU halted
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
75
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
JTAG interface
PARAMETER
fTCK
TCK input frequency
TEST
CONDITIONS
See Note 1
RInternal Internal pullup resistance on TMS, TCK, TDI/TCLK
See Note 2
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.
JTAG fuse (see Note 1)
VCC
MIN
2.2 V
3V
2.2 V/ 3 V
0
0
25
TYP
MAX
60
5
10
90
UNIT
MHz
kΩ
PARAMETER
TEST CONDITIONS
MIN MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition
TA = 25°C
2.5
V
VFB
Voltage level on TDI/TCLK for fuse blow (F versions)
6
7
V
IFB
Supply current into TDI/TCLK during fuse blow
100 mA
tFB
Time to blow fuse
1 ms
NOTE 1: Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
76
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 to P1.7, input/output with Schmitt trigger
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge Select
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
77
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P1 (P1.0 to P1.7) pin functions
PIN NAME (P1.X)
(P1 X)
P1.0/TACLK/CAOUT
/
/
P1.1/TA0
/
P1.2/TA1
/
P1.3/TA2
/
P1.4/SMCLK
/
P1.5/TA0
/
P1.6/TA1
/
P1.7/TA2
/
78
X
FUNCTION
0 P1.0 (I/O)
Timer_A3.TACLK
CAOUT
1 P1.1 (I/O)
Timer_A3.CCI0A
Timer_A3.TA0
2 P1.2 (I/O)
Timer_A3.CCI1A
Timer_A3.TA1
3 P1.3 (I/O)
Timer_A3.CCI2A
Timer_A3.TA2
4 P1.4 (I/O)
SMCLK
5 P1.5 (I/O)
Timer_A3.TA0
6 P1.6 (I/O)
Timer_A3.TA1
7 P1.7 (I/O)
Timer_A3.TA2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P1DIR.x
P1SEL.x
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P2 pin schematic: P2.0 to P2.4, P2.6, and P2.7, input/output with Schmitt trigger
Pad Logic
To
Comparator_A
From
Comparator_A
CAPD.x
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.6/ADC12CLK/
DMAE0/CA6
P2.7/TA0/CA7
D
Module X IN
P2IE.x
P2IRQ.x
EN
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge Select
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
79
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P2.0, P2.3, P2.4, P2.6 and P2.7 pin functions
PIN NAME (P2.X)
(P2 X)
P2.0/ACLK/CA2
/
/
P2.1/TAINCLK/CA3
/
/
P2.2/CAOUT/TA0/
/
/ /
CA4
P2.3/CA0/TA1
/ /
P2.4/CA1/TA2
/ /
P2.6/ADC12CLK/
/
/
DMAE0/CA6
P2.7/TA0/CA7
/ /
NOTE: X: Don’t care
80
X
FUNCTION
0 P2.0 (I/O)
ACLK
CA2
1 P2.1 (I/O)
Timer_A3.INCLK
DVSS
CA3
2 P2.2 (I/O)
CAOUT
Timer_A3.CCI0B
CA4
3 P2.3 (I/O)
Timer_A3.TA1
CA0
4 P2.4 (I/O)
Timer_A3.TA2
CA1
6 P2.6 (I/O)
ADC12CLK
DMAE0
CA6
7 P2.7 (I/O)
Timer_A3.TA0
CA7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
CAPD.x
P2DIR.x
P2SEL.x
0
I: 0; O: 1
0
0
1
1
1
X
X
0
I: 0; O: 1
0
0
0
1
0
1
1
1
X
X
0
I: 0; O: 1
0
0
1
1
0
0
1
1
X
X
0
I: 0; O: 1
0
0
1
1
1
X
X
0
I: 0; O: 1
0
0
1
X
1
X
1
0
I: 0; O: 1
0
0
1
1
0
0
1
1
X
X
0
I: 0; O: 1
0
0
1
1
1
X
X
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P2 pin schematic: P2.5, input/output with Schmitt trigger
Pad Logic
To Comparator
From Comparator
CAPD.5
To DCO
in DCO
DCOR
P2REN.5
P2DIR.5
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.5
DVSS
P2.5/ROSC/CA5
Bus
Keeper
EN
P2SEL.x
P2IN.5
EN
Module X IN
D
P2IE.5
P2IRQ.5
EN
Q
Set
P2IFG.5
P2SEL.5
P2IES.5
Interrupt
Edge Select
Port P2.5 pin functions
PIN NAME (P2.X)
(P2 X)
P2.5/R
/ OSC//CA5
X
FUNCTION
5 P2.5 (I/O)
ROSC (see Note 2)
DVSS
CA5
NOTES: 1. X: Don’t care
2. If Rosc is used it is connected to an external resistor.
CAPD
0
0
0
1 or selected
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
DCOR
P2DIR.5
0
1
0
0
I: 0; O: 1
X
1
X
P2SEL.5
0
X
1
X
81
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P3 pin schematic: P3.0 to P3.7, input/output with Schmitt trigger
Pad Logic
P3REN.x
P3DIR.x
Module
direction
P3OUT.x
Module X OUT
0
DVSS
0
DVCC
1
Direction
0: Input
1: Output
1
0
1
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P3SEL.x
P3IN.x
EN
Module X IN
D
Port P3.0 to P3.7 pin functions
PIN NAME (P3.X)
(P3 X)
1
X
FUNCTION
P3.0/UCB0STE/
/
/
UCA0CLK
CONTROL BITS / SIGNALS
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
0 P3.0 (I/O)
UCB0STE/UCA0CLK (see Note 2 and 4)
P3.1/UCB0SIMO/
/
/
1 P3.1 (I/O)
UCB0SDA
UCB0SIMO/UCB0SDA (see Note 2 and 3)
P3.2/UCB0SOMI/
/
/
2 P3.2 (I/O)
UCB0SCL
UCB0SOMI/UCB0SCL (see Note 2 and 3)
P3.3/UCB0CLK/
/
/
3 P3.3 (I/O)
UCA0STE
UCB0CLK/UCA0STE (see Note 2)
P3.4/UCA0TXD/
/
/
4 P3.4 (I/O)
UCA0SIMO
UCA0TXD/UCA0SIMO (see Note 2)
P3.5/UCA0RXD/
/
/
5 P3.5 (I/O)
UCA0SOMI
UCA0RXD/UCA0SOMI (see Note 2)
P3.6/UCA1TXD/
/
/
6 P3.6 (I/O)
UCA1SIMO
UCA1TXD/UCA1SIMO (see Note 2)
P3.7/UCA1RXD/
/
/
7 P3.7 (I/O)
UCA1SOMI
UCA1RXD/UCA1SOMI (see Note 2)
NOTES: 1. X: Don’t care
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to V SS level.
4. UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A0/B0 is
forced to 3-wire SPI mode if 4-wire SPI mode is selected.
82
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P4 pin schematic: P4.0 to P4.7, input/output with Schmitt trigger
Pad Logic
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK
P4SEL.x
P4IN.x
EN
Module X IN
D
Port P4.0 to P4.7 pin functions
PIN NAME (P4.X)
(P4 X)
P4.0/TB0
/
P4.1/TB1
/
P4.2/TB2
/
P4.3/TB3
/
P4.4/TB4
/
P4.5/TB5
/
P4.6/TB6
/
P4.7/TBCLK
/
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
X
FUNCTION
0 P4.0 (I/O)
Timer_B7.CCI0A and Timer_B7.CCI0B
Timer_B7.TB0
1 P4.1 (I/O)
Timer_B7.CCI1A and Timer_B7.CCI1B
Timer_B7.TB1
2 P4.2 (I/O)
Timer_B7.CCI2A and Timer_B7.CCI2B
Timer_B7.TB2
3 P4.3 (I/O)
Timer_B7.CCI3A and Timer_B7.CCI3B
Timer_B7.TB3
4 P4.4 (I/O)
Timer_B7.CCI4A and Timer_B7.CCI4B
Timer_B7.TB4
5 P4.5 (I/O)
Timer_B7.CCI5A and Timer_B7.CCI5B
Timer_B7.TB5
6 P4.6 (I/O)
Timer_B7.CCI6A and Timer_B7.CCI6B
Timer_B7.TB6
7 P4.7 (I/O)
Timer_B7.TBCLK
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P4DIR.x
P4SEL.x
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
1
1
83
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P5 pin schematic: P5.0 to P5.7, input/output with Schmitt trigger
Pad Logic
P5REN.x
P5DIR.x
0
Module
Direction
1
P5OUT.x
0
Module X OUT
DVSS
0
DVCC
1
Direction
0: Input
1: Output
1
P5.0/UCB1STE/UCA1CLK
P5.1/UCB1SIMO/UCB1SDA
P5.2/UCB1SOMI/UCB1SCL
P5.3/UCB1CLK/UCA1STE
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
P5SEL.x
P5IN.x
EN
Module X IN
D
Port P5.0 to P5.7 pin functions
PIN NAME (P5.X)
(P5 X)
1
X
FUNCTION
P5.0/UCB1STE/
/
/
UCA1CLK
CONTROL BITS / SIGNALS
P5DIR.x
P5SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
0
1
1
1
0 P5.0 (I/O)
UCB1STE/UCA1CLK (see Note 2 and 4)
P5.1/UCB1SIMO/
/
/
1 P5.1 (I/O)
UCB1SDA
UCB1SIMO/UCB1SDA (see Note 2 and 3)
P5.2/UCB1SOMI/
/
/
2 P5.2 (I/O)
UCB1SCL
UCB1SOMI/UCB1SCL (see Note 2 and 3)
P5.3/UCB1CLK/
/
/
3 P5.3 (I/O)
UCA1STE
UCB1CLK/UCA1STE (see Note 2)
P5.4/MCLK
/
4 P5.0 (I/O)
MCLK
P5.5/SMCLK
/
5 P5.1 (I/O)
SMCLK
P5.6/ACLK
/
6 P5.2 (I/O)
ACLK
P5.7/TBOUTH/
/
/
7 P5.7 (I/O)
SVSOUT
TBOUTH
SVSOUT
NOTES: 1. X: Don’t care
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to V SS level.
4. UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output USCI A1/B1 will
be forced to 3-wire SPI mode if 4-wire SPI mode is selected.
84
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P6 pin schematic: P6.0 to P6.4, input/output with Schmitt trigger
Pad Logic
ADC12 Ax
P6REN.x
P6DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.x
DVSS
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
Module X IN
D
Port P6.0 to P6.4 pin functions
PIN NAME (P6.X)
(P6 X)
X
FUNCTION
P6.0/A0
/
0 P6.0 (I/O)
A0 (see Note 2)
P6.1/A1
/
1 P6.1 (I/O)
A1 (see Note 2)
P6.2/A2
/
2 P6.2 (I/O)
A2 (see Note 2)
P6.3/A3
/
3 P6.3 (I/O)
A3 (see Note 2)
P6.4/A4
/
4 P6.4 (I/O)
A4 (see Note 2)
NOTES: 1. X: Don’t care
2. The ADC12 channel Ax is connected to AVss internally if not selected.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P6DIR.x
P6SEL.x
I: 0; O: 1
X
I: 0; O: 1
X
I: 0; O: 1
X
I: 0; O: 1
X
I: 0; O: 1
X
0
X
0
X
0
X
0
X
0
X
85
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P6 pin schematic: P6.5 and P6.6, input/output with Schmitt trigger
Pad Logic
DAC12_0OUT
DAC12AMP > 0
ADC12 Ax
ADC12 Ax
P6REN.x
P6DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.x
DVSS
P6.5/A5/DAC1
P6.6/A6/DAC0
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
Module X IN
D
Port P6.5 to P6.6 pin functions
PIN NAME (P6.X)
X
FUNCTION
P6.5/A5/DAC1†
/ /
†
5 P6.5 (I/O)
DVSS
A5 (see Note 2)
DAC1 (DA12OPS= 1, see Note 3)
P6.6/A6/DAC0†
/ /
†
6 P6.6 (I/O)
DVSS
A6 (see Note 2)
DAC0 (DA12OPS= 0, see Note 3)
† MSP430F261x devices only
NOTES: 1. X: Don’t care
2. The ADC12 channel Ax is connected to AVss internally if not selected.
3. The DAC outputs are floating if not selected.
86
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
CAPD.x or
P6DIR.x
P6SEL.x
DAC12AMP > 0
I: 0; O: 1
1
X
X
I: 0; O: 1
1
X
X
0
1
X
X
0
1
X
X
0
0
1
1
0
0
1
1
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P6 pin schematic: P6.7, input/output with Schmitt trigger
Pad Logic
to SVS Mux
VLD = 15
DAC12_0OUT
DAC12AMP > 0
ADC12 A7
from ADC12
P6REN.7
P6DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.7
DVSS
P6.7/A7/DAC1/SVSIN
Bus
Keeper
EN
P6SEL.7
P6IN.7
EN
Module X IN
D
Port P6.7 pin functions
PIN NAME (P6.X)
(P6 X)
X
FUNCTION
P6.7/A7/DAC1†/
/ /
†/
SVSIN†
7 P6.7 (I/O)
DVSS
A7 (see Note 2)
DAC1 (DA12OPS= 0, see Note 3)
SVSIN (VLD = 15)
NOTES: 1. X: Don’t care
2. The ADC12 channel Ax is connected to AVss internally if not selected.
3. The DAC outputs are floating if not selected.
† MSP430F261x devices only
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P6DIR.x
P6SEL.x
I: 0; O: 1
1
X
X
X
0
1
X
X
X
87
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P7 pin schematic: P7.0 to P7.7, input/output with Schmitt trigger†
Pad Logic
P7REN.x
P7DIR.x
0
0
1
P7OUT.x
0
VSS
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P7.x
P7SEL.x
P7IN.x
EN
Module X IN
D
Port P7.0 to P7.7 pin functions†
PIN NAME (P7.X)
(P7 X)
P7.0
X
0
FUNCTION
P7.0 (I/O)
Input
P7.1
1
P7.2
2
P7.1 (I/O)
Input
P7.2 (I/O)
Input
P7.3
3
P7.3 (I/O)
Input
P7.4
4
P7.5
5
P7.6
6
P7.4 (I/O)
Input
P7.5 (I/O)
Input
P7.6 (I/O)
Input
P7.7
7
P7.7 (I/O)
Input
†
80-pin devices only
88
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P7DIR.x
P7SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P8 pin schematic: P8.0 to P8.5, input/output with Schmitt trigger†
Pad Logic
P8REN.x
P8DIR.x
0
0
1
P8OUT.x
0
VSS
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8SEL.x
P8IN.x
EN
Module X IN
D
Port P8.0 to P8.5 pin functions†
PIN NAME (P8.X)
(P8 X)
P8.0
X
0
FUNCTION
P8.0 (I/O)
Input
P8.1
1
P8.2
2
P8.1 (I/O)
Input
P8.2 (I/O)
Input
P8.3
3
P8.3 (I/O)
Input
P8.4
4
P8.5
5
P8.4 (I/O)
Input
P8.5 (I/O)
Input
†
CONTROL BITS / SIGNALS
P8DIR.x
P8SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
80-pin devices only
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
89
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P8 pin schematic: P8.6, input/output with Schmitt trigger†
BCSCTL3.XT2Sx = 11
0
XT2CLK
From
P8.7/XIN
1
P8.7/XIN
XT2 off
Pad Logic
P8SEL.7
P8REN.6
P8DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.6
DVSS
P8.6/XOUT
Bus
Keeper
EN
P8SEL.6
P8IN.6
EN
Module X IN
D
Port P8.6 pin functions
†
PIN NAME (P8.X)
(P8 X)
P8.6/XOUT
/
X
6
FUNCTION
P8.6 (I/O)
XOUT (default)
†
DV
SS
80-pin devices only
90
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P8DIR.x
P8SEL.x
I: 0; O: 1
0
0
1
1
1
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
Port P8 pin schematic: P8.7, input/output with Schmitt trigger†
BCSCTL3.XT2Sx = 11
P8.6/XOUT
XT2 off
0
XT2CLK
1
P8SEL.6
Pad Logic
P8REN.7
0
P8DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.7
DVSS
P8.7/XIN
Bus
Keeper
EN
P8SEL.7
P8IN.7
EN
Module X IN
D
Port P8.7 pin functions†
PIN NAME (P8.X)
(P8 X)
P8.7/XIN
/
X
7
FUNCTION
P8.7 (I/O)
XIN (default)
†
SS
V
CONTROL BITS / SIGNALS
P8DIR.x
P8SEL.x
I: 0; O: 1
0
0
1
1
1
80-pin devices only
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
91
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
APPLICATION INFORMATION
JTAG pins: TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
Controlled
by JTAG
TDI
TDO/TDI
DVCC DVCC
Fuse
Burn and Test
Fuse
Test
and
Emulation
Module
TDI/TCLK
DVCC
TMS
TMS
DVCC
TCK
TCK
92
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF, of 1 mA at 3 V or 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 49). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
I
TF
TDI/TCLK
Figure 49. Fuse Check Mode Current
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
93
MSP430F241x, MSP430F261x
MIXED SIGNAL MICROCONTROLLER
SLAS541F -- JUNE 2007 -- REVISED DECEMBER 2009
LITERATURE
NUMBER
SLAS541
SLAS541A
SLAS541B
SLAS541C
SLAS541D
SLAS541E
SLAS541F
94
Data Sheet Revision History
SUMMARY
Product Preview release
Production Data release
Corrected the format and the content shown on the first page.
Corrected pin number of P3.6 and P3.7 in 64-pin package in the terminal function list.
Corrected the port schematics.
Corrected “calibration data” section (page 20). Typos and formatting corrected.
Added the figure “typical characteristics - LPM4 current” (Page 33).
Added preview of MSP430F261x BGA devices.
Release to market of MSP430F261x BGA devices
Added the ESD disclaimer (page 1).
Added reserved BGA pins to the terminal function list (pages 10 and following).
Corrected the references in the output port parameters (page 36).
Corrected the cumulative program time of the flash (page 75).
Corrected LFXT1Sx values in Figures 23 and 24 (page 52).
Corrected XT2Sx values in Figures 25 and 26 (page 54).
Corrected tCMErase MIN value from 200 ms to 20 ms and removed two notes in the flash memory table (page 75).
Renamed Tags Used by the ADC Calibration Tags table to Tags used by the TLV Structure (page 20).
Changed value of TAG_ADC12_1 from 0x10 to 0x08 in Tags used by the TLV Structure (page 20).
Added CAOUT to P1.0/TACLK, Changed Timer_A3.CCI0A to Timer_A3.CCI1A and Timer_A3.TA0 to Timer_A3.TA1 in
P1.2/TA1 row, Changed Timer_A3.CCI0A to Timer_A3.CCI2A and Timer_A3.TA0 to Timer_A3.TA2 in P1.3/TA2 row in
Port P1 (P1.0 to P1.7) pin functions table (page 78).
Changed TA0 to Timer_A3.CCI0B in P2.2/CAOUT/TA0/CA4 row of Port P2.0, P2.3, P2.4, P2.6 and P2.7 pin functions
table (page 80).
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2416TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2416TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2416TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2416TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2416TZQW
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
250
Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2416TZQWR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2417TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2417TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2417TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2417TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2417TZQW
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
250
Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2417TZQWR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2418TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2418TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2418TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2418TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2418TZQW
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
250
Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2418TZQWR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2419TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2419TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2419TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2419TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2419TZQW
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
250
Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2419TZQWR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2616TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2616TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2616TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2616TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2616TZQW
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
250
Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2616TZQWR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2617TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2617TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2617TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2617TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2617TZQW
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
250
Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2617TZQWR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2618TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2618TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2618TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2618TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2618TZQW
ACTIVE
BGA MI
ZQW
113
250
SNAGCU
Level-3-260C-168 HR
Addendum-Page 2
Green (RoHS &
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
4-Dec-2009
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CROSTA
R JUNI
OR
MSP430F2618TZQWR
ACTIVE
MSP430F2619TPM
ACTIVE
MSP430F2619TPMR
BGA MI
CROSTA
R JUNI
OR
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
ZQW
113
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2619TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2619TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2619TZQW
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
250
Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F2619TZQWR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2009
OTHER QUALIFIED VERSIONS OF MSP430F2618 :
• Enhanced Product: MSP430F2618-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 4
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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