Intel A80960JA-16 Embedded 32-bit microprocessor Datasheet

80960JA/JF/JD/JT 3.3 V EMBEDDED
32-BIT MICROPROCESSOR
Advance Information Datasheet
Product Features
■
■
■
■
■
Pin/Code Compatible with all 80960Jx
Processors
High-Performance Embedded Architecture
—One Instruction/Clock Execution
—Core Clock Rate is:
80960JA/JF 1x the Bus Clock
80960JD 2x the Bus Clock
80960JT 3x the Bus Clock
—Load/Store Programming Model
—Sixteen 32-Bit Global Registers
—Sixteen 32-Bit Local Registers (8 sets)
—Nine Addressing Modes
—User/Supervisor Protection Model
Two-Way Set Associative Instruction
Cache
—80960JA - 2 Kbyte
—80960JF/JD - 4 Kbyte
—80960JT - 16 Kbyte
—Programmable Cache-Locking
Mechanism
Direct Mapped Data Cache
—80960JA - 1 Kbyte
—80960JF/JD - 2 Kbyte
—80960JT - 4 Kbyte
—Write Through Operation
On-Chip Stack Frame Cache
—Seven Register Sets Can Be Saved
—Automatic Allocation on Call/Return
—0-7 Frames Reserved for High-Priority
Interrupts
■
■
■
■
■
■
■
■
On-Chip Data RAM
—1 Kbyte Critical Variable Storage
—Single-Cycle Access
3.3 V Supply Voltage
—5 V Tolerant Inputs
—TTL Compatible Outputs
High Bandwidth Burst Bus
—32-Bit Multiplexed Address/Data
—Programmable Memory Configuration
—Selectable 8-, 16-, 32-Bit Bus Widths
—Supports Unaligned Accesses
—Big or Little Endian Byte Ordering
High-Speed Interrupt Controller
—31 Programmable Priorities
—Eight Maskable Pins plus NMI
—Up to 240 Vectors in Expanded Mode
Two On-Chip Timers
—Independent 32-Bit Counting
—Clock Prescaling by 1, 2, 4 or 8
—lnternal Interrupt Sources
Halt Mode for Low Power
IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
Packages
—132-Lead Pin Grid Array (PGA)
—132-Lead Plastic Quad Flat Pack
(PQFP)
—196-Ball Mini Plastic Ball Grid Array
(MPBGA)
Notice: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 273159-001
March, 1998
80960JA/JF/JD/JT 3.3 V Microprocessor
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 80960JA/JF/JD/JT 3.3 V Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Contents
1.0
Introduction .................................................................................................................. 7
2.0
80960Jx Overview ...................................................................................................... 7
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
3.0
Package Information ...............................................................................................14
3.1
3.2
3.3
4.0
Pin Descriptions ..................................................................................................16
3.1.1 Functional Pin Definitions.......................................................................16
3.1.2 80960Jx 132-Lead PGA Pinout..............................................................22
3.1.3 80960Jx 132-Lead PQFP Pinout............................................................26
3.1.4 80960Jx 196-Ball MPBGA Pinout ..........................................................29
Package Thermal Specifications .........................................................................34
Thermal Management Accessories.....................................................................38
3.3.1 Heatsinks................................................................................................38
Electrical Specifications ........................................................................................39
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5.0
80960 Processor Core .......................................................................................... 9
Burst Bus.............................................................................................................10
Timer Unit............................................................................................................10
Priority Interrupt Controller ..................................................................................10
Instruction Set Summary .....................................................................................11
Faults and Debugging .........................................................................................11
Low Power Operation..........................................................................................11
Test Features ......................................................................................................12
Memory-Mapped Control Registers ....................................................................12
Data Types and Memory Addressing Modes ......................................................12
Absolute Maximum Ratings.................................................................................39
Operating Conditions...........................................................................................39
Connection Recommendations ...........................................................................40
VCC5 Pin Requirements (VDIFF) .......................................................................40
VCCPLL Pin Requirements.................................................................................41
DC Specifications ................................................................................................42
AC Specifications ................................................................................................44
4.7.1 AC Test Conditions and Derating Curves ..............................................47
4.7.2 AC Timing Waveforms ...........................................................................52
Bus Functional Waveforms..................................................................................58
5.1
5.2
Basic Bus States .................................................................................................68
Boundary-Scan Register .....................................................................................69
6.0
Device Identification ...............................................................................................74
7.0
Revision History .......................................................................................................77
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3
80960JA/JF/JD/JT 3.3 V Microprocessor
Figures
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80960Jx Microprocessor Package Options...........................................................7
80960Jx Block Diagram ........................................................................................9
132-Lead Pin Grid Array Bottom View - Pins Facing Up.....................................22
132-Lead Pin Grid Array Top View - Pins Facing Down .....................................23
132-Lead PQFP - Top View ................................................................................26
196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up ..................29
196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down ..................30
VCC5 Current-Limiting Resistor ..........................................................................40
VCCPLL Lowpass Filter ......................................................................................41
AC Test Load ......................................................................................................47
Output Delay or Hold vs. Load Capacitance .......................................................48
TLX vs. AD Bus Load Capacitance......................................................................48
80960JA/JF ICC Active (Power Supply) vs. Frequency .......................................49
80960JA/JF ICC Active (Thermal) vs. Frequency ................................................49
80960JD ICC Active (Power Supply) vs. Frequency............................................50
80960JD ICC Active (Thermal) vs. Frequency.....................................................50
80960JT ICC Active (Power Supply) vs. Frequency ...........................................51
80960JT ICC Active (Thermal) vs. Frequency .....................................................51
CLKIN Waveform ................................................................................................52
TOV1 Output Delay Waveform .............................................................................52
TOF Output Float Waveform................................................................................53
TIS1 and TIH1 Input Setup and Hold Waveform ...................................................53
TIS2 and TIH2 Input Setup and Hold Waveform ...................................................53
TIS3 and TIH3 Input Setup and Hold Waveform ...................................................54
TIS4 and TIH4 Input Setup and Hold Waveform ...................................................54
TLX, TLXL and TLXA Relative Timings Waveform.................................................55
DT/R and DEN Timings Waveform .....................................................................55
TCK Waveform....................................................................................................56
TBSIS1 and TBSIH1 Input Setup and Hold Waveforms .........................................56
TBSOV1 and TBSOF1 Output Delay and Output Float Waveform..........................56
TBSOV2 and TBSOF2 Output Delay and Output Float Waveform..........................57
TBSIS2 and TBSIH2 Input Setup and Hold Waveform ...........................................57
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .........58
Burst Read and Write Transactions Without Wait States, 32-Bit Bus .................59
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus...........................60
Burst Read and Write Transactions Without Wait States, 8-Bit Bus ...................61
Burst Read and Write Transactions With 1, 0 Wait States and
Extra Tr State on Read, 16-Bit Bus .....................................................................62
Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit Bus, Little Endian .................................................63
HOLD/HOLDA Waveform For Bus Arbitration ....................................................64
Cold Reset Waveform .........................................................................................65
Warm Reset Waveform .......................................................................................66
Entering the ONCE State ....................................................................................67
Bus States with Arbitration ..................................................................................68
Summary of Aligned and Unaligned Accesses (32-Bit Bus) ...............................72
Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ...........73
80960JT Device Identification Register...............................................................74
80960JD Device Identification Register ..............................................................75
80960JA/JF Device Identification Register .........................................................76
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
80960Jx Instruction Set.......................................................................................13
Pin Description Nomenclature.............................................................................16
Pin Description — External Bus Signals .............................................................17
Pin Description — Processor Control Signals, Test Signals and Power .............20
Pin Description — Interrupt Unit Signals .............................................................21
132-Lead PGA Pinout — In Signal Order............................................................24
132-Lead PGA Pinout — In Pin Order ................................................................25
132-Lead PQFP Pinout — In Signal Order .........................................................27
132-Lead PQFP Pinout — In Pin Order ..............................................................28
196-Ball MPBGA Pinout — In Signal Order ........................................................31
196-Ball MPBGA Pinout — In Pin Order .............................................................33
132-Lead PGA Package Thermal Characteristics...............................................35
196-Ball MPBGA Package Thermal Characteristics ...........................................35
132-Lead PQFP Package Thermal Characteristics ............................................36
Maximum TA at Various Airflows in °C (80960JT) ...............................................36
Maximum TA at Various Airflows in °C (80960JD) ..............................................37
Maximum TA at Various Airflows in °C (80960JA/JF)..........................................37
Absolute Maximum Ratings.................................................................................39
80960Jx Operating Conditions ............................................................................39
VDIFF Parameters ..............................................................................................40
80960Jx DC Characteristics................................................................................42
80960Jx ICC Characteristics................................................................................42
80960Jx AC Characteristics ................................................................................44
Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44) ...................47
Boundary-Scan Register Bit Order......................................................................69
Natural Boundaries for Load and Store Accesses ..............................................70
Summary of Byte Load and Store Accesses.......................................................70
Summary of Short Word Load and Store Accesses............................................70
Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)...........................71
80960Jx Device Type and Stepping Reference ..................................................74
Fields of 80960JT Device ID ...............................................................................75
80960JT Device ID Model Types ........................................................................75
Fields of 80960JD Device ID...............................................................................76
80960JD Device ID Model Types........................................................................76
Fields of 80960JA/JF Device ID ..........................................................................77
80960JA/JF Device ID Model Types ...................................................................77
Data Sheet Revision History ...............................................................................77
Advance Information Datasheet
5
80960JA/JF/JD/JT 3.3 V Microprocessor
1.0
Introduction
This document contains information for the 80960Jx microprocessor, including electrical
characteristics and package pinout information. Detailed functional descriptions — other than
parametric performance — are published in the i960® Jx Microprocessor Developer’s Manual
(272483).
Figure 1.
80960Jx Microprocessor Package Options
i
A80960JX
XXXXXXXXSS
M
© 19xx
i960
i
®
i
GD80960JX
XXXXXXXSS
M © 19xx
NG80960JX
XXXXXXXX SS
M
© 19xx
136-Ball MPBGA
132-Pin PQFP
132-Pin PGA
Throughout this data sheet, references to “80960Jx” indicate features that apply to all of the
following:
• 80960JA — 3.3 V (5 V Tolerant), 2 Kbyte instruction cache, 1 Kbyte data cache
• 80960JF — 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache
• 80960JD — 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache and clock
doubling
• 80960JT — 3.3 V (5 V Tolerant), 16 Kbyte instruction cache, 4 Kbyte data cache and clock
tripling
2.0
80960Jx Overview
The 80960Jx offers high performance to cost-sensitive 32-bit embedded applications. The 80960Jx
is object code compatible with the 80960 Core Architecture and is capable of sustained execution
at the rate of one instruction per clock. This processor’s features include generous instruction
cache, data cache and data RAM. It also boasts a fast interrupt mechanism and dual-programmable
timer units.
The 80960Jx’s clock multiplication operates the processor core at two or three times the bus clock
rate to improve execution performance without increasing the complexity of board designs.
Memory subsystems for cost-sensitive embedded applications often impose substantial wait state
penalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPU
execution from the external bus.
Advance Information Datasheet
7
80960JA/JF/JD/JT 3.3 V Microprocessor
The 80960Jx rapidly allocates and deallocates local register sets during context switches. The
processor needs to flush a register set to the stack only when it saves more than seven sets to its
local register cache.
A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full
complement of control signals simplifies the connection of the 80960Jx to external components.
The user programs physical and logical memory attributes through memory-mapped control
registers (MMRs) — an extension not found on the i960 Kx, Sx or Cx processors. Physical and
logical configuration registers enable the processor to operate with all combinations of bus width
and data object alignment. The processor supports a homogeneous byte ordering model.
This processor integrates two important peripherals: a timer unit, and an interrupt controller. These
and other hardware resources are programmed through memory-mapped control registers, an
extension to the familiar 80960 architecture.
The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and
general-purpose system timing. These operate in either single-shot or auto-reload mode and can
generate interrupts.
The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts.
The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The
ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt
latency. Clock doubling reduces interrupt latency by 40% compared to the 80960JA/JF, and clock
tripling reduces interrupt latency by 20% compared to the 80960JD. Local registers may be
dedicated to high-priority interrupts to further reduce latency. Acting independently from the core,
the ICU compares the priorities of posted interrupts with the current process priority, off-loading
this task from the core. The ICU also supports the integrated timer interrupts.
The 80960Jx features a Halt mode designed to support applications where low power consumption
is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up
to 90 percent.
The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and Boundary
Scan (JTAG), provide a powerful environment for design debug and fault diagnosis.
The Solutions960® program features a wide variety of development tools which support the i960
processor family. Many of these tools are developed by partner companies; some are developed by
Intel, such as profile-driven optimizing compilers. For more information on these products, contact
your local Intel representative.
8
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 2.
80960Jx Block Diagram
CLKIN
32-bit buses
address / data
PLL, Clocks,
Power Mgmt
Instruction Cache
Bus
Control Unit
80960JA - 2K
80960JF/JD - 4K
TAP
5
Bus Request
Queues
80960JT - 16K
Boundary Scan
Controller
Constants
DEST
SRC1
32-bit Address
32-bit Data
DEST
SRC1
SRC2
DEST
Memory
Interface
Unit
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
2.1
Address/
Data Bus
32
Interrupt
Port
Programmable
Interrupt Controller
9
Control
Execution
and
Address
Generation
Unit
effective
address
SRC2
SRC2 DEST
Multiply
Divide
Unit
SRC1
SRC1
21
Two 32-Bit
Timers
8-Set
Local Register Cache
Global / Local
Register File
Control
Two-Way Set Associative
Instruction Sequencer
128
Physical Region
Configuration
Memory-Mapped
Register Interface
1K Data RAM
Direct Mapped
Data Cache
80960JA - 1K
80960JF/JD - 2K
80960JT - 4K
80960 Processor Core
The 80960Jx family is a scalar implementation of the 80960 Core Architecture. Intel designed this
processor core as a very high performance device that is also cost-effective. Factors that contribute
to the core’s performance include:
•
•
•
•
•
•
•
•
•
•
Core operates at the bus speed with the 80960JA/JF
Core operates at two or three times the bus speed with the 80960JD and 80960JT respectively
Single-clock execution of most instructions
Independent Multiply/Divide Unit
Efficient instruction pipeline minimizes pipeline break latency
Register and resource scoreboarding allow overlapped instruction execution
128-bit register bus speeds local register caching
Two-way set associative, integrated instruction cache
Direct-mapped, integrated data cache
1 Kbyte integrated data RAM delivers zero wait state program data
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9
80960JA/JF/JD/JT 3.3 V Microprocessor
2.2
Burst Bus
A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory
and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit
words per six clock cycles. The external address/data bus is multiplexed.
Users may configure the 80960Jx’s bus controller to match an application’s fundamental memory
organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and
data caching are programmed through a group of logical memory templates and a defaults register.
The BCU’s features include:
•
•
•
•
•
•
Multiplexed external bus to minimize pin count
32-, 16- and 8-bit bus widths to simplify I/O interfaces
External ready control for address-to-data, data-to-data and data-to-next-address wait state types
Support for big or little endian byte ordering to facilitate the porting of existing program code
Unaligned bus accesses performed transparently
Three-deep load/store queue to decouple the bus from the core
Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it
performs an external bus confidence test by performing a checksum on the first words of the
initialization boot record (IBR).
The user may examine the contents of the caches by executing special cache control instructions.
2.3
Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several
clock rates and generating interrupts. Each is programmed by use of the TU registers. These
memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot
mode and auto-reload capabilities for continuous operation. Each timer has an independent
interrupt request to the 80960Jx’s interrupt controller. The TU can generate a fault when
unauthorized writes from user mode are detected. Clock prescaling is supported.
2.4
Priority Interrupt Controller
A programmable interrupt controller manages up to 240 external sources through an 8-bit external
interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or
level-triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer
channels and a single Non-Maskable Interrupt (NMI) pin. Interrupts are serviced according to their
priority levels relative to the current process priority.
Low interrupt latency is critical to many embedded applications. As part of its highly flexible
interrupt mechanism, the 80960Jx exploits several techniques to minimize latency:
•
•
•
•
10
Interrupt vectors and interrupt handler routines can be reserved on-chip
Register frames for high-priority interrupt handlers can be cached on-chip
The interrupt stack can be placed in cacheable memory space
Interrupt microcode executes at two or three times the bus frequency for the 80960JD and
80960JT respectively
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
2.5
Instruction Set Summary
The 80960Jx adds several new instructions to the i960 core architecture. The new instructions are:
•
•
•
•
•
•
•
Conditional Move
Conditional Add
Conditional Subtract
Byte Swap
Halt
Cache Control
Interrupt Control
Table 1 identifies the instructions that the 80960Jx supports. Refer to the i960® Jx Microprocessor
Developer’s Manual (272483) for a detailed description of each instruction.
2.6
Faults and Debugging
The 80960Jx employs a comprehensive fault model. The processor responds to faults by making
implicit calls to a fault handling routine. Specific information collected for each fault allows the
fault handler to diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to
detect as many as seven different trace event types. Alternatively, mark and fmark instructions
can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are
also available to trap on execution and data addresses.
2.7
Low Power Operation
Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’s
sub-micron topology provides the circuit density for optimal cache size and high operating speeds
while dissipating modest power. The processor also uses dynamic power management to turn off
clocks to unused circuits.
Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode,
the processor core stops completely while the integrated peripherals continue to function, reducing
overall power requirements up to 90 percent. Processor execution resumes from internally or
externally generated interrupts.
Advance Information Datasheet
11
80960JA/JF/JD/JT 3.3 V Microprocessor
2.8
Test Features
The 80960Jx incorporates numerous features which enhance the user’s ability to test both the
processor and the system to which it is attached. These features include ONCE (On-Circuit
Emulation) mode and Boundary Scan (JTAG).
The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1).
One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE
mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism.
ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to
electrically “remove” itself from a circuit board. This allows for system-level testing where a
remote tester — such as an in-circuit emulator — can exercise the processor system.
The provided test logic does not interfere with component or circuit board behavior and ensures
that components function correctly, connections between various components are correct, and
various components interact correctly on the printed circuit board.
The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing.
It can examine connections which might otherwise be inaccessible to a test system.
2.9
Memory-Mapped Control Registers
The 80960Jx, though compliant with i960 series processor core, has the added advantage of
memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These
give software the interface to easily read and modify internal control registers.
Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished
through regular memory-format instructions. The processor ensures that these accesses do not
generate external bus cycles.
2.10
Data Types and Memory Addressing Modes
As with all i960 family processors, the 80960Jx instruction set supports several data types and formats:
•
•
•
•
•
•
Bit
Bit fields
Integer (8-, 16-, 32-, 64-bit)
Ordinal (8-, 16-, 32-, 64-bit unsigned integers)
Triple word (96 bits)
Quad word (128 bits)
The 80960Jx provides a full set of addressing modes for C and assembly programming:
•
•
•
•
12
Two Absolute modes
Five Register Indirect modes
Index with displacement
IP with displacement
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 1.
80960Jx Instruction Set
Data Movement
Arithmetic
Logical
Bit, Bit Field and Byte
Add
Subtract
Multiply
And
Divide
Not And
Remainder
And Not
Load
Modulo
Or
Store
Shift
Exclusive Or
Move
Extended Shift
Not Or
*Conditional Select
Extended Multiply
Or Not
Load Address
Extended Divide
Nor
Add with Carry
Exclusive Nor
Subtract with Carry
Not
*Conditional Add
Nand
Set Bit
Clear Bit
Not Bit
Alter Bit
Scan For Bit
Span Over Bit
Extract
Modify
Scan Byte for Equal
*Byte Swap
*Conditional Subtract
Rotate
Comparison
Branch
Compare
Conditional Compare
Compare and Increment
Compare and Decrement
Test Condition Code
Fault
Call
Unconditional Branch
Call Extended
Conditional Branch
Call System
Compare and Branch
Return
Conditional Fault
Synchronize Faults
Branch and Link
Check Bit
Debug
Call/Return
Processor Management
Atomic
Flush Local Registers
Modify Arithmetic
Controls
Modify Trace Controls
Mark
Force Mark
Modify Process Controls
Atomic Add
*Halt
Atomic Modify
System Control
*Cache Control
*Interrupt Control
Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB implementations.
Advance Information Datasheet
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80960JA/JF/JD/JT 3.3 V Microprocessor
3.0
Package Information
The 80960Jx is offered with four speeds and three package types. The 132-pin Pin Grid Array
(PGA) device is specified for operation at VCC = 3.3 V ± 0.15 V over a case temperature range of
0° to 100°C:
•
•
•
•
•
•
•
•
•
A80960JT-100 (100 MHz core, 33 MHz bus)
A80960JT-75 (75 MHz core, 25 MHz bus)
A80960JD-66 (66 MHz core, 33 MHz bus)
A80960JD-50 (50 MHz core, 25 MHz bus)
A80960JD-40 (40 MHz core, 20 MHz bus)
A80960JD-33 (33 MHz core, 16 MHz bus)
A80960JA/JF-33 (33 MHz)
A80960JA/JF-25 (25 MHz)
A80960JA/JF-16 (16 MHz)
The 132-pin Plastic Quad Flatpack (PQFP) devices are specified for operation at
VCC = 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C:
•
•
•
•
•
•
•
•
•
NG80960JT-100 (100 MHz core, 33 MHz bus)
NG80960JT-75 (75 MHz core, 25 MHz bus)
NG80960JD-66 (66 MHz core, 33 MHz bus)
NG80960JD-50 (50 MHz core, 25 MHz bus)
NG80960JD-40 (40 MHz core, 20 MHz bus)
NG80960JD-33 (33 MHz core, 16 MHz bus)
NG80960JA/JF-33 (33 MHz)
NG80960JA/JF-25 (25 MHz)
NG80960JA/JF-16 (16 MHz)
An extended temperature 132-pin Plastic Quad Flatpack (PQFP) device is specified for operation
at VCC = 3.3 V ± 0.15 V over a case temperature range of -40° to 100°C:
• TG80960JA-25 (25 MHz)
14
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
The 196-ball Mini Plastic Ball Grid Array (MPBGA) device is specified for operation at
VCC = 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C:
•
•
•
•
•
•
•
•
GD80960JT-100 (100 MHz core, 33 MHz bus)
GD80960JT-75 (75 MHz core, 25 MHz bus)
GD80960JD-50 (50 MHz core, 25 MHz bus)
GD80960JD-40 (40 MHz core, 20 MHz bus)
GD80960JD-33 (33 MHz core, 16 MHz bus)
GD80960JA/JF-33 (33 MHz)
GD80960JA/JF-25 (25 MHz)
GD80960JA/JF-16 (16 MHz)
For package specifications and information, refer to Intel’s Packaging Handbook (240800).
Advance Information Datasheet
15
80960JA/JF/JD/JT 3.3 V Microprocessor
3.1
Pin Descriptions
This section describes the pins for the 80960Jx in the 132-pin ceramic Pin Grid Array (PGA)
package, 132-lead Plastic Quad Flatpack Package (PQFP) and 196-ball Mini Plastic Ball Grid
Array (MPBGA).
Section 3.1.1, “Functional Pin Definitions”, describes pin function; Section 3.1.2, “80960Jx
132-Lead PGA Pinout”, Section 3.1.3, “80960Jx 132-Lead PQFP Pinout” and Section 3.1.4,
“80960Jx 196-Ball MPBGA Pinout”, define the signal and pin locations for the supported package
types.
3.1.1
Functional Pin Definitions
Table 2 presents the legend for interpreting the pin descriptions which follow. Pins associated with
the bus interface are described in Table 3. Pins associated with basic control and test functions are
described in Table 4. Pins associated with the Interrupt Unit are described in Table 5.
Table 2.
Pin Description Nomenclature
Symbol
Description
I
Input pin only.
O
Output pin only.
I/O
Pin can be either an input or output.
–
Pin must be connected as described.
Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation.
S
S(E) Edge sensitive input
S(L) Level sensitive input
Asynchronous. Inputs may be asynchronous relative to CLKIN.
A (...)
A(E) Edge sensitive input
A(L) Level sensitive input
While the processor’s RESET pin is asserted, the pin:
R (...)
R(1) is driven to VCC
R(0) is driven to VSS
R(Q) is a valid output
R(X) is driven to unknown state
R(H) is pulled up to VCC
While the processor is in the hold state, the pin:
H (...)
H(1) is driven to VCC
H(0) is driven to VSS
H(Q) Maintains previous state or continues to be a valid output
H(Z) Floats
While the processor is halted, the pin:
P (...)
16
P(1) is driven to VCC
P(0) is driven to VSS
P(Q) Maintains previous state or continues to be a valid output
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 3.
Pin Description — External Bus Signals (Sheet 1 of 3)
NAME
TYPE
DESCRIPTION
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data
to and from memory. During an address (Ta) cycle, bits 31:2 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, read or write
data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,
AD15:8 and AD7:0. During write operations, unused pins are driven to determinate
values.
SIZE, which comprises bits 0-1 of the AD lines during a Ta cycle, specifies the
number of data transfers during the bus transaction.
AD31:0
I/O
S(L)
R(X)
H(Z)
P(Q)
AD1
AD0
Bus Transfers
0
0
1
1
0
1
0
1
1 Transfer
2 Transfers
3 Transfers
4 Transfers
When the processor enters Halt mode, if the previous bus operation was a:
• write — AD31:2 are driven with the last data value on the AD bus.
• read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are
driven with the value of A3:2 from the last data cycle.
Typically, AD1:0 reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
ALE
O
R(0)
H(Z)
P(0)
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a Ta cycle and deasserted before the beginning of the Td state. It is
active HIGH and floats to a high impedance state during a hold cycle (Th).
ALE
O
R(1)
H(Z)
P(1)
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is the
inverted version of ALE. This signal gives the 80960Jx a high degree of compatibility
with existing 80960Kx systems.
ADS
O
R(1)
H(Z)
P(1)
ADDRESS STROBE indicates a valid address and the start of a new bus access.
The processor asserts ADS for the entire Ta cycle. External bus control logic typically
samples ADS at the end of the cycle.
ADDRESS3:2 comprise a partial demultiplexed address bus.
A3:2
O
R(X)
H(Z)
P(Q)
32-bit memory accesses: the processor asserts address bits A3:2 during Ta. The
partial word address increments with each assertion of RDYRCV during a burst.
16-bit memory accesses: the processor asserts address bits A3:1 during Ta with A1
driven on the BE1 pin. The partial short word address increments with each
assertion of RDYRCV during a burst.
8-bit memory accesses: the processor asserts address bits A3:0 during Ta, with A1:0
driven on BE1:0. The partial byte address increments with each assertion of
RDYRCV during a burst.
Advance Information Datasheet
17
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 3.
Pin Description — External Bus Signals (Sheet 2 of 3)
NAME
TYPE
DESCRIPTION
BYTE ENABLES select which of up to four data bytes on the bus participate in the
current bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:
BE3:0
O
R(1)
H(Z)
P(1)
32-bit bus:
BE3 enables data on AD31:24
BE2 enables data on AD23:16
BE1 enables data on AD15:8
BE0 enables data on AD7:0
16-bit bus:
BE3 becomes Byte High Enable (enables data on AD15:8)
BE2 is not used (state is high)
BE1 becomes Address Bit 1 (A1)
BE0 becomes Byte Low Enable (enables data on AD7:0)
8-bit bus:
BE3 is not used (state is high)
BE2 is not used (state is high)
BE1 becomes Address Bit 1 (A1)
BE0 becomes Address Bit 0 (A0)
The processor asserts byte enables, byte high enable and byte low enable during Ta.
Since unaligned bus requests are split into separate bus transactions, these signals
do not toggle during a burst. They remain active through the last Td cycle.
For accesses to 8- and 16-bit memory, the processor asserts the address bits in
conjunction with A3:2 described above.
WIDTH/HALTED signals denote the physical memory attributes for a bus
transaction:
WIDTH/
HLTD1:0
O
R(0)
H(Z)
P(1)
WIDTH/HLTD1
WIDTH/HLTD0
0
0
1
1
0
1
0
1
8 Bits Wide
16 Bits Wide
32 Bits Wide
Processor Halted
The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in
response to a HOLD request, regardless of prior operating state.
D/C
O
R(X)
H(Z)
P(Q)
W/R
O
R(0)
H(Z)
P(Q)
DT/R
O
R(0)
H(Z)
P(Q)
DEN
18
O
R(1)
H(Z)
P(1)
DATA/CODE indicates that a bus access is a data access (1) or an instruction
access (0). D/C has the same timing as W/R.
0 = instruction access
1 = data access
WRITE/READ specifies, during a Ta cycle, whether the operation is a write (1) or
read (0). It is latched on-chip and remains valid during Td cycles.
0 = read
1 = write
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the
address/data bus. It is low during Ta and Tw/Td cycles for a read; it is high during Ta
and Tw/Td cycles for a write. DT/R never changes state when DEN is asserted.
0 = receive
1 = transmit
DATA ENABLE indicates data transfer cycles during a bus access. DEN is asserted
at the start of the first data cycle in a bus access and deasserted at the end of the
last data cycle. DEN is used with DT/R to provide control for data transceivers
connected to the data bus.
0 = data cycle
1 = not data cycle
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 3.
Pin Description — External Bus Signals (Sheet 3 of 3)
NAME
TYPE
BLAST
O
R(1)
H(Z)
P(1)
DESCRIPTION
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the
last data transfer of burst and non-burst accesses. BLAST remains active as long as
wait states are inserted via the RDYRCV pin. BLAST becomes inactive after the final
data transfer in a bus cycle.
0 = last data transfer
1 = not last data transfer
READY/RECOVER indicates that data on AD lines can be sampled or removed. If
RDYRCV is not asserted during a Td cycle, the Td cycle is extended to the next cycle
by inserting a wait state (Tw).
RDYRCV
I
S(L)
0 = sample data
1 = don’t sample data
The RDYRCV pin has another function during the recovery (Tr) state. The processor
continues to insert additional recovery states until it samples the pin HIGH. This
function gives slow external devices more time to float their buffers before the
processor begins to drive address again.
0 = insert wait states
1 = recovery complete
BUS LOCK indicates that an atomic read-modify-write operation is in progress. The
LOCK output is asserted in the first clock of an atomic operation and deasserted in
the last data transfer of the sequence. The processor does not grant HOLDA while it
is asserting LOCK. This prevents external agents from accessing memory involved
in semaphore operations.
LOCK/
ONCE
I/O
S(L)
R(H)
H(Z)
P(1)
0 = Atomic read-modify-write in progress
1 = Atomic read-modify-write not in progress
ONCE MODE: The processor samples the ONCE input during reset. If it is asserted
LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the
processor stops all clocks and floats all output pins. The pin has a weak internal
pullup which is active during reset to ensure normal operation when the pin is left
unconnected.
0 = ONCE mode enabled
1 = ONCE mode not enabled
HOLD
I
S(L)
HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the Th state. When
HOLD is deasserted, the processor deasserts HOLDA and enters either the Ti or Ta
state, resuming control of the address/data and control lines.
0 = no hold request
1 = hold request
HOLDA
BSTAT
O
R(Q)
H(1)
P(Q)
O
R(0)
H(Q)
P(0)
Advance Information Datasheet
HOLD ACKNOWLEDGE indicates to an external bus master that the processor has
relinquished control of the bus. The processor can grant HOLD requests and enter
the Th state during reset and while halted as well as during regular operation.
0 = hold not acknowledged
1 = hold acknowledged
BUS STATUS indicates that the processor may soon stall unless it has sufficient
access to the bus; see i960® Jx Microprocessor Developer’s Manual (272483).
Arbitration logic can examine this signal to determine when an external bus master
should acquire/relinquish the bus.
0 = no potential stall
1 = potential stall
19
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 4.
Pin Description — Processor Control Signals, Test Signals and Power
NAME
TYPE
DESCRIPTION
CLKIN
I
CLOCK INPUT provides the processor’s fundamental time base; both the processor
core and the external bus run at the CLKIN rate. All input and output timings are
specified relative to a rising CLKIN edge.
RESET initializes the processor and clears its internal logic. During reset, the
processor places the address/data bus and control output pins in their idle (inactive)
states.
RESET
I
A(L)
During reset, the input pins are ignored with the exception of LOCK/ONCE, STEST
and HOLD.
The RESET pin has an internal synchronizer. To ensure predictable processor
initialization during power up, RESET must be asserted a minimum of 10,000 CLKIN
cycles with VCC and CLKIN stable. On a warm reset, RESET should be asserted for
a minimum of 15 cycles.
STEST
I
S(L)
SELF TEST enables or disables the processor’s internal self-test feature at
initialization. STEST is examined at the end of reset. When STEST is asserted, the
processor performs its internal self-test and the external bus confidence test. When
STEST is deasserted, the processor performs only the external bus confidence test.
0 = self test disabled
1 = self test enabled
FAIL
O
R(0)
H(Q)
P(1)
FAIL indicates a failure of the processor’s built-in self-test performed during
initialization. FAIL is asserted immediately upon reset and toggles during self-test to
indicate the status of individual tests:
• When self-test passes, the processor deasserts FAIL and begins operation from
user code.
• When self-test fails, the processor asserts FAIL and then stops executing.
0 = self test failed
1 = self test passed
20
TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.
TCK
I
TDI
I
S(L)
TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising
edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.
TDO
O
R(Q)
HQ)
P(Q)
TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling
edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At
other times, TDO floats. TDO does not float during ONCE mode.
TRST
I
A(L)
TEST RESET asynchronously resets the Test Access Port (TAP) controller function
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
feature, connect a pulldown resistor between this pin and VSS. If TAP is not used,
this pin must be connected to VSS; however, no resistor is required. See Section 4.3,
“Connection Recommendations” on page 40.
TMS
I
S(L)
TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of
the test logic for IEEE 1149.1 Boundary Scan testing.
VCC
–
POWER pins intended for external connection to a VCC board plane.
VCCPLL
–
PLL POWER is a separate VCC supply pin for the phase lock loop clock generator. It
is intended for external connection to the VCC board plane. In noisy environments,
add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects
on timing relationships.
VCC5
–
5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O
buffers. This signal should be connected to +5 V for use with inputs which exceed
3.3 V. If all inputs are from 3.3 V components, this pin should be connected to 3.3 V.
VSS
–
GROUND pins intended for external connection to a VSS board plane.
NC
–
NO CONNECT pins. Do not make any system connections to these pins.
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 5.
Pin Description — Interrupt Unit Signals
NAME
TYPE
DESCRIPTION
EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT7:0
pins can be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs
can be programmed to be level (low) or edge (falling) sensitive.
XINT7:0
I
A(E/L)
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins
are level sensitive in this mode.
Mixed Mode: The XINT7:5 pins act as dedicated sources and the XINT4:0 pins act
as the five most significant bits of a vectored source. The least significant bits of the
vectored source are set to 0102 internally.
Unused external interrupt pins should be connected to VCC.
NMI
I
A(E)
Advance Information Datasheet
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source and is falling edge-triggered. If NMI is
unused, it should be connected to VCC.
21
80960JA/JF/JD/JT 3.3 V Microprocessor
3.1.2
80960Jx 132-Lead PGA Pinout
Figure 3.
132-Lead Pin Grid Array Bottom View - Pins Facing Up
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
P
AD25
AD22 AD19
AD18
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AD13 AD11
AD6
AD27
AD26 AD24
AD20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD10 AD7
AD3
AD30
AD29
NC
AD23 AD21
AD17
AD16
AD12
AD9
AD8
AD4
AD0
BE2
BE3
AD28
AD5
AD1
VCC
VCC
VSS
AD31
AD2
VSS
VCC
VCC
VSS
BE1
NC
VSS
VCC
VCC
VSS
BE0
VCC
VSS
ALE
VCC
VSS BSTAT
VCC
VSS
DEN
VCC
VSS
DT/R
N
N
M
M
AD15 AD14
L
L
K
K
J
J
H
H
VCCPLL VSS
CLKIN
G
G
NC
VSS
VCC
RDYRCV VSS
VCC
RESET VSS
VCC
F
F
E
E
D
D
TDI
VSS
VCC
C
C
LOCK/ HOLDA BLAST
ONCE
A3
A2
FAIL
VCC5
NC
NC
VSS
VSS
VSS
VCC
VCC
VCC
6
7
8
HOLD XINT1 XINT0 TRST STEST
NC
B
B
W/R
D/C
WIDTH/ TDO
HLTD0
VSS
XINT6 XINT4 XINT3 TCK
NC
VCC
NMI
TMS
9
10
A
A
ADS
1
22
WIDTH/ ALE
HLTD1
2
3
NC
NC
4
5
XINT7 XINT5 XINT2
11
12
13
14
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 4.
132-Lead Pin Grid Array Top View - Pins Facing Down
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P
P
AD6
AD11 AD13
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AD18
AD19 AD22
AD25
AD3
AD7 AD10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD20
AD24 AD26
AD27
AD0
AD4
AD8
AD9
AD12
AD16
AD17
VCC
AD1
VCC
VCC
N
N
M
M
AD14 AD15
AD21 AD23
NC
AD29
AD30
AD5
AD28
BE3
BE2
VSS
AD2
AD31
VSS
VCC
VSS
NC
BE1
VSS
VCC
BE0
VSS
VCC
ALE
VSS
VCC
BSTAT VSS
VCC
L
L
K
K
J
J
i
H
CLKIN
VSS VCCPLL
G
NC
A80960Jx
M
H
G
© 19xx
VCC
VSS
VCC
VSS RDYRCV
VCC
VSS RESET
DEN
VSS
VCC
VCC
VSS
DT/R
VSS
VCC
F
F
XXXXXXXX SS
E
E
D
D
TDI
C
C
NC
STEST TRST XINT0 XINT1 HOLD
NC
VCC5
FAIL
A2
VSS
VSS
VSS
NC
VCC
VCC
VCC
8
7
6
A3
BLAST HOLDA LOCK/
ONCE
B
B
NC
TCK XINT3 XINT4 XINT6
VSS
TDO WIDTH/
HLTD0
D/C
W/R
A
A
TMS
14
XINT2 XINT5 XINT7
13
Advance Information Datasheet
12
11
NMI
VCC
10
9
NC
NC
5
4
ALE WIDTH/
HLTD1
3
2
ADS
1
23
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 6.
132-Lead PGA Pinout — In Signal Order
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
A2
C5
AD31
K3
TDO
B4
VSS
B9
A3
C4
ADS
A1
TMS
A14
VSS
D2
AD0
M14
ALE
G3
TRST
C12
VSS
D13
AD1
L13
ALE
A3
VCC
A6
VSS
E2
AD2
K12
BE0
H3
VCC
A7
VSS
E13
AD3
N14
BE1
J3
VCC
A8
VSS
F2
AD4
M13
BE2
L1
VCC
A9
VSS
F13
AD5
L12
BE3
L2
VCC
D1
VSS
G2
AD6
P14
BLAST
C3
VCC
D14
VSS
G13
AD7
N13
BSTAT
F3
VCC
E1
VSS
H2
AD8
M12
CLKIN
H14
VCC
E14
VSS
H13
AD9
M11
D/C
B2
VCC
F1
VSS
J2
AD10
N12
DEN
E3
VCC
F14
VSS
J13
AD11
P13
DT/R
D3
VCC
G1
VSS
K2
AD12
M10
FAIL
C6
VCC
G14
VSS
K13
AD13
P12
HOLD
C9
VCC
H1
VSS
N5
AD14
M9
HOLDA
C2
VCC
J1
VSS
N6
AD15
M8
LOCK/ONCE
C1
VCC
J14
VSS
N7
AD16
M7
NC
A4
VCC
K1
VSS
N8
AD17
M6
NC
A5
VCC
K14
VSS
N9
AD18
P4
NC
B5
VCC
L14
VSS
N10
AD19
P3
NC
B14
VCC
P5
VSS
N11
AD20
N4
NC
C8
VCC
P6
W/R
B1
AD21
M5
NC
C14
VCC
P7
WIDTH/HLTD0
B3
AD22
P2
NC
G12
VCC
P8
WIDTH/HLTD1
A2
AD23
M4
NC
J12
VCC
P9
XINT0
C11
AD24
N3
NC
M3
VCC
P10
XINT1
C10
AD25
P1
NMI
A10
VCC
P11
XINT2
A13
AD26
N2
RDYRCV
F12
VCCPLL
H12
XINT3
B12
AD27
N1
RESET
E12
VCC5
C7
XINT4
B11
AD28
L3
STEST
C13
VSS
B6
XINT5
A12
AD29
M2
TCK
B13
VSS
B7
XINT6
B10
M1
TDI
D12
VSS
B8
XINT7
A11
AD30
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
24
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 7.
132-Lead PGA Pinout — In Pin Order
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
A1
ADS
C6
FAIL
H1
VCC
M10
AD12
A2
WIDTH/HLTD1
C7
VCC5
H2
VSS
M11
AD9
A3
ALE
C8
NC
H3
BE0
M12
AD8
A4
NC
C9
HOLD
H12
VCCPLL
M13
AD4
A5
NC
C10
XINT1
H13
VSS
M14
AD0
A6
VCC
C11
XINT0
H14
CLKIN
N1
AD27
A7
VCC
C12
TRST
J1
VCC
N2
AD26
A8
VCC
C13
STEST
J2
VSS
N3
AD24
A9
VCC
C14
NC
J3
BE1
N4
AD20
A10
NMI
D1
VCC
J12
NC
N5
VSS
A11
XINT7
D2
VSS
J13
VSS
N6
VSS
A12
XINT5
D3
DT/R
J14
VCC
N7
VSS
A13
XINT2
D12
TDI
K1
VCC
N8
VSS
A14
TMS
D13
VSS
K2
VSS
N9
VSS
B1
W/R
D14
VCC
K3
AD31
N10
VSS
B2
D/C
E1
VCC
K12
AD2
N11
VSS
B3
WIDTH/HLTD0
E2
VSS
K13
VSS
N12
AD10
B4
TDO
E3
DEN
K14
VCC
N13
AD7
B5
NC
E12
RESET
L1
BE2
N14
AD3
B6
VSS
E13
VSS
L2
BE3
P1
AD25
B7
VSS
E14
VCC
L3
AD28
P2
AD22
B8
VSS
F1
VCC
L12
AD5
P3
AD19
B9
VSS
F2
VSS
L13
AD1
P4
AD18
B10
XINT6
F3
BSTAT
L14
VCC
P5
VCC
B11
XINT4
F12
RDYRCV
M1
AD30
P6
VCC
B12
XINT3
F13
VSS
M2
AD29
P7
VCC
B13
TCK
F14
VCC
M3
NC
P8
VCC
B14
NC
G1
VCC
M4
AD23
P9
VCC
C1
LOCK/ONCE
G2
VSS
M5
AD21
P10
VCC
C2
HOLDA
G3
ALE
M6
AD17
P11
VCC
C3
BLAST
G12
NC
M7
AD16
P12
AD13
C4
A3
G13
VSS
M8
AD15
P13
AD11
A2
G14
VCC
M9
AD14
P14
AD6
C5
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Advance Information Datasheet
25
80960JA/JF/JD/JT 3.3 V Microprocessor
3.1.3
80960Jx 132-Lead PQFP Pinout
Figure 5.
132-Lead PQFP - Top View
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
AD8
AD7
AD6
AD5
AD4
V (I/O)
CC
VSS (I/O)
AD3
AD2
AD1
AD0
VCC (I/O)
VSS (I/O)
VCC (Core)
VSS (Core)
V (Core)
CC
VSS (Core)
CLKIN
VSS (CLK)
VCCPLL
VCC (CLK)
NC
NC
VCC (Core)
VSS (Core)
RESET
NC
NC
STEST
VCC (I/O)
TDI
VSS(I/O)
RDYRCV
TRST
TCK
TMS
HOLD
XINT0
XINT1
XINT2
XINT3
VCC (I/O)
VSS (I/O)
XINT4
XINT5
XINT6
XINT7
NMI
VCC (Core)
VSS (Core)
NC
NC
VCC5
NC
NC
FAIL
ALE
TDO
VCC (I/O)
VSS(I/O)
WIDTH/HLTD1
VCC(Core)
VSS (Core)
WIDTH/HLTD0
A2
A3
i960
®
i
NG80960Jx
XXXXXXXX SS
M
© 19xx
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
AD9
VCC (I/O)
VSS (I/O)
AD10
AD11
VCC (I/O)
VSS (I/O)
VCC (Core)
VSS (Core)
AD12
AD13
AD14
AD15
VCC (I/O)
VSS (I/O)
AD16
AD17
AD18
AD19
VCC (I/O)
VSS (I/O)
AD20
AD21
AD22
AD23
VCC (Core)
VSS (Core)
VCC (I/O)
VSS (I/O)
AD24
AD25
AD26
NC
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
BLAST
AD27
VCC (I/O)
VSS (I/O)
AD28
AD29
AD30
AD31
VCC (Core)
VSS (Core)
VCC (I/O)
VSS (I/O)
BE3
BE2
BE1
BE0
BSTAT
LOCK/ONCE
VCC (I/O)
VSS (I/O)
VCC (Core)
VSS (Core)
ALE
HOLDA
DEN
DT/R
VCC (I/O)
VSS (I/O)
VCC (Core)
VSS (Core)
W/R
ADS
D/C
26
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 8.
132-Lead PQFP Pinout — In Signal Order
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
AD31
60
ALE
24
VCC (Core)
47
VSS (Core)
124
AD30
61
ADS
36
VCC (Core)
59
VSS (I/O)
10
AD29
62
A3
33
VCC (Core)
74
VSS (I/O)
27
AD28
63
A2
32
VCC (Core)
92
VSS (I/O)
40
AD27
66
BE3
55
VCC (Core)
113
VSS (I/O)
48
AD26
68
BE2
54
VCC (Core)
115
VSS (I/O)
56
AD25
69
BE1
53
VCC (Core)
123
VSS (I/O)
64
AD24
70
BE0
52
VCC (I/O)
9
VSS (I/O)
71
AD23
75
WIDTH/HLTD1
28
VCC (I/O)
26
VSS (I/O)
79
AD22
76
WIDTH/HLTD0
31
VCC (I/O)
41
VSS (I/O)
85
AD21
77
D/C
35
VCC (I/O)
49
VSS (I/O)
93
AD20
78
W/R
37
VCC (I/O)
57
VSS (I/O)
97
AD19
81
DT/R
42
VCC (I/O)
65
VSS (I/O)
106
AD18
82
DEN
43
VCC (I/O)
72
VSS (I/O)
112
AD17
83
BLAST
34
VCC (I/O)
80
VSS (I/O)
131
AD16
84
RDYRCV
132
VCC (I/O)
86
NC
18
AD15
87
LOCK/ONCE
50
VCC (I/O)
94
NC
19
AD14
88
HOLD
4
VCC (I/O)
98
NC
21
AD13
89
HOLDA
44
VCC (I/O)
105
NC
22
AD12
90
BSTAT
51
VCC (I/O)
111
NC
67
AD11
95
CLKIN
117
VCC (I/O)
129
NC
121
AD10
96
RESET
125
VCCPLL
119
NC
122
AD9
99
STEST
128
VCC5
20
NC
126
AD8
100
FAIL
23
VSS (CLK)
118
NC
127
AD7
101
TCK
2
VSS (Core)
17
XINT7
14
AD6
102
TDI
130
VSS (Core)
30
XINT6
13
AD5
103
TDO
25
VSS (Core)
38
XINT5
12
AD4
104
TRST
1
VSS (Core)
46
XINT4
11
AD3
107
TMS
3
VSS (Core)
58
XINT3
8
AD2
108
VCC (CLK)
120
VSS (Core)
73
XINT2
7
AD1
109
VCC (Core)
16
VSS (Core)
91
XINT1
6
AD0
110
VCC (Core)
29
VSS (Core)
114
XINT0
5
45
VCC (Core)
39
VSS (Core)
116
NMI
15
ALE
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Advance Information Datasheet
27
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 9.
132-Lead PQFP Pinout — In Pin Order
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
TRST
34
BLAST
67
NC
100
AD8
2
TCK
35
D/C
68
AD26
101
AD7
3
TMS
36
ADS
69
AD25
102
AD6
4
HOLD
37
W/R
70
AD24
103
AD5
5
XINT0
38
VSS (Core)
71
VSS (I/O)
104
AD4
6
XINT1
39
VCC (Core)
72
VCC (I/O)
105
VCC (I/O)
7
XINT2
40
VSS (I/O)
73
VSS (Core)
106
VSS (I/O)
8
XINT3
41
VCC (I/O)
74
VCC (Core)
107
AD3
9
VCC (I/O)
42
DT/R
75
AD23
108
AD2
10
VSS (I/O)
43
DEN
76
AD22
109
AD1
11
XINT4
44
HOLDA
77
AD21
110
AD0
12
XINT5
45
ALE
78
AD20
111
VCC (I/O)
13
XINT6
46
VSS (Core)
79
VSS (I/O)
112
VSS (I/O)
14
XINT7
47
VCC (Core)
80
VCC (I/O)
113
VCC (Core)
15
NMI
48
VSS (I/O)
81
AD19
114
VSS (Core)
16
VCC (Core)
49
VCC (I/O)
82
AD18
115
VCC (Core)
17
VSS (Core)
50
LOCK/ONCE
83
AD17
116
VSS (Core)
18
NC
51
BSTAT
84
AD16
117
CLKIN
19
NC
52
BE0
85
VSS (I/O)
118
VSS (CLK)
20
VCC5
53
BE1
86
VCC (I/O)
119
VCCPLL
21
NC
54
BE2
87
AD15
120
VCC (CLK)
22
NC
55
BE3
88
AD14
121
NC
23
FAIL
56
VSS (I/O)
89
AD13
122
NC
24
ALE
57
VCC (I/O)
90
AD12
123
VCC (Core)
25
TDO
58
VSS (Core)
91
VSS (Core)
124
VSS (Core)
26
VCC (I/O)
59
VCC (Core)
92
VCC (Core)
125
RESET
27
VSS (I/O)
60
AD31
93
VSS (I/O)
126
NC
28
WIDTH/HLTD1
61
AD30
94
VCC (I/O)
127
NC
29
VCC (Core)
62
AD29
95
AD11
128
STEST
30
VSS (Core)
63
AD28
96
AD10
129
VCC (I/O)
31
WIDTH/HLTD0
64
VSS (I/O)
97
VSS (I/O)
130
TDI
32
A2
65
VCC (I/O)
98
VCC (I/O)
131
VSS (I/O)
33
A3
66
AD27
99
AD9
132
RDYRCV
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
28
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
3.1.4
80960Jx 196-Ball MPBGA Pinout
Figure 6.
196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up
1
2
3
4
5
6
7
8
9
10
NC
AD28
VCC
NC
VCC
AD22
VCC
VCC
AD15
VCC
AD30
AD27
AD29
VCC
AD23
AD20
AD17 AD14
NC
AD31
NC
AD26
AD25
AD24
AD21
AD19 AD16
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
VCC
VSS
VSS
VSS
VSS
NC
NC
VCC
VSS
VSS
VSS
NC
NC
VCC
VSS
VSS
BE1
BE2
BE3
VSS
VCC
BE0
BSTAT
ALE
LOCK/
ONCE
HOLDA
11
12
13
14
AD13
VCC
AD8
NC
AD12
AD10
AD9
AD7
AD4
VCC
VCC
AD11
AD6
AD2
VSS
VSS
AD3
AD5
AD0
AD1
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VCC VCCPLL
VSS
VSS
VSS
VSS
VSS
VSS
NC
CLKIN
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VCC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TDI
NC
RESET
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VCC
STEST
DEN
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC RDYRCV
DT/R
VCC
NC
NC
A3
VCC
ALE
VCC5
VCC
W/R
D/C
NC
NC
A2
VCC
TDO
NC
XINT4
NC
XINT6 XINT1 XINT3 HOLD
NC
ADS
BLAST
VCC WIDTH0 WIDTH1 FAIL
NC
NC
NMI
XINT7 XINT5
2
3
8
9
10
A
A
AD18
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
XINT2 XINT0 TMS TRST
TCK
N
N
P
P
1
Advance Information Datasheet
4
5
6
7
11
12
VCC
NC
13
14
29
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 7.
196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NC
AD8
VCC
AD13
AD15
VCC
AD18
VCC
AD22
VCC
NC
VCC
AD28
NC
AD4
AD7
AD9
AD10
AD12
AD14 AD17
AD20
AD23
VCC
AD29
AD27
AD30
VCC
AD2
AD6
AD11
VCC
VCC
AD16 AD19
AD21
AD24
AD25
AD26
NC
AD31
NC
AD1
AD0
AD5
AD3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
NC
NC
VCCPLL VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
NC
NC
A
A
B
B
C
C
D
D
E
E
F
F
G
G
NC
CLKIN
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
NC
NC
NC
VCC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BE3
BE2
BE1
RESET
NC
TDI
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BSTAT
BE0
VCC
STEST
VCC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
LOCK/
ONCE
ALE
RDYRCV NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
DEN
HOLDA
VCC
VCC5
ALE
VCC
A3
NC
NC
VCC
DT/R
NC
XINT4
NC
TDO
VCC
A2
NC
NC
D/C
W/R
NMI
NC
NC
FAIL WIDTH1 WIDTH0 VCC
BLAST
ADS
NC
10
9
8
3
2
H
H
J
J
K
K
L
L
M
M
TCK
TRST TMS XINT0 XINT2
N
N
HOLD XINT3 XINT1 XINT6
P
30
P
NC
VCC
14
13
XINT5 XINT7
12
11
7
6
5
4
1
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 10.
196-Ball MPBGA Pinout — In Signal Order (Sheet 1 of 2)
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
A2
N5
BE0
J2
NC
M4
VCC
J1
A3
M5
BE1
H1
NC
N3
VCC
K3
AD0
D13
BE2
H2
NC
N4
VCC
K13
AD1
D14
BE3
H3
NC
N8
VCC
L3
AD2
C14
BLAST
P3
NC
N10
VCC
M2
AD3
D11
BSTAT
J3
NC
P1
VCC
M6
AD4
B14
CLKIN
G13
NC
P8
VCC
M9
AD5
D12
DEN
L2
NC
P9
VCC
N6
AD6
C13
D/C
N2
NC
P14
VCC
P4
AD7
B13
DT/R
M1
NMI
P10
VCC
P13
AD8
A13
FAIL
P7
RDYRCV
L14
VCCPLL
F14
AD9
B12
HOLD
N14
RESET
J14
VSS
D4
AD10
B11
HOLDA
L1
STEST
K14
VSS
D5
AD11
C12
LOCK/ONCE
K2
TCK
M14
VSS
D6
AD12
B10
NC
A1
TDI
J12
VSS
D7
AD13
A11
NC
A4
TDO
N7
VSS
D8
AD14
B9
NC
A14
TMS
M12
VSS
D9
AD15
A10
NC
C1
TRST
M13
VSS
D10
AD16
C9
NC
C3
VCC5
M8
VSS
E4
AD17
B8
NC
D1
VCC
A3
VSS
E5
AD18
A8
NC
D2
VCC
A5
VSS
E6
AD19
C8
NC
D3
VCC
A7
VSS
E7
AD20
B7
NC
E1
VCC
A9
VSS
E8
AD21
C7
NC
E2
VCC
A12
VSS
E9
AD22
A6
NC
F1
VCC
B1
VSS
E10
AD23
B6
NC
F2
VCC
B5
VSS
E11
AD24
C6
NC
G1
VCC
C10
VSS
F4
AD25
C5
NC
G2
VCC
C11
VSS
F5
AD26
C4
NC
G12
VCC
E3
VSS
F6
AD27
B3
NC
G14
VCC
E12
VSS
F7
AD28
A2
NC
H12
VCC
E13
VSS
F8
AD29
B4
NC
H14
VCC
E14
VSS
F9
AD30
B2
NC
J13
VCC
F3
VSS
F10
AD31
C2
NC
K12
VCC
F12
VSS
F11
ADS
P2
NC
L12
VCC
F13
VSS
G4
ALE
K1
NC
L13
VCC
G3
VSS
G5
M7
NC
M3
VCC
H13
VSS
G6
ALE
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Advance Information Datasheet
31
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 10.
196-Ball MPBGA Pinout — In Signal Order (Sheet 2 of 2)
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
VSS
G7
VSS
H11
VSS
K7
VSS
L11
VSS
G8
VSS
J4
VSS
K8
WIDTH0
P5
VSS
G9
VSS
J5
VSS
K9
WIDTH1
P6
VSS
G10
VSS
J6
VSS
K10
W/R
N1
VSS
G11
VSS
J7
VSS
K11
XINT0
M11
VSS
H4
VSS
J8
VSS
L5
XINT1
N12
VSS
H5
VSS
J9
VSS
L6
XINT2
M10
VSS
H6
VSS
J10
VSS
L7
XINT3
N13
VSS
H7
VSS
J11
VSS
L8
XINT4
N9
VSS
H8
VSS
K4
VSS
L9
XINT5
P12
VSS
H9
VSS
K5
VSS
L10
XINT6
N11
VSS
H10
VSS
K6
VSS
L4
XINT7
P11
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
32
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 11.
196-Ball MPBGA Pinout — In Pin Order (Sheet 1 of 2)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
A1
NC
C11
VCC
F7
VSS
J3
BSTAT
A2
AD28
C12
AD11
F8
VSS
J4
VSS
A3
VCC
C13
AD6
F9
VSS
J5
VSS
A4
NC
C14
AD2
F10
VSS
J6
VSS
A5
VCC
D1
NC
F11
VSS
J7
VSS
A6
AD22
D2
NC
F12
VCC
J8
VSS
A7
VCC
D3
NC
F13
VCC
J9
VSS
A8
AD18
D4
VSS
F14
VCCPLL
J10
VSS
A9
VCC
D5
VSS
G1
NC
J11
VSS
A10
AD15
D6
VSS
G2
NC
J12
TDI
A11
AD13
D7
VSS
G3
VCC
J13
NC
A12
VCC
D8
VSS
G4
VSS
J14
RESET
A13
AD8
D9
VSS
G5
VSS
K1
ALE
A14
NC
D10
VSS
G6
VSS
K2
LOCK/ONCE
B1
VCC
D11
AD3
G7
VSS
K3
VCC
B2
AD30
D12
AD5
G8
VSS
K4
VSS
B3
AD27
D13
AD0
G9
VSS
K5
VSS
B4
AD29
D14
AD1
G10
VSS
K6
VSS
B5
VCC
E1
NC
G11
VSS
K7
VSS
B6
AD23
E2
NC
G12
NC
K8
VSS
B7
AD20
E3
VCC
G13
CLKIN
K9
VSS
B8
AD17
E4
VSS
G14
NC
K10
VSS
B9
AD14
E5
VSS
H1
BE1
K11
VSS
B10
AD12
E6
VSS
H2
BE2
K12
NC
B11
AD10
E7
VSS
H3
BE3
K13
VCC
B12
AD9
E8
VSS
H4
VSS
K14
STEST
B13
AD7
E9
VSS
H5
VSS
L1
HOLDA
B14
AD4
E10
VSS
H6
VSS
L2
DEN
C1
NC
E11
VSS
H7
VSS
L3
VCC
C2
AD31
E12
VCC
H8
VSS
L4
VSS
C3
NC
E13
VCC
H9
VSS
L5
VSS
C4
AD26
E14
VCC
H10
VSS
L6
VSS
C5
AD25
F1
NC
H11
VSS
L7
VSS
C6
AD24
F2
NC
H12
NC
L8
VSS
C7
AD21
F3
VCC
H13
VCC
L9
VSS
C8
AD19
F4
VSS
H14
NC
L10
VSS
C9
AD16
F5
VSS
J1
VCC
L11
VSS
C10
VCC
F6
VSS
J2
BE0
L12
NC
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Advance Information Datasheet
33
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 11.
196-Ball MPBGA Pinout — In Pin Order (Sheet 2 of 2)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
L13
NC
L14
RDYRCV
M1
M2
Signal
M10
XINT2
N7
TDO
P4
VCC
M11
XINT0
N8
NC
P5
WIDTH0
DT/R
M12
TMS
N9
XINT4
P6
WIDTH1
VCC
M13
TRST
N10
NC
P7
FAIL
M3
NC
M14
TCK
N11
XINT6
P8
NC
M4
NC
N1
W/R
N12
XINT1
P9
NC
M5
A3
N2
D/C
N13
XINT3
P10
NMI
M6
VCC
N3
NC
N14
HOLD
P11
XINT7
M7
ALE
N4
NC
P1
NC
P12
XINT5
M8
VCC5
N5
A2
P2
ADS
P13
VCC
M9
VCC
N6
VCC
P3
BLAST
P14
NC
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
3.2
Package Thermal Specifications
The 80960Jx is specified for operation when TC (case temperature) is within the range of 0°C to
100°C for PGA, MPBGA and PQFP packages. An extended temperature device is also available in
a PQFP package with TC -40°C to 100°C. Case temperature may be measured in any environment
to determine whether the 80960Jx is within its specified operating range. The case temperature
should be measured at the center of the top surface, opposite the pins.
θCA is the thermal resistance from case to ambient. Use the following equation to calculate TA, the
maximum ambient temperature to conform to a particular case temperature:
TA = TC - P (θCA)
Junction temperature (TJ) is commonly used in reliability calculations. TJ can be calculated from
θJC (thermal resistance from junction to case) using the following equation:
TJ = TC + P (θJC)
Similarly, if TA is known, the corresponding case temperature (TC) can be calculated as follows:
TC = TA + P (θCA)
Compute P by multiplying ICC from Table 22 and VCC. Values for θJC and θCA are given in
Table 12 for the PGA package, Table 13 for the MPBGA package, and Table 14 for the PQFP
package. For high speed operation, the processor’s θJA may be significantly reduced by adding a
heatsink and/or by increasing airflow.
Tables 15, 16, and 17 show the maximum ambient temperature (TA) permitted without exceeding
TC for the PGA, MPBGA, and PQFP packages. The values are based on typical ICC and VCC of
+3.3 V, with a TCASE of +100°C.
34
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 12.
132-Lead PGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
(0)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
1000
(5.08)
θJC (Junction-to-Case)
0.7
0.7
0.7
0.7
0.7
0.7
θCA (Case-to-Ambient) (No Heatsink)
25
19
14
12
11
10
θCA (Case-to-Ambient) (Omnidirectional Heatsink)
15
9
6
5
4
4
θCA (Case-to-Ambient) (Unidirectional Heatsink)
16
8
6
5
4
4
θJA
θCA
θJC
θJ-PIN
θJ-CAP
NOTES:
1. This table applies to a PGA device plugged into a socket or soldered directly into a board.
2. θJA = θJC + θCA
3. θJ-CAP = 5.6°C/W (approximate) (no heatsink)
4. θJ-PIN = 6.4°C/W (inner pins) (approximate) (no heatsink)
5. θJ-PIN = 6.2°C/W (outer pins) (approximate) (no heatsink)
6. θJ-CAP = 3°C/W (approximate) (with heatsink)
7. θJ-PIN = 3.3°C/W (inner pins) (approximate) (with heatsink)
8. θJ-PIN = 3.3°C/W (outer pins) (approximate) (with heatsink)
Table 13.
196-Ball MPBGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
(0)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
1000
(5.08)
θJC (Junction-to-Case)
TBD
TBD
TBD
TBD
TBD
TBD
θCA (Case-to-Ambient) (No Heatsink)
TBD
TBD
TBD
TBD
TBD
TBD
θCA (Case-to-Ambient) (Omnidirectional Heatsink)
TBD
TBD
TBD
TBD
TBD
TBD
θCA (Case-to-Ambient) (Unidirectional Heatsink)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Advance Information Datasheet
35
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 14.
132-Lead PQFP Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
50
100
200
400
600
800
(0)
(0.25)
(0.50)
(1.01)
(2.03)
(3.04)
(4.06)
θJC (Junction-to-Case)
4.1
4.3
4.3
4.3
4.3
4.7
4.9
θCA (Case-to-Ambient -No Heatsink)
23
19
18
16
14
11
9
θJA
θCA
θJC
θJB
θJL
NOTES:
1. This table applies to a PQFP device soldered directly into board.
2. θJA = θJC + θCA
3. θJL = 13°C/W (approx.)
4. θJB = 13.5°C/W (approx.)
Table 15.
Maximum TA at Various Airflows in °C (80960JT)
Airflow-ft/min (m/sec)
fCLKIN (MHz)
PQFP
Package
PGA
Package
MPBGA
Package
0
200
400
600
800
1000
(0)
(1.01)
(2.03)
(3.04)
(4.06)
(5.07)
TA without Heatsink
33
25
62
71
73
79
76
82
81
86
85
88
88
91
TA without Heatsink
33
25
58
68
68
75
76
82
80
84
81
86
83
87
TA with Omnidirectional
Heatsink1
33
25
75
81
85
88
90
92
92
94
93
95
93
95
TA with Unidirectional
Heatsink2
33
25
73
79
86
90
90
92
92
94
93
95
93
95
TA without Heatsink
33
25
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
NOTES:
1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
36
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 16.
Maximum TA at Various Airflows in °C (80960JD)
Airflow-ft/min (m/sec)
PQFP
Package
PGA
Package
MPBGA
Package
fCLKIN (MHz)
0
(0)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
1000
(5.07)
TA without Heatsink
33
25
20
16.67
61
70
75
79
73
79
82
86
76
82
85
87
81
86
88
90
85
88
90
92
86
90
91
93
TA without Heatsink
33
25
20
16.67
58
68
73
78
68
75
79
83
76
82
85
87
80
84
87
89
81
86
88
90
83
87
89
91
TA with Omnidirectional
Heatsink1
33
25
20
16.67
75
81
84
87
85
88
90
92
90
92
93
95
92
94
95
96
93
95
96
96
93
95
96
96
TA with Unidirectional
Heatsink2
33
25
20
16.67
73
79
82
86
86
90
91
93
90
92
93
95
92
94
95
96
93
95
96
96
93
96
96
96
TA without Heatsink
25
20
16.67
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
NOTES:
1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Table 17.
Maximum TA at Various Airflows in °C (80960JA/JF)
Airflow-ft/min (m/sec)
fCLKIN (MHz)
0
(0)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
1000
(5.07)
33
25
16
79
84
89
86
89
92
87
90
93
90
92
95
92
94
96
93
94
96
25
84
89
90
92
94
94
TA without Heatsink
33
25
16
78
83
88
83
87
91
87
90
93
89
92
94
90
92
95
91
93
95
TA with Omnidirectional
Heatsink1
33
25
16
87
90
93
92
94
96
95
96
97
96
97
98
96
97
98
96
97
98
TA with Unidirectional
Heatsink2
33
25
16
86
89
92
93
94
96
95
96
97
96
97
98
96
97
98
96
97
98
TA without Heatsink
33
25
16
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
For NG80960JA/JF
PQFP
Package
TA without Heatsink
For TG80960JA-25
TA without Heatsink
PGA
Package
MPBGA
Package
NOTES:
1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Advance Information Datasheet
37
80960JA/JF/JD/JT 3.3 V Microprocessor
3.3
Thermal Management Accessories
The following is a list of suggested sources for 80960Jx thermal solutions. This is neither an
endorsement or a warranty of the performance of any of the listed products and/or companies.
3.3.1
Heatsinks
1. Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75234-8993
(972) 243-4321
2. Wakefield Engineering
60 Audubon Road
Wakefield, MA 01880
(617) 245-5900
3. Aavid Thermal Technologies, Inc.
One Kool Path
Laconia, NH 03247-0400
(603) 528-3400
38
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
Warning:
Note:
Table 18.
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
This document contains information on products in the sampling and initial production phases of
development. It is valid for the devices indicated in the revision history. The specifications within
this data sheet are subject to change without notice. Verify with your local Intel sales office that
you have the latest data sheet before finalizing a design.
Absolute Maximum Ratings
Parameter
4.2
Maximum Rating
Storage Temperature
–65oC to +150oC
Case Temperature Under Bias
–65oC to +110oC
Supply Voltage wrt. VSS
–0.5 V to + 4.6 V
Voltage on VCC5 wrt. VSS
–0.5 V to + 6.5 V
Voltage on Other Pins wrt. VSS
–0.5 V to VCC + 0.5 V
Operating Conditions
Table 19 indicates the operating conditions for the 80960Jx.
Table 19.
80960Jx Operating Conditions
Symbol
Parameter
Min
Max
Units
VCC
Supply Voltage
3.15
3.45
V
VCC5
Input Protection Bias
3.15
5.5
V
15
15
12
12
12
12
12
12
12
33.3
25
33.3
25
20
16.67
33.3
25
16
MHz
0
-40
100
100
Notes
(1)
Input Clock Frequency
fCLKIN
TC
80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
Operating Case Temperature
PGA, MPBGA, and PQFP
Extended temp PQFP (TG80960JA-25)
°C
NOTE:
1. See Section 4.4, “VCC5 Pin Requirements (VDIFF)” on page 40.
Advance Information Datasheet
39
80960JA/JF/JD/JT 3.3 V Microprocessor
4.3
Connection Recommendations
For clean on-chip power distribution, VCC and VSS pins separately feed the device’s functional units.
Power and ground connections must be made to all 80960Jx power and ground pins. On the circuit board,
every VCC pin should connect to a power plane and every VSS pin should connect to a ground plane. Place
liberal decoupling capacitance near the 80960Jx, since the processor can cause transient power surges.
Pay special attention to the Test Reset (TRST) pin. It is essential that the JTAG Boundary Scan Test Access
Port (TAP) controller initializes to a known state whether it will be used or not. If the JTAG Boundary Scan
function will be used, connect a pulldown resistor between the TRST pin and VSS. If the JTAG Boundary
Scan function will not be used (even for board-level testing), connect the TRST pin to VSS.
Do not connect the TDI, TDO, and TCK pins if the TAP Controller will not be used.
Note:
4.4
Pins identified as NC must not be connected in the system.
VCC5 Pin Requirements (VDIFF)
In 3.3 V only systems where the 80960Jx input pins are driven from 3.3 V logic, connect the VCC5
pin directly to the 3.3 V VCC plane.
In mixed voltage systems where the processor is powered by 3.3 V and interfaces with 5 V
components, VCC5 must be connected to 5 V. This allows proper 5 V tolerant buffer operation,
and prevents damage to the input pins. The voltage differential between the 80960Jx VCC5 pin and
its 3.3 V VCC pins must not exceed 2.25 V. If this requirement is not met, current flow through the
pin may exceed the value at which the processor is damaged. Instances when the voltage can
exceed 2.25 V is during power up or power down, where one source reaches its level faster than the
other, briefly causing an excess voltage differential. Another instance is during steady-state
operation, where the differential voltage of the regulator (provided a regulator is used) cannot be
maintained within 2.25 V. Two methods are possible to prevent this from happening:
• Use a regulator that is designed to prevent the voltage differential from exceeding 2.25 V, or,
• As shown in Figure 8, place a 100 Ω resistor in series with the VCC5 pin to limit the current
through VCC5.
Figure 8.
VCC5 Current-Limiting Resistor
VCC5 Pin
+5 V (±0.25 V)
100 Ω
(±5%, 0.5 W)
If the regulator cannot prevent the 2.25 V differential, the addition of the resistor is a simple and
reliable method for limiting current. The resistor can also prevent damage in the case of a power
failure, where the 5 V supply remains on and the 3.3 V supply goes to zero.
Table 20.
VDIFF Parameters
Symbol
VDIFF
40
Parameter
VCC5-VCC
Difference
Min
Max
2.25
Units
Notes
V
VCC5 input should not exceed VCC by more than 2.25 V
during power-up and power-down, or during
steady-state operation.
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
4.5
VCCPLL Pin Requirements
To reduce clock skew on the i960 80960Jx processor, the VCCPLL pin for the Phase Lock Loop
(PLL) circuit is isolated on the pinout. The lowpass filter, as shown in Figure 9, reduces noise
induced clock jitter and its effects on timing relationships in system designs. The 4.7 µF capacitor
must be low ESR solid tantalum; the 0.01 µF capacitor must be of the type X7R and the node
connecting VCCPLL must be as short as possible.
Figure 9.
VCCPLL Lowpass Filter
100 Ω (80960JA/JF/JD)
10 Ω (80960JT)
VCC
(Board Plane)
+
4.7 µF
0.01 µF
VCCPLL
(On 80960Jx)
F_CA078A
Advance Information Datasheet
41
80960JA/JF/JD/JT 3.3 V Microprocessor
4.6
DC Specifications
Table 21.
80960Jx DC Characteristics
Symbol
Parameter
Min
Typ
Max
Units
Notes
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VCC5 + 0.3
V
VOL
Output Low Voltage
0.4
V
IOL = 3 mA
0.2
V
IOL = 100 µA
VOH
Output High Voltage
VOLP
Output Ground Bounce
CIN
Input Capacitance
PGA
PQFP
MPBGA
15
15
15
COUT
I/O or Output Capacitance
PGA
PQFP
MPBGA
15
15
15
CCLK
CLKIN Capacitance
PGA
PQFP
MPBGA
15
15
15
2.4
IOH = -1 mA
V
VCC - 0.2
<0.8
IOH = -200 µA
V
(1,2)
pF
fCLKIN = fMIN (2)
pF
fCLKIN = fMIN (2)
pF
fCLKIN = fMIN (2)
NOTES:
1. Typical is measured with VCC = 3.3 V and temperature = 25 °C.
2. Not tested.
Table 22.
80960Jx ICC Characteristics (Sheet 1 of 2)
Symbol
ILI1
Input Leakage Current for each pin
except TCK, TDI, TRST and TMS
ILI2
Input Leakage Current for TCK, TDI,
TRST and TMS
ILO
Output Leakage Current
Rpu
Internal Pull-UP Resistance for
ONCE, TMS, TDI and TRST
ICC Active
(Power Supply)
42
Parameter
80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
Typ
-140
20
Max
Units
Notes
±1
µA
0 ≤ VIN ≤ VCC
-250
µA
VIN = 0.45V (1)
±1
µA
0.4 ≤ VOUT ≤ VCC
30
kΩ
600
450
580
447
367
310
320
260
194
mA
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 22.
80960Jx ICC Characteristics (Sheet 2 of 2)
Symbol
ICC Active
(Thermal)
Parameter
80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
Typ
Max
500
380
510
390
320
260
271
215
152
Units
Notes
mA
(2,4)
(2,4)
(2,4)
(2,4)
(2,4)
(2,4)
(2,4)
(2,4)
(2,4)
Reset mode
80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
ICC Test
(Power modes)
ONCE mode
80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
mA
Halt mode
80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
ICC5 Current on the
VCC5 Pin
450
400
475
425
345
300
250
200
150
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
50
40
50
40
34
34
31
26
21
(5)
10
200
µA
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
NOTES:
1. These pins have internal pullup devices. Typical leakage current is not tested.
2. Measured with device operating and outputs loaded to the test condition in Figure 10 “AC Test Load” on
page 47.
3. ICC Active (Power Supply) value is provided for selecting your system’s power supply. It is measured using
one of the worst case instruction mixes with VCC = 3.45 V. This parameter is characterized but not tested.
4. ICC Active (Thermal) value is provided for your system’s thermal management. Typical ICC is measured with
VCC =3.3 V and temperature = 25°C. This parameter is characterized but not tested.
5. ICC Test (Power modes) refers to the ICC values that are tested when the 80960JD is in Reset mode, Halt
mode or ONCE mode with VCC = 3.45 V.
6. ICC5 is tested at VCC = 3.3 V, VCC5 = 5.25 V.
Advance Information Datasheet
43
80960JA/JF/JD/JT 3.3 V Microprocessor
4.7
AC Specifications
The 80960Jx AC timings are based upon device characterization.
Table 23.
80960Jx AC Characteristics (Sheet 1 of 3)
Symbol
Parameter
Min
Max
Unit
Notes
INPUT CLOCK TIMINGS
CLKIN Frequency
TF
80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
15
15
12
12
12
12
12
12
12
33.3
25
33.3
25
20
16.67
33.3
25
16
30
40
30
40
50
60
30
40
62.5
66.7
66.7
83.3
83.3
83.3
83.3
83.3
83.3
83.3
MHz
CLKIN Period
TC
TCS
80960JT-100
80960JT-75
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
± 250
CLKIN Period Stability
ns
ps
(1, 2)
TCH
CLKIN High Time
8
ns
Measured at 1.5 V
(1)
TCL
CLKIN Low Time
8
ns
Measured at 1.5 V
(1)
TCR
CLKIN Rise Time
4
ns
0.8 V to 2.0 V (1)
TCF
CLKIN Fall Time
4
ns
2.0 V to 0.8 V (1)
ns
(3)
SYNCHRONOUS OUTPUT TIMINGS
TOV1
Output Valid Delay, Except ALE/ALE
Inactive and DT/R for 3.3 V input signals
2.5
13.5
Same as above, but for 5.5 V input signals
2.5
16.5
Output Valid Delay, DT/R
TOV2
80960JT
80960JD
80960JA/JF
0.5TC + 7
0.5TC + 7
0.5TC + 4
0.5TC + 9
0.5TC + 9
0.5TC + 18
TOF
Output Float Delay
2.5
13.5
ns
ns
(4)
NOTE:
See Table 24 on page 47 for note definitions for this table.
44
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 23.
80960Jx AC Characteristics (Sheet 2 of 3)
Symbol
Parameter
Min
Max
Unit
Notes
6
6
9
ns
(5)
1.5
1.5
1.0
ns
(5)
6.5
6.5
10.0
ns
(6)
1
ns
(6)
7
7
8
ns
(7)
2
2
1
ns
(7)
7
7
8
ns
(8)
2
2
1
ns
(8)
0.5TC - 5
0.5TC - 8
ns
(9)
0.5TC - 7
ns
Equal Loading (9)
SYNCHRONOUS INPUT TIMINGS
Input Setup to CLKIN — AD31:0, NMI,
XINT7:0
TIS1
80960JT
80960JD
80960JA/JF
Input Hold from CLKIN — AD31:0, NMI,
XINT7:0
TIH1
80960JT
80960JD
80960JA/JF
Input Setup to CLKIN — RDYRCV and
HOLD
TIS2
TIH2
80960JT
80960JD
80960JA/JF
Input Hold from CLKIN — RDYRCV and
HOLD
Input Setup to CLKIN — RESET
TIS3
80960JT
80960JD
80960JA/JF
Input Hold from CLKIN — RESET
TIH3
80960JT
80960JD
80960JA/JF
Input Setup to RESET — ONCE, STEST
TIS4
80960JT
80960JD
80960JA/JF
Input Hold from RESET — ONCE, STEST
TIH4
80960JT
80960JD
80960JA/JF
RELATIVE OUTPUT TIMINGS
Address Valid to ALE/ALE Inactive
TLX
For 3.3 V Data Input Signals
For 5.0 V Data Input Signals
TLXL
ALE/ALE Width
TLXA
Address Hold from ALE/ALE Inactive
TDXD
DT/R Valid to DEN Active
TBSF
TCK Frequency
TBSCH
TCK High Time
15
ns
Measured at 1.5 V
(1)
TBSCL
TCK Low Time
15
ns
Measured at 1.5 V
(1)
TBSCR
TCK Rise Time
5
ns
0.8 V to 2.0 V (1)
TBSCF
TCK Fall Time
5
ns
2.0 V to 0.8 V (1)
BOUNDARY SCAN TEST SIGNAL TIMINGS
0.5TF
MHz
NOTE:
See Table 24 on page 47 for note definitions for this table.
Advance Information Datasheet
45
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 23.
80960Jx AC Characteristics (Sheet 3 of 3)
Symbol
Parameter
Min
Max
Unit
Notes
TBSIS1
Input Setup to TCK — TDI, TMS
4
TBSIH1
Input Hold from TCK — TDI, TMS
6
ns
TBSOV1
TDO Valid Delay
3
30
ns
(1,10)
TBSOF1
TDO Float Delay
3
30
ns
(1,10)
TBSOV2
All Outputs (Non-Test) Valid Delay
3
30
ns
(1,10)
TBSOF2
All Outputs (Non-Test) Float Delay
3
30
ns
(1,10)
TBSIS2
Input Setup to TCK — All Inputs
(Non-Test)
4
ns
TBSIH2
Input Hold from TCK — All Inputs
(Non-Test)
6
ns
ns
NOTE:
See Table 24 on page 47 for note definitions for this table.
46
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 24.
Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44)
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than IOL. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition
at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
10.Relative to falling edge of TCK.
11.Worst-case TOV condition occurs on I/O pins when pins transition from a floating high input to driving a
low output state. The Address/Data Bus pins encounter this condition between the last access of a read,
and the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at
50 pF loads.
4.7.1
AC Test Conditions and Derating Curves
The AC Specifications in Section 4.7, “AC Specifications” are tested with the 50 pF load indicated
in Figure 10. Figure 11 shows how timings and output rise and fall times vary with load
capacitance.
Figure 10.
AC Test Load
Output Pin
CL
Advance Information Datasheet
CL = 50 pF for all signals
47
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 11.
Output Delay or Hold vs. Load Capacitance
AC Timings vs. Load Capacitance
nom + 7
nom + 6
Tov (ns)
nom + 5
nom + 4
Rising
nom + 3
Falling
nom + 2
nom + 1
nom + 0
50
100
AD Bus Capacitive Load (pF)
Rise and Fall times are identical.
Figure 12.
150
TLX vs. AD Bus Load Capacitance
AC Timings vs. Load Capacitance
nom + 7
nom + 6
Tlx (ns)
nom + 5
nom + 4
Rising
nom + 3
Falling
nom + 2
nom + 1
nom + 0
50
Rise and Fall times are identical.
Note:
48
100
150
AD Bus Capacitive Load (pF)
The TLX Derating curve applies only when an imbalance in the capacitive load occurs between the
AD bus and ALE. The TLX derating is based on a 50 pF load on ALE. The derating applies to ALE
and ALE.
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 13.
80960JA/JF ICC Active (Power Supply) vs. Frequency
Icc Active (Power Supply) (mA)
Icc Active (Power Supply) vs Frequency
350
300
250
200
150
100
50
0
12
15
18
21
24
27
30
33
CLKIN Frequency MHz
Figure 14.
80960JA/JF ICC Active (Thermal) vs. Frequency
ICC Active (Thermal) vs. Frequency
Icc Active (Thermal) vs. Frequency
Icc Active (Thermal) (mA)
ICC Active (Thermal) (mA)
300
250
200
150
100
50
0
12
15
18
21
24
27
30
33
CLKIN Frequency MHz
Advance Information Datasheet
49
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 15.
80960JD ICC Active (Power Supply) vs. Frequency
Icc Active (Power Supply) vs. Frequency
Icc Active (Power Supply) (mA)
600
500
400
300
200
100
0
12
15
18
21
24
27
30
33
CLKIN Frequency (MHz)
Figure 16.
80960JD ICC Active (Thermal) vs. Frequency
Icc Active (Thermal) vs. Frequency
Icc Active (Thermal) (mA)
600
500
400
300
200
100
0
12
15
18
21
24
27
30
33
CLKIN Frequency (MHz)
50
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 17.
80960JT ICC Active (Power Supply) vs. Frequency
Icc Active (Power Supply) vs. Frequency
Icc Active (Power Supply) (mA)
600
500
400
300
200
100
0
15
18
21
24
27
30
33
CLKIN Frequency (MHz)
Figure 18.
80960JT ICC Active (Thermal) vs. Frequency
Icc Active (Thermal) vs. Frequency
Icc Active (Thermal) (mA)
1000
800
600
400
200
0
15
18
21
24
27
30
33
CLKIN Frequency (MHz)
Advance Information Datasheet
51
80960JA/JF/JD/JT 3.3 V Microprocessor
4.7.2
AC Timing Waveforms
Figure 19.
CLKIN Waveform
TCR
TCF
2.0V
1.5V
0.8V
TCH
TCL
TC
Figure 20.
TOV1 Output Delay Waveform
CLKIN
1.5V
1.5V
TOV1
AD31:0,
ALE (active),
ALE (active),
ADS, A3:2,
BE3:0,
WIDTH/HLTD1:0,
D/C, W/R, DEN,
BLAST, LOCK,
HOLDA, BSTAT, FAIL
52
1.5V
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 21.
TOF Output Float Waveform
1.5V
CLKIN
1.5V
TOF
AD31:0,
ALE, ALE
ADS, A3:2,
BE3:0,
WIDTH/HLTD1:0,
D/C, W/R, DT/R,
DEN, BLAST, LOCK
Figure 22.
TIS1 and TIH1 Input Setup and Hold Waveform
CLKIN
1.5V
1.5V
1.5V
TIH1
TIS1
AD31:0
NMI
XINT7:0
Figure 23.
Valid
1.5V
TIS2 and TIH2 Input Setup and Hold Waveform
CLKIN
1.5V
1.5V
1.5V
TIH2
TIS2
HOLD,
RDYRCV
Advance Information Datasheet
1.5V
Valid
1.5V
53
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 24.
TIS3 and TIH3 Input Setup and Hold Waveform
CLKIN
1.5V
1.5V
TIH3
TIS3
RESET
Figure 25.
TIS4 and TIH4 Input Setup and Hold Waveform
RESET
TIH4
TIS4
ONCE,
STEST
54
Valid
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 26.
TLX, TLXL and TLXA Relative Timings Waveform
Ta
Tw/Td
1.5V
CLKIN
1.5V
1.5V
TLXL
ALE
ALE
TLX
AD31:0
Figure 27.
1.5V
Valid
1.5V
1.5V
TLXA
1.5V
Valid
DT/R and DEN Timings Waveform
Ta
CLKIN
Tw/Td
1.5V
1.5V
1.5V
TOV2
Valid
DT/R
TDXD
DEN
TOV1
Advance Information Datasheet
55
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 28.
TCK Waveform
TBSCR
TBSCF
2.0V
1.5V
0.8V
TBSCH
Figure 29.
TBSCL
TBSIS1 and TBSIH1 Input Setup and Hold Waveforms
TCK
1.5V
1.5V
TBSIS1
TMS
TDI
Figure 30.
1.5V
TBSIH1
1.5V
Valid
TBSOV1 and TBSOF1 Output Delay and Output Float Waveform
TCK
1.5V
1.5V
TBSOV1
TDO
56
1.5V
1.5V
1.5V
TBSOF1
Valid
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 31.
TBSOV2 and TBSOF2 Output Delay and Output Float Waveform
TCK
1.5V
1.5V
TBSOF2
TBSOV2
Non-Test
Outputs
Figure 32.
1.5V
Valid
1.5V
TBSIS2 and TBSIH2 Input Setup and Hold Waveform
TCK
1.5V
1.5V
TBSIS2
Non-Test
Inputs
Advance Information Datasheet
1.5V
1.5V
TBSIH2
Valid
1.5V
57
80960JA/JF/JD/JT 3.3 V Microprocessor
5.0
Bus Functional Waveforms
Figure 33 through Figure 38 illustrate typical 80960Jx bus transactions. Figure 39 depicts the bus
arbitration sequence. Figure 40 illustrates the processor reset sequence from the time power is
applied to the device. Figure 41 illustrates the processor reset sequence when the processor is in
operation. Figure 42 illustrates the processor ONCE sequence from the time power is applied to the
device. Figure 44 and Figure 45 also show accesses on 32-bit buses. Table 27 through Table 29
summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to
data alignment.
Figure 33.
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
Ta
Td
Tr
Ti
Ti
Ta
Td
Tr
Ti
Ti
CLKIN
AD31:0
D
In
ADDR
Invalid
DATA Out
ADDR
ALE
ADS
A3:2
BE3:0
WIDTH1:0
10
10
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF030A
58
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 34.
Burst Read and Write Transactions Without Wait States, 32-Bit Bus
TA
TD
TD
TR
TA
TD
TD
TD
TD
TR
CLKIN
AD31:0
ADDR
D
In
D
In
ADDR
DATA DATA DATA
Out Out Out
DATA
Out
ALE
ADS
A3:2
00 or 10
01 or 11
00
01
10
11
BE3:0
WIDTH1:0
10
10
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
Advance Information Datasheet
59
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 35.
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus
TA
TW
TW
TD
TW
TD
TW
TD
TW
TD
TR
CLKIN
AD31:0
ADDR
DATA
Out
DATA
Out
DATA
Out
DATA
Out
ALE
ADS
A3:2
00
01
10
11
BE3:0
WIDTH1:0
10
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF032A
60
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 36.
Burst Read and Write Transactions Without Wait States, 8-Bit Bus
TA
TD
TD
TR
TA
TD
TD
TD
TD
TR
CLKIN
AD31:0
ADDR
D
In
D
In
ADDR DATA DATA DATA
Out
Out
Out
DATA
Out
ALE
ADS
A3:2
BE1/A1
BE0/A0
WIDTH1:0
00,01,10 or 11
00,01,10 or 11
00 or 10
01 or
11
00
00
01
10
11
00
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF033A
Advance Information Datasheet
61
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 37.
Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on
Read, 16-Bit Bus
TA
TW
TD
TD
TR
TR
TA
TW
TD
TD
TR
CLKIN
AD31:0
D
In
ADDR
D
In
DATA
Out
ADDR
DATA
Out
ALE
ADS
BE1/A1
00,01,10, or 11
00,01,10, or 11
A3:2
0
1
0
1
BE3/BHE
BE0/BLE
WIDTH1:0
01
01
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
62
F_JF034A
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 38.
Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit Bus, Little Endian
TA
TD
TR
TA
TD
TR
TA
TD
TR
TA
TD
TR
CLKIN
AD31:0
D
In
A
D
In
A
D
In
A
D
In
A
ALE
ADS
A3:2
00
00
BE3:0
1101
0011
WIDTH1:0
D/C
01
0000
10
1110
10
Valid
W/R
BLAST
DT/R
DEN
RDYRCV
Advance Information Datasheet
63
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 39.
HOLD/HOLDA Waveform For Bus Arbitration
TH
TH
TI or TA
~
TI or TR
~
Valid
~
~
Valid
~
Outputs:
AD31:0,
ALE, ALE,
ADS, A3:2,
BE3:0,
WIDTH/HLTD1:0,
D/C, W/R,
DT/R, DEN,
BLAST, LOCK
~
~
CLKIN
~
HOLD
(Note)
~
HOLDA
NOTE: HOLD is sampled on the rising edge of CLKIN. The processor asserts HOLDA to grant the bus on the
same edge in which it recognizes HOLD if the last state was Ti or the last Tr of a bus transaction. Similarly,
the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.
64
Advance Information Datasheet
VCC and CLKIN stable to RESET High, minimum
10,000 CLKIN periods, for PLL stabilization.
Valid
(Output)
Built-in self-test (Note 4)
(Input)
Valid Output (Note 3)
Valid Input (Note 3)
Idle (Note 2)
(Note 1)
First
Bus
Activity
3. Since the bus is idle, hold requests are honored during reset and built-in self-test.
4. When selected, built-in self test requires approximately (in CLKIN periods): 393,000 for 80960JT, 207,000 for 80960JD, and 414,000
for 80960JA/JF.
2. If the processor fails built-in self-test, it initiates one dummy load bus access. The load address indicates the point of self-test failure.
Notes:
1. The processor asserts FAIL during built-in self-test. If self- test passes, the FAIL pin is deasserted.The processor also asserts FAIL
during the bus confidence test. If the bus confidence test passes, FAIL is deasserted and the processor begins user program execution.
RESET
STEST
LOCK/
ONCE
HOLDA
HOLD
AD31:0, A3:2,D/C
FAIL
~
~
~
~
~
~
ALE, ADS,
BE3:0, DEN,
BLAST
ALE,W/R, DT/R
WIDTH/HLTD1:0
~
~
~
~
~
~
~
~
~
~
VCC
~
~
~
~
~
~
~
~
~
~
~
~
~
~ ~
~ ~
~ ~
~
~ ~
~ ~
~ ~
~
~
~
~
~
~
~ ~
~
~
~
~ ~
~
~ ~
~
~
~
~
~
~
~
~
~
~
~ ~
~
~
~
~
~
~
~
~
~
~
~
~
~ ~
~
~ ~
~ ~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~ ~
~
~ ~
~
Advance Information Datasheet
~
~ ~
~ ~
~
Figure 40.
CLKIN
80960JA/JF/JD/JT 3.3 V Microprocessor
Cold Reset Waveform
65
RESET
STEST
LOCK/ONCE
HOLDA
HOLD
AD31:0, A3:2, D/C
FAIL
ALE, W/R,DT/R, BSTAT,
WIDTH/HLTD1:0
ALE, ADS, BE3:0,
DEN, BLAST
Minimum RESET Low Time
15 CLKIN Cycles
Maximum RESET Low to Reset State
4 CLKIN Cycles
~
~
~
~
~
~
~
~
~
~
~
~ ~
~~
~ ~
~
~
~ ~
~ ~
~~
~ ~
~ ~
~~
~
~
~
~
~
~
~
80960JT - 26 CLKIN
Cycles
80960JD - 46 CLKIN
Cycles
80960JA/JF - 92 CLKIN
Cycles
RESET High to First Bus
Activity:
Valid
~
~
~
~
~
~
~
~ ~
~
~
~ ~
~
~
~
~
~
~
~ ~
~
~
~
~
~
66
~
~
Figure 41.
~
~
CLKIN
80960JA/JF/JD/JT 3.3 V Microprocessor
Warm Reset Waveform
Advance Information Datasheet
CLKIN
VCC
ALE, ADS,
BE3:0, DEN, BLAST
ALE,W/R,
DT/R, WIDTH/HLTD1:0
VCC and CLKIN stable to RESET High,
minimum 10,000 CLKIN periods, for PLL
stabilization.
(Note 1)
(Input)
2. The ONCE input may be removed after the processor enters ONCE Mode.
NOTES:
1. ONCE mode may be entered prior to the rising edge of RESET: ONCE input is not latched until the rising edge of RESET.
RESET
STEST
LOCK/
ONCE
HOLDA
HOLD
~
~
AD31:0, A3:2,
D/C
~
~
~
~
~
~
~ ~
~
~
FAIL
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~
~
~ ~
~
~
~ ~
~ ~
~ ~
~ ~
~
~
~
~
~
~
~ ~
~
~
~
~
~
~
~
~
~
~
~~
~
~
~
~ ~
~
~ ~
~
~
~ ~
~
~
~
~
~
~
~ ~
~
~
~
~
~
~
~
~
~
~
~
Advance Information Datasheet
~
~ ~
~ ~
~ ~
~
Figure 42.
~
~
CLKIN may not be allowed to float.
It must be driven high or low or continue to run.
80960JA/JF/JD/JT 3.3 V Microprocessor
Entering the ONCE State
67
80960JA/JF/JD/JT 3.3 V Microprocessor
5.1
Basic Bus States
The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold
(Th). During system operation, the processor continuously enters and exits different bus states.
The bus occupies the idle (Ti) state when no address/data transactions are in progress and when RESET is
asserted. When the processor needs to initiate a bus access, it enters the Ta state to transmit the address.
Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data
lines. Assertion of the RDYRCV input signal indicates completion of each transfer. When data is
not ready, the processor can wait as long as necessary for the memory or I/O device to respond.
After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case of a
burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next data word.
The processor asserts the BLAST signal during the last Tw/Td states of an access. Once all data words
transfer in a burst access (up to four), the bus enters the Tr state to allow devices on the bus to recover.
The processor remains in the Tr state until RDYRCV is deasserted. When the recovery state
completes, the bus enters the Ti state if no new accesses are required. If an access is pending, the
bus enters the Ta state to transmit the new address.
Figure 43.
Bus States with Arbitration
(READY AND BURST)
OR NOT READY
Tw/Td
Ta
RECOVERED AND
REQUEST
PENDING AND (NO
HOLD OR LOCKED)
READY AND NO BURST
REQUEST PENDING
AND (NO HOLD OR
LOCKED)
NOT
RECOVERED
REQUEST
PENDING AND
NO HOLD
NO REQUEST
AND (NO HOLD
OR LOCKED)
RECOVERED AND
NO REQUEST AND
(NO HOLD OR
LOCKED)
Tr
Ti
ONCE & RESET
DEASSERTION
NO REQUEST
AND NO HOLD
To
RESET
HOLD AND
NOT LOCKED
Ti — IDLE STATE
Ta — ADDRESS STATE
Tw / Td — WAIT/DATA STATE
Tr — RECOVERY STATE
Th — HOLD STATE
To — ONCE STATE
68
Th
RECOVERED AND
HOLD AND NOT
LOCKED
READY
NOT READY
BURST
NO BURST
RECOVERED
NOT RECOVERED
REQUEST PENDING
NO REQUEST
HOLD
NO HOLD
LOCKED
NOT LOCKED
RESET
ONCE
HOLD
— RDYRCV ASSERTED
— RDYRCV NOT ASSERTED
— BLAST NOT ASSERTED
— BLAST ASSERTED
— RDYRCV NOT ASSERTED
— RDYRCV ASSERTED
— NEW TRANSACTION
— NO NEW TRANSACTION
— HOLD REQUEST ASSERTED
— HOLD REQUEST NOT ASSERTED
— ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS
— NO ATOMIC EXECUTION IN PROGRESS
— RESET ASSERTED
— ONCE ASSERTED
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
5.2
Boundary-Scan Register
The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and HIGHZ pins.
Table 25 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that
contain “CTL” select the direction of bidirectional pins or HIGHZ output pins. If a “1” is loaded
into the control cell, the associated pin(s) are HIGHZ or selected as input.
Table 25.
Boundary-Scan Register Bit Order
Bit
Signal
Input/
Output
Bit
Signal
Input/
Output
Bit
Signal
Input/
Output
0
RDYRCV (TDI)
I
24
DEN
O
48
AD17
I/O
1
HOLD
I
25
HOLDA
O
49
AD16
I/O
2
XINT0
I
26
ALE
O
50
AD15
I/O
3
XINT1
I
27
LOCK/ONCE
cell
Enable cell1
51
AD14
I/O
4
XINT2
I
28
LOCK/ONCE
I/O
52
AD13
I/O
5
XINT3
I
29
BSTAT
O
53
AD12
I/O
6
XINT4
I
30
BE0
O
54
AD cells
Enable
cell1
7
XINT5
I
31
BE1
O
55
AD11
I/O
8
XINT6
I
32
BE2
O
56
AD10
I/O
9
XINT7
I
33
BE3
O
57
AD9
I/O
10
NMI
I
34
AD31
I/O
58
AD8
I/O
11
FAIL
I
35
AD30
I/O
59
AD7
I/O
12
ALE
O
36
AD29
I/O
60
AD6
I/O
13
WIDTH/HLTD1
O
37
AD28
I/O
61
AD5
I/O
14
WIDTH/HLTD0
O
38
AD27
I/O
62
AD4
I/O
15
A2
O
39
AD26
I/O
63
AD3
I/O
16
A3
O
40
AD25
I/O
64
AD2
I/O
41
AD24
I/O
65
AD1
I/O
17
CONTROL1
Enable cell
1
1
18
CONTROL2
Enable cell
42
AD23
I/O
66
AD0
I/O
19
BLAST
O
43
AD22
I/O
67
CLKIN
I
20
D/C
O
44
AD21
I/O
68
RESET
I
21
ADS
O
45
AD20
I/O
69
STEST
(TDO)
I
22
W/R
O
46
AD19
I/O
23
DT/R
O
47
AD18
I/O
NOTE:
1. Enable cells are active low.
Advance Information Datasheet
69
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 26.
Natural Boundaries for Load and Store Accesses
Data Width
Table 27.
Byte
1
Short Word
2
Word
4
Double Word
8
Triple Word
16
Quad Word
16
Summary of Byte Load and Store Accesses
Address Offset from
Natural Boundary
(in Bytes)
+0 (aligned)
Table 28.
Accesses on 8-Bit Bus
(WIDTH1:0=00)
• byte access
Accesses on 16 Bit
Bus (WIDTH1:0=01)
• byte access
Accesses on 32 Bit
Bus (WIDTH1:0=10)
• byte access
Summary of Short Word Load and Store Accesses
Address Offset from
Natural Boundary
(in Bytes)
70
Natural Boundary (Bytes)
Accesses on 8-Bit Bus
(WIDTH1:0=00)
Accesses on 16 Bit
Bus (WIDTH1:0=01)
Accesses on 32 Bit
Bus (WIDTH1:0=10)
+0 (aligned)
• burst of 2 bytes
• short-word access
• short-word access
+1
• 2 byte accesses
• 2 byte accesses
• 2 byte accesses
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 29.
Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)
Address Offset
from Natural
Boundary in Bytes
Accesses on 8-Bit Bus
(WIDTH1:0=00)
Accesses on 16 Bit Bus
(WIDTH1:0=01)
Accesses on 32 Bit
Bus (WIDTH1:0=10)
• case n=1:
burst of 2 short words
+0 (aligned)
(n =1, 2, 3, 4)
• case n=2:
burst of 4 short words
• n burst(s) of 4 bytes
• case n=3:
burst of 4 short words
burst of 2 short words
• burst of n word(s)
• case n=4:
2 bursts of 4 short words
+1 (n =1, 2, 3, 4)
• byte access
+5 (n = 2, 3, 4)
• burst of 2 bytes
+9 (n = 3, 4)
• n-1 burst(s) of 4 bytes
+13 (n = 3, 4)
• byte access
+2 (n =1, 2, 3, 4)
+6 (n = 2, 3, 4)
+10 (n = 3, 4)
+14 (n = 3, 4)
• burst of 2 bytes
• n-1 burst(s) of 4 bytes
• burst of 2 bytes
+3 (n =1, 2, 3, 4)
• byte access
+7 (n = 2, 3, 4)
• n-1 burst(s) of 4 bytes
+11 (n = 3, 4)
• burst of 2 bytes
+15 (n = 3, 4)
• byte access
• byte access
• byte access
• short-word access
• short-word access
• n-1 burst(s) of 2 short
words
• n-1 word
access(es)
• byte access
• byte access
• short-word access
• short-word access
• n-1 burst(s) of 2 short
words
• n-1 word
access(es)
• short-word access
• short-word access
•
• byte access
byte access
• n-1 burst(s) of 2 short
words
• n-1 word
access(es)
• short-word access
• short-word access
• byte access
• byte access
• n burst(s) of 2 short words
• n word access(es)
+4 (n = 2, 3, 4)
+8 (n = 3, 4)
• n burst(s) of 4 bytes
+12 (n = 3, 4)
Advance Information Datasheet
71
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 44.
Summary of Aligned and Unaligned Accesses (32-Bit Bus)
0
4
8
12
16
20
24
Word Offset 0
1
2
3
4
5
6
Byte Offset
Short Access (Aligned)
Byte, Byte Accesses
Short-Word
Load/Store
Short Access (Aligned)
Byte, Byte Accesses
Word Access (Aligned)
Byte, Short, Byte, Accesses
Word
Load/Store
Short, Short Accesses
Byte, Short, Byte Accesses
One Double-Word Burst (Aligned)
Byte, Short, Word, Byte Accesses
Short, Word, Short Accesses
Double-Word
Load/Store
Byte, Word, Short, Byte Accesses
Word, Word Accesses
One Double-Word
Burst (Aligned)
72
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 45.
Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)
0
4
8
12
16
20
24
1
2
3
4
5
6
Byte Offset
Word Offset
0
One Three-Word
Burst (Aligned)
Byte, Short, Word,
Word, Byte Accesses
Triple-Word
Load/Store
Short, Word, Word,
Short Accesses
Byte, Word, Word,
Short, Byte Accesses
Word, Word,
Word Accesses
Word, Word,
Word Accesses
Word,
Word,
Word
Accesses
One Four-Word
Burst (Aligned)
Byte, Short, Word, Word,
Word, Byte Accesses
Quad-Word
Load/Store
Short, Word, Word, Word,
Short Accesses
Byte, Word, Word, Word,
Short, Byte Accesses
Word, Word, Word,
Word Accesses
Word,
Word,
Word,
Word,
Accesses
Advance Information Datasheet
73
80960JA/JF/JD/JT 3.3 V Microprocessor
6.0
Device Identification
80960Jx processors may be identified electrically, according to device type and stepping (see
Figure 46, and Table 31 through Table 36). Table 30 identifies the device type and stepping for all
5V, 80960Jx processors. Figure 46, and Table 31 through Table 36 identify all 3.3V-5V-tolerant
80960Jx processors. The device ID was enhanced to differentiate between 3.3V and 5V supply
voltages, and between non-clock-doubled and clock-doubled cores when stepping from the A2
stepping to the C0 stepping. The 32-bit identifier is accessible in three ways:
• Upon reset, the identifier is placed into the g0 register.
• The identifier may be accessed from supervisor mode at any time by reading the DEVICEID
register at address FF008710H.
• The IEEE Standard 1149.1 Test Access Port may select the DEVICE ID register through the
IDCODE instruction.
• The device and stepping letter is also printed on the top side of the product package.
Table 30.
Figure 46.
80960Jx Device Type and Stepping Reference
Device and
Stepping
Version
Number
80960JT A0, A1
0000
0000 1000 0010 1011
80960JD C0
0011
0000 1000 0011 0000
80960JF C0
0011
0000 1000 0010 0000
80960JA C0
0011
0000 1000 0010 0001
Part Number
X
Complete ID
(Hex)
0000 0001 001
1
0082B013
0000 0001 001
1
30830013
0000 0001 001
1
30820013
0000 0001 001
1
30821013
Manufacturer
80960JT Device Identification Register
Part Number
Version VCC
0
28
74
Product
Type
0 0 0 1
24
0 0
Gen
0
20
0 0 1
Model
0
16
Manufacturer ID
1 0 1 1 0
12
0 0 0 0
8
0 0
1
4
0 0 1
1
1
0
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 31.
Fields of 80960JT Device ID
Field
Value
Definition
Version
See Table 32
Indicates major stepping changes.
VCC
0 = 3.3 V device
Indicates that a device is 3.3 V.
Product Type
000 100
(Indicates i960 CPU)
Designates type of product.
Generation Type 0001 = J-series
Indicates the generation (or series) the product belongs
to.
Model
Indicates member within a series and specific model
information.
D DPCC
D = Clock Multiplier
(01) Clock-Tripled
(P) Product Derivative
(0) Jx
C = Cache Size
(11) 16K I-cache, 4K D-cache
Manufacturer ID
Table 32.
Figure 47.
000 0000 1001
(Indicates Intel)
Manufacturer ID assigned by IEEE.
80960JT Device ID Model Types
Device
Version
VCC
Product
Gen.
Model
Manufacturer ID
‘1’
80960JT A0, A1
0000
0
000100
0001
01011
00000001001
1
80960JD Device Identification Register
Part Number
Version VCC
0
28
Advance Information Datasheet
Product
Type
0 0 0 1
24
0 0
Gen
0
20
0 0 1
Model
1
16
Manufacturer ID
0 0 0 1 0
12
0 0 0 0
8
0 0
1
4
0 0 1
1
1
0
75
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 33.
Fields of 80960JD Device ID
Field
Value
Version
Definition
See Table 30
Indicates major stepping changes.
0 = 3.3 V device
VCC
Indicates that a device is 3.3 V.
1 = 5V device
Product Type
00 0100
(Indicates i960 CPU)
Designates type of product.
Generation Type
0001 = J-series
Indicates the generation (or series) the product belongs to.
D000C
D = Clock Doubled
(0) Not Clock-Doubled
(1) Clock Doubled
Model
Indicates member within a series and specific model information.
C = Cache Size
(0) 4K I-cache, 2K
D-cache
(1) 2K I-cache, 1K
D-cache
Manufacturer ID
Table 34.
Figure 48.
000 0000 1001
(Indicates Intel)
Manufacturer ID assigned by IEEE.
80960JD Device ID Model Types
Device
Version
VCC
Product
Gen.
Model
Manufacturer ID
‘1’
80960JD C0
0011
0
000100
0001
10000
00000001001
1
80960JA/JF Device Identification Register
Part Number
Version VCC
0
28
76
Product
Type
0 0 0 1
24
0 0
Gen
0
20
Model
Manufacturer ID
0 0 1
0
16
12
0 0 0 0
8
0 0
1
4
0 0 1
1
1
0
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 35.
Fields of 80960JA/JF Device ID
Field
Value
Definition
Version
See Table 36
Indicates major stepping changes.
VCC
0 = 3.3 V device
Indicates that a device is 3.3 V.
1 = 5V device
Product Type
00 0100
(Indicates i960 CPU)
Designates type of product.
Generation Type
0001 = J-series
Indicates the generation (or series) to which the
product belongs.
0000C
Indicates member within a series and specific
model information.
Model
C = Cache Size
0 = 4K I-cache, 2K D-cache
1 = 2K I-cache, 1K D-cache
Manufacturer ID
Table 36.
000 0000 1001
(Indicates Intel)
80960JA/JF Device ID Model Types
Device
7.0
Manufacturer ID assigned by IEEE.
Version
VCC
Product
Gen.
Model
Manufacturer ID
‘1’
80960JA C0
0011
0
000100
0001
00001
00000001001
1
80960JF C0
0011
0
000100
0001
00000
00000001001
1
Revision History
This data sheet supersedes revisions 273109-001, 272971-002, and 276146-001. Table 37 indicates
significant changes since the previous revisions.
Table 37.
Data Sheet Revision History
Figure 1 “80960Jx Microprocessor Package
Options” on page 7
Added MPBGA package diagram
Section 3.1.4, “80960Jx 196-Ball MPBGA
Pinout” on page 29
Added new Figures 6 and 7, Tables 10, 11 and 13
Figure 12 “TLX vs. AD Bus Load Capacitance” on
page 48
Added with following note
Throughout document
Merged 80960JA/JF/JD/JT 3.3 volt Processor data sheets
Advance Information Datasheet
77