Features • Third Generation Programmable Logic Structure – High-Density Replacement for Discrete Logic • High-Speed — Plus a New, Low-Power Version • Increased Logic Flexibility – 42 Inputs and 20 Sum Terms • Flexible Output Logic • • • • – 20 Flip-Flops - 10 Extra – All Can Be Individually Buried or 10 Output Directly – Each has Individual Asynchronous Reset and Clock Terms Multiple Feedback Paths Provide for Buried State Machines and I/O Bus Compatibility Proven and Reliable High-Speed CMOS EPROM Process – 2000V ESD Protection – 200 mA Latchup Immunity Reprogrammable – Tested 100% for Programmability 24-pin, 300-mil Dual-In-line and 28-Lead Surface Mount Packages High Density UV Erasable Programmable Logic Device Logic Diagram ATV750 ATV750L Description The ATV750(L) is 100% more powerful than most other programmable logic devices in 24-pin packages. Increased product terms, sum terms, and flip-flops translate into more usable gates. Each of the ATV750(L)’s twenty-two logic pins can be used as an input. Ten of these can be used as input, output, or bi-directional I/O pins. All twenty flip-flops can be fed back into the array independently. This flexibility allows burying all of the sum terms and flip-flops. There are 171 product terms available. A variable format is used to assign between four and eight product terms per sum term. There are two sum terms per output, providing added flexibility. (continued) Logic Inputs I/O Bidirectional Buffers * No Internal Connection VCC +5V Supply 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN IN IN * IN IN IN 4 3 2 1 28 27 26 IN IN IN IN IN IN IN IN IN IN IN IN GND 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 Function I/O I/O I/O * I/O I/O I/O Rev. 0024E–05/98 IN IN GND * IN I/O I/O Pin Name PLCC/LCC (Top View) IN IN IN * VCC I/O I/O DIP/SOIC Pin Configurations 1 The ATV750(L) has more flip-flops available than other PLDs in this density range. Complex state machines are easily implemented. Product terms are available providing asynchronous resets, flip-flop clocks, and output enables. One reset and one clock term are provided per flip-flop, with one enable term per output. One product term provides a global synchronous preset. Register preload simplifies testing. The device has an internal power up clear function. Absolute Maximum Ratings Temperature Under Bias ............................... -55°C to + 125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns. Storage Temperature .................................... -65°C to + 150°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) Integrated UV Erase Dose.............................. 7258 W.sec/cm2 1. Logic Options Combined Terms Separate Terms Output Options 2 ATV750/L Combined Terms Separate Terms ATV750/L DC and AC Operating Conditions ATV750-20 ATV750/750L-25 0°C - 70°C 0°C - 70°C Ind. -40°C - 85°C -40°C - 85°C Mil. -55°C - 125°C -55°C - 125°C 5V ± 10% 5V ± 10% Com. Operating Temperature (Case) VCC Power Supply DC Characteristics Symbol Parameter Condition ILI Input Load Current VIN = -0.1V to VCC + 1V ILO Output Leakage Current VOUT = -0.1V to VCC + 0.1V ICC Power Supply Current IOS(1) Output Short Circuit Current VIL Input Low Voltage VIH Input High Voltage VOL VOH Note: Output Low Voltage Output High Voltage VCC = MAX, VIN = GND, Outputs Open Min Max Units 10 µA 10 µA Com. 120 mA Ind.,Mil. 140 mA ATV750 Com. 1.0 12 mA Ind.,Mil. 1.0 15 mA -120 mA -0.6 0.8 V 2.0 VCC + 0.75 V IOL = 12 mA Com.,Ind. 0.5 V IOL = 8 mA Mil. 0.5 V IOL = 24 mA, Com. 1.0 V ATV750L VOUT = 0.5V VIN = VIH or VIL, VCC = MIN VIN = VIH or VIL, VCC = MIN Typ IOH = -100 µA VCC - 0.3 V IOH = -4.0 mA 2.4 V 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 3 AC Waveforms(1) Note: 4 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. ATV750/L ATV750/L AC Characteristics ATV750-20 Symbol Parameter tPD Input or Feedback to Non-Registered Output tEA Max Units 20 25 ns Input to Output Enable 20 25 ns tER Input to Output Disable 20 25 ns tCO Clock to Output 20 22 ns tCF Clock to Feedback 5 10 ns tS Input Setup Time 10 12 ns tSF Feedback Setup Time 5 7 ns tH Hold Time 5 5 ns tP Clock Period 18 22 ns tW Clock Width 8 10 ns FMAX Maximum Frequency tAW Asynchronous Reset Width 15 20 ns tAR Asynchronous Reset Recovery Time 15 20 ns tAP Asynchronous Reset to Registered Output Reset tSP Setup Time, Synchronous Preset Input Test Waveforms and Measurement Levels Min Max ATV750/750L-25 10 Min 5 55 45 20 12 25 15 MHz ns ns Output Test Loads tR, tF < 5 ns (10% to 90%) 5 Functional Logic Diagram ATV750, Upper Half 6 ATV750/L ATV750/L Functional Logic Diagram ATV750, Lower Half 7 Preload of Registered Outputs The ATV750's registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A VIH level on the I/O pin will force the register high; a VIL will force it low, independent of the output polarity. The preload state is entered by placing an 10.5V to 11.5V signal on pin 8 on DIPs, and pin 10 on SMPs. When the clock term is pulsed high, the data on the I/O pin is placed into the register chosen by the Select Pin. Level forced on registered output pin during PRELOAD cycle Select Pin State Register #1 state after cycle Register#2 State after cycle VIH Low High X VIL Low Low X VIH High X High VIL High X Low Power-Up Reset The registers in the ATV750(L) are designed to reset during power up. At a point delayed slightly from VCC crossing 3.8V, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock term high, and 3. The signals from which the clock is derived must remain stable during tPR. Pin Capacitance Parameter Description tPR Power-Up Reset Time Min Typ Max Units 600 1000 ns (f = 1 MHz, T = 25°C)(1) Typ Max Units CIN 5 8 pF VIN = 0V COUT 6 8 pF VOUT = 0V Note: 8 Conditions 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. ATV750/L ATV750/L Using the ATV750's Many Advanced Features The ATV750's flexibility puts more usable gates in 24-pins Security Fuse Usage than other PLDs. The ATV750(L) starts with an architecture similar to the popular AT22V10, and adds several features: • Asynchronous Clocks Each of the flip-flops in the ATV750(L) has a dedicated product term driving the clock. The user is no longer constrained to using one clock for all the registers. Buried state machines, counters, and registers can all coexist in one device, while running on separate clocks. The ATV750(L) clock period matches that of similar synchronous devices. • A Full Bank of 10 More Registers The ATV750(L) provides two flip-flops for each output macrocell - a total of 20. Each register has its own clock and reset product terms, as well as its own SUM term. • Independent I/O Pin and Feedback Paths Each I/O pin on the ATV750(L) has a dedicated input path. Each of the 20 registers has individual feedback terms into the array. This feature, combined with individual product terms for each I/O's output enable, facilitates designs using bi-directional I/O buses. • Combinable Sum Terms Each output macrocell’s two SUM terms can be combined in an OR gate before the output or the register. This provides up to 16 product terms per output or flipflop. This architecture increases the number of usable gates available. Programming Software Support Software which is capable of transforming Boolean equations, state machine descriptions and truth tables into JEDEC files for the ATV750(L) is available from several PLD software vendors. Please refer to the Software Support Information table in the Programmable Logic Development Tools section for more information. Synchronous Preset and Asynchronous Reset One synchronous preset line is provided for all 20 registers in the ATV750(L). The appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. Appropriate setup and hold times must be met, as shown in the switching waveform diagram. An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and slave halves of the flipflops are reset when the input signals received combine so as to force the internal resets high. A single fuse is provided to prevent unauthorized copying of the ATV750(L) fuse patterns. Once programmed, the output buffers will remain in a high impedance state during verify. The security fuse should be programmed last, as its effect is immediate. Erasure Characteristics The entire memory array of an ATV750(L) is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 minutes exposure using 12,000 µW/cm 2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W•sec/cm2. To prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight. Atmel CMOS PLDs Atmel’s Programmable Logic Devices utilize an advanced 1.5-micron CMOS EPROM technology. This technology's state of the art features are the optimum combination for PLDs: • CMOS technology provides high speed, low power, and high noise immunity. • EPROM technology is the most cost effective method for producing PLDs - surpassing bipolar fusible link technology in low cost, while providing the necessary reprogrammability. • EPROM reprogrammability, which is 100% tested before shipment, provides inherently better programmability and reliability than one-time fusible PLDs. • Atmel's EPROM process has proven extremely reliable in the volume production of a full line of advanced EPROM memory products, from 64K to one-megabit devices. 9 10 ATV750/L ATV750/L Ordering Information tPD (ns) tCO (ns) fMAX (MHz) 20 20 55 25 22 45 Ordering Code Package Operation Range ATV750-20JC ATV750-20PC ATV750-20SC 28J 24P3 24S Commercial (0°C to 70°C) ATV750-20JI ATV750-20PI ATV750-20SI 28J 24P3 24S Industrial (-40°C to 85°C) ATV750-20DM ATV750-20GM ATV750-20LM ATV750-20NM 24DW3 24D3 28LW 28L Military (-55°C to 125°C) ATV750-20DM/883 ATV750-20GM/883 ATV750-20LM/883 ATV750-20NM/883 24DW3 24D3 28LW 28L Military/883C (-55°C to 125°C) ATV750-25JC ATV750-25PC ATV750-25SC 28J 24P3 24S Commercial (0°C to 70°C) ATV750-25JI ATV750-25PI ATV750-25SI 28J 24P3 24S Industrial (-40°C to 85°C) ATV750-25DM ATV750-25GM ATV750-25LM ATV750-25NM 24DW3 24D3 28LW 28L Military (-55°C to 125°C) ATV750-25DM/883 ATV750-25GM/883 ATV750-25LM/883 ATV750-25NM/883 24DW3 24D3 28LW 28L Military/883C (-55°C to 125°C) Class B, Fully Compliant 20 20 55 5962-88726 04 LA 5962-88726 04 3X 5962-94524 03 MLA 5962-94524 03 M3X 24DW3 28LW 24D3 28L Military/883C (-55°C to 125°C) Class B, Fully Compliant 25 22 45 5962-88726 03 LA 5962-88726 03 3X 5962-94524 02 MLA 5962-94524 02 M3X 24DW3 28LW 24D3 28L Military/883C (-55°C to 125°C) Class B, Fully Compliant 11 Ordering Information (Continued) tPD (ns) tCO (ns) fMAX (MHz) 25 22 45 25 22 45 Ordering Code Package ATV750L-25JC ATV750L-25PC ATV750L-25SC 28J 24P3 24S Commercial (0°C to 70°C) ATV750L-25JI ATV750L-25PI ATV750L-25SI 28J 24P3 24S Industrial (-40°C to 85°C) ATV750L-25DM ATV750L-25GM ATV750L-25LM ATV750L-25NM 24DW3 24D3 28LW 28L Military (-55°C to 125°C) ATV750L-25DM/883 ATV750L-25GM/883 ATV750L-25LM/883 ATV750L-25NM/883 24DW3 24D3 28LW 28L Military/883C (-55°C to 125°C) Class B, Fully Compliant 5962-88726 07 LX 5962-88726 07 3X 5962-94524 05 MLA 5962-94524 05 M3X 24DW3 28LW 24D3 28L Military/883C (-55°C to 125°C) Class B, Fully Compliant Package Type 24DW3 24-Lead, 0.300" Wide, Windowed, Ceramic Dual In-line Package (Cerdip) 24D3 24-Lead, 0.300" Wide, Non-Windowed (OTP) Ceramic Dual In-line Package (Cerdip) 28J 28-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 28LW 28-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) 28L 28-Pad, Non-Windowed, Ceramic Leadless Chip Carrier OTP (LCC) 24P3 24-Lead, 0.300" Wide, Plastic Dual In-line Package OTP (PDIP) 24S 24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC) 12 ATV750/L Operation Range ATV750/L Packaging Information 24DW3, 24-Lead, 0.300" Wide, Windowed, Ceramic Dual In-line Package (Cerdip) Dimensions in Inches and (Millimeters) 24D3, 24-Lead, 0.300" Wide, Non-Windowed (OTP) Ceramic Dual In-line Package (Cerdip) Dimensions in Inches and (Millimeters) 1.28(32.5) 1.24(31.5) PIN 1 .310(7.87) .285(7.24) .098(2.49) MAX .005(.127) MIN 1.100(27.94) REF .200(5.08) MAX SEATING PLANE .060(1.52) .015(.381) .023(.584) .014(.356) .200(5.08) .125(3.18) .110(2.79) .090(2.29) .015(.381) .008(.203) .065(1.65) .045(1.14) .325(8.25) .300(7.62) 0 REF 15 .400(10.2) MAX 28J, 28-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) Dimensions in Inches and (Millimeters) .045(1.14) X 45° PIN NO. 1 IDENTIFY .032(.813) .026(.660) 28LW, 28-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) Dimensions in Inches and (Millimeters) .045(1.14) X 30° - 45° .456(11.6) SQ .450(11.4) .495(12.6) SQ .485(12.3) .050(1.27) TYP .300(7.62) REF SQ .012(.305) .008(.203) .430(10.9) SQ .390(9.91) .021(.533) .013(.330) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .022(.559) X 45° MAX (3X) 13 Packaging Information 28L, 28-Pad, Non-Windowed, Ceramic Leadless Chip Carrier OTP (LCC) Dimensions in Inches and (Millimeters) 24P3, 24-Lead, 0.300" Wide, Plastic Dual Inline Package OTP (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 AF 1.27(32.3) 1.25(31.7) PIN 1 .266(6.76) .250(6.35) .090(2.29) MAX 1.100(27.94) REF .200(5.06) MAX .005(.127) MIN SEATING PLANE .070(1.78) .020(.508) .023(.584) .014(.356) .151(3.84) .125(3.18) .110(2.79) .090(2.29) .065(1.65) .040(1.02) .325(8.26) .300(7.62) .012(.305) .008(.203) 0 REF 15 .400(10.2) MAX 24S, 24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC) Dimensions in Inches and (Millimeters) .020(.508) .013(.330) .299(7.60) .420(10.7) .291(7.39) .393(9.98) PIN 1 ID .050(1.27) BSC .616(15.6) .598(15.2) .105(2.67) .092(2.34) .012(.305) .003(.076) .013(.330) .009(.229) 0 REF 8 14 .050(1.27) .015(.381) ATV750/L