AD AD9518-0ABCPZ-RL7 6-output clock generator Datasheet

FUNCTIONAL BLOCK DIAGRAM
CP
REF1
REFIN
REF2
CLK
LF
STATUS
MONITOR
PLL
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.55 GHz to 2.95 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
3 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
Automatic synchronization of all outputs on power-up
Manual output synchronization available
Available in a 48-lead LFCSP
VCO
DIVIDER
AND MUXs
DIV/Φ
LVPECL
DIV/Φ
LVPECL
DIV/Φ
LVPECL
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
AD9518-0
06429-001
FEATURES
SWITCHOVER
AND MONITOR
Data Sheet
6-Output Clock Generator with
Integrated 2.8 GHz VCO
AD9518-0
Figure 1.
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9518-0 1 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz
to 2.95 GHz. Optionally, an external VCO/VCXO of up to
2.4 GHz can be used.
The AD9518-0 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
The AD9518-0 features six LVPECL outputs (in three pairs).
The LVPECL outputs operate to 1.6 GHz.
For applications that require additional outputs, a crystal
reference input, zero-delay, or EEPROM for automatic
configuration at startup, the AD9520 and AD9522 are available.
In addition, the AD9516 and AD9517 are similar to the AD9518
but have a different combination of outputs.
Each pair of outputs has dividers that allow both the divide ratio
and coarse delay (or phase) to be set. The range of division for
the LVPECL outputs is 1 to 32.
The AD9518-0 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9518-0 is specified for operation over the industrial
range of −40°C to +85°C.
1
AD9518 is used throughout the data sheet to refer to all the members of
the AD9518 family. However, when AD9518-0 is used, it refers to that specific
member of the AD9518 family.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.
AD9518-0
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance .................................................................... 13
Applications ....................................................................................... 1
ESD Caution................................................................................ 13
General Description ......................................................................... 1
Pin Configuration and Function Descriptions........................... 14
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ........................................... 16
Revision History ............................................................................... 3
Terminology .................................................................................... 20
Specifications..................................................................................... 4
Detailed Block Diagram ................................................................ 21
Power Supply Requirements ....................................................... 4
Theory of Operation ...................................................................... 22
PLL Characteristics ...................................................................... 4
Operational Configurations ...................................................... 22
Clock Inputs .................................................................................. 6
Digital Lock Detect (DLD) ....................................................... 30
Clock Outputs ............................................................................... 6
Clock Distribution ..................................................................... 34
Timing Characteristics ................................................................ 6
Reset Modes ................................................................................ 38
Clock Output Additive Phase Noise (Distribution Only;
VCO Divider Not Used) .............................................................. 7
Power-Down Modes .................................................................. 38
Serial Control Port ......................................................................... 40
Clock Output Absolute Phase Noise (Internal VCO Used) .... 7
Serial Control Port Pin Descriptions ....................................... 40
Clock Output Absolute Time Jitter (Clock Generation
Using Internal VCO) .................................................................... 8
General Operation of Serial Control Port ............................... 40
Clock Output Absolute Time Jitter (Clock Cleanup Using
Internal VCO) ............................................................................... 8
MSB/LSB First Transfers ........................................................... 41
The Instruction Word (16 Bits) ................................................ 41
Clock Output Absolute Time Jitter (Clock Generation
Using External VCXO) ................................................................ 8
Thermal Performance .................................................................... 44
Clock Output Additive Time Jitter (VCO Divider
Not Used)....................................................................................... 9
Control Register Map Overview .............................................. 45
Clock Output Additive Time Jitter (VCO Divider Used) ....... 9
Applications Information .............................................................. 59
Serial Control Port ..................................................................... 10
Frequency Planning Using the AD9518 .................................. 59
PD, SYNC, and RESET Pins ..................................................... 10
Using the AD9518 Outputs for ADC Clock Applications .... 59
LD, STATUS, and REFMON Pins ............................................ 11
LVPECL Clock Distribution ..................................................... 60
Power Dissipation ....................................................................... 11
Outline Dimensions ....................................................................... 61
Timing Diagrams ............................................................................ 12
Ordering Guide .......................................................................... 61
Control Registers ............................................................................ 45
Control Register Map Descriptions ......................................... 47
Absolute Maximum Ratings .......................................................... 13
Rev. C | Page 2 of 64
Data Sheet
AD9518-0
REVISION HISTORY
1/12—Rev. B to Rev. C
Change to 0x232 Description, Table 49........................................58
9/11—Rev. A to Rev. B
Changes to Applications and General Description Sections ....... 1
Change to CPRSET Pin Resistor Parameter, Table 1 .................... 4
Changes to Table 2 ............................................................................ 4
Change to Test Conditions/Comments Column of Output
Differential Voltage (VOD) Parameter, Table 4 ............................... 5
Change to Logic 1 Current and Logic 0 Current Parameters,
Table 14 .............................................................................................10
Change to Test Conditions/Comments Column of LVPECL
Channel (Divider Plus Output Driver) Parameter, Table 16 .....11
Changes to Table 19 ........................................................................14
Changes to Captions, Figure 11 and Figure 16............................17
Added Figure 26, Renumbered Sequentially ...............................19
Change to PLL External Loop Filter Section ...............................27
Changes to Reference Switchover and Prescaler Sections .........28
Changes to Comments/Conditions Column, Table 27 ..............29
Changes to Automatic/Internal Holdover Mode and
Frequency Status Monitors Sections .............................................32
Changes to VCO Calibration Section ...........................................33
Changes to Clock Distribution Section ........................................34
Change to Write Section .................................................................40
Change to Figure 47 ........................................................................42
Changes to Table 41 ........................................................................44
Changes to Register Address 0x01C, Table 42 ............................45
Changes to Register Address 0x017, Bits[1:0] and
Register Address 0x018, Bits[2:0], Table 44 .................................50
Changes to Register Address 0x01C, Bits[5:1], Table 44............53
Change to Bit 5, Register Address 0x191, Register
Address 0x194, and Register Address 0x197, Table 46...............56
Changes to LVPECL Clock Distribution Section .......................60
Updated Outline Dimensions and Changes to
Ordering Guide ...............................................................................61
1/10—Rev. 0 to Rev. A
Added 48-Lead LFCSP Package (CP-48-8) .................... Universal
Changes to Features, Applications, and General Description..... 1
Change to CPRSET Pin Resistor Parameter .................................. 4
Changes to VCP Supply Parameter................................................. 11
Changes to Table 18 ........................................................................ 13
Added Exposed Paddle Notation to Figure 4;
Changes to Table 19 ........................................................................ 14
Change to High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz Section; Change to Table 21 .......... 22
Changes to Table 23 ........................................................................ 24
Change to Configuration and Register Settings Section ........... 25
Change to Phase Frequency Detector (PFD) Section ................ 26
Changes to Charge Pump (CP), On-Chip VCO, PLL
External Loop Filter, and PLL Reference Inputs Sections ......... 27
Change to Figure 31; Added Figure 32......................................... 27
Changes to Reference Switchover and Prescaler Sections ......... 28
Changes to A and B Counters Section and Table 27 .................. 29
Change to Holdover Section .......................................................... 31
Changes to VCO Calibration Section........................................... 33
Changes to Clock Distribution Section........................................ 34
Change to Table 32; Change to Channel Frequency
Division (0, 1, and 2) Section ........................................................ 35
Change to Write Section ................................................................ 40
Change to Figure 46 ........................................................................ 42
Added Thermal Performance Section; Added Table 41 ............ 44
Changes to 0x003 Register Address .............................................. 45
Changes to Table 43 ........................................................................ 47
Changes to Table 44 ........................................................................ 48
Changes to Table 45 ........................................................................ 55
Changes to Table 46 ........................................................................ 57
Changes to Table 47 ........................................................................ 58
Changes to Table 48 ........................................................................ 59
Added Frequency Planning Using the AD9518 Section ............ 60
Changes to LVDS Clock Distribution Section ............................ 61
Changes to Figure 52 and Figure 54; Added Figure 53 .............. 61
Added Exposed Paddle Notation to Outline Dimensions;
Changes to Ordering Guide ........................................................... 62
8/07—Revision 0: Initial Version
Rev. C | Page 3 of 64
AD9518-0
Data Sheet
SPECIFICATIONS
Typical values are given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted.
Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
VS
VS_LVPECL
VCP
RSET Pin Resistor
CPRSET Pin Resistor
Min
3.135
2.375
VS
2.7
BYPASS Pin Capacitor
Typ
3.3
4.12
5.1
Max
3.465
VS
5.25
10
220
Unit
V
V
V
kΩ
kΩ
nF
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA);
actual current can be calculated by CP_lsb = 3.06/CPRSET;
connect to ground
Bypass for internal LDO regulator; necessary for LDO stability;
connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
Frequency Range
VCO Gain (KVCO)
Tuning Voltage (VT)
Min
2550
Max
Unit
Test Conditions/Comments
2950
MHz
MHz/V
V
See Figure 11
See Figure 6
VCP ≤ VS when using internal VCO; outside of this range,
the CP spurs may increase due to CP up/down mismatch
50
0.5
Frequency Pushing (Open Loop)
Phase Noise at 100 kHz Offset
Phase Noise at 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Typ
VCP −
0.5
1
−105
−123
0
Input Sensitivity
MHz/V
dBc/Hz
dBc/Hz
250
250
MHz
mV p-p
f = 2800 MHz
f = 2800 MHz
Differential mode (can accommodate single-ended input
by ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled;
be careful to match VCM (self-bias voltage)
PLL figure of merit (FOM) increases with increasing slew rate
(see Figure 10); the input sensitivity is sufficient for ac-coupled
LVPECL and LVDS signals
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
Pulse Width High/Low
Input Capacitance
1.35
1.30
4.0
4.4
1.60
1.50
4.8
5.3
20
0
V
V
kΩ
kΩ
250
250
MHz
MHz
V p-p
V
V
µA
ns
0.8
2.0
0.8
+100
−100
1.8
2
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Antibacklash Pulse Width
1.75
1.60
5.9
6.4
100
45
1.3
2.9
6.0
Self-bias voltage of REFIN 1
Self-bias voltage of REFIN1
Self-biased1
Self-biased1
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/µs
Slew rate > 50 V/µs; CMOS levels
Should not exceed VS p-p
pF
This value determines the allowable input duty cycle and is the
amount of time that a square wave is high/low
Each pin, REFIN/REFIN (REF1/REF2)
MHz
MHz
ns
ns
ns
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
Register 0x017[1:0] = 01b
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
Register 0x017[1:0] = 10b
Rev. C | Page 4 of 64
Data Sheet
Parameter
CHARGE PUMP (CP)
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
CPRSET Range
ICP High Impedance Mode Leakage
Sink-and-Source Current Matching
ICP vs. CPV
ICP vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL DIVIDER DELAYS
000
001
010
011
100
101
110
111
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In Band Is Within the LBW of the PLL)
At 500 kHz PFD Frequency
At 1 MHz PFD Frequency
At 10 MHz PFD Frequency
At 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
AD9518-0
Min
Typ
Max
4.8
0.60
2.5
2.7/10
1
2
1.5
2
mA
mA
%
kΩ
nA
%
%
%
300
600
900
200
1000
2400
3000
3000
300
Off
330
440
550
660
770
880
990
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1
2
CPV = VCP/2 V
0.5 < CPV < VCP − 0.5 V
0.5 < CPV < VCP − 0.5 V
CPV = VCP/2 V
See the VCXO/VCO Feedback Divider N—P, A, B, R section
A, B counter input frequency (prescaler input frequency
divided by P)
Register 0x019: R, Bits[5:3]; N, Bits[2:0] (see Table 44)
ps
ps
ps
ps
ps
ps
ps
ps
The PLL in-band phase noise floor is estimated by measuring
the in-band phase noise at the output of the VCO and
subtracting 20 log(N) (where N is the value of the N divider)
−165
−162
−151
−143
−220
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
3.5
7.5
3.5
ns
ns
ns
Reference slew rate > 0.25 V/ns; FOM + 10 log(fPFD) is an
approximation of the PFD/CP in-band phase noise (in the flat
region) inside the PLL loop bandwidth; when running closedloop, the phase noise, as observed at the VCO output, is increased
by 20 log(N)
Signal available at LD, STATUS, and REFMON pins
when selected by appropriate register settings
Selected by Register 0x017[1:0] and Register 0x018[4]
Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
7
15
11
ns
ns
ns
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
PLL DIGITAL LOCK DETECT WINDOW 2
Required to Lock (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
To Unlock After Lock (Hysteresis)2
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Test Conditions/Comments
CPV is CP pin voltage; VCP is charge pump power supply voltage
Programmable
With CPRSET = 5.1 kΩ
REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. C | Page 5 of 64
AD9518-0
Data Sheet
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Min
Typ
01
01
Input Sensitivity, Differential
1
Unit
2.4
1.6
GHz
GHz
mV p-p
2
V p-p
1.8
1.8
V
V
mV p-p
kΩ
pF
150
Input Level, Differential
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Max
1.3
1.3
3.9
1.57
150
4.7
2
5.7
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed)
Measured at 2.4 GHz; jitter performance is improved
with slew rates > 1 V/ns
Larger voltage swings may turn on the protection
diodes and may degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
Output Frequency, Maximum
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
Min
Typ
Max
2950
Unit
MHz
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Differential (OUT, OUT)
Using direct to output; see Figure 16 for peak-to-peak
differential amplitude
VS_LVPECL −
1.12
VS_LVPECL −
2.03
550
VS_LVPECL −
0.98
VS_LVPECL −
1.77
790
VS_LVPECL −
0.84
VS_LVPECL −
1.49
980
V
mV
This is VOH − VOL for each leg of a differential pair for
default amplitude setting with driver not toggling; the
peak-to-peak amplitude measured using a differential
probe across the differential pair with the driver toggling
is roughly 2× these values (see Figure 16 for variation
over frequency)
Min
Typ
Max
Unit
70
70
180
180
ps
ps
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V; level = 810 mV
20% to 80%, measured differentially
80% to 20%, measured differentially
835
995
1180
ps
See Figure 28
773
933
0.8
1090
ps
ps/°C
See Figure 30
5
15
ps
13
40
ps
220
ps
V
TIMING CHARACTERISTICS
Table 5.
Parameter
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL,
CLK-TO-LVPECL OUTPUT
High Frequency Clock Distribution
Configuration
Clock Distribution Configuration
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS 1
LVPECL Outputs That Share the
Same Divider
LVPECL Outputs on Different
Dividers
All LVPECL Outputs Across Multiple
Parts
1
This is the difference between any two similar delay paths while operating at the same voltage and temperature.
Rev. C | Page 6 of 64
Data Sheet
AD9518-0
CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)
Table 6.
Parameter
CLK-TO-LVPECL ADDITIVE PHASE NOISE
Min
CLK = 1 GHz, Output = 1 GHz
Divider = 1
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 100 MHz Offset
CLK = 1 GHz, Output = 200 MHz
Divider = 5
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
>10 MHz Offset
Typ
Max
−109
−118
−130
−139
−144
−146
−147
−149
Unit
Test Conditions/Comments
Distribution section only; does not include
PLL and VCO
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−120
−126
−139
−150
−155
−157
−157
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVPECL ABSOLUTE PHASE NOISE
VCO = 2.95 GHz; Output = 2.95 GHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
VCO = 2.75 GHz; Output = 2.75 GHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
VCO = 2.55 GHz; Output = 2.55 GHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
Min
Typ
Max
Unit
−47
−78
−104
−122
−140
−146
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−49
−79
−105
−123
−141
−146
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−51
−80
−106
−125
−142
−146
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. C | Page 7 of 64
Test Conditions/Comments
Internal VCO; direct to LVPECL output
AD9518-0
Data Sheet
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
Min
VCO = 2.95 GHz; LVPECL = 491.52 MHz; PLL LBW = 75 kHz
Typ
Max
148
342
212
320
184
304
221
345
210
334
VCO = 2.95 GHz; LVPECL = 122.88 MHz; PLL LBW = 75 kHz
VCO = 2.70 GHz; LVPECL = 122.88 MHz; PLL LBW = 187 kHz
VCO = 2.70 GHz; LVPECL = 61.44 MHz; PLL LBW = 187 kHz
VCO = 2.58 GHz; LVPECL = 61.44 MHz; PLL LBW = 75 kHz
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is clean,
so a wider PLL loop bandwidth is used;
reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
Min
VCO = 2.80 GHz; LVPECL = 155.52 MHz; PLL LBW = 12.8 kHz
VCO = 2.95 GHz; LVPECL = 77.76 MHz; PLL LBW = 12.8 kHz
Typ
Max
513
544
Unit
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 19.44 MHz; R = 1
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Min
Typ
Max
54
77
109
79
114
163
124
176
259
Rev. C | Page 8 of 64
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup using an external 245.76 MHz VCXO
(Toyocom TCO-2112); reference = 15.36 MHz;
R=1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Data Sheet
AD9518-0
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min
Typ
Max
Unit
CLK = 622.08 MHz; LVPECL = 622.08 MHz;
Divider = 1
CLK = 622.08 MHz; LVPECL = 155.52 MHz;
Divider = 4
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
40
fs rms
Test Conditions/Comments
Distribution section only; does not include PLL and
VCO; uses rising edge of clock signal
BW = 12 kHz to 20 MHz
80
fs rms
BW = 12 kHz to 20 MHz
215
fs rms
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
245
fs rms
Calculated from SNR of ADC method; DCC not used
for even divides
Calculated from SNR of ADC method; DCC on
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
Min
Typ
210
Max
Unit
fs rms
Rev. C | Page 9 of 64
Test Conditions/Comments
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method
AD9518-0
Data Sheet
SERIAL CONTROL PORT
Table 13.
Parameter
CS (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO (WHEN INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup and Hold, tS, tH
CS Minimum Pulse Width High, tPWH
Min
Typ
Max
2.0
0.8
3
110
2
Unit
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
V
V
µA
µA
pF
SCLK has an internal 30 kΩ pull-down resistor
2.0
0.8
110
1
2
2.0
0.8
10
20
2
2.7
0.4
25
16
16
2
1.1
8
2
3
V
V
µA
µA
pF
V
V
nA
nA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
PD, SYNC, AND RESET PINS
Table 14.
Parameter
INPUT CHARACTERISTICS
Min
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
RESET TIMING
Pulse Width Low
SYNC TIMING
Pulse Width Low
2.0
Typ
Max
0.8
1
110
2
Unit
Test Conditions/Comments
These pins each have a 30 kΩ internal pull-up
resistor
V
V
µA
µA
pF
50
ns
1.5
High speed
clock cycles
Rev. C | Page 10 of 64
High speed clock is CLK input signal
Data Sheet
AD9518-0
LD, STATUS, AND REFMON PINS
Table 15.
Parameter
OUTPUT CHARACTERISTICS
Min
Output Voltage High (VOH)
Output Voltage Low (VOL)
MAXIMUM TOGGLE RATE
2.7
Max
Unit
0.4
100
V
V
MHz
3
pF
On-chip capacitance; used to calculate RC time constant
for analog lock detect readback; use a pull-up resistor
1.02
MHz
8
kHz
Frequency above which the monitor always indicates the
presence of the reference
Frequency above which the monitor always indicates the
presence of the reference
ANALOG LOCK DETECT
Capacitance
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range
Extended Range (REF1 and REF2 Only)
LD PIN COMPARATOR
Trip Point
Hysteresis
Typ
1.6
260
Test Conditions/Comments
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs;
see Table 44, Register 0x017, Register 0x01A, and
Register 0x01B
Applies when mux is set to any divider or counter output,
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; beware that spurs may
couple to output when any of these pins are toggling
V
mV
POWER DISSIPATION
Table 16.
Parameter
POWER DISSIPATION, CHIP
Power-On Default
Typ
Max
Unit
Test Conditions/Comments
0.76
1.0
W
Full Operation
1.1
1.7
W
PD Power-Down
75
185
mW
PD Power-Down, Maximum Sleep
31
No clock; no programming; default register values;
does not include power dissipated in external resistors
PLL on; internal VCO = 2750 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs at 687.5 MHz;
does not include power dissipated in external resistors
PD pin pulled low; does not include power dissipated
in terminations
PD pin pulled low; PLL power-down, Register 0x010[1:0] =
01b; SYNC power-down, Register 0x230[2] = 1b; REF for
distribution power-down, Register 0x230[1] = 1b
PLL operating; typical closed-loop configuration
Power delta when a function is enabled/disabled
VCO divider bypassed
All references off to differential reference enabled
All references off to REF1 or REF2 enabled; differential
reference not enabled
CLK input selected to VCO selected
PLL off to PLL on, normal operation; no reference
enabled
Divider bypassed to divide-by-2 to divide-by-32
No LVPECL output on to one LVPECL output on,
independent of frequency
Second LVPECL output turned on, same channel
VCP Supply
POWER DELTAS, INDIVIDUAL FUNCTIONS
VCO Divider
REFIN (Differential)
REF1, REF2 (Single-Ended)
Min
4
mW
4.8
mW
30
20
4
mW
mW
mW
VCO
PLL
70
75
mW
mW
Channel Divider
LVPECL Channel (Divider Plus Output Driver)
30
160
mW
mW
LVPECL Driver
90
mW
Rev. C | Page 11 of 64
AD9518-0
Data Sheet
TIMING DIAGRAMS
DIFFERENTIAL
80%
tCLK
LVPECL
CLK
tRP
tFP
Figure 3. LVPECL Timing, Differential
Figure 2. CLK/CLK to Clock Output Timing, DIV = 1
Rev. C | Page 12 of 64
06429-061
tPECL
06429-060
20%
Data Sheet
AD9518-0
ABSOLUTE MAXIMUM RATINGS
Table 17.
Parameter
VS, VS_LVPECL to GND
VCP to GND
REFIN, REFIN to GND
REFIN to REFIN
RSET to GND
CPRSET to GND
CLK, CLK to GND
CLK to CLK
SCLK, SDIO, SDO, CS to GND
OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,
OUT3, OUT3,OUT4, OUT4, OUT5, OUT5
to GND
SYNC to GND
REFMON, STATUS, LD to GND
Junction Temperature 1
Storage Temperature Range
Lead Temperature (10 sec)
1
Rating
−0.3 V to +3.6 V
−0.3 V to +5.8 V
−0.3 V to VS + 0.3 V
−3.3 V to +3.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−1.2 V to +1.2 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
150°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 18.
Package Type1
48-Lead LFCSP
1
θJA
24.7
Unit
°C/W
Thermal impedance measurements were taken on a 4-layer board in still air
in accordance with EIA/JESD51-2.
ESD CAUTION
See Table 18 for θJA.
Rev. C | Page 13 of 64
AD9518-0
Data Sheet
1
37
38
39
40
41
42
44
45
46
43
36
PIN 1
INDICATOR
2
35
3
34
4
33
5
32
6
AD9518-0
31
7
TOP VIEW
(Not to Scale)
30
8
NC
VS
GND
OUT2
OUT2
VS_LVPECL
VS_LVPECL
29
OUT3
OUT3
27 GND
26 VS
25 VS
28
9
10
11
06429-003
24
23
22
21
20
19
18
17
16
15
SCLK
CS
SDO
SDIO
RESET
PD
OUT4
OUT4
VS_LVPECL
OUT5
OUT5
VS
14
12
13
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
VS
CLK
CLK
47
48
REFIN (REF1)
REFIN (REF2)
CPRSET
VS
RSET
VS
OUT0
OUT0
VS_LVPECL
OUT1
OUT1
VS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CONNECT.
2. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 4. Pin Configuration
Table 19. Pin Function Descriptions
Pin No.
1
Input/
Output
O
Pin Type
3.3 V CMOS
Mnemonic
REFMON
2
O
3.3 V CMOS
LD
3
I
Power
VCP
4
5
6
O
O
I
3.3 V CMOS
3.3 V CMOS
CP
STATUS
REF_SEL
7
I
3.3 V CMOS
SYNC
8
I
Loop filter
LF
9
10, 24, 25,
26, 35, 37,
43, 45
11
O
I
Loop filter
Power
BYPASS
VS
I
CLK
12
I
Differential
clock input
Differential
clock input
CLK
Description
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 44,
Register 0x01B.
Lock Detect (Output). This pin has multiple selectable outputs; see Table 44,
Register 0x01A.
Power Supply for Charge Pump (CP). VS ≤ VCP ≤ 5.0 V. This pin is usually 3.3 V for most
applications; but if a 5 V external VCXO is used, this pin should be 5 V.
Charge Pump (Output). Connects to external loop filter.
Status (Output). This pin has multiple selectable outputs; see Table 44, Register 0x017.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is used for manual holdover. Active low. This pin has an internal
30 kΩ pull-up resistor.
Loop Filter (Input). Connects to VCO control voltage node internally. This pin has 31 pF of
internal capacitance to ground, which may influence the loop filter design for large
loop bandwidths.
This pin is for bypassing the LDO to ground with a capacitor.
3.3 V Power Pins.
Along with CLK, this is the self-biased differential input for the clock distribution section.
This pin can be left floating if internal VCO is used.
Along with CLK, this is the self-biased differential input for the clock distribution section.
This pin can be left floating if internal VCO is used.
Rev. C | Page 14 of 64
Data Sheet
AD9518-0
Input/
Output
I
I
Pin Type
3.3 V CMOS
3.3 V CMOS
Mnemonic
SCLK
CS
15
16
17
18
19
20
21, 30, 31,
40
22
23
27, 34
28
29
32
33
36
38
39
41
42
44
O
I/O
I
I
O
O
I
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
LVPECL
LVPECL
Power
SDO
SDIO
RESET
PD
OUT4
OUT4
VS_LVPECL
Description
Serial Control Port Data Clock Signal.
Serial Control Port Chip Select, Active Low. This pin has an internal 30 kΩ pull-up
resistor.
Serial Control Port. Unidirectional serial data output.
Serial Control Port. Bidirectional serial data input/output.
Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
O
O
LVPECL
LVPECL
GND
LVPECL
LVPECL
LVPECL
LVPECL
OUT5
OUT5
GND
OUT3
OUT3
OUT2
OUT2
NC
OUT1
OUT1
OUT0
OUT0
RSET
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
Ground. See the description for EPAD.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
No Connection.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
Resistor connected here sets internal bias currents. Nominal value = 4.12 kΩ.
46
O
CPRSET
Resistor connected here sets the CP current range. Nominal value = 5.1 kΩ.
47
I
REFIN (REF2)
48
I
Along with REFIN, this is the self-biased differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF2.
Along with REFIN, this is the self-biased differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF1.
Ground. The external paddle on the bottom of the package must be connected to
ground for proper operation.
Pin No.
13
14
EPAD
O
O
O
O
O
O
O
O
O
LVPECL
LVPECL
LVPECL
LVPECL
Current set
resistor
Current set
resistor
Reference
input
Reference
input
GND
REFIN (REF1)
GND
Rev. C | Page 15 of 64
AD9518-0
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
300
5.0
3 CHANNELS—6 LVPECL
280
4.5
220
3 CHANNELS—3 LVPECL
180
160
2 CHANNELS—2 LVPECL
140
3.5
PUMP DOWN
2.5
2.0
1.5
1.0
120
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
0
06429-007
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOLTAGE ON CP PIN (V)
Figure 5. Current vs. Frequency, Direct to Output, LVPECL Outputs
06429-012
0.5
1 CHANNEL—1 LVPECL
100
Figure 8. Charge Pump Characteristics at VCP = 5.0 V
–140
PFD PHASE NOISE REFERRED TO PFD INPUT
(dBc/Hz)
65
60
KVCO (MHz/V)
PUMP UP
3.0
55
50
40
2.55
2.65
2.75
2.85
2.95
VCO FREQUENCY (GHz)
–150
–155
–160
–165
–170
0.1
06429-010
45
–145
1
10
100
PFD FREQUENCY (MHz)
Figure 6. KVCO vs. VCO Frequency
06429-013
CURRENT (mA)
240
200
4.0
CURRENT FROM CP PIN (mA)
260
Figure 9. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
–210
5.0
4.5
PLL FIGURE OF MERIT (dBc/Hz)
3.5
PUMP DOWN
PUMP UP
3.0
2.5
2.0
1.5
1.0
–214
–216
–218
–220
–222
0
0
0.5
1.0
1.5
2.0
2.5
3.0
VOLTAGE ON CP PIN (V)
Figure 7. Charge Pump Characteristics at VCP = 3.3 V
–224
0
0.5
1.0
1.5
2.0
2.5
SLEW RATE (V/ns)
Figure 10. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN
Rev. C | Page 16 of 64
06429-136
0.5
06429-011
CURRENT FROM CP PIN (mA)
–212
4.0
Data Sheet
AD9518-0
1.0
2.1
DIFFERENTIAL OUTPUT (V)
1.7
1.5
1.3
0.6
0.2
–0.2
–0.6
1.1
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
FREQUENCY (GHz)
–1.0
06429-138
0.9
2.55
0
5
10
15
20
25
TIME (ns)
Figure 11. VCO Tuning Voltage vs. Frequency
(Note that VCO calibration centers the dc tuning voltage
for the PLL setup that is active during calibration.)
06429-014
VCO TUNING VOLTAGE (V)
1.9
Figure 14. LVPECL Output (Differential) at 100 MHz
10
1.0
0
DIFFERENTIAL OUTPUT (V)
RELATIVE POWER (dB)
–10
–20
–30
–40
–50
–60
–70
–80
0.6
0.2
–0.2
–0.6
–90
CENTER 122.88MHz
5MHz/DIV
SPAN 50MHz
–1.0
0
1
2
TIME (ns)
Figure 12. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;
LBW = 190 kHz; ICP = 4.2 mA; fVCO = 2.7 GHz
06429-015
–110
06429-137
–100
Figure 15. LVPECL Output (Differential) at 1600 MHz
1600
10
0
DIFFERENTIAL SWING (mV p-p)
RELATIVE POWER (dB)
–10
–20
–30
–40
–50
–60
–70
–80
–90
1400
1200
1000
CENTER 122.8803006MHz
100kHz/DIV
SPAN 1MHz
800
0
1
2
FREQUENCY (GHz)
Figure 13. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz;
LBW = 190 kHz; ICP = 4.2 mA; fVCO = 2.7 GHz
Rev. C | Page 17 of 64
Figure 16. LVPECL Differential Swing vs. Frequency
Using a Differential Probe Across the Output Pair
3
06429-020
–110
06429-135
–100
AD9518-0
Data Sheet
–70
–120
–80
–125
PHASE NOISE (dBc/Hz)
–100
–110
–120
–130
–140
–135
–140
–145
–150
–155
–150
100k
1M
10M
100M
FREQUENCY (Hz)
–160
10
06429-023
–160
10k
–130
Figure 17. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2950 MHz
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
06429-026
PHASE NOISE (dBc/Hz)
–90
Figure 20. Phase Noise (Additive) LVPECL at 245.76 MHz, Divide-by-1
–110
–80
–90
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–120
–100
–110
–120
–130
–130
–140
–150
100k
1M
10M
100M
FREQUENCY (Hz)
–160
10
06429-024
–150
10k
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
06429-027
–140
Figure 21. Phase Noise (Additive) LVPECL at 200 MHz, Divide-by-5
Figure 18. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2750 MHz
–100
–80
–90
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–110
–100
–110
–120
–130
–120
–130
–140
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 19. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2550 MHz
Rev. C | Page 18 of 64
–150
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 22. Phase Noise (Additive) LVPECL at 1600 MHz, Divide-by-1
06429-128
–150
10k
06429-025
–140
AD9518-0
–120
–130
–130
–140
–150
–160
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 23. Phase Noise (Absolute) Clock Generation; Internal VCO at 2.7 GHz;
PFD = 15.36 MHz; LBW = 110 kHz; LVPECL Output = 122.88 MHz
–140
–150
–160
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
06429-140
PHASE NOISE (dBc/Hz)
–120
06429-141
PHASE NOISE (dBc/Hz)
Data Sheet
Figure 25. Phase Noise (Absolute); External VCXO (Toyocom TCO-2112) at
245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
1000
–90
OC-48 OBJECTIVE MASK
AD9518
–110
–120
–130
–140
–160
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
06429-139
–150
Figure 24. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 2.8 GHz;
PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz
Rev. C | Page 19 of 64
100
fOBJ
10
1
NOTE: 375UI MAX AT 10Hz OFFSET IS THE
MAXIMUM JITTER THAT CAN BE
GENERATED BY THE TEST EQUIPMENT.
FAILURE POINT IS GREATER THAN 375UI.
0.1
0.01
0.1
1
10
100
JITTER FREQUENCY (kHz)
Figure 26. GR-253 Jitter Tolerance Plot
1000
06429-148
INPUT JITTER AMPLITUDE (UI p-p)
PHASE NOISE (dBc/Hz)
–100
AD9518-0
Data Sheet
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as
a series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of
ADCs, DACs, and RF mixers. It lowers the achievable dynamic
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings
varies. In a square wave, the time jitter is a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or 1 sigma
of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that can be
attributed to the device or subsystem being measured. The phase
noise of any external oscillators or clock sources is subtracted.
This makes it possible to predict the degree to which the device
impacts the total system phase noise when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own phase noise to the total. In many cases, the
phase noise of one element dominates the system phase noise.
When there are multiple contributors to phase noise, the total
is the square root of the sum of squares of the individual
contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that can be
attributed to the device or subsystem being measured. The time
jitter of any external oscillators or clock sources is subtracted. This
makes it possible to predict the degree to which the device impacts
the total system time jitter when used in conjunction with the
various oscillators and clock sources, each of which contributes
its own time jitter to the total. In many cases, the time jitter of
the external oscillators and clock sources dominates the system
time jitter.
Rev. C | Page 20 of 64
Data Sheet
AD9518-0
DETAILED BLOCK DIAGRAM
REF_ SEL
VS
GND
RSET
REFMON
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
R
DIVIDER
STATUS
REFIN (REF1)
PLL
REFERENCE
LOCK
DETECT
REF2
PROGRAMMABLE
R DELAY
VCO STATUS
REFIN (REF2)
BYPASS
CPRSET VCP
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
0
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4
DIVIDE BY
1 TO 32
OUT4
LVPECL
OUT5
OUT5
AD9518-0
Figure 27. Detailed Block Diagram
Rev. C | Page 21 of 64
06429-002
SCLK
SDIO
SDO
CS
OUT2
LVPECL
AD9518-0
Data Sheet
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
Table 20. Default Settings of Some PLL Registers
The AD9518 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 42 and Table 43 through Table 49). Each section
or function must be individually programmed by setting the
appropriate bits in the corresponding control register or registers.
Register
0x010[1:0] = 01b
0x1E0[2:0] = 010b
0x1E1[0] = 0b
0x1E1[1] = 0b
High Frequency Clock Distribution—CLK or External
VCO > 1600 MHz
When using the internal PLL with an external VCO, the PLL
must be turned on.
The AD9518 power-up default configuration has the PLL
powered off and the routing of the input set so that the CLK/CLK
input is connected to the distribution section through the VCO
divider (divide-by-2/divide-by-3/divide-by-4/divide-by-5/divideby-6). This is a distribution-only mode that allows for an external
input up to 2.4 GHz (see Table 3). The maximum frequency that
can be applied to the channel dividers is 1600 MHz; therefore,
higher input frequencies must be divided down before reaching
the channel dividers. This input routing can also be used for lower
input frequencies, but the minimum divide is 2 before the channel
dividers.
When the PLL is enabled, this routing also allows the use of the
PLL with an external VCO or VCXO with a frequency of less than
2400 MHz. In this configuration, the internal VCO is not used
and is powered off. The external VCO/VCXO feeds directly into
the prescaler.
The register settings shown in Table 20 are the default values
of these registers at power-up or after a reset operation. If the
contents of the registers are altered by prior programming after
power-up or reset, these registers can also be set intentionally to
these values.
Function
PLL asynchronous power-down (PLL off ).
Set VCO divider = 4.
Use the VCO divider.
CLK selected as the source.
Table 21. Settings When Using an External VCO
Register
0x010[1:0] = 00b
0x010 to 0x01D
0x1E1[1] = 0b
Function
PLL normal operation (PLL on).
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and ICP,
according to the intended loop configuration.
CLK selected as the source.
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 22. Setting the PFD Polarity
Register
0x010[7] = 0b
0x010[7] = 1b
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
Rev. C | Page 22 of 64
Function
PFD polarity positive (higher control voltage
produces higher frequency).
PFD polarity negative (higher control
voltage produces lower frequency).
Data Sheet
AD9518-0
REF_ SEL
VS
GND
RSET
REFMON
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
R
DIVIDER
STATUS
REFIN (REF1)
PLL
REFERENCE
LOCK
DETECT
REF2
PROGRAMMABLE
R DELAY
VCO STATUS
REFIN (REF2)
BYPASS
CPRSET VCP
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
0
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4
DIVIDE BY
1 TO 32
OUT4
LVPECL
OUT5
AD9518-1
OUT5
Figure 28. High Frequency Clock Distribution or External VCO > 1600 MHz
Rev. C | Page 23 of 64
06430-029
SCLK
SDIO
SDO
CS
OUT2
LVPECL
AD9518-0
Data Sheet
Internal VCO and Clock Distribution
Table 23. Settings When Using an Internal VCO
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the channel
dividers does not exceed their specified maximum frequency of
1600 MHz (see Table 3). The internal PLL uses an external loop
filter to set the loop bandwidth. The external loop filter is also
crucial to the loop stability.
Register
0x010[1:0] = 00b
0x010 to 0x01D
When using the internal VCO, it is necessary to calibrate the
VCO (Register 0x018[0]) to ensure optimal performance.
For internal VCO and clock distribution applications, use the
register settings that are shown in Table 23.
0x018[0] = 0b,
0x232[0] = 1b
0x1E0[2:0]
0x1E1[0] = 0b
0x1E1[1] = 1b
0x018[0] = 1b,
0x232[0] = 1b
REF_ SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
R
DIVIDER
STATUS
REFIN (REF1)
PLL
REFERENCE
LOCK
DETECT
REF2
PROGRAMMABLE
R DELAY
VCO STATUS
REFIN (REF2)
BYPASS
Function
PLL normal operation (PLL on).
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and ICP
according to the intended loop configuration.
Reset VCO calibration. This process is not
required the first time after power-up, but it
must be performed subsequently.
Set VCO divider to divide-by-2, divide-by-3,
divide-by-4, divide-by-5, or divide-by-6.
Use VCO divider as the source for the
distribution section.
Select VCO as the source.
Initiate VCO calibration.
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
0
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4
DIVIDE BY
1 TO 32
OUT4
LVPECL
OUT5
OUT5
AD9518-1
Figure 29. Internal VCO and Clock Distribution
Rev. C | Page 24 of 64
06430-030
SCLK
SDIO
SDO
CS
OUT2
LVPECL
Data Sheet
AD9518-0
REF_ SEL
VS
GND
RSET
REFMON
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
R
DIVIDER
STATUS
REFIN (REF1)
PLL
REFERENCE
LOCK
DETECT
REF2
PROGRAMMABLE
R DELAY
VCO STATUS
REFIN (REF2)
BYPASS
CPRSET VCP
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
0
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
SCLK
SDIO
SDO
CS
OUT2
LVPECL
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4
DIVIDE BY
1 TO 32
OUT4
LVPECL
OUT5
OUT5
06430-028
AD9518-1
Figure 30. Clock Distribution or External VCO < 1600 MHz
Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is less than 1600 MHz, a configuration that bypasses
the VCO divider can be used. This configuration differs from the
High Frequency Clock Distribution—CLK or External VCO >
1600 MHz section only in that the VCO divider (divide-by-2/
divide-by-3/divide-by-4/divide-by-5/divide-by-6) is bypassed.
This limits the frequency of the clock source to <1600 MHz (due
to the maximum input frequency allowed at the channel dividers).
Table 25. Settings for Using Internal PLL with External VCO <
1600 MHz
Register
0x1E1[0] = 1b
0x010[1:0] = 00b
Function
Bypass the VCO divider as source for
distribution section
PLL normal operation (PLL on), along with
other appropriate PLL settings in Register 0x010
to Register 0x01D
For clock distribution applications where the external clock is
less than 1600 MHz, use the register settings shown in Table 24.
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the
VCO/VCXO. This loop filter determines the loop bandwidth
and stability of the PLL. Make sure to select the proper PFD
polarity for the VCO/VCXO being used.
Table 24. Settings for Clock Distribution < 1600 MHz
Table 26. Setting the PFD Polarity
Register
0x010[1:0] = 01b
0x1E1[0] = 1b
Register
0x010[7] = 0b
Configuration and Register Settings
0x1E1[1] = 0b
Function
PLL asynchronous power-down (PLL off )
Bypass the VCO divider as source for
distribution section
CLK selected as the source
When using the internal PLL with an external VCO of <1600 MHz,
the PLL must be turned on.
0x010[7] = 1b
Function
PFD polarity positive (higher control voltage
produces higher frequency)
PFD polarity negative (higher control voltage
produces lower frequency)
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
Rev. C | Page 25 of 64
AD9518-0
Data Sheet
Phase-Locked Loop (PLL)
REF_SEL
VS
GND
RSET
REFMON
CPRSET
VCP
DIST
REF
REFERENCE
SWITCHOVER
LD
LOCK
DETECT
REF1
STATUS
REF2
PROGRAMMABLE
R DELAY
R DIVIDER
STATUS
PLL
REF
HOLD
REFIN (REF1)
REFIN (REF2)
BYPASS
N DIVIDER
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE PUMP
CP
VCO STATUS
LF
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
0
1
CLK
1
06429-064
VCO
0
Figure 31. PLL Functional Blocks
The AD9518 includes an on-chip PLL with an on-chip VCO.
The PLL blocks can be used either with the on-chip VCO to
create a complete phase-locked loop, or with an external VCO
or VCXO. The PLL requires an external loop filter, which
usually consists of a small number of capacitors and resistors.
The configuration and components of the loop filter help to
establish the loop bandwidth and stability of the operating PLL.
managed through programmable register settings (see Table 42
and Table 44) and by the design of the external loop filter.
Successful PLL operation and satisfactory PLL loop performance
are highly dependent upon proper configuration of the PLL
settings. The design of the external loop filter is crucial to the
proper operation of the PLL. A thorough knowledge of PLL
theory and design is helpful.
The AD9518 PLL is useful for generating clock frequencies
from a supplied reference frequency. This includes conversion
of reference frequencies to much higher frequencies for subsequent
division and distribution. In addition, the PLL can be exploited
to clean up jitter and phase noise on a noisy reference. The exact
choices of PLL parameters and loop dynamics are very application
specific. The flexibility and depth of the AD9518 PLL allow the
part to be tailored to function in many different applications
and signal environments.
ADIsimCLK™ (V1.2 or later) is a free program that can help
with the design and exploration of the capabilities and features
of the AD9518, including the design of the PLL loop filter. It is
available at www.analog.com/clocks.
Configuration of the PLL
The AD9518 allows flexible configuration of the PLL,
accommodating various reference frequencies, PFD comparison
frequencies, VCO frequencies, internal or external VCO/VCXO,
and loop dynamics. This is accomplished by the various settings
that include the R divider, the N divider, the PFD polarity (only
applicable to external VCO/VCXO), the antibacklash pulse width,
the charge pump current, the selection of internal VCO or
external VCO/VCXO, and the loop bandwidth. These are
Phase Frequency Detector (PFD)
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. The
antibacklash pulse width is set by Register 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD, which in turn determines the correct
antibacklash pulse setting. The antibacklash pulse setting is
specified in the phase/frequency detector parameter of Table 2.
Rev. C | Page 26 of 64
Data Sheet
AD9518-0
Charge Pump (CP)
AD9518-0
VCO
LF
31pF
R2
CP
R1
CHARGE
PUMP
BYPASS
C1
C2
C3
06429-065
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs, and
tells the CP to pump up or pump down to charge or discharge the
integrating node (part of the loop filter). The integrated and
filtered CP current is transformed into a voltage that drives the
tuning node of the internal VCO through the LF pin (or the tuning
pin of an external VCO) to move the VCO frequency up or down.
The CP can be set (Register 0x010[6:4]) for high impedance
(allows holdover operation), for normal operation (attempts to
lock the PLL loop), for pump up, or for pump down (test modes).
The CP current is programmable in eight steps from (nominally)
600 µA to 4.8 mA. The exact value of the CP current LSB is set
by the CPRSET resistor, which is nominally 5.1 kΩ. If the value
of the resistor connected to the CP_RSET pin is doubled, the
resulting charge pump current range becomes 300 µA to 2.4 mA.
CBP = 220nF
Figure 32. Example of External Loop Filter for a PLL Using the Internal VCO
When using an external VCO, the external loop filter should be
referenced to ground. See Figure 33 for an example of an external
loop filter for a PLL using an external VCO. For more information
on suggested loop filters, see the UG-075 User Guide.
AD9518-0
EXTERNAL
VCO/VCXO
CLK/CLK
On-Chip VCO
The on-chip VCO is powered by an on-chip, low dropout (LDO),
linear voltage regulator. The LDO provides some isolation of
the VCO from variations in the power supply voltage level. The
BYPASS pin should be connected to ground by a 220 nF
capacitor to ensure stability. This LDO employs the same
technology used in the anyCAP® line of regulators from Analog
Devices, Inc., making it insensitive to the type of capacitor used.
Driving an external load from the BYPASS pin is not supported.
Note that the reference input signal must be present and the
VCO divider must not be static during VCO calibration.
PLL External Loop Filter
When using the internal VCO, the external loop filter should
be referenced to the BYPASS pin for optimal noise and spurious
performance. An example of an external loop filter for a PLL
that uses the internal VCO is shown in Figure 32. The thirdorder design that is shown in Figure 32 usually offers the best
performance. A loop filter must be calculated for each desired
PLL configuration. The values of the components depend upon the
VCO frequency, the KVCO, the PFD frequency, the CP current, the
desired loop bandwidth, and the desired phase margin. The loop
filter affects the phase noise, loop settling time, and loop stability.
A basic knowledge of PLL theory is helpful for understanding
loop filter design. ADIsimCLK can help with the calculation
of a loop filter according to the application requirements.
R2
CP
CHARGE
PUMP
R1
C1
C2
C3
06429-265
The AD9518 includes an on-chip VCO that covers the frequency
range shown in Table 2. The calibration procedure ensures that
the VCO operating voltage is centered for the desired VCO
frequency. The VCO must be calibrated when the VCO loop is
first set up, as well as any time the nominal VCO frequency
changes. However, once the VCO is calibrated, the VCO has
sufficient operating range to stay locked over temperature and
voltage extremes without needing additional calibration. See the
VCO Calibration section for more information.
Figure 33. Example of External Loop Filter for a PLL Using an External VCO
PLL Reference Inputs
The AD9518 features a flexible PLL reference input circuit that
allows either a fully differential input or two separate single-ended
inputs. The input frequency range for the reference inputs is
specified in Table 2. Both the differential and the single-ended
inputs are self-biased, allowing for easy ac coupling of input signals.
The differential input and the single-ended inputs share the two
pins, REFIN and REFIN (REF1 and REF2, respectively). The
desired reference input type is selected and controlled by
Register 0x01C (see Table 42 and Table 44).
When the differential reference input is selected, the self-bias level
of the two sides is offset slightly (~100 mV, see Table 2) to prevent
chattering of the input buffer when the reference is slow or missing.
This increases the voltage swing that is required of the driver and
overcomes the offset. The differential reference input can be
driven by either ac-coupled LVDS or ac-coupled LVPECL signals.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave.
Each single-ended input can be independently powered down
when not needed to increase isolation and reduce power. Either
a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential reference input is powered down whenever the
PLL is powered down, or when the differential reference input
is not selected. The single-ended buffers power down when the
PLL is powered down and when their individual power down
registers are set. When the differential mode is selected, the
single-ended inputs are powered down.
Rev. C | Page 27 of 64
AD9518-0
Data Sheet
In differential mode, the reference input pins are internally selfbiased so that they can be ac-coupled via capacitors. It is possible
to dc couple to these inputs. If the differential REFIN is driven
by a single-ended signal, the unused side (REFIN) should be
decoupled via a suitable capacitor to a quiet ground. Figure 34
shows the equivalent circuit of REFIN.
VS
Automatic revertive switchover relies on the REFMON pin to
indicate when REF1 disappears. By programming Register 0x01B =
0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed
to be high when REF1 is invalid, which commands the switch to
REF2. When REF1 is valid again, the REFMON pin goes low, and
the part again locks to REF1. It is also possible to use the STATUS
pin for this function, and REF2 can be used as the preferred
reference.
A switchover deglitch feature ensures that the PLL does not
receive rising edges that are far out of alignment with the newly
selected reference.
85kΩ
REF1
Automatic nonrevertive switching is not supported.
Reference Divider R
VS
10kΩ
The reference inputs are routed to the reference divider, R.
R (a 14-bit counter) can be set to any value from 0 to 16,383
by writing to Register 0x011 and Register 0x012. (Both R = 0 and
R = 1 give divide-by-1.) The output of the R divider goes to one
of the PFD inputs to be compared with the VCO frequency
divided by the N divider. The frequency applied to the PFD
must not exceed the maximum allowable frequency, which
depends on the antibacklash pulse setting (see Table 2).
12kΩ
REFIN
150Ω
REFIN
150Ω
10kΩ
10kΩ
VS
REF2
The R counter has its own reset. The R counter can be reset
using the shared reset bit of the R, A, and B counters. It can
also be reset by a SYNC operation.
06429-066
85kΩ
VCXO/VCO Feedback Divider N—P, A, B, R
The N divider is a combination of a prescaler (P) and two counters,
A and B. The total divider value is
Figure 34. REFIN Equivalent Circuit
Reference Switchover
The AD9518 supports dual single-ended CMOS inputs, as well
as a single differential reference input. In the dual single-ended
reference mode, the AD9518 supports automatic and manual
PLL reference clock switching between REF1 (on Pin REFIN)
and REF2 (on Pin REFIN). This feature supports networking
and other applications that require smooth switching of redundant
references. When used in conjunction with the automatic holdover
function, the AD9518 can achieve a worst-case reference input
switchover with an output frequency disturbance as low as 10 ppm.
When using reference switchover, the single-ended reference
inputs should be dc-coupled CMOS levels and never be allowed
to go to high impedance. If these inputs are allowed to go to high
impedance, noise may cause the buffer to chatter, causing
a false detection of the presence of a reference.
Reference switchover can be performed manually or automatically. Manual switchover is performed either through
Register 0x01C or by using the REF_SEL pin. Manual switchover
requires the presence of a clock on the reference input that is
being switched to, or that the deglitching feature be disabled
(Register 0x01C[7]). The reference switching logic fails if this
condition is not met, and the PLL does not reacquire.
N = (P × B) + A
where the value of P can be 2, 4, 8, 16, or 32.
Prescaler
The prescaler of the AD9518 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3,
4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes
of operation are given in Table 44, Register 0x016[2:0]. Not all
modes are available at all frequencies (see Table 2).
When operating the AD9518 in dual modulus mode (P//P + 1),
the equation used to relate input reference frequency to VCO
output frequency is
fVCO = (fREF/R) × (P × B + A) = fREF × N/R
However, when operating the prescaler in an FD mode of 1, 2,
or 3, the A counter is not used (A = 0) and the equation
simplifies to
fVCO = (fREF/R) × (P × B) = fREF × N/R
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,
in which case the previous equation also applies.
Rev. C | Page 28 of 64
Data Sheet
AD9518-0
By using combinations of the DM and FD modes, the AD9518
can achieve values of N all the way down to N = 1 and up to
N = 262,175. Table 27 shows how a 10 MHz reference input
can be locked to any integer multiple of N.
Note that the same value of N can be derived in different ways, as
illustrated by the case of N = 12. The user can choose a fixed divide
mode of P = 2 with B = 6, use the dual modulus mode of 2/3 with
A = 0, B = 6, or use the dual modulus mode of 4/5 with A = 0,
B = 3.
The maximum frequency into the prescaler in 2/3 dual-modulus
mode is limited to 200 MHz. There are only two cases where
this frequency limitation limits the flexibility of that N divider:
N = 7 and N = 11. In these two cases, the maximum frequency
into the prescaler is 300 MHz and is achieved by using the P = 1
FD mode. In all other cases, the user can achieve the desired N
divider value by using the other prescaler modes.
A and B Counters
The B counter must be ≥3 or bypassed, and, unlike the R counter,
A = 0 is actually zero.
When the prescaler is in dual modulus mode, the A counter
must be less than the B counter.
The maximum input frequency to the A/B counter is reflected
in the maximum prescaler output frequency (~300 MHz) that is
specified in Table 2. This is the prescaler input frequency (VCO or
CLK) divided by P. For example, a dual modulus mode of P = 8/9
is not allowed if the VCO frequency is greater than 2400 MHz
because the frequency going to the A/B counter is too high.
When the AD9518 B counter is bypassed (B = 1), the A counter
should be set to 0, and the overall resulting divide is equal to the
prescaler setting, P. The possible divide ratios in this mode are
1, 2, 3, 4, 8, 16, and 32. This mode is useful only when an external
VCO/VCXO is used because the frequency range of the internal
VCO requires an overall feedback divider greater than 32.
Although manual reset is not normally required, the A/B counters
have their own reset bit. Alternatively, the A and B counters can be
reset using the shared reset bit of the R, A, and B counters. Note
that these reset bits are not self-clearing.
R, A, and B Counters—SYNC Pin Reset
The R, A, and B counters can also be reset simultaneously through
the SYNC pin. This function is controlled by Register 0x019[7:6]
(see Table 44). The SYNC pin reset is disabled by default.
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See Register 0x019 in Table 44.
Table 27. Using a 10 MHz Reference Input to Generate Different VCO Frequencies
fREF
(MHz)
10
10
10
10
10
10
10
10
R
1
1
1
1
1
1
1
1
P
1
2
1
1
1
2
2
2
A
X
X
X
X
X
X
0
1
B
1
1
3
4
5
3
3
3
N
1
2
3
4
5
6
6
7
fVCO
(MHz)
10
20
30
40
50
60
60
70
Mode
FD
FD
FD
FD
FD
FD
DM
DM
10
10
10
10
10
10
10
10
1
1
1
1
1
10
1
1
2
2
8
8
16
32
8
16
2
1
6
7
7
6
0
14
3
4
18
18
9
47
25
16
8
9
150
151
151
1510
200
270
80
90
1500
1510
1510
1510
2000
2700
DM
DM
DM
DM
DM
DM
DM
DM
10
10
32
22
84
2710
2710
DM
Comments/Conditions
P = 1, B = 1 (A and B counters are bypassed).
P = 2, B = 1 (A and B counters are bypassed).
A counter is bypassed.
A counter is bypassed.
A counter is bypassed.
A counter is bypassed.
Maximum frequency into prescaler in P = 2/3 mode is 200 MHz.
If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz
to 300 MHz, use P = 1, and N = 7 or 11, respectively.
P = 8 is not allowed (2700 ÷ 8 > 300 MHz).
P = 32 is not allowed (A > B is not allowed).
P = 32, A = 22, B = 84.
P = 16 is also permitted.
Rev. C | Page 29 of 64
AD9518-0
Data Sheet
By selecting the proper output through the mux on each pin,
the DLD function can be made available at the LD, STATUS,
and REFMON pins. The DLD circuit indicates a lock when the
time difference of the rising edges at the PFD inputs is less than
a specified value (the lock threshold). The loss of a lock is
indicated when the time difference exceeds a specified value
(the unlock threshold). Note that the unlock threshold is wider
than the lock threshold, which allows some phase error in
excess of the lock window to occur without chattering on the
lock indicator.
The lock detect window timing depends on three settings:
the digital lock detect window bit (Register 0x018[4]), the
antibacklash pulse width setting (Register 0x017[1:0], see Table 2),
and the lock detect counter (Register 0x018[6:5]). A lock is not
indicated until there is a programmable number of consecutive
PFD cycles with a time difference that is less than the lock detect
threshold. The lock detect circuit continues to indicate a lock
until a time difference greater than the unlock threshold occurs
on a single subsequent cycle. For the lock detect to work properly,
the period of the PFD frequency must be greater than the unlock
threshold. The number of consecutive PFD cycles required for
lock is programmable (Register 0x018[6:5]).
This function is set when it is selected as the output from the
LD pin control (Register 0x01A[5:0]). The current source lock
detect provides a current of 110 µA when DLD is true, and it
shorts to ground when DLD is false. If a capacitor is connected
to the LD pin, it charges at a rate that is determined by the current
source during the DLD true time but is discharged nearly instantly
when DLD is false. By monitoring the voltage at the LD pin (top
of the capacitor), it is possible to get a logic high level only after
the DLD has been true for a sufficiently long time. Any momentary
DLD false resets the charging. By selecting a properly sized
capacitor, it is possible to delay a lock detect indication until
the PLL is stably locked and the lock detect does not chatter.
The voltage on the capacitor can be sensed by an external
comparator connected to the LD pin. However, there is an
internal LD pin comparator that can be read at the REFMON
pin control (Register 0x01B[4:0]) or the STATUS pin control
(Register 0x017[7:2]) as an active high signal. It is also available
as an active low signal (REFMON, Register 0x01B[4:0] and
STATUS, Register 0x017[7:2]). The internal LD pin comparator
trip point and hysteresis are listed in Table 15.
AD9518-0
110µA
Analog Lock Detect (ALD)
DLD
The AD9518 provides an ALD function that can be selected for
use at the LD pin. There are two versions of ALD, as follows:
•
N-channel open-drain lock detect. This signal requires a
pull-up resistor to the positive supply, VS. The output is
normally high with short, low-going pulses. Lock is indicated
by the minimum duty cycle of the low-going pulses.
P-channel open-drain lock detect. This signal requires a
pull-down resistor to GND. The output is normally low
with short, high-going pulses. Lock is indicated by the
minimum duty cycle of the high-going pulses.
The analog lock detect function requires an R-C filter to
provide a logic level indicating lock/unlock.
C
LD PIN
COMPARATOR
Figure 36. Current Source Digital Lock Detect
External VCXO/VCO Clock Input (CLK/CLK)
CLK is a differential input that can be used as an input to drive
the AD9518 clock distribution section. This input can receive
up to 2.4 GHz. The pins are internally self-biased, and the input
signal should be ac-coupled via capacitors.
CLOCK INPUT
STAGE
VS
VS = 3.3V
AD9518-0
R2
LD
CLK
VOUT
CLK
C
2.5kΩ
06429-067
ALD
R1
REFMON
OR
STATUS
2.5kΩ
5kΩ
5kΩ
Figure 35. Example of Analog Lock Detect Filter
Using an N-Channel Open-Drain Driver
06429-032
•
VOUT
LD
06429-068
DIGITAL LOCK DETECT (DLD)
Figure 37. CLK Equivalent Input Circuit
Current Source Digital Lock Detect (DLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is made possible by using
the current source lock detect function.
The CLK/CLK input can be used either as a distribution-only
input (with the PLL off), or as a feedback input for an external
VCO/VCXO using the internal PLL when the internal VCO is
not used. The CLK/CLK input can be used for frequencies up
to 2.4 GHz.
Rev. C | Page 30 of 64
Data Sheet
AD9518-0
Holdover
Automatic/Internal Holdover Mode
The AD9518 PLL has a holdover function, which is implemented
by putting the charge pump into a state of high impedance. This
is useful when the PLL reference clock is lost. Holdover mode
allows the VCO to maintain a relatively constant frequency
even though there is no reference clock. Without this function,
the charge pump is placed into a constant pump-up or pumpdown state, resulting in a massive VCO frequency shift. Because
the charge pump is placed in a high impedance state, any
leakage that occurs at the charge pump output or the VCO
tuning node causes a drift of the VCO frequency. This can be
mitigated by using a loop filter that contains a large capacitive
component because this drift is limited by the current leakage
induced slew rate (ILEAK/C) of the VCO control voltage. For
most applications, the frequency accuracy is sufficient for 3 sec
to 5 sec.
When enabled, this function automatically puts the charge pump
into a high impedance state when the loop loses lock. The
assumption is that the only reason the loop loses lock is due to
the PLL losing the reference clock; therefore, the holdover function
puts the charge pump into a high impedance state to maintain
the VCO frequency as close as possible to the original frequency
before the reference clock disappears. See Figure 38 for a flow chart
of the automatic/internal holdover function operation.
PLL ENABLED
DLD == LOW
Both a manual holdover, using the SYNC pin, and an automatic
holdover mode are provided. To use either function, the
holdover function must be enabled (Register 0x01D[0] and
Register 0x01D[2]).
YES
ANALOG LOCK DETECT PIN INDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
(0x01D[3] = 1: USE LD PIN VOLTAGE
WITH HOLDOVER.
0x01D[3] = 0: IGNORE LD PIN VOLTAGE,
TREAT LD PIN AS ALWAYS HIGH.)
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
YES
Manual Holdover Mode
A manual holdover mode can be enabled that allows the user to
place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state, take the SYNC pin high. The charge pump then leaves
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state as long as there is
no reference clock present.
NO
CHARGE PUMP IS MADE
HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
HIGH IMPEDANCE
CHARGE PUMP
YES
NO
CHARGE PUMP REMAINS HIGH
IMPEDANCE UNTIL THE REFERENCE
HAS RETURNED.
REFERENCE
EDGE AT PFD?
YES
YES
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN
NOW RESETTLE.
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
The B-counter (in the N divider) is reset synchronously with
the charge pump leaving the high impedance state on the
reference path PFD event. This helps align the edges out of the
R and N dividers for faster settling of the PLL. Because the
prescaler is not reset, this feature works best when the B and R
numbers are close because this results in a smaller phase
difference for the loop to settle out.
When using this mode, set the channel dividers to ignore the
SYNC pin (at least after an initial SYNC event). If the dividers
are not set to ignore the SYNC pin, the distribution outputs turn
off each time SYNC is taken low to put the part into holdover.
Rev. C | Page 31 of 64
YES
NO
DLD == HIGH
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF
THE DLD DELAY COUNTER) WITH THE
REFERENCE AND FEEDBACK CLOCKS
INSIDE THE LOCK WINDOW AT THE PFD.
THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE
AND LOCK BEFORE THE HOLDOVER
FUNCTION CAN BE RETRIGGERED.
Figure 38. Flow Chart of Automatic/Internal Holdover Mode
06429-069
Note that the VCO cannot be calibrated with the holdover
enabled because the holdover resets the N divider during
calibration, which prevents proper calibration. Disable holdover
before issuing a VCO calibration.
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
NO
AD9518-0
Data Sheet
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD mode. It is possible to disable
the LD comparator (Register 0x01D[3]), which causes the holdover
function to always sense LD as high. If DLD is used, it is possible
for the DLD signal to chatter some while the PLL is reacquiring
lock. The holdover function may retrigger, thereby preventing
the holdover mode from ever terminating. Use of the current
source lock detect mode is recommended to avoid this situation
(see the Current Source Digital Lock Detect section).
Once in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N divider)
is reset synchronously with the charge pump leaving the high
impedance state on the reference path PFD event. This helps to
align the edges out of the R and N dividers for faster settling of
the PLL and to reduce frequency errors during settling. Because
the prescaler is not reset, this feature works best when the B and
R numbers are close because this results in a smaller phase
difference for the loop to settle out.
After leaving holdover, the loop then reacquires lock and the
LD pin must charge (if Register 0x01D[3] = 1) before it can
re-enter holdover (CP high impedance).
The holdover function always responds to the state of the
currently selected reference (Register 0x01C). If the loop loses
lock during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
The following registers affect automatic/internal holdover:
•
•
•
Register 0x018[6:5], lock detect counter. These bits change
the number of consecutive PFD cycles with edges inside the
lock detect window that are required for the DLD indicator
to indicate lock. This impacts the time required before the
LD pin can begin to charge, as well as the delay from the end
of a holdover event until the holdover function can be
re-engaged.
Register 0x018[3], disable digital lock detect. This bit must be
set to 0b to enable the DLD circuit. Automatic/internal holdover does not operate correctly without the DLD function
enabled.
Register 0x01A[5:0], lock detect pin output select. Set these
bits to 000100b for the current source lock detect mode
if using the LD pin comparator. Load the LD pin with
a capacitor of an appropriate value.
•
•
•
Register 0x01D[3], enable LD pin comparator. 1 = enable;
0 = disable. When disabled, the holdover function always
senses the LD pin as high.
Register 0x01D[1], enable external holdover control.
Register 0x01D[0] and Register 0x01D[2], enable holdover
function. If holdover is disabled, both external and
automatic/internal holdover are disabled.
For example, to use automatic holdover with the following:
•
•
•
Automatic reference switchover, prefer REF1
Digital lock detect: five PFD cycles, high range window
Automatic holdover using the LD pin comparator
Set the following registers (in addition to the normal PLL registers):
•
•
•
•
•
•
•
•
•
•
•
Register 0x018[6:5] = 00b; lock detect counter = five cycles.
Register 0x018[4] = 0b; lock detect window = high range.
Register 0x018[3] = 0b; DLD normal operation.
Register 0x01A[5:0] = 000100b; current source lock detect
mode.
Register 0x01B[7:0] = 0xF7; set REFMON pin to status of
REF1 (active low).
Register 0x01C[2:1] = 11b; enable REF1 and REF2 input
buffers.
Register 0x01D[3] = 1b; enable LD pin comparator.
Register 0x01D[2]=1b; enable the holdover function.
Register 0x01D[1] = 0b; use internal/automatic holdover
mode.
Register 0x01D[0] = 1b; enable the holdover function.
(VCO calibration must be complete before this bit is
enabled.)
Connect REFMON pin to REFSEL pin.
Frequency Status Monitors
The AD9518 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is shown
in Figure 39. The VCO status frequency monitor is also capable
of monitoring the CLK input if the CLK input is selected as the
input to the N divider.
The PLL reference frequency monitors have two threshold
frequencies: normal and extended (see Table 15). The reference
frequency monitor thresholds are selected in Register 0x01A
The frequency monitor status can be found in Register 0x01F,
Bits[3:1].
Rev. C | Page 32 of 64
Data Sheet
AD9518-0
REF_SEL
VS
GND
RSET
REFMON
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
LOCK
DETECT
STATUS
R
DIVIDER
STATUS
REFIN (REF1)
PLL
REFERENCE
REF2
CPRSET VCP
PROGRAMMABLE
R DELAY
REFIN (REF2)
BYPASS
LOW DROPOUT
REGULATOR (LDO)
N DIVIDER
P, P + 1
PRESCALER
A/B
COUNTERS
LF
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
VCO STATUS
VCO
STATUS
0
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
1
1
06429-070
CLK
0
Figure 39. Reference and VCO Status Monitors
VCO Calibration
6.
The AD9518 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. VCO calibration centers
the dc voltage at the internal VCO input (at the LF pin) for the
selected configuration; this is normally required only during
initial configuration and any time the PLL settings change. VCO
calibration is controlled by a calibration controller driven by the
R divider output. The calibration requires that the input reference
clock be present at the REFIN pins, and that the PLL be set up
properly to lock the PLL loop. During the first initialization after
a power-up or a reset of the AD9518, a VCO calibration sequence
is initiated by setting Register 0x018[0] = 1b. This can be done
during initial setup, before executing an update registers operation
(Register 0x232[0] = 1b). Subsequent to initial setup, a VCO
calibration sequence is initiated by resetting Register 0x018[0] = 0b,
executing an update registers operation, setting Register 0x018[0] =
1b, and executing another update registers operation. A readback
bit (Bit 6 in Register 0x1F) indicates when a VCO calibration is
finished by returning a logic true (that is, 1b).
7.
8.
A sync is executed during the VCO calibration; therefore, the
outputs of the AD9518 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Table 44
(Register 0x018[2:1]).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
The sequence of operations for the VCO calibration is as follows:
1.
2.
3.
4.
5.
Program the PLL registers to the proper values for the PLL
loop. Note that that automatic holdover mode must be
disabled, and the VCO divider must not be set to “Static.”
Ensure that the input reference signal is present.
For the initial setting of the registers after a power-up or reset,
initiate VCO calibration by setting Register 0x018[0] = 1b.
Subsequently, whenever a calibration is desired, set
Register 0x018[0] = 0b, update registers; and then set
Register 0x018[0] = 1b, update registers.
A sync operation is initiated internally, causing the outputs
to go to a static state determined by normal sync function
operation.
The VCO calibrates to the desired setting for the requested
VCO frequency.
Internally, the SYNC signal is released, allowing outputs
to continue clocking.
The PLL loop is closed.
The PLL locks.
fCAL_CLOCK = fREFIN/(R × cal_div)
where:
fREFIN is the frequency of the REFIN signal.
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(Register 0x018[2:1]).
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
Rev. C | Page 33 of 64
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
AD9518-0
Data Sheet
Table 28. Example Time to Complete a VCO Calibration
with Different fREFIN Frequencies
fREFIN (MHz)
100
10
10
R Divider
1
10
100
PFD
100 MHz
1 MHz
100 kHz
Time to Calibrate VCO
88 µs
8.8 ms
88 ms
VCO calibration must be manually initiated. This allows for
flexibility in deciding what order to program registers and when
to initiate a calibration, instead of having it happen every time
certain PLL registers have their values change. For example, this
allows for the VCO frequency to be changed by small amounts
without having an automatic calibration occur each time; this
should be done with caution and only when the user knows that
the VCO control voltage is not going to exceed the nominal best
performance limits. For example, a few 100 kHz steps are fine,
but a few MHz might not be. In addition, because the calibration
procedure results in rapid changes in the VCO frequency, the
distribution section is automatically placed in SYNC until the
calibration is finished. Therefore, this temporary loss of outputs
must be expected.
A VCO calibration should be initiated under the following
conditions:
•
•
After changing any of the PLL R, P, B, and A divider
settings, or after a change in the PLL reference clock
frequency. This, in effect, means any time a PLL register
or reference clock is changed such that a different VCO
frequency results.
Whenever system calibration is desired. The VCO is
designed to operate properly over extremes of temperatures
even when it is first calibrated at the opposite extreme.
However, a VCO calibration can be initiated at any time,
if desired.
CLOCK DISTRIBUTION
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for
N + 1 input clock cycles and low for M + 1 input clock cycles
(where D = N + M + 2). For example, a divide-by-5 can be high
for one divider input cycle and low for four cycles, or a divideby-5 can be high for three divider input cycles and low for two
cycles. Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 31 input clock cycles. The divider outputs
can also be set to start high or start low.
Internal VCO or External CLK as Clock Source
The clock distribution of the AD9518 has two clock input sources:
an internal VCO or an external clock connected to the CLK/CLK
pins. Either the internal VCO or CLK must be chosen as the
source of the clock signal to distribute. When the internal VCO
is selected as the source, the VCO divider must be used. When
CLK is selected as the source, it is not necessary to use the VCO
divider if the CLK frequency is less than the maximum channel
divider input frequency (1600 MHz); otherwise, the VCO divider
must be used to reduce the frequency to one that is acceptable
by the channel dividers. Table 29 shows how the VCO, CLK,
and VCO divider are selected. Register 0x1E1[1:0] selects the
channel divider source and determines whether the VCO divider
is used. It is not possible to select the VCO without using the
VCO divider.
Table 29. Selecting VCO or CLK as Source for Channel
Divider, and Whether VCO Divider Is Used
A clock channel consists of a pair of outputs that share a
common divider. A clock output consists of the drivers that
connect to the output pins. The clock outputs have LVPECL
signal levels at the pins.
The AD9518 has three channels, each with two LVPECL
outputs, for a total of six LVPECL outputs.
Each channel has its own programmable divider that divides
the clock frequency that is applied to its input. The channel
dividers can divide by any integer from 2 to 32, or the divider
can be bypassed to achieve a divide-by-one.
If the user wishes to use the channel dividers, the VCO divider
must be used after the on-chip VCO. This is because the internal
VCO frequency is above the maximum channel divider input
frequency (1600 MHz). The VCO divider can be set to divide by
2, 3, 4, 5, or 6. External clock signals connected to the CLK
input also require the VCO divider if the frequency of the signal
is greater than 1600 MHz.
Register 0x1E1
Bit 1
Bit 0
0
0
0
1
1
0
1
1
Channel Divider Source
CLK
CLK
VCO
Not allowed
VCO Divider
Used
Not used
Used
Not allowed
CLK or VCO Direct to LVPECL Outputs
It is possible to connect either the internal VCO or the CLK
(whichever is selected as the input to the VCO divider) directly
to the LVPECL outputs, OUT0 to OUT5. This configuration
can pass frequencies up to the maximum frequency of the VCO
directly to the LVPECL outputs. The LVPECL outputs may not
be able to provide a full voltage swing at the highest frequencies.
To connect the LVPECL outputs directly to the internal VCO or
CLK, the VCO divider must be selected as the source to the
distribution section, even if no channel uses it.
Rev. C | Page 34 of 64
Data Sheet
AD9518-0
Either the internal VCO or the CLK can be selected as the source
for the direct-to-output routing.
Table 30. Settings for Routing VCO Divider Input Directly
to LVPECL Outputs
Register Setting
0x1E1[1:0] = 00b
0x1E1[1:0] = 10b
0x192[1] = 1b
0x195[1] = 1b
0x198[1] = 1b
Selection
CLK is the source; VCO divider selected
VCO is the source; VCO divider selected
Direct to OUT0 and OUT1 outputs
Direct to OUT2 and OUT3 outputs
Direct to OUT4 and OUT5 outputs
The divider can be bypassed (equivalent to divide-by-1, divider
circuit is powered down) by setting the bypass bit. The dutycycle correction can be enabled or disabled according to the
setting of the DCCOFF bits.
Table 32. Setting DX for Divider 0, Divider 1, and Divider 21
Divider
0
1
2
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
Bypass
0x191[7]
0x194[7]
0x197[7]
Clock Frequency Division
1
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (2, 3, 4, 5, 6) and the
division of the channel divider. Table 31 indicates how the
frequency division for a channel is set.
Channel Frequency Division (0, 1, and 2)
Table 31. Frequency Division for Divider 0 to Divider 2
CLK or VCO
Selected
CLK/VCO
CLK/VCO
CLK/VCO
VCO
Divider
2 to 6
2 to 6
2 to 6
Channel
Divider
1 (bypassed)
1 (bypassed)
2 to 32
Direct to
Output
Yes
No
No
CLK
CLK
Not used
Not used
1 (bypassed)
2 to 32
No
No
Frequency
Division
1
(2 to 6) × (1)
(2 to 6) ×
(2 to 32)
1
2 to 32
The channel dividers feeding the LVPECL output drivers
contain one 2-to-32 frequency divider. This divider provides for
division by 2 to 32. Division by 1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Table 42 through Table 49).
VCO Divider
The VCO divider provides frequency division between the
internal VCO or the external CLK input and the clock
distribution channel dividers. The VCO divider can be set
to divide by 2, 3, 4, 5, or 6 (see Table 47, Register 0x1E0[2:0]).
Channel Dividers—LVPECL Outputs
Each pair of LVPECL outputs is driven by a channel divider.
There are three channel dividers (0, 1, and 2) driving a total
of six LVPECL outputs (OUT0 to OUT5). Table 32 gives the
register locations used for setting the division and other functions
of these dividers. The division is set by the values of M and N.
DCCOFF
0x192[0]
0x195[0]
0x198[0]
Note that the value stored in the register = # of cycles minus 1.
For each channel (where the channel number is x: 0, 1, or 2),
the frequency division, DX, is set by the values of M and N
(four bits each, representing Decimal 0 to Decimal 15), where
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
The cycles are cycles of the clock signal currently routed to the
input of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, DX = 1.
Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows
each channel divider to divide by any integer from 2 to 32.
Duty Cycle and Duty-Cycle Correction (0, 1, and 2)
The duty cycle of the clock signal at the output of a channel is
a result of some or all of the following conditions:
•
•
•
•
What are the M and N values for the channel?
Is the DCC enabled?
Is the VCO divider used?
What is the CLK input duty cycle? (The internal VCO has
a 50% duty cycle.)
The DCC function is enabled by default for each channel divider.
However, the DCC function can be disabled individually for
each channel divider by setting the DCCOFF bit for that channel.
Certain M and N values for a channel divider result in a non-50%
duty cycle. A non-50% duty cycle can also result with an even
division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle. Duty-cycle correction
requires the following channel divider conditions:
•
•
An even division must be set as M = N.
An odd division must be set as M = N + 1.
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2), expressed as a percentage (%).
Rev. C | Page 35 of 64
AD9518-0
Data Sheet
Table 33. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%
Even, Odd
DX
N+M+2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Even, Odd
Odd
VCO
Divider
Even
Odd = 3
Odd = 5
Output Duty Cycle
DCCOFF = 1 DCCOFF = 0
50%
50%
33.3%
50%
40%
50%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
50%; requires M = N
50%; requires M = N + 1
Table 34. Duty Cycle with VCO Divider, Input Duty Cycle Is X%
VCO
Divider
Even
Odd = 3
Odd = 5
Even
DX
N+M+2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Odd
Odd = 3
Even
Odd = 3
Odd
Odd = 5
Even
Odd = 5
Odd
Output Duty Cycle
DCCOFF = 1 DCCOFF = 0
50%
50%
DX
N+M+2
1
Any
Even
50%
Odd
X%
Odd
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 36).
These settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which
to offset, or delay, the rising edge of the output of the divider.
This delay is with respect to a nondelayed output (that is, with
a phase offset of zero). The amount of the delay is set by five bits
loaded into the phase offset (PO) register plus the start high (SH)
bit for each channel divider. When the start high bit is set, the
delay is also affected by the number of low cycles (M) that are
programmed for the divider.
The sync function must be used to make phase offsets effective
(see the Synchronizing the Outputs—Sync Function section).
Table 36. Setting Phase Offset and Division for Divider 0,
Divider 1, and Divider 2
Divider
0
1
2
33.3%
(1 + X%)/3
40%
(2 + X%)/5
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
50%,
requires M = N
50%,
requires M = N + 1
50%,
requires M = N
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
50%,
requires M = N
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
Table 35. Channel Divider Output Duty Cycle When the
VCO Divider Is Not Used
Input Clock
Duty Cycle
Any
Phase Offset or Coarse Time Delay (0, 1, and 2)
Output Duty Cycle
DCCOFF = 1 DCCOFF = 0
1 (divider
Same as input
bypassed)
duty cycle
(N + 1)/
50%, requires M = N
(M + N + 2)
(N + 1)/
50%, requires
(M + N + 2)
M=N+1
(N + 1)/
(N + 1 + X%)/(2 × N + 3),
(M + N + 2)
requires M = N + 1
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO is connected directly to the output, the duty cycle is 50%.
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
Start
High (SH)
0x191[4]
0x194[4]
0x197[4]
Phase
Offset (PO)
0x191[3:0]
0x194[3:0]
0x197[3:0]
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to DX).
TX = period of the clock signal at the input of the divider, DX
(in seconds).
Φ = 16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide-by is set as N = high cycles and M = low cycles.
Case 1
For Φ ≤ 15,
Δt = Φ × TX
Δc = Δt/TX = Φ
Case 2
For Φ ≥ 16,
Δt = (Φ − 16 + M + 1) × TX
Δc = Δt/TX
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 40 shows the results of setting such a coarse
offset between outputs.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CHANNEL
DIVIDER INPUT
Tx
CHANNEL DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
SH = 0
DIVIDER 0 PO = 0
DIVIDER 1
SH = 0
PO = 1
DIVIDER 2
SH = 0
PO = 2
1 × Tx
2 × Tx
Figure 40. Effect of Coarse Phase Offset (or Delay)
Rev. C | Page 36 of 64
06429-071
The duty cycle at the output of the channel divider for various
configurations is shown in Table 33 to Table 35.
Data Sheet
AD9518-0
Synchronizing the Outputs—Sync Function
The most common way to execute the sync function is to use
the SYNC pin to do a manual synchronization of the outputs.
This requires a low-going signal on the SYNC pin, which is held
low and then released when synchronization is desired. The
timing of the sync operation is shown in Figure 41 (using the
VCO divider) and Figure 42 (VCO divider not used). There is
an uncertainty of up to one cycle of the clock at the input to the
channel divider due to the asynchronous nature of the SYNC
signal with respect to the clock edges inside the AD9518. The
delay from the SYNC rising edge to the beginning of synchronized
output clocking is between 14 and 15 cycles of clock at the channel
divider input, plus either one cycle of the VCO divider input
(see Figure 41), or one cycle of the channel divider input (see
Figure 42), depending on whether the VCO divider is used.
Cycles are counted from the rising edge of the signal.
The AD9518 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions and subsequently releasing these
outputs to continue clocking at the same instant with the preset
conditions applied. This allows for the alignment of the edges of
two or more outputs or for the spacing of edges according to the
coarse phase offset settings for two or more outputs.
Output synchronization is executed in several ways, as follows:



CHANNEL DIVIDER
OUTPUT CLOCKING
Another common way to execute the sync function is by setting
and resetting the soft sync bit at Register 0x230[0] (see Table 43
through Table 49 for details). Both the setting and resetting
of the soft sync bit require an update all registers operation
(Register 0x232[0] = 1) to take effect.
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER OUTPUT STATIC
INPUT TO VCO DIVIDER
1
1
INPUT TO CHANNEL DIVIDER
2
3
4
5
6
7
9
8
11
10
13
12
14
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
06429-073

By forcing the SYNC pin low, then releasing it (manual sync).
By setting, then resetting, any one of the following three bits:
the soft sync bit (Register 0x230[0]), the soft reset bit
(Register 0x000[2] [mirrored]), and the power-down
distribution reference bit (Register 0x230[1]).
By executing synchronization of the outputs as part of the
chip power-up sequence.
By forcing the RESET pin low, then releasing it (chip reset).
By forcing the PD pin low, then releasing (chip power-down).
Following completion of a VCO calibration. An internal
SYNC signal is automatically asserted at the beginning of
a VCO calibration, then released upon its completion.
Figure 41. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER OUTPUT STATIC
INPUT TO CLK
IINPUT TO CHANNEL DIVIDER
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
06429-074


Figure 42. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
Rev. C | Page 37 of 64
AD9518-0
Data Sheet
A sync operation brings all outputs that have not been excluded
(by the nosync bit) to a preset condition before allowing the outputs
to begin clocking in synchronicity. The preset condition takes
into account the settings in each of the channel’s start high bit
and its phase offset. These settings govern both the static state
of each output when the sync operation is happening and the
state and relative phase of the outputs when they begin clocking
again upon completion of the sync operation. Between outputs
and after synchronization, this allows for the setting of phase
offsets.
The AD9518 outputs are in pairs, sharing a channel divider
per pair. The synchronization conditions apply to both outputs
of a pair.
Each channel (a divider and its outputs) can be excluded from
any sync operation by setting the nosync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do not
set their outputs static during a sync operation, and their outputs
are not synchronized with those of the nonexcluded channels.
LVPECL Outputs—OUT0 to OUT3
The LVPECL differential voltage (VOD) is selectable from ~400 mV
to ~960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]).
The LVPECL outputs have dedicated pins for power supply
(VS_LVPECL), allowing a separate power supply to be used.
VS_LVPECL can be from 2.5 V to 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring
a board layout change. Each LVPECL output can be powered
down or powered up, as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have several power-down
modes. This includes a safe power-down mode that continues
to protect the output devices while powered down, although it
consumes somewhat more power than a total power-down. If
the LVPECL output pins are terminated, it is best to select the
safe power-down mode. If the pins are left floating (that is, not
connected), total power-down mode is fine.
3.3V
The AD9518 has several ways to force the chip into a reset
condition that restores all registers to their default values and
makes these settings active.
Power-On Reset—Start-Up Conditions When VS Is Applied
A power-on reset (POR) is issued when the VS power supply is
turned on. This initializes the chip to the power-on conditions
that are determined by the default register settings. These are
indicated in the Default Value (Hex) column of Table 42. At
power-on, the AD9518 also executes a sync operation, which
brings the outputs into phase alignment according to the default
settings.
Asynchronous Reset via the RESET Pin
An asynchronous hard reset is executed by momentarily pulling
RESET low. A reset restores the chip registers to the default settings.
Soft Reset via Register 0x000[2]
A soft reset is executed by writing Register 0x000[2] and
Register 0x000[5] = 1b. This bit is not self-clearing; it must be
cleared by writing Register 0x000[2] and Register 0x000[5] = 0b to
reset it and complete the soft reset operation. A soft reset restores
the default values to the internal registers. The soft reset bit does
not require an update registers command (Register 0x232) to be
issued.
POWER-DOWN MODES
Chip Power-Down via PD
The AD9518 can be put into a power-down condition by
pulling the PD pin low. Power-down turns off most of the
functions and currents inside the AD9518. The chip remains in
this power-down state until PD is brought back to logic high.
When the AD9518 wakes up, it returns to the settings programmed
into its registers prior to the power-down, unless the registers
are changed by new programming while the PD pin is held low.
The PD power-down shuts down the currents on the chip,
except the bias current that is necessary to maintain the LVPECL
outputs in a safe shutdown mode. This is needed to protect the
LVPECL output circuitry from damage that could be caused by
certain termination and load configurations when tristated.
Because this is not a complete power-down, it can be called
sleep mode.
When the AD9518 is in a PD power-down, the chip is in the
following state:
OUT
06429-033
OUT
GND
RESET MODES
Figure 43. LVPECL Output Simplified Equivalent Circuit
•
•
•
•
•
•
Rev. C | Page 38 of 64
The PLL is off (asynchronous power-down).
The VCO is off.
The CLK input buffer is off.
All dividers are off.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
Data Sheet
AD9518-0
If the AD9518 clock outputs must be synchronized to each
other, a SYNC is required upon exiting power-down (see the
Synchronizing the Outputs—Sync Function section). A VCO
calibration is not required when exiting power-down.
PLL Power-Down
The PLL section of the AD9518 can be selectively powered down.
There are three PLL operating modes set by Register 0x010[1:0],
as shown in Table 44.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated.
In synchronous power-down mode, the PLL power-down is
gated by the charge pump to prevent unwanted frequency jumps.
The device goes into power-down on the occurrence of the next
charge pump event after the registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
Register 0x230[1] = 1b. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
(00b), it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down.
If the LVPECL power-down mode is set to 11b, the LVPECL
output is not protected from reverse bias and may be damaged
under certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
individually by writing to the appropriate registers. The register
map details the individual power-down settings for each output.
The LVPECL outputs have multiple power-down modes
(see Table 45), which give some flexibility in dealing with the
various output termination conditions. When the mode is set to
10b, the LVPECL output is protected from reverse bias to
2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is
not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
operation when the distribution block is powered down with
Register 0x230[1] = 1b (see the Distribution Power-Down
section).
Individual Circuit Block Power-Down
Other AD9518 circuit blocks (such as CLK, REF1, and REF2)
can be powered down individually. This gives flexibility in
configuring the part for power savings whenever certain chip
functions are not needed.
Rev. C | Page 39 of 64
AD9518-0
Data Sheet
SERIAL CONTROL PORT
The AD9518 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9518 serial control port is compatible with most synchronous
transfer formats, including both the Motorola SPI and Intel®
SSR® protocols. The serial control port allows read/write access
to all registers that configure the AD9518. Single or multiple
byte transfers are supported, as well as MSB first or LSB first
transfer formats. The AD9518 serial control port can be
configured for a single bidirectional I/O pin (SDIO only)
or for two unidirectional I/O pins (SDIO/SDO). By default,
the AD9518 is in bidirectional mode, long instruction (long
instruction is the only instruction mode supported).
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and
writes. Write data bits are registered on the rising edge of this
clock, and read data bits are registered on the falling edge. This
pin is internally pulled down by a 30 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin that acts
either as an input only (unidirectional mode) or as both an input
and an output (bidirectional mode). The AD9518 defaults to
the bidirectional I/O mode (Register 0x000[0] = 0b).
SDO (serial data out) is used only in the unidirectional I/O mode
(Register 0x000[0] = 1b) as a separate output pin for reading
back data.
CS (chip select bar) is an active low control that gates the read
and write cycles. When CS is high, SDO and SDIO are in a high
impedance state. This pin is internally pulled up by a 30 kΩ
resistor to VS.
13
CS
14
SDO
15
SDIO
16
AD9518-0
SERIAL
CONTROL
PORT
06429-036
SCLK
Figure 44. Serial Control Port
GENERAL OPERATION OF SERIAL CONTROL PORT
A write or a read operation to the AD9518 is initiated by pulling
CS low.
CS stalled high is supported in modes where three or fewer bytes
of data (plus instruction data) are transferred (see Table 37).
In these modes, CS can temporarily return high on any byte
boundary, allowing time for the system controller to process the
next byte. CS can go high on byte boundaries only and can go
high during either part (instruction or data) of the transfer.
During this period, the serial control port state machine enters
a wait state until all data is sent. If the system controller decides
to abort the transfer before all of the data is sent, the state machine
must be reset, either by completing the remaining transfers or
by returning CS low for at least one complete SCLK cycle (but
less than eight SCLK cycles). Raising CS on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 37), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented (see the MSB/LSB
First Transfers section). CS must be raised at the end of the last
byte to be transferred, thereby ending the stream mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9518.
The first part writes a 16-bit instruction word into the AD9518,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9518 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
is the transfer of data into the serial control port buffer of the
AD9518. Data bits are registered on the rising edge of SCLK.
The length of the transfer (1, 2, 3 bytes or streaming mode) is
indicated by two bits ([W1:W0]) in the instruction byte. When
the transfer is 1, 2, or 3 bytes, but not streaming, CS can be raised
after each sequence of eight bits to stall the bus (except after the
last byte, where it ends the cycle). When the bus is stalled, the serial
transfer resumes when CS is lowered. Raising CS on a nonbyte
boundary resets the serial control port. During a write, streaming
mode does not skip over reserved or blank registers; therefore,
the user must know the bit pattern to write to the reserved registers
to preserve proper operation of the part. Refer to the control
register map (see Table 42) to determine if the default value for
reserved registers is nonzero. It does not matter what data is
written to blank registers.
Because data is written into a serial control port buffer area, and
not directly into the actual control registers of the AD9518, an
additional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9518,
thereby causing them to become active. The update registers
operation consists of setting Register 0x232[0] = 1b (this bit is
self-clearing). Any number of bytes of data can be changed
before an update registers operation is executed. The update
registers operation simultaneously actuates all register changes
that have been written to the buffer since any previous update.
Rev. C | Page 40 of 64
Data Sheet
AD9518-0
Read
If the instruction word is for a read operation, the next N × 8
SCLK cycles clock out the data from the address specified in the
instruction word, where N is 1 to 3 as determined by [W1:W0].
If N = 4, the read operation is in streaming mode, continuing
until CS is raised. Streaming mode does not skip over reserved
or blank registers. The readback data is valid on the falling
edge of SCLK.
The default mode of the AD9518 serial control port is the
bidirectional mode. In bidirectional mode, both the sent data
and the readback data appear on the SDIO pin. It is also possible to
set the AD9518 to unidirectional mode via the SDO active bit,
Register 0x000[0] = 1b. In unidirectional mode, the readback
data appears on the SDO pin.
A readback request reads the data that is in the serial control
port buffer area, or the data that is in the active registers (see
Figure 45). Readback of the buffer or active registers is controlled
by Register 0x004[0].
The AD9518 supports only the long instruction mode; therefore,
Register 0x000[4:3] must be set to 11b. (This register uses mirrored
bits.) Long instruction mode is the default at power-up or reset.
SDO
CS
SERIAL
CONTROL
PORT
UPDATE
REGISTERS
WRITE REGISTER 0x232 = 0x01
TO UDATE REGISTERS
06429-037
SDIO
Figure 45. Relationship Between Serial Control Port Buffer Registers and
Active Registers of the AD9518
THE INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits,
[W1:W0], indicate the length of the transfer in bytes. The final
13 bits are the address ([A12:A0]) at which to begin the read or
write operation.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0] (see Table 37).
Table 37. Byte Transfer Count
W1
0
0
1
1
W0
0
1
0
1
Bytes to Transfer
1
2
3
Streaming mode
MSB/LSB FIRST TRANSFERS
The AD9518 instruction word and byte data can be MSB first
or LSB first. Any data written to Register 0x000 must be mirrored;
the upper four bits (Bits[7:4]) with the lower four bits (Bits[3:0]).
This makes it irrelevant whether LSB first or MSB first is in
effect. As an example of this mirroring, see the default setting
for this register: 0x18, which mirrors Bit 4 and Bit 3. This sets
the long instruction mode (which is the default and the only
mode that is supported).
The default for the AD9518 is MSB first.
When LSB first is set by Register 0x000[1] and Register 0x000[6],
it takes effect immediately because it affects only the operation
of the serial control port and does not require that an update be
executed.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from the high address to the low
address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the
multibyte transfer cycle.
ACTIVE REGISTERS
SCLK
BUFFER REGISTERS
The AD9518 uses Register Address 0x000 to Register
Address 0x232.
The 13 bits found in [A12:A0] select the address within the
register map that is written to or read from during the data
transfer portion of the communications cycle. Only Bits[A9:A0]
are needed to cover the range of the 0x232 registers used by the
AD9518. Bits[A12:A10] must always be set to 0b. For multibyte
transfers, this address is the starting byte address. In MSB first
mode, subsequent bytes decrement the address.
When LSB first is active, the instruction and data bytes must be
written from LSB to MSB. Multibyte data transfers in LSB first
format start with an instruction byte that includes the register
address of the least significant data byte followed by multiple
data bytes. The internal byte address generator of the serial
control port increments for each byte of the multibyte
transfer cycle.
The AD9518 serial control port register address decrements
from the register address just written toward 0x000 for multibyte
I/O operations if the MSB first mode is active (default). If the
LSB first mode is active, the register address of the serial control
port increments from the address just written toward Register
Address 0x232 for multibyte I/O operations.
Streaming mode always terminates when it hits Address 0x232.
Note that unused addresses are not skipped during multibyte
I/O operations.
Table 38. Streaming Mode (No Addresses Are Skipped)
Write Mode
LSB first
MSB first
Rev. C | Page 41 of 64
Address Direction
Increment
Decrement
Stop Sequence
0x230, 0x231, 0x232, stop
0x001, 0x000, 0x232, stop
AD9518-0
Data Sheet
Table 39. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
LSB
I0
R/W
W1
W0
A12 = 0
A11 = 0
A10 = 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
SCLK DON'T CARE
R/W W1 W0 A12 A11 A10 A9
A8
A7
A6 A5
A4 A3 A2
A1 A0
16-BIT INSTRUCTION HEADER
D7 D6 D5
D4 D3
D2 D1
D0
D7
D6 D5
REGISTER (N) DATA
D4 D3 D2
D1 D0
DON'T CARE
REGISTER (N – 1) DATA
06429-038
SDIO DON'T CARE
DON'T CARE
Figure 46. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data
CS
SCLK
DON’T CARE
SDIO
DON’T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDO DON’T CARE
REGISTER (N) DATA
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
REGISTER (N – 3) DATA
DON’T
CARE
06429-039
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
Figure 47. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data
tDS
tS
tDH
CS
DON’T CARE
SDIO
DON’T CARE
tC
tCLK
tLOW
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON’T CARE
06429-040
SCLK
tHIGH
Figure 48. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
CS
SCLK
DATA BIT N
06429-041
tDV
SDIO
SDO
DATA BIT N – 1
Figure 49. Serial Control Port Timing Diagram—Read
CS
SCLK DON'T CARE
DON'T CARE
A0 A1 A2 A3
A4
A5 A6
A7
A8
A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4
16-BIT INSTRUCTION HEADER
D5 D6
REGISTER (N) DATA
D7
D0
D1 D2
D6
REGISTER (N + 1) DATA
Figure 50. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data
Rev. C | Page 42 of 64
D3 D4 D5
D7
DON'T CARE
06429-042
SDIO DON'T CARE
Data Sheet
AD9518-0
tC
tS
CS
tCLK
tHIGH
SCLK
tLOW
tDS
SDIO
BIT N
BIT N + 1
Figure 51. Serial Control Port Timing Diagram—Write
Table 40. Serial Control Port Timing
Parameter
tDS
tDH
tCLK
tS
tC
tHIGH
tLOW
tDV
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 49)
Rev. C | Page 43 of 64
06429-043
tDH
AD9518-0
Data Sheet
THERMAL PERFORMANCE
Table 41. Thermal Parameters for the 48-Lead LFCSP
Symbol
θJA
θJMA
θJMA
θJB
ΨJB
ΨJB
ΨJB
θJC
ΨJT
ΨJT
ΨJT
Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board
Junction-to-ambient thermal resistance, natural convection per JEDEC JESD51-2 (still air)
Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)
Junction-to-ambient thermal resistance, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air)
Junction-to-board thermal resistance, natural convection per JEDEC JESD51-8 (still air)
Junction-to-board characterization parameter, natural convection per JEDEC JESD51-6 (still air)
and JEDEC JESD51-8
Junction-to-board characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)
and JEDEC JESD51-8
Junction-to-board characterization parameter, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air)
and JEDEC JESD51-8
Junction-to-case thermal resistance (die-to-heat sink) per MIL-STD-883, Method 1012.1
Junction-to-top-of-package characterization parameter, natural convection per JEDEC JESD51-2 (still air)
Junction-to-top-of-package characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-2 (still air)
Junction-to-top-of-package characterization parameter, 2.0 m/sec airflow per JEDEC JESD51-2 (still air)
Value (°C/W)
24.7
21.6
19.4
12.9
11.9
11.8
11.6
1.3
0.5
0.2
0.3
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order
approximation of TJ by the following equation:
Use the following equation to determine the junction
temperature of the AD9518 on the application PCB:
TJ = TCASE + (ΨJT × PD)
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the user at the
top center of the package.
ΨJT is the value from Table 41.
PD is the power dissipation of the device (see Table 16).
TJ = TA + (θJA × PD)
where TA is the ambient temperature (°C).
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of ΨJB are provided for package comparison and PCB
design considerations.
Rev. C | Page 44 of 64
Data Sheet
AD9518-0
CONTROL REGISTERS
CONTROL REGISTER MAP OVERVIEW
Table 42. Control Register Map Overview
Reg.
Addr.
(Hex)
Parameter
Bit 7 (MSB)
Serial Port Configuration
Serial port
SDO
0x000
configuration
active
0x001
0x002
0x003
Part ID
Readback
0x004
control
PLL
0x010
0x011
0x012
0x013
0x014
0x015
0x016
PFD and
charge pump
R counter
A counter
B counter
PLL Control 1
0x017
0x018
PLL Control 2
PLL Control 3
0x019
PLL Control 4
0x01A
PLL Control 5
0x01B
PLL Control 6
0x01C
PLL Control 7
0x01D
PLL Control 8
0x01E
0x01F
PLL Control 9
PLL readback
0x020
to
0x04F
0x0A0
to
0x0AB
0x0AC
to
0x0EF
Bit 6
Bit 5
Bit 4
LSB first
Soft reset
Long
Long
instruction
instruction
Blank
Reserved
Part ID (read only)
Blank
PFD
polarity
Bit 3
Charge pump current
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value
(Hex)
Soft reset
LSB first
SDO active
0x18
Charge pump mode
Read back
active
registers
PLL power-down
14-bit R divider, Bits[7:0] (LSB)
14-bit R divider, Bits[13:8] (MSB)
6-bit A counter
13-bit B counter, Bits[7:0] (LSB)
Blank
13-bit B counter, Bits[12:8] (MSB)
Set CP pin
Reset R
Reset A and
Reset all
B counter
Prescaler P
to VCP/2
counter
B counters
counters
bypass
STATUS pin control
Antibacklash pulse width
Disable
Digital lock
VCO calibration divider
VCO cal now
Reserved
Lock detect counter
digital lock
detect
detect
window
R, A, B counters
R path delay
N path delay
SYNC pin reset
Reference
Reserved
LD pin control
frequency
monitor
threshold
REF2
VCO
REF1 (REFIN)
REFMON pin control
frequency
frequency
(REFIN)
monitor
monitor
frequency
monitor
Select
Use
REF2
REF1
Differential
Disable
Reserved
REF_SEL pin
power-on
power-on
reference
switchover REF2
deglitch
PLL status
LD pin
Holdover
External
Holdover
Reserved
register
comparator
enable
holdover
enable
disable
enable
control
Reserved
Digital
REF1
REF2
VCO cal
Holdover
REF2
VCO
Reserved
lock detect
frequency > frequency >
finished
active
selected
frequency >
threshold
threshold
threshold
Blank
Blank
Blank
Reserved
Blank
Rev. C | Page 45 of 64
0x21
0x00
0x7D
0x01
0x00
0x00
0x03
0x00
0x06
0x00
0x06
0x00
0x00
0x00
0x00
0x00
0x00
N/A
AD9518-0
Reg.
Addr.
(Hex)
Parameter
LVPECL Outputs
0x0F0
OUT0
Data Sheet
Bit 7 (MSB)
Bit 6
Bit 5
OUT1
Blank
0x0F2
OUT2
Blank
0x0F3
OUT3
Blank
0x0F4
OUT4
Blank
0x0F5
OUT5
Blank
0x0F6
to
0x13F
0x140
to
0x143
0x144
to
0x18F
LVPECL Channel Dividers
Divider 0
0x190
Divider 0 low cycles
(PECL)
Divider 0
Divider 0
Divider 0
0x191
bypass
nosync
force high
0x192
Blank
0x193
Divider 1
(PECL)
0x195
0x196
0x197
Divider 1
force high
Blank
Divider 2
(PECL)
Divider 2
bypass
0x199
to
0x1A3
0x1A4
to
0x1DF
VCO Divider and CLK Input
0x1E0
VCO divider
0x1E1
Input CLKs
Divider 2
force high
Bit 0 (LSB)
OUT0 power-down
0x08
OUT1 power-down
0x0A
OUT2 power-down
0x08
OUT3 power-down
0x0A
OUT4 power-down
0x08
OUT5 power-down
0x0A
Reserved
Blank
Divider 0
start high
Reserved
Divider 1
start high
Divider 0 high cycles
0x00
Divider 0 phase offset
0x80
Divider 0
direct to
output
Divider 1 high cycles
Divider 0
DCCOFF
Divider 2
start high
Reserved
Divider 1
direct to
output
Divider 2 high cycles
0x00
Divider 1
DCCOFF
0x00
0x00
Divider 2 phase offset
Divider 2
direct to
output
0x00
0xBB
Divider 1 phase offset
Reserved
Divider 2
nosync
Blank
Bit 1
Blank
Divider 2 low cycles
0x198
0x1E2
to
0x22A
Divider 1
nosync
Bit 2
OUT0 LVPECL
differential voltage
OUT1 LVPECL
differential voltage
OUT2 LVPECL
differential voltage
OUT3 LVPECL
differential voltage
OUT4 LVPECL
differential voltage
OUT5 LVPECL
differential voltage
Divider 1 low cycles
Divider 1
bypass
0x194
Bit 3
OUT0
invert
OUT1
invert
OUT2
invert
OUT3
invert
OUT4
invert
OUT5
invert
Blank
0x0F1
Bit 4
Default
Value
(Hex)
0x00
Divider 2
DCCOFF
0x00
Reserved
Blank
Blank
Reserved
Reserved
Power down
Power
VCO clock
down
interface
clock input
section
Blank
Rev. C | Page 46 of 64
Power
down VCO
and CLK
VCO Divider
Select
Bypass VCO
VCO or CLK
divider
0x02
0x00
Data Sheet
Reg.
Addr.
(Hex)
Parameter
System
Power-down
0x230
and sync
AD9518-0
Bit 7 (MSB)
0x231
Update All Registers
Update all
0x232
registers
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Power
down sync
Power
down
distribution
reference
Reserved
Reserved
Blank
Blank
Bit 0 (LSB)
Default
Value
(Hex)
Soft sync
0x00
0x00
Update all
registers (selfclearing bit)
0x00
CONTROL REGISTER MAP DESCRIPTIONS
Table 43 through Table 49 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2].
Table 43. Serial Port Configuration and Part ID
Reg.
Addr
(Hex)
0x000
Bits
[7:4]
Name
Mirrored, Bits[3:0]
3
Long instruction
2
Soft reset
1
LSB first
0
SDO active
0x003
[7:0]
Part ID (read only)
0x004
0
Read back active registers
Description
Bits[7:4] should always mirror Bits[3:0] such that it does not matter whether the part is in MSB
or LSB first mode (see Bit 1, Register 0x000). The user should set the bits as follows:
Bit 7 = Bit 0.
Bit 6 = Bit 1.
Bit 5 = Bit 2.
Bit 4 = Bit 3.
Short/long instruction mode. This part uses long instruction mode only, so this bit should
always be set to 1b.
0: 8-bit instruction (short).
1: 16-bit instruction (long) (default).
Soft reset.
1: soft reset; restores default values to internal registers. Not self-clearing. Must be cleared to
0b to complete reset operation.
MSB or LSB data orientation.
0: data-oriented MSB first; addressing decrements (default).
1: data-oriented LSB first; addressing increments.
Selects unidirectional or bidirectional data transfer mode.
0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default).
1: SDO used for read, SDIO used for write; unidirectional mode.
Uniquely identifies the dash version (-0 through -4) of the AD9518.
AD9518-0: 0x21.
AD9518-1: 0x61.
AD9518-2: 0xA1.
AD9518-3: 0x63.
AD9518-4: 0xE3.
Selects register bank used for a readback.
0: reads back buffer registers (default).
1: reads back active registers.
Rev. C | Page 47 of 64
AD9518-0
Data Sheet
Table 44. PLL
Reg.
Addr.
(Hex)
0x010
Bits
7
Name
PFD polarity
[6:4]
CP current
[3:2]
CP mode
[1:0]
PLL power-down
0x011
[7:0]
0x012
[5:0]
0x013
0x014
[5:0]
[7:0]
0x015
[4:0]
0x016
7
14-bit R divider,
Bits[7:0] (LSB)
14-bit R divider,
Bits[13:8] (MSB)
6-bit A counter
13-bit B counter,
Bits[7:0] (LSB)
13-bit B counter,
Bits[12:8] (MSB)
Set CP pin to VCP/2
6
Reset R counter
5
Reset A, B counters
4
Reset all counters
3
B counter bypass
Description
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires
positive polarity; Bit 7 = 0b.
0: positive; higher control voltage produces higher frequency (default).
1: negative; higher control voltage produces lower frequency.
Charge pump current (with CPRSET = 5.1 kΩ).
6
5
4
ICP (mA)
0
0
0
0.6.
0
0
1
1.2.
0
1
0
1.8.
0
1
1
2.4.
1
0
0
3.0.
1
0
1
3.6.
1
1
0
4.2.
1
1
1
4.8 (default).
Charge pump operating mode.
3
2
Charge Pump Mode
0
0
High impedance state.
0
1
Force source current (pump up).
1
0
Force sink current (pump down).
1
1
Normal operation (default).
PLL operating mode.
1
0
Mode
0
0
Normal operation.
0
1
Asynchronous power-down (default).
1
0
Normal operation.
1
1
Synchronous power-down.
R divider LSBs—lower eight bits (default = 0x01).
R divider MSBs—upper six bits (default = 0x00).
A counter (part of N divider) (default = 0x00).
B counter (part of N divider)—lower eight bits (default = 0x03).
B counter (part of N divider)—upper five bits (default = 0x00).
Sets the CP pin to one-half of the VCP supply voltage.
0: CP normal operation (default).
1: CP pin set to VCP/2.
Resets R counter (R divider).
0: normal (default).
1: holds the R counter in reset.
Resets A and B counters (part of N divider).
0: normal (default).
1: holds the A and B counters in reset.
Resets R, A, and B counters.
0: normal (default).
1: holds the R, A, and B counters in reset.
B counter bypass. This is valid only when operating the prescaler in FD mode.
0: normal (default).
1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.
Rev. C | Page 48 of 64
Data Sheet
Reg.
Addr.
(Hex)
0x017
Bits
[2:0]
[7:2]
Name
Prescaler P
STATUS pin control
AD9518-0
Description
Prescaler: DM = dual modulus and FD = fixed divide.
2
1
0
Mode Prescaler
0
0
0
FD
Divide-by-1.
0
0
1
FD
Divide-by-2.
0
1
0
DM
Divide-by-2 (2/3 mode).
0
1
1
DM
Divide-by-4 (4/5 mode).
1
0
0
DM
Divide-by-8 (8/9 mode).
1
0
1
DM
Divide-by-16 (16/17 mode).
1
1
0
DM
Divide-by-32 (32/33 mode) (default).
1
1
1
FD
Divide-by-3.
Selects the signal that is connected to the STATUS pin.
Level or
Dynamic
Signal
Signal at STATUS Pin
7
6
5
4 3 2
0
0
0
0
0 0
LVL
Ground (dc) (default).
0
0
0
0
0 1
DYN
N divider output (after the delay).
0
0
0
0
1 0
DYN
R divider output (after the delay).
0
0
0
0
1 1
DYN
A divider output.
0
0
0
1
0 0
DYN
Prescaler output.
0
0
0
1
0 1
DYN
PFD up pulse.
0
0
0
1
1 0
DYN
PFD down pulse.
0
X
X
X X X
LVL
Ground (dc); for all other cases of 0XXXXXb not specified previously.
The selections that follow are the same as REFMON.
1
0
0
0
0 0
LVL
Ground (dc).
1
0
0
0
0 1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
0
1 0
DYN
REF2 clock (not available in differential mode).
1
0
0
0
1 1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
0
1
0 0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
0
1
0 1
LVL
Status of selected reference (status of differential reference); active high.
Status of unselected reference (not available in differential mode);
1
0
0
1
1 0
LVL
active high.
1
0
0
1
1 1
LVL
Status REF1 frequency; active high.
1
0
1
0
0 0
LVL
Status REF2 frequency; active high.
1
0
1
0
0 1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1 0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1 1
LVL
Status of VCO frequency; active high.
1
0
1
1
0 0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
1
0 1
LVL
Digital lock detect (DLD); active high.
1
0
1
1
1 0
LVL
Holdover active; active high.
1
0
1
1
1 1
LVL
LD pin comparator output; active high.
1
1
0
0
0 0
LVL
VS (PLL supply).
1
1
0
0
0 1
DYN
REF1 clock (differential reference when in differential mode).
1
1
0
0
1 0
DYN
REF2 clock (not available in differential mode).
1
1
0
0
1 1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
1
0
1
0 0
DYN
Unselected reference to PLL (not available when in differential mode).
1
1
0
1
0 1
LVL
Status of selected reference (status of differential reference); active low.
1
1
0
1
1 0
LVL
Status of unselected reference (not available in differential mode); active low.
1
1
0
1
1 1
LVL
Status of REF1 frequency; active low.
1
1
1
0
0 0
LVL
Status of REF2 frequency; active low.
1
1
1
0
0 1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
1
1
0
1 0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
1
1
0
1 1
LVL
Status of VCO frequency; active low.
1
1
1
1
0 0
LVL
Selected reference (low = REF2, high = REF1).
1
1
1
1
0 1
LVL
Digital lock detect (DLD); active low.
1
1
1
1
1 0
LVL
Holdover active; active low.
1
1
1
1
1 1
LVL
LD pin comparator output; active low.
Rev. C | Page 49 of 64
AD9518-0
Reg.
Addr.
(Hex)
0x018
0x019
Data Sheet
Bits
[1:0]
Name
Antibacklash pulse
width
[6:5]
Lock detect counter
4
Digital lock detect
window
3
Disable digital lock
detect
[2:1]
VCO cal divider
0
VCO cal now
[7:6]
R, A, B counters,
SYNC pin reset
[5:3]
[2:0]
R path delay
N path delay
Description
1
0
Antibacklash Pulse Width (ns)
0
0
2.9 (default); this is the recommended setting, and it does not normally need to be changed.
0
1
1.3; this setting may be necessary if the PFD frequency > 50 MHz.
1
0
6.0.
1
1
2.9.
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
6
5
PFD Cycles to Determine Lock
0
0
5 (default).
0
1
16.
1
0
64.
1
1
255.
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock
detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
0: high range (default).
1: low range.
Digital lock detect operation.
0: normal lock detect operation (default).
1: disables lock detect.
VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
2
1
VCO Calibration Clock Divider
0
0
2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R.
0
1
4. This setting is fine for PFD frequencies < 25 MHz.
1
0
8. This setting is fine for PFD frequencies < 50 MHz.
1
1
16 (default). This setting is fine for any PFD frequency but also results in the longest VCO calibration time.
Bit used to initiate VCO calibration. This bit must be toggled from 0b to 1b in the active registers. To initiate calibration,
use the following three steps: first, ensure that the input reference signal is present; second, set to 0b (if not zero
already), followed by the update all registers bit (Register 0x232, Bit 0); and third, program to 1b, again followed by the
update all registers bit (Register 0x232, Bit 0). Clearing this bit discards the VCO calibration and usually results in the
PLL losing lock. The user must ensure that the holdover enable bits in Register 0x01D = 00b during VCO calibration.
7
6
Action
0
0
Does nothing on SYNC (default).
0
1
Asynchronous reset.
1
0
Synchronous reset.
1
1
Does nothing on SYNC.
R path delay (default = 0x00); see Table 2.
N path delay (default = 0x00); see Table 2.
Rev. C | Page 50 of 64
Data Sheet
Reg.
Addr.
(Hex)
0x01A
Bits
6
Name
Reference
frequency monitor
threshold
[5:0]
LD pin control
AD9518-0
Description
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO
frequency monitor’s detection threshold (see Table 15: REF1, REF2, and VCO frequency status monitor).
0: frequency valid if frequency is above the higher frequency threshold (default).
1: frequency valid if frequency is above the lower frequency threshold.
Selects the signal that is connected to the LD pin.
Level or
Dynamic
Signal
Signal at LD Pin
5
4
3
2
1
0
0
0
0
0
0
0
LVL
Digital lock detect (high = lock, low = unlock) (default).
0
0
0
0
0
1
DYN
P-channel, open-drain lock detect (analog lock detect).
0
0
0
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect).
0
0
0
0
1
1
HIZ
High-Z LD pin.
0
0
0
1
0
0
CUR
Current source lock detect (110 µA when DLD is true).
0
X
X
X
X
X
LVL
Ground (dc); for all other cases of 0XXXXXb not specified previously.
The selections that follow are the same as REFMON.
1
0
0
0
0
0
LVL
Ground (dc).
1
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
Status of unselected reference (not available in differential mode);
1
0
0
1
1
0
LVL
active high.
1
0
0
1
1
1
LVL
Status REF1 frequency; active high.
1
0
1
0
0
0
LVL
Status REF2 frequency; active high.
1
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
1
LVL
Status of VCO frequency (active high).
1
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
1
0
1
LVL
Digital lock detect (DLD); active high.
1
0
1
1
1
0
LVL
Holdover active; active high.
1
0
1
1
1
1
LVL
Not available. Do not use.
1
1
0
0
0
0
LVL
VS (PLL supply).
1
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
1
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
1
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
Status of unselected reference (not available in differential mode);
1
1
0
1
1
0
LVL
active low.
1
1
0
1
1
1
LVL
Status of REF1 frequency; active low.
1
1
1
0
0
0
LVL
Status of REF2 frequency; active low.
1
1
1
0
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
1
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
1
1
0
1
1
LVL
Status of VCO frequency; active low.
1
1
1
1
0
0
LVL
Selected reference (low = REF2, high = REF1).
1
1
1
1
0
1
LVL
Digital lock detect (DLD); active low.
1
1
1
1
1
0
LVL
Holdover active; active low.
1
1
1
1
1
1
LVL
Not available. Do not use.
Rev. C | Page 51 of 64
AD9518-0
Reg.
Addr.
(Hex)
0x01B
Data Sheet
Bits
7
Name
VCO frequency
monitor
6
REF2 (REFIN)
frequency monitor
5
REF1 (REFIN)
frequency monitor
[4:0]
REFMON pin
control
Description
Enables or disables VCO frequency monitor.
0: disables VCO frequency monitor (default).
1: enables VCO frequency monitor.
Enables or disables REF2 frequency monitor.
0: disables REF2 frequency monitor (default).
1: enables REF2 frequency monitor.
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
0: disables REF1 (REFIN) frequency monitor (default).
1: enables REF1 (REFIN) frequency monitor.
Selects the signal that is connected to the REFMON pin.
Level or
Dynamic
Signal
4
3
2 1
0
Signal at REFMON Pin
0
0
0
0
0
LVL
Ground (dc) (default).
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
0
0
0
1
0
DYN
REF2 clock (not available in differential mode).
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
0
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
0
0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active high.
0
0
1
1
1
LVL
Status REF1 frequency; active high.
0
1
0
0
0
LVL
Status REF2 frequency; active high.
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
0
1
0
1
1
LVL
Status of VCO frequency; active high.
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
0
1
1
0
1
LVL
Digital lock detect (DLD); active low.
0
1
1
1
0
LVL
Holdover active; active high.
0
1
1
1
1
LVL
LD pin comparator output; active high.
1
0
0
0
0
LVL
VS (PLL supply).
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active low.
1
0
1
1
1
LVL
Status of REF1 frequency; active low.
1
1
0
0
0
LVL
Status of REF2 frequency; active low.
1
1
0
0
1
LVL
(Status of REF1 frequency) AND (Status of REF2 frequency).
1
1
0
1
0
LVL
(DLD) AND (Status of selected reference) AND (Status of VCO).
1
1
0
1
1
LVL
Status of VCO frequency; active low.
1
1
1
0
0
LVL
Selected reference (low = REF2, high = REF1).
1
1
1
0
1
LVL
Digital lock detect (DLD); active low.
1
1
1
1
0
LVL
Holdover active; active low.
1
1
1
1
1
LVL
LD pin comparator output; active low.
Rev. C | Page 52 of 64
Data Sheet
Reg.
Addr.
(Hex)
0x01C
0x01D
0x01F
Bits
7
Name
Disable switchover
deglitch
6
Select REF2
5
Use REF_SEL pin
[4:3]
2
Reserved
REF2 power-on
1
REF1 power-on
0
Differential
reference
4
PLL status register
disable
3
LD pin comparator
enable
2
Holdover enable
1
External holdover
control
0
Holdover enable
6
VCO cal finished
5
Holdover active
4
REF2 selected
3
VCO frequency >
threshold
2
REF2 frequency >
threshold
AD9518-0
Description
Disables or enables the switchover deglitch circuit.
0: enables switchover deglitch circuit (default).
1: disables switchover deglitch circuit.
If Register 0x01C, Bit 5 = 0b, selects reference for PLL.
0: selects REF1 (default).
1: selects REF2.
Sets method of PLL reference selection.
0: uses Register 0x01C, Bit 6 (default).
1: uses REF_SEL pin.
Reserved (default: 00b).
This bit turns the REF2 power on.
0: REF2 power off (default).
1: REF2 power on.
This bit turns the REF1 power on.
0: REF1 power off (default).
1: REF1 power on.
Selects the PLL reference mode: differential or single-ended. Single-ended must be selected for the automatic
switchover between REF1 and REF2 to work.
0: single-ended reference mode (default).
1: differential reference mode.
Disables the PLL status register readback.
0: PLL status register enable (default).
1: PLL status register disable.
Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When
in the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if
the PLL was previously in a locked state (see Figure 38). Otherwise, this function can be used with the REFMON and
STATUS pins to monitor the voltage on this pin.
0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true (high) (default).
1: enables LD pin comparator.
Along with Bit 0, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
0: automatic holdover mode; holdover controlled by automatic holdover circuit (default).
1: external holdover mode; holdover controlled by SYNC pin.
Along with Bit 2, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
Read-only register. Indicates status of the VCO calibration.
0: VCO calibration not finished.
1: VCO calibration finished.
Read-only register. Indicates if the part is in the holdover state (see Figure 38). This is not the same as holdover enabled.
0: not in holdover.
1: holdover state active.
Read-only register. Indicates which PLL reference is selected as the input to the PLL.
0: REF1 selected (or differential reference if in differential mode).
1: REF2 selected.
Read-only register. Indicates if the VCO frequency is greater than the threshold (see Table 15: REF1, REF2, and VCO
frequency status monitor).
0: VCO frequency is less than the threshold.
1: VCO frequency is greater than the threshold.
Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by
Register 0x1A, Bit 6.
0: REF2 frequency is less than threshold frequency.
1: REF2 frequency is greater than threshold frequency.
Rev. C | Page 53 of 64
AD9518-0
Reg.
Addr.
(Hex)
Data Sheet
Bits
1
Name
REF1 frequency >
threshold
0
Digital lock detect
Description
Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A, Bit 6.
0: REF1 frequency is less than threshold frequency.
1: REF1 frequency is greater than threshold frequency.
Read-only register. Digital lock detect.
0: PLL is not locked.
1: PLL is locked.
Table 45. LVPECL Outputs
Reg.
Addr.
(Hex)
0x0F0
0x0F1
0x0F2
Bits
4
Name
OUT0 invert
[3:2]
OUT0 LVPECL
differential voltage
[1:0]
OUT0 power-down
4
OUT1 invert
[3:2]
OUT1 LVPECL
differential voltage
[1:0]
OUT1 power-down
4
OUT2 invert
[3:2]
OUT2 LVPECL
differential voltage
[1:0]
OUT2 power-down
Description
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400.
0
1
600.
1
0
780 (default).
1
1
960.
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation (default).
0
1
Partial power-down, reference on; use only if there are no external load resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down.
1
1
Total power-down, reference off; use only if there are no external load resistors.
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400.
0
1
600.
1
0
780 (default).
1
1
960.
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation.
0
1
Partial power-down, reference on; use only if there are no external load resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down (default).
1
1
Total power-down, reference off; use only if there are no external load resistors.
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400.
0
1
600.
1
0
780 (default).
1
1
960.
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation (default).
0
1
Partial power-down, reference on; use only if there are no external load resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down.
1
1
Total power-down, reference off; use only if there are no external load resistors.
Rev. C | Page 54 of 64
Output
On
Off
Off
Off
Output
On
Off
Off
Off
Output
On
Off
Off
Off
Data Sheet
Reg.
Addr.
(Hex)
0x0F3
0x0F4
0x0F5
Bits
4
Name
OUT3 invert
[3:2]
OUT3 LVPECL
differential voltage
[1:0]
OUT3 power-down
4
OUT4 invert
[3:2]
OUT4 LVPECL
differential voltage
[1:0]
OUT4 power-down
4
OUT5 invert
[3:2]
OUT5 LVPECL
differential voltage
[1:0]
OUT5 power-down
AD9518-0
Description
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400.
0
1
600.
1
0
780 (default).
1
1
960.
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation.
0
1
Partial power-down, reference on; use only if there are no external load resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down (default).
1
1
Total power-down, reference off; use only if there are no external load resistors.
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400.
0
1
600.
1
0
780 (default).
1
1
960.
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation (default).
0
1
Partial power-down, reference on; use only if there are no external load resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down.
1
1
Total power-down, reference off; use only if there are no external load resistors.
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400.
0
1
600.
1
0
780 (default).
1
1
960.
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation.
0
1
Partial power-down, reference on; use only if there are no external load resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down (default).
1
1
Total power-down, reference off; use only if there are no external load resistors.
Rev. C | Page 55 of 64
Output
On
Off
Off
Off
Output
On
Off
Off
Off
Output
On
Off
Off
Off
AD9518-0
Data Sheet
Table 46. LVPECL Channel Dividers
Reg.
Addr.
(Hex)
0x190
0x191
0x192
0x193
0x194
Bits
[7:4]
Name
Divider 0 low cycles
[3:0]
Divider 0 high cycles
7
Divider 0 bypass
6
Divider 0 nosync
5
Divider 0 force high
4
Divider 0 start high
[3:0]
1
Divider 0 phase offset
Divider 0 direct to output
0
Divider 0 DCCOFF
[7:4]
Divider 1 low cycles
[3:0]
Divider 1 high cycles
7
Divider 1 bypass
6
Divider 1 nosync
5
Divider 1 force high
4
Divider 1 start high
[3:0]
Divider 1 phase offset
Description
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that the Divider 0 nosync bit (Bit 6) also be set.
This bit has no effect if the Divider 0 bypass bit (Bit 7) is set.
0: divider output forced to low (default).
1: divider output forced to high.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Connects OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0xB).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0xB).
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that the Divider 1 nosync bit (Bit 6) also be set.
This bit has no effect if the Divider 1 bypass bit (Bit 7) is set.
0: divider output forced to low (default).
1: divider output forced to high.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Rev. C | Page 56 of 64
Data Sheet
Reg.
Addr.
(Hex)
0x195
0x196
0x197
0x198
Bits
1
Name
Divider 1 direct to output
0
Divider 1 DCCOFF
[7:4]
Divider 2 low cycles
[3:0]
Divider 2 high cycles
7
Divider 2 bypass
6
Divider 2 nosync
5
Divider 2 force high
4
Divider 2 start high
[3:0]
1
Divider 2 phase offset
Divider 2 direct to output
0
Divider 2 DCCOFF
AD9518-0
Description
Connects OUT2 and OUT3 to Divider 1 or directly to VCO or CLK.
0: OUT2 and OUT3 are connected to Divider 1 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses and powers down the divider; route input to divider output.
0: uses divider (default).
1: bypasses divider.
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that the Divider 2 nosync bit (Bit 6) also be set.
This bit has no effect if the Divider 2 bypass bit (Bit 7) is set.
0: divider output forced to low (default).
1: divider output forced to high.
Select clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Connects OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.
0: OUT4 and OUT5 are connected to Divider 2 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Table 47. VCO Divider and CLK Input
Reg.
Addr.
(Hex)
0x1E0
Bits
[2:0]
Name
VCO divider
Description
2
1 0
0
0 0
0
0 1
0
1 0
0
1 1
1
0 0
1
0 1
1
1
0
1
1
1
Divide
2.
3.
4 (default).
5.
6.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Rev. C | Page 57 of 64
AD9518-0
Reg.
Addr.
(Hex)
0x1E1
Data Sheet
Bits
4
Name
Power down clock input section
3
Power down VCO clock interface
2
Power down VCO and CLK
1
Select VCO or CLK
0
Bypass VCO divider
Description
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
Powers down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
Powers down both VCO and CLK input.
0; normal operation (default).
1: power-down.
Selects either the VCO or the CLK as the input to VCO divider.
0: selects external CLK as input to VCO divider (default).
1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider; cannot select VCO as input when this is selected.
Table 48. System
Reg.
Addr.
(Hex)
0x230
Bits
2
Name
Power down SYNC
1
Power down distribution
reference
0
Soft sync
Description
Powers down the sync function.
0: normal operation of the sync function (default).
1: powers down sync circuitry.
Powers down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
The soft sync bit works the same as the SYNC pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a sync.
0: same as SYNC high (default).
1: same as SYNC low.
Table 49. Update All Registers
Reg.
Addr.
(Hex)
0x232
Bits
0
Name
Update all registers
Description
This bit must be set to 1b to transfer the contents of the buffer registers into the active
registers. This bit is self-clearing; that is, it does not have to be set back to 0b.
1 (self-clearing): updates all active registers to the contents of the buffer registers.
Rev. C | Page 58 of 64
Data Sheet
AD9518-0
APPLICATIONS INFORMATION
Within the AD9518 family, lower VCO frequencies generally
result in slightly lower jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency is
usually less than 150 fs over the entire VCO frequency range
(1.45 GHz to 2.95 GHz) of the AD9518 family. If the desired
frequency plan can be achieved with a version of the AD9518
that has a lower VCO frequency, choosing the lower frequency
part results in the lowest phase noise and the lowest jitter.
However, choosing a higher VCO frequency may result in more
flexibility in frequency planning.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current and, thus, allows the designer
to fine-tune the PLL loop bandwidth in either direction.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com. It is a very accurate tool for
determining the optimal loop filter for a given application.
USING THE AD9518 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock.




where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Figure 52 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
110
18
1
SNR = 20log 2πf t
A J
100
16
90
tJ =
100
fS
200
f
80
14
S
400
f
70
12
S
1ps
60
2ps
10
10p
s
8
ENOB
The AD9518 has the following four frequency dividers: the
reference (or R) divider, the feedback (or N) divider, the VCO
divider, and the channel divider. When trying to achieve a
particularly difficult frequency divide ratio requiring a large
amount of frequency division, some of the frequency division
can be done by either the VCO divider or the channel divider,
thus allowing a higher phase detector frequency and more
flexibility in choosing the loop bandwidth.
 1
SNR(dB) = 20 × log 
 2πf t
A J

50
40
6
30
10
100
1k
fA (MHz)
06429-044
The AD9518 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9518, keep in mind the following
guidelines.
Considering an ideal ADC of infinite resolution where the step
size and quantization error can be ignored, the available SNR
can be expressed approximately by
SNR (dB)
FREQUENCY PLANNING USING THE AD9518
Figure 52. SNR and ENOB vs. Analog Input Frequency
For more information, see the AN-756 Application Note, Sampled
Systems and the Effects of Clock Phase Noise and Jitter; and the
AN-501 Application Note, Aperture Uncertainty and ADC System
Performance, at www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
may result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can provide
superior clock performance in a noisy environment.) The AD9518
features LVPECL outputs that provide differential clock outputs,
which enable clock solutions that maximize converter SNR
performance. The input requirements of the ADC (differential
or single-ended, logic level, termination) should be considered
when selecting the best clocking/converter solution.
Rev. C | Page 59 of 64
AD9518-0
Data Sheet
LVPECL CLOCK DISTRIBUTION
VS_LVPECL
In most applications, an LVPECL far-end Thevenin termination
(see Figure 53) or Y-termination (see Figure 54) is recommended.
In each case, the VS of the receiving buffer should match the
VS_LVPECL voltage. If it does not, ac coupling is recommended (see
Figure 55). In the case of Figure 55, pull-down resistors of <150 Ω
are not recommended when VS_LVPECL = 3.3 V; if used, damage to
the LVPECL drivers may result. The minimum recommended
pull-down resistor size for VS_LVPECL = 2.5 V is 100 Ω.
The resistor network is designed to match the transmission line
impedance (50 Ω) and the switching threshold (VS − 1.3 V).
VS_DRV
127Ω
127Ω
SINGLE-ENDED
(NOT COUPLED)
50Ω
VS
LVPECL
83Ω
83Ω
06429-145
LVPECL
50Ω
Figure 53. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
VS_LVPECL
VS = 3.3V
LVPECL
Z0 = 50Ω
50Ω
100Ω DIFFERENTIAL
100Ω
(COUPLED)
0.1nF TRANSMISSION LINE
LVPECL
200Ω
Figure 55. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
shown in Figure 54, where VS_LVPECL = 2.5 V, the 50 Ω termination
resistor that is connected to ground should be changed to 19 Ω.
Thevenin-equivalent termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below VOL of the LVPECL
driver. In this case, VS_LVPECL on the AD9518 should equal VS of
the receiving buffer. Although the resistor combination shown
in Figure 54 results in a dc bias point of VS_LVPECL − 2 V, the actual
common-mode voltage is VS_LVPECL − 1.3 V because there is
additional current flowing from the AD9518 LVPECL driver
through the pull-down resistor.
The circuit is identical when VS_LVPECL = 2.5 V, except that the pulldown resistor is 62.5 Ω and the pull-up resistor is 250 Ω.
50Ω
50Ω
200Ω
LVPECL
06429-147
Z0 = 50Ω
LVPECL
06429-146
The LVPECL outputs (because they are open emitter) require
a dc termination to bias the output transistors. The simplified
equivalent circuit in Figure 43 shows the LVPECL output stage.
VS_LVPECL
VS
0.1nF
Figure 54. DC-Coupled 3.3 V LVPECL Y-Termination
Rev. C | Page 60 of 64
Data Sheet
AD9518-0
OUTLINE DIMENSIONS
0.30
0.23
0.18
0.60 MAX
0.60 MAX
37
36
PIN 1
INDICATOR
6.85
6.75 SQ
6.65
48
0.50
REF
(BOTTOM VIEW)
1.00
0.85
0.80
12° MAX
0.80 MAX
0.65 TYP
0.50
0.40
0.30
13
12
0.22 MIN
5.50 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PIN 1
INDICATOR
*5.55
5.50 SQ
5.45
EXPOSED
PAD
25
24
TOP VIEW
1
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
02-23-2010-C
7.10
7.00 SQ
6.90
Figure 56. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9518-0ABCPZ
AD9518-0ABCPZ-RL7
AD9518-0A/PCBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
Z = RoHS Compliant Part.
Rev. C | Page 61 of 64
Package Option
CP-48-8
CP-48-8
AD9518-0
Data Sheet
NOTES
Rev. C | Page 62 of 64
Data Sheet
AD9518-0
NOTES
Rev. C | Page 63 of 64
AD9518-0
Data Sheet
NOTES
©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06429-0-1/12(C)
Rev. C | Page 64 of 64