TI1 BQ29732DSET Cost-effective voltage and current protection integrated circuit Datasheet

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bq2970, bq2971, bq2972, bq2973
SLUSBU9C – MARCH 2014 – REVISED MARCH 2016
bq297xx Cost-Effective Voltage and Current Protection Integrated Circuit for Single-Cell
Li-Ion and Li-Polymer Batteries
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
Input Voltage Range Pack+: VSS – 0.3 V to 12 V
FET Drive:
– CHG and DSG FET Drive Output
Voltage Sensing Across External FETs for
Overcurrent Protection (OCP) Is Within ± 5 mV
(Typical)
Fault Detection
– Overcharge Detection (OVP)
– Over-Discharge Detection (UVP)
– Charge Overcurrent Detection (OCC)
– Discharge Overcurrent Detection (OCD)
– Load Short-Circuit Detection (SCP)
Zero Voltage Charging for Depleted Battery
Factory Programmed Fault Protection Thresholds
– Fault Detection Voltage Thresholds
– Fault Trigger Timers
– Fault Recovery Timers
Modes of Operation Without Battery Charger
Enabled
– NORMAL Mode ICC = 4 µA
– Shutdown Iq = 100 nA
Operating Temperature Range TA = –40°C to
+85°C
Package:
– 6-Pin DSE (1.50 mm × 1.50 mm × 0.75 mm)
Simplified Schematic
Tablet PC
Mobile Handset
Handheld Data Terminals
3 Description
The bq2970 battery cell protection device provides an
accurate monitor and trigger threshold for overcurrent
protection during high discharge/charge current
operation or battery overcharge conditions.
The bq2970 device provides the protection functions
for Li-Ion/Li-Polymer cells, and monitors across the
external power FETs for protection due to high
charge or discharge currents. In addition, there is
overcharge and depleted battery monitoring and
protection. These features are implemented with low
current consumption in NORMAL mode operation.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
bq2970, bq2971,
bq2972, bq2973 (2)
WSON (6)
1.50 mm × 1.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) For available released devices, see the Released Device
Configurations table.
OCD Detection Accuracy Versus Temperature
0.0
2.2k
V–
COUT
BAT
DOUT
VSS
330
0.1 µF
NC
CELLP
CELLN
PACK–
D
S
CHG
S
DSG
OCD Detection Accuracy (mV)
PACK +
±0.5
±1.0
±1.5
±2.0
±2.5
±3.0
±3.5
±4.0
±40
±20
0
20
40
60
Temperature (ƒC)
80
100
120
C012
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
bq2970, bq2971, bq2972, bq2973
SLUSBU9C – MARCH 2014 – REVISED MARCH 2016
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Configurations...........................................
Pin Configuration and Functions .........................
1
1
1
2
3
4
6.1 Pin Descriptions ........................................................ 4
7
Specifications......................................................... 5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
DC Characteristics ....................................................
Programmable Fault Detection Thresholds .............
Programmable Fault Detection Timer Ranges ........
Typical Characteristics ..............................................
5
5
5
5
6
6
7
7
Parameter Measurement Information ................ 11
8.1 Timing Charts.......................................................... 11
8.2 Test Circuits ............................................................ 13
8.3 Test Circuit Diagrams ............................................. 15
9
Detailed Description ............................................ 15
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description ................................................
Device Functional Modes........................................
15
16
16
16
10 Applications and Implementation...................... 20
10.1 Application Information.......................................... 20
10.2 Typical Application ................................................ 20
11 Power Supply Recommendations ..................... 23
12 Layout................................................................... 23
12.1 Layout Guidelines ................................................ 23
12.2 Layout Example .................................................... 23
13 Device and Documentation Support ................. 24
13.1
13.2
13.3
13.4
13.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
14 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November, 2015) to Revision C
Page
•
Added the device numbers bq2971, bq2972, bq2973. Changed document title to bq297xx................................................. 1
•
Added bq29708~bq29733 to Device Configurations table. Clarified recovery delay and moved info to footnote 2 .............. 3
•
Changed UVP release voltage value based on 100mV hysteresis from UVP threshold ..................................................... 20
•
Added Related Links table.................................................................................................................................................... 24
Changes from Revision A (June, 2014) to Revision B
Page
•
Changed the device number to bq2970 ................................................................................................................................ 1
•
Deleted the Related Links table from the Device and Documentation Support section....................................................... 24
Changes from Original (March, 2014) to Revision A
Page
•
Changed part number in document to "bq297xy" from "bq29700"......................................................................................... 1
•
Added notes to see the orderable addendum and Released Device Configurations table ................................................... 1
•
Added Device Configurations table for part numbers bq29700 through bq29707 ................................................................. 3
•
Changed Terminal to Pin ....................................................................................................................................................... 4
•
Added ohm symbol to value .................................................................................................................................................. 6
•
Changed "RANGE" to "CONDITION" and "ACCURACY" to "MIN, TYP, and MAX" column headings ................................ 6
•
Added prefix "Factory Device Configuration:" ....................................................................................................................... 6
•
Added Factory Programmable Options reference ............................................................................................................... 15
•
Added Factory Programmable Options table ....................................................................................................................... 15
2
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SLUSBU9C – MARCH 2014 – REVISED MARCH 2016
5 Device Configurations
PART
NUMBER (1)
OVP (V)
OVP
DELAY (s)
UVP (V)
UVP
DELAY
(ms)
OCC (V)
OCC
DELAY
(ms)
OCD (V)
OCD
DELAY
(ms)
SCD (V)
SCD DELAY
(µs)
bq29700
4.275
1.25
2.800
144
-0.100
8
0.100
20
0.5
250
bq29701
4.280
1.25
2.300
144
-0.100
8
0.125
8
0.5
250
bq29702
4.350
1
2.800
96
-0.155
8
0.160
16
0.3
250
bq29703
4.425
1.25
2.300
20
-0.100
8
0.160
8
0.5
250
bq29704
4.425
1.25
2.500
20
-0.100
8
0.125
8
0.5
250
bq29705
4.425
1.25
2.500
20
-0.100
8
0.150
8
0.5
250
bq29706
3.850
1.25
2.500
144
-0.150
8
0.200
8
0.6
250
bq29707
4.280
1
2.800
96
-0.090
6
0.090
16
0.3
250
bq29708 (2)
4.350
0.25
2.300
20
-0.100
8
0.200
20
0.5
250
bq29709 (2)
4.325
1.25
2.500
144
-0.100
8
0.150
8
0.5
250
bq29710 (2)
4.300
1.25
2.300
144
-0.100
8
0.130
8
0.5
250
bq29711 (2)
4.300
1.25
2.100
144
-0.100
8
0.130
8
0.5
250
bq29712 (2)
4.350
1.25
2.300
20
-0.100
8
0.130
8
0.5
250
bq29713 (2)
4.350
1.25
2.100
144
-0.100
8
0.120
8
0.5
250
bq29714 (2)
4.350
1.25
2.100
144
-0.100
8
0.150
8
0.5
250
bq29715 (2)
4.375
1.25
2.500
144
-0.100
8
0.120
20
0.5
250
bq29716
4.425
1.25
2.300
20
-0.100
8
0.165
8
0.5
250
bq29717
4.425
1.25
2.500
20
-0.100
8
0.130
8
0.5
250
bq29718
4.425
1.25
2.500
20
-0.100
8
0.100
8
0.5
250
bq29719 (2)
4.425
1.25
2.800
20
-0.100
8
0.120
8
0.5
250
bq29720 (2)
4.425
1.25
2.500
144
-0.100
8
0.100
8
0.5
250
(2)
4.425
1.25
2.500
144
-0.100
8
0.130
8
0.5
250
bq29722 (2)
4.425
1
2.500
20
-0.100
8
0.100
8
0.5
250
bq29723
4.425
1
2.500
96
-0.060
4
0.100
8
0.3
250
bq29724 (2)
4.425
1.25
2.500
20
-0.100
8
0.150
8
0.5
250
bq29725 (2)
4.275
1.25
2.300
144
-0.100
8
0.100
8
0.5
250
bq29726 (2)
4.280
1.25
2.300
144
-0.100
8
0.100
8
0.5
250
bq29727 (2)
4.280
1.25
2.300
144
-0.100
8
0.130
8
0.5
250
bq29728 (2)
4.280
1.25
2.800
144
-0.100
8
0.150
8
0.5
250
bq29729
4.275
1.25
2.300
20
-0.100
8
0.130
8
0.5
250
bq29730 (2)
4.280
1.25
2.800
144
-0.100
8
0.100
8
0.5
250
bq29731 (2)
4.280
1.25
2.800
144
-0.100
8
0.150
20
0.5
250
bq29732
4.280
1.25
2.500
144
-0.100
8
0.190
8
0.5
250
bq29733 (2)
4.400
1.25
2.800
20
-0.100
8
0.120
8
0.3
250
bq297xy
3.85 ~ 4.6
0.25, 1,
1.25, 4.5
2.0 ~ 2.8
20, 96, 125,
144
-0.045 ~ 0.155
4, 6, 8, 16
0.090 ~
0.200
8, 16, 20,
48
0.3, 0.4,
0.5, 0.6
250
bq29721
(1)
(2)
All the protections have a recovery delay time. The recovery timer starts as soon as the fault is triggered. The device will start to check
for recovery condition only when the recovery timer expires. This is NOT a delay time between recovery condition to FETs recovery.
OVP recovery delay = 12ms; UVP/OCC/OCD recovery delay = 8ms.
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6 Pin Configuration and Functions
DSE Package
6-PIN WSON
Top View
NC
1
6
V–
COUT
2
5
BAT
DOUT
3
4
VSS
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
BAT
5
P
VDD pin
COUT
2
O
Gate Drive Output for Charge FET
DOUT
3
O
Gate Drive Output for Discharge FET
NC
1
NC
VSS
4
P
V–
6
I/O
No Connection (electrically open, do not connect to BAT or VSS)
Ground pin
Input pin for charger negative voltage
6.1 Pin Descriptions
6.1.1 Supply Input: BAT
This pin is the input supply for the device and is connected to the positive terminal of the battery pack. There is a
0.1-µF input capacitor to ground for filtering noise.
6.1.2 Cell Negative Connection: VSS
This pin is an input to the device for cell negative ground reference. Internal circuits associated with cell voltage
measurements and overcurrent protection input to differential amplifier for either Vds sensing or external sense
resistor sensing will be referenced to this node.
6.1.3 Voltage Sense Node: V–
This is a sense node used for measuring several fault detection conditions, such as overcurrent charging or
overcurrent discharging configured as Vds sensing for protection. This input, in conjunction with VSS, forms the
differential measurement for the stated fault detection conditions. A 2.2-kΩ resistor is connected between this
input pin and Pack– terminal of the system in the application.
6.1.4 Discharge FET Gate Drive Output: DOUT
This pin is an output to control the discharge FET. The output is driven from an internal circuitry connected to the
BAT supply. This output will transition from high to low when a fault is detected, and requires the DSG FET to
turn OFF. A high impedance resistor of 5 MΩ is connected from DOUT to VSS for gate capacitance discharge
when the FET is turned OFF.
6.1.5 Charge FET Gate Drive Output: COUT
This pin is an output to control the charge FET. The output is driven from an internal circuitry connected to the
BAT supply. This output transitions from high to low when a fault is detected, and requires the CHG FET to turn
OFF. A high impedance resistor of 5 MΩ is connected from COUT to Pack– for gate capacitance discharge when
FET is turned OFF.
4
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7 Specifications
7.1 Absolute Maximum Ratings (1)
Supply control and input
MIN
MAX
UNIT
–0.3
12
V
V– pin(pack–)
BAT – 28
BAT + 0.3
V
DOUT (Discharge FET Output), GDSG (Discharge FET Gate Drive)
VSS – 0.3
BAT + 0.3
V
BAT – 28
BAT + 0.3
V
–40
85
°C
–55
150
°C
Input voltage: BAT
FET drive and protection COUT (Charge FET Output), GCHG (Charge FET Gate Drive)
Operating temperature: TFUNC
Storage temperature, Tstg
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
VESD (1)
(1)
(2)
(3)
Electrostatic
Discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (2)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (3)
±500
UNIT
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 1000 V
may have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V
may have higher performance.
7.3 Recommended Operating Conditions (1)
MIN
MAX
UNIT
Supply control and
input
Positive input voltage: BAT
–0.3
8
V
Negative input voltage: V–
BAT – 25
BAT
V
FET drive and
protection
Discharge FET control: DOUT
VSS
BAT
V
Charge FET control: COUT
BAT – 25
BAT
V
Operating temperature: TAmb
–40
85
°C
Storage temperature: TS
–55
150
°C
300
°C
250
°C/W
Temperature Ratings
Lead temperature (soldering 10 s)
Thermal resistance junction to ambient, θJA
(1)
(1)
For more information about traditional and new thermal metrics, see the IC package Thermal Metrics application report, SPRA953.
7.4 Thermal Information
bq297xx
THERMAL METRIC (1)
DSE (WSON)
UNIT
12 PINS
RθJA, High K
Junction-to-ambient thermal resistance (2)
190.5
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance (3)
94.9
°C/W
RθJB
Junction-to-board thermal resistance (4)
149.3
°C/W
(1)
(2)
(3)
(4)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
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Thermal Information (continued)
bq297xx
THERMAL METRIC (1)
DSE (WSON)
UNIT
12 PINS
ψJT
Junction-to-top characterization parameter (5)
6.4
°C/W
ψJB
Junction-to-board characterization parameter (6)
152.8
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance (7)
N/A
°C/W
(5)
(6)
(7)
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
7.5 DC Characteristics
Typical Values stated where TA = 25°C and BAT = 3.6 V. Min/Max values stated where TA = –40°C to 85°C, and BAT = 3 V
to 4.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
CURRENT CONSUMPTION
BAT – VSS
1.5
8
BAT – V–
1.5
28
VBAT
Device operating range
INORMAL
Current consumption in NORMAL mode
BAT = 3.8 V, V– = 0 V
IPower_down
Current consumption in power down mode
BAT = V– = 1.5 V
4
V
5.5
µA
0.1
µA
0.5
V
FET OUTPUT, DOUT and COUT
VOL
Charge FET low output
IOL = 30 µA, BAT = 3.8 V
0.4
VOH
Charge FET high output
IOH = –30 µA, BAT = 3.8 V
VOL
Discharge FET low output
IOL = 30 µA, BAT = 2 V
VOH
Discharge FET high output
IOH = –30 µA, BAT = 3.8 V
3.4
3.7
VBAT = 1.8 V, V– = 0 V
100
300
3.4
3.7
V
0.2
0.5
V
V
PULL UP INTERNAL RESISTANCE ON V–
RV–D
Resistance between V– and VBAT
550
kΩ
24
µA
CURRENT SINK ON V–
IV–S
Current sink on V– to VSS
VBAT = 3.8 V
8
LOAD SHORT DETECTION ON V–
Vshort
Short detection voltage
VBAT = 3.8 V and RPackN = 2.2 kΩ
VBAT – 1 V
V
0-V BATTERY CHARGE FUNCTION
V0CHG
0-V battery charging starter voltage
0-V battery charging function allowed
V0INH
0-V battery charging inhibit voltage
0-V battery charging function disallowed
1.7
V
0.75
V
7.6 Programmable Fault Detection Thresholds
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
TA = 25°C
–10
10
mV
VOVP
Overcharge detection voltage
Factory Device Configuration: 3.85 V to
4.60 V in 50-mV steps
TA = 0°C to
60°C
–20
20
mV
VOVP–Hys
Overcharge release hysteresis
voltage
100 mV and (VSS – V–) > OCC (min) for release, TA =
25°C
–20
20
mV
VUVP
Over-discharge detection
voltage
Factory Device Configuration: 2.00 V to 2.80 V in 50-mV
steps, TA = 25°C
–50
50
mV
VUVP+Hys
Over-discharge release
hysteresis voltage
100 mV and (BAT – V–) > 1 V for release, TA = 25°C
–50
50
mV
Discharging overcurrent
detection voltage
Factory Device Configuration: 90 mV to
200 mV in 5-mV steps
TA = 25°C
–10
10
mV
VOCD
TA = –40°C to
85°C
–15
15
mV
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Programmable Fault Detection Thresholds (continued)
PARAMETER
CONDITION
MIN
Release of
VOCD
Release of discharging
overcurrent detection voltage
VOCC
TA = 25°C
Charging overcurrent detection Factory Device Configuration: –45 mV to
TA = –40°C to
voltage
–155 mV in 5-mV steps
85°C
Release of
VOCC
Release of overcurrent
detection voltage
Release when VSS – V– ≥ OCC (min)
VSCC
Short Circuit detection voltage
Factory Device Configuration: 300 mV,
400 mV, 500 mV, 600 mV
VSCCR
Release of Short Circuit
detection voltage
Release when BAT – V– ≥ 1 V
TYP
Release when BAT – V– > 1 V
MAX
1
V
–10
10
mV
–15
15
mV
40
TA = 25°C
UNIT
mV
–100
100
1
mV
V
7.7 Programmable Fault Detection Timer Ranges
MAX
UNIT
tOVPD
Overcharge detection delay time
PARAMETER
Factory Device Configuration: 0.25 s, 1 s, 1.25 s, 4.5 s
CONDITION
–20%
MIN
20%
s
tUVPD
Over-discharge detection delay
time
Factory Device Configuration: 20 ms, 96 ms, 125 ms, 144
ms
–20%
20%
ms
tOCDD
Discharging overcurrent detection
Factory Device Configuration: 8 ms, 16 ms, 20 ms, 48 ms
delay time
–20%
20%
ms
tOCCD
Charging overcurrent detection
delay time
–20%
20%
ms
tSCCD
Short Circuit detection delay time 250 µs (fixed)
–50%
50%
µs
100
120
Factory Device Configuration: 4 ms, 6 ms, 8 ms, 16 ms
TYP
7.8 Typical Characteristics
6
0.050
Current Consumption ( A)
Current Consumption ( A)
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
5
4
3
2
1
0.005
0
0.000
±40
±20
0
20
40
60
80
100
Temperature (ƒC)
120
±40
±20
0
20
40
60
80
Temperature (ƒC)
C001
C002
VBAT = 3.9 V
VBAT = 1.5 V
Figure 1. 1.5-V IBAT Versus Temperature
Figure 2. 3.9-V IBAT Versus Temperature
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1.34
±1.32
1.32
±1.34
V(±) ± BAT Voltage (V)
Internal Oscillator Frequency (kHz)
Typical Characteristics (continued)
1.30
1.28
1.26
1.24
1.22
±1.36
±1.38
±1.40
±1.42
±1.44
1.20
1.18
±1.46
±40
±20
0
20
40
60
80
100
Temperature (ƒC)
120
±40
BAT ± VSS Voltage (V)
0.70
0.65
0.60
0.55
0.50
0.45
0.40
20
40
60
40
60
80
100
120
C004
Figure 4. 0-V Charging Allowed Versus Temperature
OVP Deetction Threshold Accuracy (mV)
0.75
0
20
VBAT, Setting = 0 V
Figure 3. Internal Oscillator Frequency Versus Temperature
±20
0
Temperature (ƒC)
FOSC, Setting = 1.255 kHz
±40
±20
C003
80
100
Temperature (ƒC)
4
2
0
±2
±4
±6
±8
±10
±12
120
±40
±20
0
20
40
60
80
100
Temperature (ƒC)
C005
120
C006
OVP, Setting = 4.275 V
Figure 5. 0-V Charging Disallowed Versus Temperature
UVP Detection Accuracy Threshold (mV)
OVP Detection Delay Time (ms)
1350
1300
1250
1200
1150
1100
±40
±20
0
20
40
60
Temperature (ƒC)
80
100
120
±2
±4
±6
±8
±10
±12
±40
±20
0
20
40
60
Temperature (ƒC)
80
100
120
C008
UVP, Setting = 2.800 V
Figure 7. OVP Detection Dely Time Versus Temperature
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C007
tOVPD, Setting = 1.25 s
8
Figure 6. OVP Detection Accuracy Versus Temperature
Figure 8. UVP Detection Accuracy Versus Temperature
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Typical Characteristics (continued)
0.0
OCC Detection Accuracy (mV)
UVP Detection Delay Time (ms)
160
155
150
145
140
135
130
±0.2
±0.4
±0.6
±0.8
±1.0
±1.2
±1.4
±1.6
±1.8
±40
±20
0
20
40
60
80
100
Temperature (ƒC)
120
±40
20
40
60
80
100
120
C010
VOCC, Setting = –100 mV
Figure 9. UVP Detection Delay Time Versus Temperature
Figure 10. OCC Detection Accuracy Versus Temperature
8.6
0.0
8.4
±0.5
OCD Detection Accuracy (mV)
OCC Detection Delay Time (ms)
0
Temperature (ƒC)
tUVPD, Setting = 144 ms
8.2
8.0
7.8
7.6
7.4
7.2
7.0
±1.0
±1.5
±2.0
±2.5
±3.0
±3.5
±4.0
±40
±20
0
20
40
60
80
100
Temperature (ƒC)
120
±40
±20
0
20
40
60
80
100
Temperature (ƒC)
C011
tOCCD, Setting = 8 ms
120
C012
VOCD, Setting = 100 mV
Figure 11. OCC Detection Delay Time Versus Temperature
Figure 12. OCD Detection Accuracy Versus Temperature
22.5
4.5
22.0
4.0
SCC Detection Accuracy (mV)
OCD Detection Delay Time (ms)
±20
C009
21.5
21.0
20.5
20.0
19.5
19.0
18.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
±40
±20
0
20
40
60
Temperature (ƒC)
80
100
120
±40
±20
0
tUVPD, Setting = 20 ms
Figure 13. OCD Detection Delay Time Versus Temperature
20
40
60
80
100
Temperature (ƒC)
C013
120
C014
VSCC, Setting = 500 mV
Figure 14. SCC Detection Accuracy Versus Temperature
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1.24
3.795
1.22
3.790
1.20
3.785
1.18
VOH (V)
Power On Reset Threshold (V)
Typical Characteristics (continued)
1.16
3.780
3.775
1.14
3.770
1.12
1.10
3.765
±40
±20
0
20
40
60
80
100
120
Temperature (ƒC)
±40
±20
0
20
40
60
Temperature (ƒC)
C015
80
100
120
C016
VBAT, Setting = 3.9 V
Figure 15. Power On Reset Versus Temperature
Figure 16. COUT Versus Temperature with Ioh = –30 µA
3.7160
VOH (V)
3.7155
3.7150
3.7145
3.7140
3.7135
±40
±20
0
20
40
60
80
100
Temperature (ƒC)
120
C017
VBAT, Setting = 3.9 V
Figure 17. DOUT Versus Temperature with Ioh = –30 µA
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8 Parameter Measurement Information
8.1 Timing Charts
Normal
Overcharge
Normal
OverDischarge
Normal
DOUT
BAT
VOVP
VOVP– Hys
VUVP – Hys
VUVP
BAT
COUT
VSS
BAT
VSS
V–
PACK–
BAT
VOCD
VSS
PACK–
t UVPD
tOVPD
Charger
Connected
Load
Connected
Charger
Connected
Figure 18. Overcharge Detection, Over-Discharge Detection
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Timing Charts (continued)
Normal
Discharge Overcurrent
Normal
Discharge Overcurrent
Normal
BAT
VOVP
VOVP–Hys
VUVP+Hys
DOUT
VUVP
BAT
COUT
VSS
BAT
VSS
V–
PACK–
BAT
VSCC
VOCD
VSS
t OCDD
t SCCD
Load
Connected
Load
Disconnected
Load ShortCircuit
Figure 19. Discharge Overcurrent Detection
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8.2 Test Circuits
The following tests are referenced as follows: The COUT and DOUT outputs are “H,” which are higher than the
threshold voltage of the external logic level FETs and regarded as ON state. Conversely, “L” is less than the turn
ON threshold for external NMOS FETs and regarded as OFF state. The COUT pin is with respect to V–, and the
DOUT pin is with respect to VSS.
1. Overcharge detection voltage and overcharge release voltage (Test Circuit 1):
The overcharge detection voltage (VOVP) is measured between the BAT and VSS pins, respectively. Once V1
is increased, the over-detection is triggered, and the delay timer expires, COUT transitions from a high to low
state and then reduces the V1 voltage to check for the overcharge hysteresis parameter (VOVP-Hys). This delta
voltage between overcharge detection voltages (VOVP) and the overcharge release occurs when the CHG
FET drive output goes from low to high.
2. Over-discharge detection voltage and over-discharge release voltage (Test Circuit 2):
Over-discharge detection (VUVP) is defined as the voltage between BAT and VSS at which the DSG drive
output goes from high to low by reducing the V1 voltage. V1 is set to 3.5 V and gradually reduced while V2 is
set to 0 V. The over-discharge release voltage is defined as the voltage between BAT and VSS at which the
DOUT drive output transition from low to high when V1 voltage is gradually increased from a VUVP condition.
The overcharge hysteresis voltage is defined as the delta voltage between VUVP and the instance at which
the DOUT output drive goes from low to high.
3. Discharge overcurrent detection voltage (Test Circuit 2):
The discharge overcurrent detection voltage (VOCD) is measured between V– and VSS pins and triggered
when the V2 voltage is increased above VOCD threshold with respect to VSS. This delta voltage once
satisfied will trigger an internal timer tOCDD before the DOUT output drive transitions from high to low.
4. Load short circuit detection voltage (Test Circuit 2):
Load short-circuit detection voltage (VSCC) is measured between V– and VSS pins and triggered when the V2
voltage is increased above VSCC threshold with respect to VSS within 10 µs. This delta voltage, once
satisfied, triggers an internal timer tSCCD before the DOUT output drive transitions from high to low.
5. Charge overcurrent detection voltage (Test Circuit 2):
The charge overcurrent detection voltage (VOCC) is measured between VSS and V– pins and triggered when
the V2 voltage is increased above VOCC threshold with respect to V–. This delta voltage, once satisfied, l
triggers an internal timer tOCCD before the COUT output drive transitions from high to low.
6. Operating current consumption (Test Circuit 2):
The operating current consumption IBNORMAL is the current measured going into the BAT pin under the
following conditions: V1 = 3.9 V and V2 = 0 V.
7. Power down current consumption (Test Circuit 2):
The operating current consumption IPower_down is the current measured going into the BAT pin under the
following conditions: V1 = 1.5 V and V2 = 1.5 V.
8. Resistance between V– and BAT pin (Test Circuit 3):
Measure the resistance (RV_D) between V– and BAT pins by setting the following conditions: V1 = 1.8 V and
V2 = 0 V.
9. Current sink between V– and VSS (Test Circuit 3):
Measure the current sink IV–S between V– and VSS pins by setting the following condition: V1 = 4 V.
10. COUT current source when activated High (Test Circuit 4):
Measure ICOUT current source on the COUT pin by setting the following conditions: V1 = 3.9 V, V2 = 0 V and
V3 = 3.4 V.
11. COUT current sink when activated Low (Test Circuit 4):
Measure ICOUT current sink on COUT pin by setting the following conditions: V1 = 4.5 V, V2 = 0 V and V3 =
0.5 V.
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Test Circuits (continued)
12. DOUT current source when activated High (Test Circuit 4):
Measure IDOUT current source on DOUT pin by setting the following conditions: V1 = 3.9 V, V2 = 0 V and V3
= 3.4 V.
13. DOUT current sink when activated Low (Test Circuit 4):
Measure IDOUT current sink on DOUT pin by setting the following conditions: V1 = 2.0 V, V2 = 0 V and V3 =
0.4 V.
14. Overcharge detection delay (Test Circuit 5):
The overcharge detection delay time tOVPD is the time delay before the COUT drive output transitions from
high to low once the voltage on V1 exceeds the VOVP threshold. Set V2 = 0 V and then increase V1 until BAT
input exceeds the VOVP threshold and to check the time for when COUT goes from high to low.
15. Over-discharge detection delay (Test Circuit 5):
The over-discharge detection delay time tUVPD is the time delay before the DOUT drive output transitions
from high to low once the voltage on V1 decreases to VUVP threshold. Set V2 = 0 V and then decrease V1
until BAT input reduces to the VUVPthreshold and to check the time of when DOUT goes from high to low.
16. Discharge overcurrent detection delay (Test Circuit 5):
The discharge overcurrent detection delay time tOCDD is the time for DOUT drive output to transition from
high to low after the voltage on V2 is increased from 0 V to 0.35 V, with V1 = 3.5 V and V2 starts from 0 V
and increases to trigger threshold.
17. Load short circuit detection delay (Test Circuit 5):
The load short-circuit detection delay time tSCCD is the time for DOUT drive output to transition from high to
low after the voltage on V2 is increased from 0 V to V1 – 1 V, with V1 = 3.5 V and V2 starts from 0 V and
increases to trigger threshold.
18. Charge overcurrent detection delay (Test Circuit 5):
The charge overcurrent detection delay time tOCCD is the time for COUT drive output to transition from high to
low after the voltage on V2 is decreased from 0 V to –0.3 V, with V1 = 3.5 V and V2 starts from 0 V and
decreases to trigger threshold.
19. 0-V battery charge starting charger voltage (Test Circuit 2):
The 0-V charge for start charging voltage V0CHA is defined as the voltage between BAT and V– pins at which
COUT goes high when voltage on V2 is gradually decreased from a condition of V1 = V2 = 0 V.
20. 0-V battery charge inhibition battery voltage (Test Circuit 2):
The 0-V charge inhibit for charger voltage V0INH is defined as the voltage between BAT and VSS pins at
which COUT should go low as V1 is gradually decreased from V1 = 2 V and V2 = –4 V.
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8.3 Test Circuit Diagrams
V-
6
COUT
BAT
5
DOUT
VSS
4
1
NC
2
3
V-
6
COUT
BAT
5
DOUT
VSS
4
1
NC
2
3
I
BAT
220Ω
V
COUT
V
V
COUT
V
V1
V V
V2
A
V1
V V
DOUT
DOUT
Figure 20. Test Circuit 1
Figure 21. Test Circuit 2
I
V-
1
NC
V-
6
A
I
A
2 COUT
BAT
5
3 DOUT
VSS
4
I
A
V-
6
COUT
BAT
5
DOUT
VSS
4
1
NC
2
3
COUT
V2
BAT
V2
I
DOUT
V3
A
V1
V1
V4
Figure 22. Test Circuit 3
Figure 23. Test Circuit 4
NC
V-
6
2 COUT
BAT
5
3 DOUT
VSS
4
1
Oscilloscope
Oscilloscope
V2
V1
Figure 24. Test Circuit 5
9 Detailed Description
9.1 Overview
This bq2970 device is a primary protector for a single-cell Li-Ion/Li-Polymer battery pack. The device uses a
minimum number of external components to protect for overcurrent conditions due to high discharge/charge
currents in the application. In addition, it monitors and helps to protect against battery pack overcharging or
depletion of energy in the pack. The bq2970 device is capable of having an input voltage of 8 V from a charging
adapter and can tolerate a voltage of BAT – 25 V across the two input pins. In the condition when a fault is
triggered, there are timer delays before the appropriate action is taken to turn OFF either the CHG or DSG FETs.
There is also a timer delay for the recovery period once the threshold for recovery condition is satisfied. These
parameters are fixed once they are programmed. There is also a feature called zero voltage charging that
enables depleted cells to be charged to a acceptable level before the battery pack can be used for normal
operation. Zero voltage charging is allowed if the charger voltage is above 1.7 V. For Factory Programmable
Options, see Table 1.
Table 1. Factory Programmable Options
PARAMETER
FACTORY DEVICE CONFIGURATION
VOVP
Overcharge detection voltage
3.85 V to 4.60 V in 50-mV steps
VUVP
Over-discharge detection voltage
2.00 V to 2.80 V in 50-mV steps
VOCD
Discharging overcurrent detection voltage
90 mV to 200 mV in 5-mV steps
VOCC
Charging overcurrent detection voltage
–45 mV to –155 mV in 5-mV steps
VSCC
Short Circuit detection voltage
300 mV, 400 mV, 500 mV, 600 mV
tOVPD
Overcharge detection delay time
0.25s, 1.00s, 1.25s, 4.50 s
tUVPD
Over-discharge detection delay time
20 ms, 96 ms, 125 ms, 144 ms
tOCDD
Discharging overcurrent detection delay time
8 ms, 16 ms, 20 ms, 48 ms
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Overview (continued)
Table 1. Factory Programmable Options (continued)
PARAMETER
FACTORY DEVICE CONFIGURATION
tOCCD
Charging overcurrent detection delay time
4 ms, 6 ms, 8 ms, 16 ms
tSCCD
Short Circuit detection delay time
250 µs (fixed)
For available released devices, see the Released Device Configurations table.
9.2 Functional Block Diagram
Oscillator
BAT 5
Charger
Detection
Circuit
Counter
Logic circuit
Overcharge
Comparator (OVP)
with Hys
2 COUT
Overcharge
Current
Comparator
Delay
Short Detect
Over-Discharge
Comparator (UVP)
with Hys
Logic circuit
3 DOUT
Over-Discharge
Current Comparator
R V–D
VSS 4
BAT
6 V–
IV–S
9.3 Feature Description
The bq2970 family of devices measures voltage drops across several input pins for monitoring and detection of
the following faults: OCC, OCD, OVP, and UVP. An internal oscillator initiates a timer to the fixed delays
associated with each parameter once the fault is triggered. Once the timer expires due to a fault condition, the
appropriate FET drive output (COUT or DOUT) is activated to turn OFF the external FET. The same method is
applicable for the recovery feature once the system fault is removed and the recovery parameter is satisfied, then
the recovery timer is initiated. If there are no reoccurrences of this fault during this period, the appropriate gate
drive is activated to turn ON the appropriate external FET.
9.4 Device Functional Modes
9.4.1 Normal Operation
This device monitors the voltage of the battery connected between BAT pin and VSS pin and the differential
voltage between V– pin and VSS pin to control charging and discharging. The system is operating in NORMAL
mode when the battery voltage range is between the over-discharge detection threshold (VUVP) and the
overcharge detection threshold (VOVP), and the V– pin voltage is within the range for charge overcurrent
threshold (VOCC) to over-discharge current threshold (VOCD) when measured with respect to VSS. If these
conditions are satisfied, the device turns ON the drive for COUT and DOUT FET control.
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Device Functional Modes (continued)
CAUTION
When the battery is connected for the first time, the discharging circuit may not be
enabled. In this case, short the V– pin to the VSS pin.
Alternatively, connect the charger between the Pack+ and Pack– terminals in the
system.
9.4.2 Overcharge Status
This mode is detected when the battery voltage measured is higher than the overcharge detection threshold
(VOVP) during charging. If this condition exists for a period greater than the overcharge detection delay (tOVPD) or
longer, the COUT output signal is driven low to turn OFF the charging FET to prevent any further charging of the
battery.
The overcharge condition is released if one of the following conditions occurs:
• If the V– pin is higher than the overcharge detection voltage (VOCC_Min), the device releases the overcharge
status when the battery voltage drops below the overcharge release voltage (VOVP-Hys).
• If the V– pin is higher than or equal to the over-discharge detection voltage (VOCD), the device releases the
overcharge status when the battery voltage drops below the overcharge detection voltage (VOVP).
The discharge is initiated by connecting a load after the overcharge detection. The V– pin rises to a voltage
greater than VSS due to the parasitic diode of the charge FET conducting to support the load. If the V– pin
voltage is higher than or equal to the discharge overcurrent detection threshold (VOCD), the overcurrent condition
status is released only if the battery voltage drops lower than or equal to the overcharge detection voltage (VOVP).
CAUTION
1. If the battery is overcharged to a level greater than overcharge detection (VOVP) and the
battery voltage does not drop below the overcharge detection voltage (VOVP) with a heavy
load connected, the discharge overcurrent and load short-circuit detection features do not
function until the battery voltage drops below the overcharge detection voltage (VOVP). The
internal impedance of a battery is in the order of tens of mΩ, so application of a heavy load
on the output should allow the battery voltage to drop immediately, enabling discharge
overcurrent detection and load short-circuit detection features after an overcharge release
delay.
2. When a charger is connected after an overcharge detection, the overcharge status does not
release even if the battery voltage drops below the overcharge release threshold. The
overcharge status is released when the V– pin voltage exceeds the overcurrent detection
voltage (VOCD) by removing the charger.
9.4.3 Over-Discharge Status
If the battery voltage drops below the over-discharge detection voltage (VUVP) for a time greater than (tUVPD) the
discharge control output, DOUT is switched to a low state and the discharge FET is turned OFF to prevent
further discharging of the battery. This is referred to as an over-discharge detection status. In this condition, the
V– pin is internally pulled up to BAT by the resistor RV–D. When this occurs, the voltage difference between V–
and BAT pins is 1.3 V or lower, and the current consumption of the device is reduced to power-down level
ISTANDBY. The current sink IV–S is not active in power-down state or over-discharge state. The power-down state is
released when a charger is connected and the voltage delta between V– and BAT pins is greater than 1.3 V.
If a charger is connected to a battery in over-discharge state and the voltage detected at the V– is lower than
–0.7 V, the device releases the over-discharge state and allows the DOUT pin to go high and turn ON the
discharge FET once the battery voltage exceeds over-discharge detection voltage (VUVP).
If a charger is connected to a battery in over-discharge state and the voltage detected at the V– is higher than
–0.7 V, the device releases the over-discharge state and allows the DOUT pin to go high and turn ON the
discharge FET once the battery voltage exceeds over-discharge detection release hysteresis voltage (VUVP +Hys).
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Device Functional Modes (continued)
9.4.4 Discharge Overcurrent Status (Discharge Overcurrent, Load Short-Circuit)
When a battery is in normal operation and the V– pin is equal to or higher than the discharge overcurrent
threshold for a time greater than the discharge overcurrent detection delay, the DOUT pin is pulled low to turn
OFF the discharge FET and prevent further discharge of the battery. This is known as the discharge overcurrent
status. In the discharge overcurrent status, the V– and VSS pins are connected by a constant current sink IV–S.
When this occurs and a load is connected, the V– pin is at BAT potential. If the load is disconnected, the V– pin
goes to VSS (BAT/2) potential.
This device detects the status when the impedance between Pack+ and Pack– (see Figure 26) increases and is
equal to the impedance that enables the voltage at the V– pin to return to BAT – 1 V or lower. The discharge
overcurrent status is restored to the normal status.
Alternatively, by connecting the charger to the system, the device returns to normal status from discharge
overcurrent detection status, because the voltage at the V– pin drops to BAT – 1 V or lower.
The resistance RV–D between V– and BAT is not connected in the discharge overcurrent detection status.
9.4.5 Charge Overcurrent Status
When a battery is in normal operation status and the voltage at V– pin is lower than the charge overcurrent
detection due to high charge current for a time greater than charge overcurrent detection delay, the COUT pin is
pulled low to turn OFF the charge FET and prevent further charging to continue. This is known as charge
overcurrent status.
The device is restored to normal status from charge overcurrent status when the voltage at the V– pin returns to
charge overcurrent detection voltage or higher by removing the charger from the system.
The charge overcurrent detection feature does not work in the over-discharge status.
The resistance RV–D between V– and BAT and the current sink IV–S is not connected in the charge overcurrent
status.
9.4.6 0-V Charging Function (Available)
This feature enables recharging a connected battery that has very low voltage due to self-discharge. When the 0V battery charge starting charger voltage V0CHG or higher voltage is applied to Pack+ and Pack– connections by
the charger, the COUT pin gate drive is fixed by the BAT pin voltage.
Once the voltage between the gate and the source of the charging FET becomes equal to or greater than the
turn ON voltage due to the charger voltage, the charging FET is ON and the battery is charged with current flow
through the charging FET and the internal parasitic diode of the discharging FET. Once the battery voltage is
equal to or higher than the over-discharge release voltage, the device enters normal status.
CAUTION
1. Some battery providers do not recommend charging a depleted (self-discharged) battery.
Consult the battery supplier to determine whether to have the 0-V battery charger function.
2. The 0-V battery charge feature has a higher priority than the charge overcurrent detection
function. In this case, the 0-V charging will be allowed and the battery charges forcibly,
which results in charge overcurrent detection being disabled if the battery voltage is lower
than the over-discharge detection voltage.
9.4.7 0-V Charging Function (Unavailable)
This feature inhibits recharging a battery that has an internal short circuit of a 0-V battery. If the battery voltage is
below the charge inhibit voltage V0INH or lower, the charge FET control gate is fixed to the Pack– voltage to
inhibit charging. When battery is equal to V0INH or higher, charging can be performed.
18
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bq2970, bq2971, bq2972, bq2973
www.ti.com
SLUSBU9C – MARCH 2014 – REVISED MARCH 2016
Device Functional Modes (continued)
CAUTION
Some battery providers do not recommend charging a depleted (self-discharged)
battery. Consult the battery supplier to determine whether to enable or inhibit the 0-V
battery charger function.
9.4.8 Delay Circuit
The detection delay timers are based from an internal clock with a frequency of 10 kHz.
DOUT
BAT
tD
0 ≤ tD ≤ tSCCD
VSS
Time
tD ˂ tOCDD
V–
VSCC
VOCD
VSS
Time
Figure 25. Delay Circuit
If the over-discharge current is detected, but remains below the over-discharge short circuit detection threshold,
the over-discharge detection conditions must be valid for a time greater than or equal to over-discharge current
delay tOCCD time before the DOUT goes low to turn OFF the discharge FET. However, during any time the
discharge overcurrent detection exceeds the short circuit detection threshold for a time greater than or equal to
load circuit detection delay tSCCD, the DOUT pin goes low in a faster delay for protection.
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: bq2970 bq2971 bq2972 bq2973
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10 Applications and Implementation
10.1 Application Information
The bq2970 devices are a family of primary protectors used for protection of the battery pack in the application.
The application drives two low-side NMOS FETs that are controlled to provide energy to the system loads or
interrupt the power in the event of a fault condition.
10.2 Typical Application
PACK +
V–
NC
BAT
DOUT
VSS
0.1 µF
COUT
330
2.2k
CELLP
CELLN
PACK–
D
S
CHG
S
DSG
NOTE: The 5-M resistor for an external gate-source is optional.
Figure 26. Typical Application Schematic, bq2970
10.2.1 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE at TA = 25°C
Input voltage range
4.5 V to 7 V
Maximum operating discharge current
7A
Maximum Charge Current for battery pack
4.5 A
Overvoltage Protection (OVP)
4.275 V
Overvoltage detection delay timer
1.2 s
Overvoltage Protection (OVP) release voltage
4.175 V
Undervoltage Protection (UVP)
2.8 V
Undervoltage detection delay timer
150 ms
Undervoltage Protection (UVP) release voltage
2.9 V
Charge Overcurrent detection (OCC) voltage
–70 mV
Charge Overcurrent Detection (OCC) delay timer
9 ms
Discharge Overcurrent Detection (OCD) voltage
100 mV
Discharge Overcurrent Detection (OCD) delay timer
18 ms
Load Short Circuit Detection SCC) voltage, BAT to –V ≤ threshold
500 mV
Load Short Circuit Detection (SCC) delay timer
250 µs
Load Short Circuit release voltage, BAT to –V ≥ Threshold
1V
20
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SLUSBU9C – MARCH 2014 – REVISED MARCH 2016
10.2.2 Detailed Design Procedure
NOTE
The external FET selection is important to ensure the battery pack protection is sufficient
and complies to the requirements of the system.
•
•
•
•
•
•
•
•
FET Selection: Because the maximum desired discharge current is 7 A, ensure that the Discharge
Overcurrent circuit does not trigger until the discharge current is above this value.
The total resistance tolerated across the two external FETs (CHG + DSG) should be 100 mV/7 A = 14.3 mΩ.
Based on the information of the total ON resistance of the two switches, determine what would be the Charge
Overcurrent Detection threshold, 14.3 mΩ × 4.5 A = 65 mV. Selecting a device with a 70-mV trigger threshold
for Charge Overcurrent trigger is acceptable.
The total Rds ON should factor in any worst-case parameter based on the FET ON resistance, de-rating due
to temperature effects and minimum required operation, and the associated gate drive (Vgs). Therefore, the
FET choice should meet the following criteria:
Vdss = 25 V
Each FET Rds ON = 7.5 mΩ at Tj = 25°C and Vgs = 3.5 V
Imax > 50 A to allow for short Circuit Current condition for 350 µs (max delay timer). The only limiting factor
during this condition is Pack Voltage/(Cell Resistance + (2 × FET_RdsON) + Trace Resistance).
Use the CSD16406Q3 FET for the application.
An RC filter is required on the BAT for noise, and enables the device to operate during sharp negative
transients. The 330-Ω resistor also limits the current during a reverse connection on the system.
It is recommended to place a high impedance 5-MΩ across the gate source of each external FET to deplete
any charge on the gate-source capacitance.
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: bq2970 bq2971 bq2972 bq2973
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10.2.3 Application Performance Plots
Orange Line (Channel 1) = Power Up Ramp on BAT Pin
Turquoise Line (Channel 2) = DOUT Gate Drive Output
DOUT goes from low to high when UVP Recovery = UVP Set
Threshold +100 mV
Figure 27. UVP Recovery
Orange Line (Channel 1) = Power Up Ramp on BAT pin
Turquoise Line (Channel 2) = DOUT Gate Drive Output
Figure 29. Initial Power Up, DOUT
Orange Line (Channel 1) = Power Up Ramp on BAT Pin
Turquoise Line (Channel 2) = COUT Gate Drive Output
COUT goes from high to low when OVP threshold = OVP set
Threshold + set delay time
Figure 31. OVP Set Condition
22
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Orange Line (Channel 1) = Power Down Ramp on BAT Pin
Turquoise Line (Channel 2) = DOUT Date Drive Output
DOUT goes from high to low when UVP threshold = UVP set
Threshold + set delay time
Figure 28. UVP Set Condition
Orange Line (Channel 1) = Power Up Ramp on BAT Pin
Turquoise Line (Channel 2) = COUT Gate Drive Output
Figure 30. Initial Power Up, COUT
Orange Line (Channel 1) = Decrease Voltage on BAT Pin
Turquoise Line (Channel 2) = COUT Gate Drive Output
COUT goes from low to high when OVP Recovery = OVP Set
Threshold –100 mV
Figure 32. OVP Recovery Condition
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: bq2970 bq2971 bq2972 bq2973
bq2970, bq2971, bq2972, bq2973
www.ti.com
SLUSBU9C – MARCH 2014 – REVISED MARCH 2016
11 Power Supply Recommendations
The recommended power supply for this device is a maximum 8-V operation on the BAT input pin.
12 Layout
12.1 Layout Guidelines
The following are the recommended layout guidelines:
1. Ensure the external power FETs are adequately compensated for heat dissipation with sufficient thermal
heat spreader based on worst-case power delivery.
2. The connection between the two external power FETs should be very close to ensure there is not an
additional drop for fault sensing.
3. The input RC filter on the BAT pin should be close to the terminal of the IC.
12.2 Layout Example
Power Trace Line
PACK+
PACK–
V–
6
COUT
BAT
5
DOUT
VSS
4
1
NC
2
3
Power Trace Line
Power Trace Line
S
G
1
4
S
S
1
S
2
2
S
S
3
G
3
4
CSD16406Q3
CSD16406Q3
D
D
D
5
6
7
8
7
D
D
6
8
D
5
D
D
Power Trace
Via connects between two layers
Figure 33. bq2970 Board Layout
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: bq2970 bq2971 bq2972 bq2973
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
bq2970
Click here
Click here
Click here
Click here
Click here
bq2971
Click here
Click here
Click here
Click here
Click here
bq2972
Click here
Click here
Click here
Click here
Click here
bq2973
Click here
Click here
Click here
Click here
Click here
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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Product Folder Links: bq2970 bq2971 bq2972 bq2973
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ29700DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FA
BQ29700DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FA
BQ29701DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FY
BQ29701DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FY
BQ29702DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FZ
BQ29702DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FZ
BQ29703DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
F1
BQ29703DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
F1
BQ29704DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
F2
BQ29704DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
F2
BQ29705DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
F3
BQ29705DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
F3
BQ29706DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
F4
BQ29706DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
F4
BQ29707DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
F5
BQ29707DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
F5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2016
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Mar-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
BQ29700DSER
WSON
DSE
6
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29700DSET
WSON
DSE
6
250
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29701DSER
WSON
DSE
6
3000
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29701DSET
WSON
DSE
6
250
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29702DSER
WSON
DSE
6
3000
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29702DSET
WSON
DSE
6
250
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29703DSER
WSON
DSE
6
3000
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29703DSET
WSON
DSE
6
250
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29704DSER
WSON
DSE
6
3000
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29704DSET
WSON
DSE
6
250
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29705DSER
WSON
DSE
6
3000
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29705DSET
WSON
DSE
6
250
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29706DSER
WSON
DSE
6
3000
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29706DSET
WSON
DSE
6
250
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29707DSER
WSON
DSE
6
3000
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
BQ29707DSET
WSON
DSE
6
250
180.0
8.4
1.75
1.75
1.0
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Mar-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ29700DSER
WSON
DSE
6
3000
210.0
185.0
35.0
BQ29700DSET
WSON
DSE
6
250
210.0
185.0
35.0
BQ29701DSER
WSON
DSE
6
3000
210.0
185.0
35.0
BQ29701DSET
WSON
DSE
6
250
210.0
185.0
35.0
BQ29702DSER
WSON
DSE
6
3000
210.0
185.0
35.0
BQ29702DSET
WSON
DSE
6
250
210.0
185.0
35.0
BQ29703DSER
WSON
DSE
6
3000
210.0
185.0
35.0
BQ29703DSET
WSON
DSE
6
250
210.0
185.0
35.0
BQ29704DSER
WSON
DSE
6
3000
210.0
185.0
35.0
BQ29704DSET
WSON
DSE
6
250
210.0
185.0
35.0
BQ29705DSER
WSON
DSE
6
3000
210.0
185.0
35.0
BQ29705DSET
WSON
DSE
6
250
210.0
185.0
35.0
BQ29706DSER
WSON
DSE
6
3000
210.0
185.0
35.0
BQ29706DSET
WSON
DSE
6
250
210.0
185.0
35.0
BQ29707DSER
WSON
DSE
6
3000
210.0
185.0
35.0
BQ29707DSET
WSON
DSE
6
250
210.0
185.0
35.0
Pack Materials-Page 2
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