TI DSG5402PGE100 Fixed-point digital signal processor Datasheet

/ SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M × 16-Bit
Maximum Addressable External Program
Space
4K x 16-Bit On-Chip ROM
16K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for
Efficient Program and Data Management
Instructions With a 32-Bit Long Word
Operand
Instructions With Two- or Three-Operand
Reads
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable Bank
Switching
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
– Two Multichannel Buffered Serial Ports
(McBSPs)
– Enhanced 8-Bit Parallel Host-Port
Interface (HPI8)
– Two 16-Bit Timers
– Six-Channel Direct Memory Access
(DMA) Controller
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic
10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (1.8-V Core)
Available in a 144-Pin Plastic Low-Profile
Quad Flatpack (LQFP) (PGE Suffix) and a
144-Pin Ball Grid Array (BGA) (GGU Suffix)
NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview
(literature number SPRU307).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright  2000, Texas Instruments Incorporated
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)*%( ,((%*. (&+*"&% '(&))"% &) %&* %))("#. "%#+
*)*"% & ## '($*()
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1
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
TABLE OF CONTENTS
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Software-Programmable Wait-State Generator . . . . . . . . . 16
Programmable Bank-Switching Wait States . . . . . . . . . . . . 18
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Enhanced 8-Bit Host-Port Interface . . . . . . . . . . . . . . . . . . . 19
Multichannel Buffered Serial Ports . . . . . . . . . . . . . . . . . . . . 20
Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 27
McBSP Control Registers And Subaddresses . . . . . . . . . . 29
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . 29
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Measurement Information . . . . . . . . . . . . . . . . . .
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . .
Divide-By-Two Clock Option (PLL Disabled) . . . . . . . . . . . .
Multiply-By-N Clock Option . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory and Parallel I/O Interface Timing . . . . . . . . . . . . . .
Ready Timing For Externally Generated Wait States . . . . .
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . . . . . . .
Instruction Acquisition (IAQ), Interrupt Acknowledge
(IACK), External Flag (XF), and TOUT Timings . . . . .
Multichannel Buffered Serial Port Timing . . . . . . . . . . . . . . .
HPI8 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
34
34
35
35
36
37
38
39
45
49
50
52
54
61
65
REVISION HISTORY
REVISION
2
DATE
PRODUCT STATUS
HIGHLIGHTS
*
October 1998
Advanced Information
Original
A
April 1999
Advanced Information
Revised to update characteristic data
B
July 1999
Advanced Information
Revised to update characteristic data
C
September 1999
Advanced Information
Revised to update characteristic data
D
January 2000
Production Data
Revised to release production data.
E
August 2000
Production Data
Added Table of Contents, Revision History, and corrected IDLE3
current on page 35.
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description
The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’5402 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis
of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the
high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition,
data can be transferred between data and program spaces. Such parallelism supports a powerful set of
arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition,
the ’5402 includes the control mechanisms to manage interrupts, repeated operations, and function calls.
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description (continued)
109
111
110
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
75
35
74
36
73
A18
A17
VSS
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
VSS
HPIENA
CVDD
NC
TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT0
HD2
NC
CLKMD3
CLKMD2
CLKMD1
VSS
DVDD
NC
NC
NC
NC
HCNTL0
VSS
BCLKR0
BCLKR1
BFSR0
BFSR1
BDR0
HCNTL1
BDR1
BCLKX0
BCLKX1
VSS
HINT/TOUT1
CVDD
BFSX0
BFSX1
HRDY
DV DD
V SS
HD0
BDX0
BDX1
IACK
HBIL
NMI
INT0
INT1
INT2
INT3
CVDD
HD1
VSS
NC
NC
72
76
34
71
77
33
70
78
32
69
79
31
68
80
30
67
81
29
66
82
28
65
83
27
64
84
26
63
85
25
62
86
24
61
87
23
60
88
22
59
89
21
58
90
20
57
91
19
56
92
18
55
93
17
54
94
16
53
95
15
52
96
14
51
97
13
50
98
12
49
99
11
48
100
10
47
101
9
46
102
8
45
103
7
44
104
6
43
105
5
42
106
4
41
3
40
107
39
108
2
38
1
37
NC
NC
VSS
DVDD
A10
HD7
A11
A12
A13
A14
A15
NC
HAS
VSS
NC
CVDD
HCS
HR/W
READY
PS
DS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DVDD
VSS
NC
NC
143
144
NC
NC
CV DD
A9
A8
A7
A6
A5
A4
HD6
A3
A2
A1
A0
DVDD
HDS2
VSS
HDS1
NC
CVDD
HD5
D15
D14
D13
HD4
D12
D11
D10
D9
D8
D7
D6
DV DD
VSS
NC
A19
TMS320VC5402 PGE PACKAGE†‡
(TOP VIEW)
† NC = No internal connection
‡ DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O
pins and the core CPU.
The TMS320VC5402PGE (144-pin LQFP) package is footprint-compatible with the ’LC548, ’LC/VC549, and
’VC5410 devices.
4
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description (continued)
TMS320VC5402 GGU PACKAGE
(BOTTOM VIEW)
13 12 11 10 9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
The pin assignments table to follow lists each signal quadrant and BGA ball number for the
TMS320VC5402GGU (144-pin BGA) package which is footprint-compatible with the ’LC548 and ’LC/VC549
devices.
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Pin Assignments for the TMS320VC5402GGU (144-Pin BGA) Package†
SIGNAL
NAME
BGA BALL #
SIGNAL
NAME
BGA BALL #
SIGNAL
NAME
BGA BALL #
SIGNAL
NAME
BGA BALL #
NC
A1
NC
B1
NC
N13
NC
N1
A19
A13
NC
M13
NC
N2
NC
VSS
DVDD
C2
A12
L12
HCNTL0
M3
L13
N3
D4
CLKMD1
K10
VSS
BCLKR0
VSS
DVDD
B11
C1
DVDD
VSS
A10
K4
D6
D10
HD7
D3
CLKMD2
K11
BCLKR1
L4
D7
C10
A11
D2
CLKMD3
K12
BFSR0
M4
D8
B10
A12
D1
NC
K13
BFSR1
N4
D9
A10
A13
E4
HD2
J10
BDR0
K5
D10
D9
A14
E3
TOUT0
J11
HCNTL1
L5
D11
C9
A15
E2
EMU0
J12
BDR1
M5
D12
B9
NC
E1
EMU1/OFF
J13
BCLKX0
N5
HD4
A9
HAS
F4
TDO
H10
BCLKX1
K6
D13
D8
VSS
NC
F3
TDI
H11
D14
C8
TRST
H12
VSS
HINT/TOUT1
L6
F2
M6
D15
B8
A11
CVDD
F1
TCK
H13
HD5
A8
G2
TMS
G12
CVDD
BFSX0
N6
HCS
M7
CVDD
B7
HR/W
G1
NC
G13
BFSX1
N7
NC
A7
READY
G3
HRDY
L7
HDS1
C7
G4
CVDD
HPIENA
G11
PS
G10
DVDD
K7
D7
DS
H1
F13
N8
F12
VSS
HD0
VSS
HDS2
M8
DVDD
B6
F11
BDX0
L8
A0
C6
IS
H2
VSS
CLKOUT
R/W
H3
HD3
A6
MSTRB
H4
X1
F10
BDX1
K8
A1
D6
IOSTRB
J1
X2/CLKIN
E13
IACK
N9
A2
A5
MSC
J2
RS
E12
HBIL
M9
A3
B5
XF
J3
D0
E11
NMI
L9
HD6
C5
HOLDA
J4
D1
E10
INT0
K9
A4
D5
A4
IAQ
K1
D2
D13
INT1
N10
A5
HOLD
K2
D3
D12
INT2
M10
A6
B4
BIO
K3
D4
D11
INT3
L10
A7
C4
MP/MC
L1
D5
C13
CVDD
N11
A8
A3
DVDD
L2
A16
C12
HD1
M11
A9
B3
VSS
NC
L3
VSS
A17
C11
CVDD
C3
B13
VSS
NC
L11
M1
N12
NC
A2
NC
M2
A18
B12
NC
M12
NC
B2
† DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core
CPU.
6
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terminal functions
The following table lists each signal, function, and operating mode(s) grouped by function.
Terminal Functions
TERMINAL
NAME
TYPE†
DESCRIPTION
DATA SIGNALS
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
O/Z
Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen
address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O, while the upper
four address pins (A16 to A19) are only used to address external program space. These pins are placed in the
high-impedance state when the hold mode is enabled, or when OFF is low.
I/O/Z
Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer
data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the
high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the
high-impedance state when OFF is low.
(LSB)
(MSB)
The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus
holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven
by the ’5402, the bus holders keep the pins at the previous logic level. The data bus holders on the ’5402 are
disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR).
(LSB)
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is low.
INT0
INT1
INT2
INT3
I
External user interrupts. INT0–INT3 are prioritized and are maskable by the interrupt mask register (IMR) and
the interrupt mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register (IFR).
NMI
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
† I = input, O = output, Z = high impedance, S = supply
‡ All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
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Terminal Functions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
I
Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the
CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program
memory. RS affects various registers and status bits.
I
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the
internal program ROM is mapped into the upper 4K words of program memory space. If the pin is driven high
during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode
that is selected at reset.
BIO
I
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. For the XC instruction, the BIO condition is sampled during the decode phase of the
pipeline; all other instructions sample BIO during the read phase of the pipeline.
XF
O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is
low, and is set high at reset.
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)
RS
MP/MC
MULTIPROCESSING SIGNALS
MEMORY CONTROL SIGNALS
DS
PS
IS
O/Z
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing
a particular external memory space. Active period corresponds to valid address information. DS, PS, and IS are
placed into the high-impedance state in the hold mode; the signals also go into the high-impedance state when
OFF is low.
MSTRB
O/Z
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when OFF is low.
I
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
R/W
O/Z
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in
the high-impedance state in hold mode; it also goes into the high-impedance state when OFF is low.
IOSTRB
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when OFF is low.
I
Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the
’C54x, these lines go into the high-impedance state.
O/Z
Hold acknowledge. HOLDA indicates that the ’5402 is in a hold state and that the address, data, and control lines
are in the high-impedance state, allowing the external memory interface to be accessed by other devices.
HOLDA also goes into the high-impedance state when OFF is low.
MSC
O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive
high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external
wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF
is low.
IAQ
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
bus. IAQ goes into the high-impedance state when OFF is low.
READY
HOLD
HOLDA
† I = input, O = output, Z = high impedance, S = supply
‡ All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
8
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Terminal Functions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
O/Z
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low.
I
Clock mode select signals. These inputs select the mode that the clock generator is initialized to after reset. The
logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized
to the selected mode. After reset, the clock mode can be changed through software, but the clock mode select
signals have no effect until the device is reset again.
OSCILLATOR/TIMER SIGNALS
CLKOUT
CLKMD1
CLKMD2
CLKMD3
Oscillator input. This is the input to the on-chip oscillator.
X2/CLKIN
I
X1
O
If the internal oscillator is not used, X2/CLKIN functions as the clock input, and can be driven by an external clock
source.‡
Output pin from the internal oscillator for the crystal.
If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state
when OFF is low.‡
TOUT0
O/Z
Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT
cycle wide. TOUT0 also goes into the high-impedance state when OFF is low.
TOUT1
O/Z
Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is one
CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI and is only available when
the HPI is disabled. TOUT1 also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
BCLKR0
BCLKR1
I/O/Z
Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following
reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BDR0
BDR1
I
BFSR0
BFSR1
I/O/Z
Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured
as an input following reset. The BFSR pulse initiates the receive data process over BDR.
BCLKX0
BCLKX1
I/O/Z
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when
OFF goes low.
BDX0
BDX1
O/Z
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when OFF is low.
BFSX0
BFSX1
I/O/Z
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX
can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the
high-impedance state when OFF is low.
Serial data receive input
MISCELLANEOUS SIGNAL
NC
No connection
HOST-PORT INTERFACE SIGNALS
HD0–HD7
HCNTL0
HCNTL1
I/O/Z
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the
high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to
reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven
by the ’5402, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled
at reset and can be enabled/disabled via the HBH bit of the BSCR.
I
Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have
internal pullup resistors that are only enabled when HPIENA = 0.
† I = input, O = output, Z = high impedance, S = supply
‡ All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
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Terminal Functions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
HBIL
I
Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup
resistor that is only enabled when HPIENA = 0.
HCS
I
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input
has an internal pullup resistor that is only enabled when HPIENA = 0.
HDS1
HDS2
I
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs
have internal pullup resistors that are only enabled when HPIENA = 0.
HAS
I
Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA
register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0.
HR/W
I
Read/write. HR/W controls the direction of an HPI transfer. R/W has an internal pullup resistor that is only
enabled when HPIENA = 0.
HRDY
O/Z
Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the
high-impedance state when OFF is low.
HINT
O/Z
Host interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT can
also be configured as the timer 1 output (TOUT1), when the HPI is disabled. The signal goes into the
high-impedance state when OFF is low.
I
HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor
is always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low
during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the ’5402
is reset.
HOST-PORT INTERFACE SIGNALS (CONTINUED)
HPIENA
SUPPLY PNS
CVDD
S
DVDD
S
+VDD. Dedicated 1.8-V power supply for the core CPU
+VDD. Dedicated 3.3-V power supply for the I/O pins
VSS
S
Ground
TCK
I
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction
register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur
on the falling edge of TCK.
TDI
I
IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when OFF is low.
TMS
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
TRST
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode,
and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
TEST PINS
† I = input, O = output, Z = high impedance, S = supply
‡ All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
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Terminal Functions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
I/O/Z
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by
way of the IEEE standard 1149.1 scan system.
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST
is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers
into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). The OFF feature is selected by the following pin combinations:
TRST = low
EMU0 = high
EMU1/OFF = low
TEST PINS (CONTINUED)
EMU0
EMU1/OFF
† I = input, O = output, Z = high impedance, S = supply
‡ All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVDD), rather than the 3V I/O supply (DVDD).
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
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memory
The ’5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration.
on-chip ROM with bootloader
The ’5402 features a 4K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the
’5402 programmed with contents unique to any particular application. A security option is available to protect
a custom ROM. This security option is described in the TMS320C54x DSP CPU and Peripherals Reference Set,
Volume 1 (literature number SPRU131). Note that only the ROM security option, and not the ROM/RAM option,
is available on the ’5402 .
A bootloader is available in the standard ’5402 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin
is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location
contains a branch instruction to the start of the bootloader program. The standard ’5402 bootloader provides
different ways to download the code to accomodate various system requirements:
Parallel from 8-bit or 16-bit-wide EPROM
Parallel from I/O space 8-bit or 16-bit mode
Serial boot from serial ports 8-bit or 16-bit mode
Host-port interface boot
The standard on-chip ROM layout is shown in Table 1.
Table 1. Standard On-Chip ROM Layout†
ADDRESS RANGE
DESCRIPTION
F000h – F7FFh
Reserved
F800h – FBFFh
Bootloader
FC00h – FCFFh
µ-law expansion table
FD00h – FDFFh
A-law expansion table
FE00h – FEFFh
Sine look-up table
FF00h – FF7Fh
Reserved
FF80h – FFFFh
Interrupt vector table
† In the ’VC5402 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.
on-chip RAM
The ’5402 device contains 16K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of
two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a
write in one cycle. The DARAM is located in the address range 0060h–3FFFh in data space, and can be mapped
into program/data space by setting the OVLY bit to one.
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memory map
Hex Page 0 Program
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
Hex Page 0 Program
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
007F
0080
007F
0080
On-Chip DARAM
(OVLY = 1)
External
(OVLY = 0)
Hex
0000
005F
0060
3FFF
4000
3FFF
4000
EFFF
F000
External
EFFF
F000
ROM (DROM=1)
or External
(DROM=0)
On-Chip ROM
(4K x 16-bit)
FEFF
FF00
FF7F
FF80
Reserved
FEFF
FF00
Reserved
(DROM=1)
or External
(DROM=0)
FF7F
FF80
Interrupts
(External)
Interrupts
(On-Chip)
FFFF
FFFF
MP/MC= 1
(Microprocessor Mode)
Scratch-Pad
RAM
On-Chip DARAM
(16K x 16-bit)
External
External
Memory
Mapped
Registers
007F
0080
On-Chip DARAM
(OVLY = 1)
External
(OVLY = 0)
3FFF
4000
Data
FFFF
MP/MC= 0
(Microcomputer Mode)
Figure 1. Memory Map
relocatable interrupt vector table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,
these vectors can be remapped to the beginning of any 128-word page in program space after device reset.
This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see Figure 2) with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
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relocatable interrupt vector table (continued)
15
7
6
5
4
3
2
1
0
IPTR
MP/MC
OVLY
AVIS
DROM
CLK
OFF
SMUL
SST
R/W
R/W
R/W
R
R
R
R/W
R/W
LEGEND: R = Read, W = Write
Figure 2. Processor Mode Status (PMST) Registers
extended program memory
The ’5402 uses a paged extended memory scheme in program space to allow access of up to 1024K program
memory locations. In order to implement this scheme, the ’5402 includes several features that are also present
on the ’548/’549 devices:
Twenty address lines, instead of sixteen
An extra memory-mapped register, the XPC register, defines the page selection. This register is
memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.
Six extra instructions for addressing extended program space. These six instructions affect the XPC.
–
FB[D] pmad (20 bits) – Far branch
–
FBACC[D] Accu[19:0] – Far branch to the location specified by the value in accumulator A or
accumulator B
–
FCALL[D] pmad (20 bits) – Far call
–
FCALA[D] Accu[19:0] – Far call to the location specified by the value in accumulator A or accumulator B
–
FRET[D] – Far return
–
FRETE[D] – Far return with interrupts enabled
In addition to these new instructions, two ’54x instructions are extended to use 20 bits in the ’5402:
–
READA data_memory (using 20-bit accumulator address)
–
WRITA data_memory (using 20-bit accumulator address)
All other instructions, software interrupts and hardware interrupts do not modify the XPC register and access
only memory within the current page.
Program memory in the ’5402 is organized into 16 pages that are each 64K in length, as shown in Figure 3.
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0 0000
1 0000
1 3FFF
Page 1
Lower
16K
External
2 0000
2 3FFF
Page 2
Lower
16K
External
...
...
2 4000
1 4000
...
F 0000
F 3FFF
Page 15
Lower
16K
External
F 4000
Page 0
Page 1
Upper
48K
External
64K
Words
0 FFFF
Page 2
Upper
48K
External
2 FFFF
1 FFFF
Page 15
Upper
48K
External
...
F FFFF
† See Figure 1
‡ The lower 16K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM
is mapped to the lower 16K words of all program space pages.
Figure 3. Extended Program Memory
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on-chip peripherals
The ’5402 device has the following peripherals:
Software-programmable wait-state generator with programmable bank-switching wait states
An enhanced 8-bit host-port interface (HPI8)
Two multichannel buffered serial ports (McBSPs)
Two hardware timers
A clock generator with a phase-locked loop (PLL)
A direct memory access (DMA) controller
software-programmable wait-state generator
The software wait-state generator of the ’5402 can extend external bus cycles by up to fourteen machine cycles.
Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When
all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are
automatically disabled. Disabling the wait-state generator clocks reduces the power comsumption of the ’5402.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of
the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized
to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 4
and described in Table 2.
15
XPA
R/W-0
14
12 11
I/O
R/W-111
9 8
Data
R/W-111
6
Data
R/W-111
5
3
Program
R/W-111
2
0
Program
R/W-111
LEGEND: R=Read, W=Write, 0=Value after reset
Figure 4. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
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software-programmable wait-state generator (continued)
Table 2. Software Wait-State Register (SWWSR) Bit Fields
BIT
NO.
NAME
RESET
VALUE
15
XPA
0
Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for program space wait states.
14–12
I/O
1
I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
11–9
Data
1
Upper data space. The field value (0–7) corresponds to the base number of wait states for external
data space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
8–6
Data
1
Lower data space. The field value (0–7) corresponds to the base number of wait states for external
data space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
FUNCTION
Upper program space. The field value (0–7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
5–3
Program
1
XPA = 0: x8000 – xFFFFh
XPA = 1: The upper program space bit field has no effect on wait states.
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait
states.
Program space. The field value (0–7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
2–0
Program
1
XPA = 0: x0000–x7FFFh
XPA = 1: 00000–FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait
states.
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the
base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 5 and described
in Table 3.
15
1
0
SWSM
Reserved
R/W-0
R/W-0
LEGEND: R = Read, W = Write
Figure 5. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 3. Software Wait-State Control Register (SWCR) Bit Fields
PIN
NO.
NAME
RESET
VALUE
15–1
Reserved
0
FUNCTION
These bits are reserved and are unaffected by writes.
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
0
SWSM
0
SWSM = 0: wait-state base values are unchanged (multiplied by 1).
SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states.
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programmable bank-switching wait states
The programmable bank-switching logic of the ’5402 is functionally equivalent to that of the ’548/’549 devices.
This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or
data memory space. A bank-switching wait state can also be automatically inserted when accesses cross the
data space boundary into program space.
The bank-switching control register (BSCR) defines the bank size for bank-switching wait states. Figure 6
shows the BSCR and its bits are described in Table 4.
15
12
11
10
BNKCMP
PS-DS
R/W-1111
R/W-1
3
Reserved
R-0
2
1
0
HBH
BH
EXIO
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write
Figure 6. Bank-Switching Control Register (BSCR), MMR Address 0029h
Table 4. Bank-Switching Control Register (BSCR) Fields
NO.
RESET
VALUE
FUNCTION
1111
Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of
an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15) are compared, resulting in a
bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.
PS - DS
1
Program read – data read access. Inserts an extra cycle between consecutive accesses of program read
and data read or data read and program read.
PS-DS = 0
No extra cycles are inserted by this feature.
PS-DS = 1
One extra cycle is inserted between consecutive data and program reads.
Reserved
0
These bits are reserved and are unaffected by writes.
2
HBH
0
HPI Bus holder. Controls the HPI bus holder feature. HBH is cleared to 0 at reset.
HBH = 0
The bus holder is disabled.
HBH = 1
The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the
previous logic level.
1
BH
0
Bus holder. Controls the data bus holder feature. BH is cleared to 0 at reset.
BH = 0
The bus holder is disabled.
BH = 1
The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the
previous logic level.
0
External bus interface off. The EXIO bit controls the external bus-off function.
EXIO = 0
The external bus interface functions as usual.
usual
EXIO = 1
The address bus, data bus, and control signals become inactive after completing the
c rrent bus
current
b s cycle.
c cle Note that the DROM,
DROM MP/MC,
MP/MC and OVLY bits in the PMST and the HM
bit of ST1 cannot be modified when the interface is disabled.
15–12
11
10–3
0
18
BIT
NAME
BNKCMP
EXIO
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parallel I/O ports
The ’5402 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW
instruction. The IS signal indicates a read/write operation through an I/O port. The ’5402 can interface easily
with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
enhanced 8-bit host-port interface
The ’5402 host-port interface, also referred to as the HPI8, is an enhanced version of the standard 8-bit HPI
found on earlier ’54x DSPs (’542, ’545, ’548, and ’549). The HPI8 is an 8-bit parallel port for interprocessor
communication. The features of the HPI8 include:
Standard features:
Sequential transfers (with autoincrement) or random-access transfers
Host interrupt and ’54x interrupt capability
Multiple data strobes and control pins for interface flexibility
Enhanced features of the ’5402 HPI8:
Access to entire on-chip RAM through DMA bus
Capability to continue transferring during emulation stop
The HPI8 functions as a slave and enables the host processor to access the on-chip memory of the ’5402. A
major enhancement to the ’5402 HPI over previous versions is that it allows host access to the entire on-chip
memory range of the DSP. The HPI8 memory map is identical to that of the DMA controller shown in Figure 7.
The host and the DSP both have access to the on-chip RAM at all times and host accesses are always
synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has
priority, and the DSP waits for one HPI8 cycle. Note that since host accesses are always synchronized to the
’5402 clock, an active input clock (CLKIN) is required for HPI8 accesses during IDLE states, and host accesses
are not allowed while the ’5402 reset pin is asserted.
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers
are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with
the HPI8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an
HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register
is accessible by both the host and the ’5402.
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multichannel buffered serial ports
The ’5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow
direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based
on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides:
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
Direct interface to:
–
T1/E1 framers
–
MVIP switching compatible and ST-BUS compliant devices
–
IOM-2 compliant devices
–
Serial peripheral interface devices
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSPs consist of separate transmit and receive channels that operate independently. The external
interface of each McBSP consists of the following pins:
BCLKX
BDX
BFSX
BCLKR
BDR
BFSR
Transmit reference clock
Transmit data
Transmit frame synchronization
Receive reference clock
Receive data
Receive frame synchronization
The six pins listed are functionally equivalent to previous serial port interface pins in the ’C5000 family of DSPs.
On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins,
respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR).
Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows
DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.
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multichannel buffered serial ports (continued)
On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins,
respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on
the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR).
If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until the DRR
is available. This structure allows storage of the two previous words while the reception of the current word is
in progress.
The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP
interrupts, event signals, and status flags. The DMA is capable of handling data movement between the
McBSPs and memory with no intervention from the CPU.
In addition to the standard serial port functions, the McBSP provides programmable clock and frame
synchronization signals. The programmable functions include:
Frame synchronization pulse width
Frame period
Frame synchronization delay
Clock reference (internal vs. external)
Clock division
Clock and frame synchronization polarity
The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.
When companding is used, transmit data is encoded according to specified companding law and received data
is decoded to 2s complement format.
The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using
TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth,
multichannel selection allows independent enabling of particular channels for transmission and reception. Up
to 32 channels in a stream of up to 128 channels can be enabled.
The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI)
protocol. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit
operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate
together as a master or as a slave.
The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU
clock frequency divided by 2.
hardware timer
The ’5402 device features two 16-bit timing circuits with 4-bit prescalers. The main counter of each timer is
decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timers can be stopped, restarted, reset, or disabled by specific control bits.
clock generator
The clock generator provides clocks to the ’5402 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external clock source.
NOTE:All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage
levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V
power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended operating conditions
section of this document for the allowable voltage levels of the X2/CLKIN pin.
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
clock generator (continued)
The reference clock input is then divided by two (DIV mode) to generate clocks for the ’5402 device, or the PLL
circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by
a scale factor, allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive
circuit that, once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the ’5402
device.
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of
the ’5402 to enable the internal oscillator.
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
NOTE: All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage
levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V
power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended operating conditions
section of this document for the allowable voltage levels of the X2/CLKIN pin.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved.Devices that have a built-in
software-programmable PLL can be configured in one of two clock modes:
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved
using the PLL circuitry.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be
completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the configuration of the PLL clock module. Upon reset,
the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 –
CLKMD3 pins as shown in Table 5.
Table 5. Clock Mode Settings at Reset
22
CLKMD1
CLKMD2
CLKMD3
CLKMD
RESET VALUE
0
0
0
E007h
PLL x 15
0
0
1
9007h
PLL x 10
0
1
0
4007h
PLL x 5
1
0
0
1007h
PLL x 2
1
1
0
F007h
PLL x 1
1
1
1
0000h
1/2 (PLL disabled)
1
0
1
F000h
1/4 (PLL disabled)
0
1
1
—
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Reserved (bypass mode)
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DMA controller
The ’5402 direct memory access (DMA) controller transfers data between points in the memory map without
intervention by the CPU. The DMA controller allows movements of data to and from internal program/data
memory or internal peripherals (such as the McBSPs) to occur in the background of CPU operation. The DMA
has six independent programmable channels allowing six different contexts for DMA operation.
features
The DMA has the following features:
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for internal accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented,
post-decremented, or be adjusted by a programmable value.
Each read or write transfer may be initialized by selected events.
Upon completion of a half-block or an entire-block transfer, each DMA channel may send an interrupt to the
CPU.
The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words).
DMA memory map
The DMA memory map is shown in Figure 7 to allow DMA transfers to be unaffected by the status of the MPMC,
DROM, and OVLY bits.
Hex
0000
Reserved
001F
0020
0023
0024
McBSP
Registers
Reserved
005F
0060
Scratch-Pad
RAM
007F
0080
(16K x 16-bit)
On-Chip DARAM
3FFF
4000
Reserved
FFFF
Figure 7. ’5402 DMA Memory Map
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
DMA priority level
Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
DMA source/destination address modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
DMA in autoinitialization mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can
be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and
DMGCR). Autoinitialization allows:
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfer; but with the global reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
Repetitive operation: The CPU does not preload the global reload register with new values for each block
transfer but only loads them on the first block transfer.
DMA transfer counting
The DMA channel element count register (DMCTRx) and the frame count register (DMSFCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum number
of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon the last read
transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with
the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count of 0 (default
value) means the block transfer contains a single frame.
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded
with the DMA global count reload register (DMGCR).
DMA transfers in double-word mode
Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
DMA channel index registers
The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode
control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and
DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is
the last in the current frame. The normal adjustment value (element index) is contained in the element index
registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined by
the selected DMA frame index register, either DMFRI0 or DMFRI1.
24
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DMA channel index registers (continued)
The element index and the frame index affect address adjustment as follows:
Element index: For all except the last transfer in the frame, the element index determines the amount to be
added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by
the SIND/DIND bits.
Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment as selected
by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.
DMA interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available
modes are shown in Table 6.
Table 6. DMA Interrupts
DINM
IMOD
ABU (non-decrement)
MODE
1
0
At full buffer only
INTERRUPT
ABU (non-decrement)
1
1
At half buffer and full buffer
Multi-Frame
1
0
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
Multi-Frame
1
1
At end of frame and end of block (DMCTRn = 0)
Either
0
X
No interrupt generated
Either
0
X
No interrupt generated
DMA controller synchronization events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit
field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization event
for a channel. The list of possible events and the DSYN values are shown in Table 7.
Table 7. DMA Synchronization Events
DSYN VALUE
DMA SYNCHRONIZATION EVENT
0000b
No synchronization used
0001b
McBSP0 receive event
0010b
McBSP0 transmit event
0011–0100b
Reserved
0101b
McBSP1 receive event
0110b
McBSP1 transmit event
0111b–0110b
Reserved
1101b
Timer0 interrupt
1110b
External interrupt 3
1111b
Timer1 interrupt
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
DMA channel interrupt selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources
for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt
line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an
interrupt line with timer 1 (IMR/IFR bit 7). The interrupt source for DMA channel 0 is shared with a reserved
interrupt source. When the ’5402 is reset, the interrupts from these four DMA channels are deselected. The
INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used to select these
interrupts, as shown in Table 8.
Table 8. DMA Channel Interrupt Selection
INTSEL Value
IMR/IFR[6]
IMR/IFR[7]
IMR/IFR[10]
IMR/IFR[11]
00b (reset)
Reserved
TINT1
BRINT1
BXINT1
01b
Reserved
TINT1
DMAC2
DMAC3
10b
DMAC0
DMAC1
DMAC2
DMAC3
11b
26
Reserved
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memory-mapped registers
The ’5402 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h to
1Fh. Table 9 gives a list of CPU memory-mapped registers (MMRs) available on ’5402. The device also has
a set of memory-mapped registers associated with peripherals. Table 10, Table 11, and Table 12 show
additional peripheral MMRs associated with the ’5402.
Table 9. CPU Memory-Mapped Registers
ADDRESS
NAME
IMR
IFR
DESCRIPTION
DEC
HEX
0
0
Interrupt mask register
1
1
Interrupt flag register
2–5
2–5
Reserved for testing
ST0
6
6
Status register 0
ST1
7
7
Status register 1
AL
8
8
Accumulator A low word (15–0)
–
AH
9
9
Accumulator A high word (31–16)
AG
10
A
Accumulator A guard bits (39–32)
BL
11
B
Accumulator B low word (15–0)
BH
12
C
Accumulator B high word (31–16)
BG
13
D
Accumulator B guard bits (39–32)
TREG
14
E
Temporary register
TRN
15
F
Transition register
AR0
16
10
Auxiliary register 0
AR1
17
11
Auxiliary register 1
AR2
18
12
Auxiliary register 2
AR3
19
13
Auxiliary register 3
AR4
20
14
Auxiliary register 4
AR5
21
15
Auxiliary register 5
AR6
22
16
Auxiliary register 6
AR7
23
17
Auxiliary register 7
SP
24
18
Stack pointer register
BK
25
19
Circular buffer size register
BRC
26
1A
Block repeat counter
RSA
27
1B
Block repeat start address
REA
28
1C
Block repeat end address
PMST
29
1D
Processor mode status (PMST) register
XPC
30
1E
Extended program page register
–
31
1F
Reserved
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory-mapped registers (continued)
Table 10. Peripheral Memory-Mapped Registers
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NAME
ADDRESS
DESCRIPTION
TYPE
DRR20
20h
McBSP0 data receive register 2
McBSP #0
DRR10
21h
McBSP0 data receive register 1
McBSP #0
DXR20
22h
McBSP0 data transmit register 2
McBSP #0
DXR10
23h
McBSP0 data transmit register 1
McBSP #0
TIM
24h
Timer0 register
Timer0
PRD
25h
Timer0 period counter
Timer0
TCR
26h
Timer0 control register
Timer0
–
27h
Reserved
SWWSR
28h
Software wait-state register
External Bus
BSCR
29h
Bank-switching control register
External Bus
–
2Ah
Reserved
SWCR
2Bh
Software wait-state control register
2Ch
HPI control register
HPIC
–
2Dh–2Fh
External Bus
HPI
Reserved
TIM1
30h
Timer1 register
Timer1
PRD1
31h
Timer1 period counter
Timer1
TCR1
32h
Timer1 control register
Timer1
–
SPSA0
SPSD0
–
GPIOCR
GPIOSR
–
33h–37h
38h
39h
3Ah–3Bh
Reserved
McBSP0 subbank address register†
McBSP0 subbank data register†
McBSP #0
McBSP #0
Reserved
3Ch
General-purpose I/O pins control register
GPIO
3Dh
General-purpose I/O pins status register
GPIO
3Eh–3Fh
Reserved
DRR21
40h
McBSP1 data receive register 2
McBSP #1
DRR11
41h
McBSP1 data receive register 1
McBSP #1
DXR21
42h
McBSP1 data transmit register 2
McBSP #1
43h
McBSP1 data transmit register 1
McBSP #1
DXR11
–
SPSA1
SPSD1
–
44h–47h
48h
49h
4Ah–53h
DMPREC
54h
DMSA
55h
DMSDI
56h
DMSDN
CLKMD
Reserved
McBSP1 subbank address register†
McBSP1 subbank data register†
McBSP #1
Reserved
DMA channel priority and enable control register
DMA subbank address register‡
DMA
DMA
57h
DMA subbank data register with autoincrement‡
DMA subbank data register‡
58h
Clock mode register
PLL
–
59h–5Fh
Reserved
† See Table 11 for a detailed description of the McBSP control registers and their sub-addresses.
‡ See Table 12 for a detailed description of the DMA subbank addressed registers.
28
McBSP #1
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DMA
DMA
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
McBSP control registers and subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location.
The serial port subbank address (SPSA) register is used as a pointer to select a particular register within the
subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected register.
Table 11 shows the McBSP control registers and their corresponding sub-addresses.
Table 11. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
NAME
ADDRESS
SUBADDRESS
39h
SPCR11
49h
00h
Serial port control register 1
39h
SPCR21
49h
01h
Serial port control register 2
RCR10
39h
RCR11
49h
02h
Receive control register 1
RCR20
39h
RCR21
49h
03h
Receive control register 2
XCR10
39h
XCR11
49h
04h
Transmit control register 1
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NAME
ADDRESS
SPCR10
SPCR20
DESCRIPTION
XCR20
39h
XCR21
49h
05h
Transmit control register 2
SRGR10
39h
SRGR11
49h
06h
Sample rate generator register 1
SRGR20
39h
SRGR21
49h
07h
Sample rate generator register 2
MCR10
39h
MCR11
49h
08h
Multichannel register 1
MCR20
39h
MCR21
49h
09h
Multichannel register 2
RCERA0
39h
RCERA1
49h
0Ah
Receive channel enable register partition A
RCERB0
39h
RCERB1
49h
0Bh
Receive channel enable register partition B
XCERA0
39h
XCERA1
49h
0Ch
Transmit channel enable register partition A
XCERB0
39h
XCERB1
49h
0Dh
Transmit channel enable register partition B
PCR0
39h
PCR1
49h
0Eh
Pin control register
DMA subbank addressed registers
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register
within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register with
autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
post-incremented so that a subsequent access affects the next register within the subbank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 12 shows the DMA controller
subbank addressed registers and their corresponding subaddresses.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
29
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
DMA subbank addressed registers (continued)
Table 12. DMA Subbank Addressed Registers
DMA
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ÁÁÁÁÁ
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Á
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Á
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ADDRESS
SUBADDRESS
DMSRC0
56h/57h
00h
DMA channel 0 source address register
DMDST0
56h/57h
01h
DMA channel 0 destination address register
DMCTR0
56h/57h
02h
DMA channel 0 element count register
DMSFC0
56h/57h
03h
DMA channel 0 sync select and frame count register
DMMCR0
56h/57h
04h
DMA channel 0 transfer mode control register
DMSRC1
56h/57h
05h
DMA channel 1 source address register
DMDST1
56h/57h
06h
DMA channel 1 destination address register
DMCTR1
56h/57h
07h
DMA channel 1 element count register
DMSFC1
56h/57h
08h
DMA channel 1 sync select and frame count register
DMMCR1
56h/57h
09h
DMA channel 1 transfer mode control register
DMSRC2
56h/57h
0Ah
DMA channel 2 source address register
DMDST2
56h/57h
0Bh
DMA channel 2 destination address register
DMCTR2
56h/57h
0Ch
DMA channel 2 element count register
DMSFC2
56h/57h
0Dh
DMA channel 2 sync select and frame count register
DMMCR2
56h/57h
0Eh
DMA channel 2 transfer mode control register
DMSRC3
56h/57h
0Fh
DMA channel 3 source address register
DMDST3
56h/57h
10h
DMA channel 3 destination address register
DMCTR3
56h/57h
11h
DMA channel 3 element count register
DMSFC3
56h/57h
12h
DMA channel 3 sync select and frame count register
DMMCR3
56h/57h
13h
DMA channel 3 transfer mode control register
DMSRC4
56h/57h
14h
DMA channel 4 source address register
DMDST4
56h/57h
15h
DMA channel 4 destination address register
DMCTR4
56h/57h
16h
DMA channel 4 element count register
DMSFC4
56h/57h
17h
DMA channel 4 sync select and frame count register
DMMCR4
56h/57h
18h
DMA channel 4 transfer mode control register
DMSRC5
56h/57h
19h
DMA channel 5 source address register
DMDST5
56h/57h
1Ah
DMA channel 5 destination address register
DMCTR5
56h/57h
1Bh
DMA channel 5 element count register
DMSFC5
56h/57h
1Ch
DMA channel 5 sync select and frame count register
DMMCR5
56h/57h
1Dh
DMA channel 5 transfer mode control register
DMSRCP
56h/57h
1Eh
DMA source program page address (common channel)
DMDSTP
56h/57h
1Fh
DMA destination program page address (common channel)
DMIDX0
56h/57h
20h
DMA element index address register 0
DMIDX1
56h/57h
21h
DMA element index address register 1
DMFRI0
56h/57h
22h
DMA frame index register 0
DMFRI1
56h/57h
23h
DMA frame index register 1
DMGSA
56h/57h
24h
DMA global source address reload register
DMGDA
56h/57h
25h
DMA global destination address reload register
DMGCR
56h/57h
26h
DMA global count reload register
DMGFR
56h/57h
27h
DMA global frame count reload register
NAME
30
DESCRIPTION
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 13.
Table 13. Interrupt Locations and Priorities
NAME
LOCATION
DECIMAL
HEX
PRIORITY
FUNCTION
RS, SINTR
0
00
1
Reset (hardware and software reset)
NMI, SINT16
4
04
2
Nonmaskable interrupt
SINT17
8
08
—
Software interrupt #17
SINT18
12
0C
—
Software interrupt #18
SINT19
16
10
—
Software interrupt #19
SINT20
20
14
—
Software interrupt #20
SINT21
24
18
—
Software interrupt #21
SINT22
28
1C
—
Software interrupt #22
SINT23
32
20
—
Software interrupt #23
SINT24
36
24
—
Software interrupt #24
SINT25
40
28
—
Software interrupt #25
SINT26
44
2C
—
Software interrupt #26
SINT27
48
30
—
Software interrupt #27
SINT28
52
34
—
Software interrupt #28
SINT29
56
38
—
Software interrupt #29
SINT30
60
3C
—
Software interrupt #30
INT0, SINT0
64
40
3
External user interrupt #0
INT1, SINT1
68
44
4
External user interrupt #1
INT2, SINT2
72
48
5
External user interrupt #2
TINT0, SINT3
76
4C
6
Timer0 interrupt
BRINT0, SINT4
80
50
7
McBSP #0 receive interrupt
BXINT0, SINT5
84
54
8
McBSP #0 transmit interrupt
Reserved(DMAC0), SINT6
88
58
9
Reserved (default) or DMA channel 0 interrupt. The selection is made in the DMPREC
register.
TINT1(DMAC1), SINT7
92
5C
10
Timer1 interrupt (default) or DMA channel 1
interrupt. The selection is made in the
DMPREC register.
INT3, SINT8
96
60
11
External user interrupt #3
HPINT, SINT9
100
64
12
HPI interrupt
BRINT1(DMAC2), SINT10
104
68
13
McBSP #1 receive interrupt (default) or DMA
channel 2 interrupt. The selection is made in
the DMPREC register.
BXINT1(DMAC3), SINT11
108
6C
14
McBSP #1 transmit interrupt (default) or DMA
channel 3 interrupt. The selection is made in
the DMPREC register.
DMAC4,SINT12
112
70
15
DMA channel 4 interrupt
DMAC5,SINT13
116
74
16
DMA channel 5 interrupt
120–127
78–7F
—
Reserved
Reserved
POST OFFICE BOX 1443
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31
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
interrupts (continued)
The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 8.
15–14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RES
DMAC5
DMAC4
BXINT1
or
DMAC3
BRINT1
or
DMAC2
HPINT
INT3
TINT1
or
DMAC1
RES
or
DMAC0
BXINT0
BRINT0
TINT0
INT2
INT1
INT0
Figure 8. IFR and IMR Registers
Table 14. IFR and IMR Register Bit Fields
BIT
32
FUNCTION
NUMBER
NAME
15–14
–
13
DMAC5
DMA channel 5 interrupt flag/mask bit
12
DMAC4
DMA channel 4 interrupt flag/mask bit
11
BXINT1/DMAC3
This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA
channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.
10
BRINT1/DMAC2
This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA
channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.
9
HPINT
8
INT3
7
TINT1/DMAC1
This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1
interrupt flag/mask bit. The selection is made in the DMPREC register.
6
DMAC0
This bit can be configured as either reserved, or the DMA channel 0 interrupt flag/mask bit. The
selection is made in the DMPREC register.
5
BXINT0
McBSP0 transmit interrupt flag/mask bit
4
BRINT0
McBSP0 receive interrupt flag/mask bit
3
TINT0
2
INT2
External interrupt 2 flag/mask bit
1
INT1
External interrupt 1 flag/mask bit
0
INT0
External interrupt 0 flag/mask bit
Reserved for future expansion
Host to ’54x interrupt flag/mask
External interrupt 3 flag/mask
Timer 0 interrupt flag/mask bit
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
documentation support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the TMS320C5000 platform of DSPs:
TMS320C5000 DSP Family Functional Overview (literature number SPRU307)
Silicon Updates for the TMS320VC5402/TMS320UC5402 DSP (literature number SPRZ155)
Device-specific data sheets (such as this document)
Complete User Guides
Development-support tools
Hardware and software application reports
The five-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:
Volume 1: CPU and Peripherals (literature number SPRU131)
Volume 2: Mnemonic Instruction Set (literature number SPRU172)
Volume 3: Algebraic Instruction Set (literature number SPRU179)
Volume 4: Applications Guide (literature number SPRU173)
Volume 5: Enhanced Peripherals (literature number SPRU302)
The reference set describes in detail the TMS320C54x DSP generation of TMS320 DSP products currently
available and the hardware and software applications, including algorithms, for fixed-point TMS320 DSP
devices.
For general background information on DSPs and Texas Instruments (TI) devices, see the three-volume
publication Digital Signal Processing Applications with the TMS320 Family (literature numbers SPRA012,
SPRA016, and SPRA017).
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320, TMS320C5000, and TMS320C54x are trademarks of Texas Instruments.
POST OFFICE BOX 1443
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33
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage I/O range, DVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.0 V
Supply voltage core range, CVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.4 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to VSS.
recommended operating conditions
DVDD
Device supply voltage, I/O§
CVDD
Device supply voltage, core§
VSS
Supply voltage, GND
VIH
High-level
High
level input voltage
DVDD = 3.30.3 V
All other inputs
VIL
IOH
IOL
NOM
MAX
3
3.3
3.6
V
1.71
1.8
1.98
V
0
RS, INTn, NMI, BIO, BCLKR0, BCLKR1,
BCLKX0, BCLKX1, HCS, HDS1, HDS2, TDI,
TMS, CLKMDn
X2/CLKIN¶
TCK, TRST
Low-level input voltage
DVDD = 3.30.3 V
MIN
UNIT
V
2.2
DVDD + 0.3
1.35
CVDD+0.3
2.5
DVDD + 0.3
2
DVDD + 0.3
RS, INTn, NMI, X2/CLKIN¶, BIO, BCLKR0,
BCLKR1, BCLKX0, BCLKX1, HCS, HDS1,
HDS2, TCK, CLKMDn
–0.3
0.6
All other inputs
–0.3
0.8
V
V
High-level output current
–300
µA
Low-level output current
1.5
mA
TC
Operating case temperature
–40
100
°C
§ Texas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be
designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.
Excessive exposure to these conditions can adversely affect the long term reliability of the devices. System-level concerns such as bus contention
may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as or prior to the I/O
buffers and then powered down after the I/O buffers.
¶ All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN pin.
It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to
the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
34
POST OFFICE BOX 1443
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
VOH
High-level output voltage
IOH = MAX
VOL
Low-level output voltage
IIZ
Input current for D[15:0], HD[7:0]
out
uts in high
outputs
impedance
All other inputs
IOL = MAX
Bus holders enabled, DVDD = MAX,
VI = VSS to DVDD
II
DVDD = MAX, VO = VSS to DVDD
TRST
With internal pulldown
HPIENA
With internal pulldown
TMS, TCK, TDI, HPI
With internal pullups,
HPIENA = 0
((VI = VSS
to DVDD)
IDDP
UNIT
V
0.4
input only pins
All other input-only
IDDC
MAX
2.4
X2/CLKIN
Input
current
u cu
e
TYP†
–175
175
–5
5
–40
40
–5
300
–5
300
–300
5
5
–5
V
µA
µA
5
Supply current, core CPU
CVDD = 1.8 V, fclock = 100 MHz¶, TC = 25°C#
45
mA
Supply current, pins
DVDD = 3.3 V, fclock = 100 MHz¶, TC = 25°C||
30
mA
2
mA
20
µA
5
pF
IDD
Su ly current,
Supply
standby
Ci
Input capacitance
IDLE2
PLL × 1 mode,
IDLE3
Divide-by-two mode, CLKIN stopped
100 MHz input
Co
Output capacitance
5
pF
† All values are typical unless otherwise specified.
‡ All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN pin.
It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to
the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
§ HPI input signals except for HPIENA.
¶ Clock mode: PLL × 1 with external source
# This value represents the current consumption of the CPU, on-chip memory, and on-chip peripherals. Conditions include: program execution
from on-chip RAM, with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed.
|| This value was obtained using the following conditions: external memory writes at a rate of 20 million writes per second, CLKOFF=0, full-duplex
operation of McBSP0 and McBSP1 at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this
calculation is performed, refer to the Calculation of TMS320C54x Power Dissipation Application Report (literature number SPRA164).
PARAMETER MEASUREMENT INFORMATION
IOL
50 Ω
Tester Pin
Electronics
VLoad
CT
Output
Under
Test
IOH
Where:
IOL
IOH
VLoad
CT
=
=
=
=
1.5 mA (all outputs)
300 µA (all outputs)
1.5 V
40 pF typical load circuit capacitance
Figure 9. 3.3-V Test Load Circuit
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
35
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
internal oscillator with external crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT
is a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD register.
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series resistance
of 30 Ω and power dissipation of 1 mW.
The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 10.
The load capacitors, C1 and C2, should be chosen such that the equation below is satisfied. CL in the equation
is the load specified for the crystal.
CL C 1C 2
( C 1 C 2)
recommended operating conditions of internal oscillator with external crystal (see Figure 10)
MIN
fclock
Input clock frequency
10
X1
X2/CLKIN
Crystal
C1
C2
Figure 10. Internal Oscillator With External Crystal
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
MAX
UNIT
20
MHz
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
divide-by-two clock option (PLL disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate
the internal machine cycle. The selection of the clock mode is described in the clock generator section.
When an external clock source is used, the frequency injected must conform to specifications listed in the timing
requirements table.
NOTE:All revisions of the ’5402 can be operated with an external clock source, provided that the proper
voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to
the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended
operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
timing requirements (see Figure 11)
tc(CI)
tf(CI)
Cycle time, X2/CLKIN
MIN
MAX
20
†
ns
8
ns
Fall time, X2/CLKIN
UNIT
tr(CI)
Rise time, X2/CLKIN
8
ns
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]† (see Figure 10,
Figure 11, and the recommended operating conditions table)
PARAMETER
MIN
10‡
TYP
MAX
2tc(CI)
10
†
UNIT
ns
17
ns
tc(CO)
td(CIH-CO)
Cycle time, CLKOUT
tf(CO)
tr(CO)
Fall time, CLKOUT
2
ns
Rise time, CLKOUT
2
ns
Delay time, X2/CLKIN high to CLKOUT high/low
4
tw(COL)
Pulse duration, CLKOUT low
H–2
H
ns
tw(COH)
Pulse duration, CLKOUT high
H–2
H
ns
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
‡ It is recommended that the PLL clocking option be used for maximum frequency operation.
tr(CI)
tc(CI)
tf(CI)
X2/CLKIN
tw(COH)
tf(CO)
tc(CO)
tr(CO)
td(CIH-CO)
tw(COL)
CLKOUT
Figure 11. External Divide-by-Two Clock Timing
POST OFFICE BOX 1443
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37
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multiply-by-N clock option
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate
the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator
section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in the timing requirements table.
NOTE:All revisions of the ’5402 can be operated with an external clock source, provided that the proper
voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to
the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended
operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
timing requirements (see Figure 12)†
Integer PLL multiplier N (N = 1–15)
tc(CI)
PLL multiplier N = x.5
Cycle time, X2/CLKIN
PLL multiplier N = x.25, x.75
MIN
20‡
MAX
20‡
20‡
100
UNIT
200
ns
50
tf(CI)
Fall time, X2/CLKIN
8
ns
tr(CI)
Rise time, X2/CLKIN
8
ns
† N = Multiplication factor
‡ The multiplication factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified
range (tc(CO))
switching characteristics over
(see Figure 10 and Figure 12)
recommended
operating
conditions
PARAMETER
MIN
[H
=
MAX
10
TYP
tc(CI)/N†
4
10
17
tc(CO)
td(CI-CO)
Cycle time, CLKOUT
tf(CO)
tr(CO)
Fall time, CLKOUT
2
Rise time, CLKOUT
2
tw(COL)
tw(COH)
Pulse duration, CLKOUT low
H–2
Pulse duration, CLKOUT high
H–2
Delay time, X2/CLKIN high/low to CLKOUT high/low
0.5tc(CO)]
tp
Transitory phase, PLL lock up time
† N = Multiplication factor
tr(CI)
tc(CI)
tf(CI)
X2/CLKIN
td(CI-CO)
tc(CO)
tw(COL)
tp
CLKOUT
tf(CO)
tw(COH)
Unstable
Figure 12. External Multiply-by-One Clock Timing
38
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
tr(CO)
UNIT
ns
ns
ns
ns
H
ns
H
ns
30
s
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing
timing requirements for a memory read (MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 13)
MAX
UNIT
ta(A)M
ta(MSTRBL)
Access time, read data access from address valid
MIN
2H–7
ns
Access time, read data access from MSTRB low
2H–8
ns
tsu(D)R
th(D)R
Setup time, read data before CLKOUT low
th(A-D)R
Hold time, read data after address invalid
Hold time, read data after CLKOUT low
th(D)MSTRBH Hold time, read data after MSTRB high
† Address, PS, and DS timings are all included in timings referenced as address.
6
ns
–2
ns
0
ns
0
ns
switching characteristics over recommended operating conditions for a memory read
(MSTRB = 0)† (see Figure 13)
td(CLKL-A)
td(CLKH-A)
td(CLKL-MSL)
td(CLKL-MSH)
PARAMETER
Delay time, CLKOUT low to address valid‡
MIN
MAX
UNIT
–2
3
ns
Delay time, CLKOUT high (transition) to address valid§
–2
3
ns
Delay time, CLKOUT low to MSTRB low
–1
3
ns
Delay time, CLKOUT low to MSTRB high
–1
3
ns
–2
3
ns
–2
3
ns
th(CLKL-A)R
Hold time, address valid after CLKOUT low‡
th(CLKH-A)R
Hold time, address valid after CLKOUT high§
† Address, PS, and DS timings are all included in timings referenced as address.
‡ In the case of a memory read preceded by a memory read
§ In the case of a memory read preceded by a memory write
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
39
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
CLKOUT
td(CLKL-A)
th(CLKL-A)R
A[19:0]
th(A-D)R
tsu(D)R
ta(A)M
th(D)R
D[15:0]
th(D)MSTRBH
td(CLKL-MSL)
td(CLKL-MSH)
ta(MSTRBL)
MSTRB
R/W
PS, DS
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 13. Memory Read (MSTRB = 0)
40
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a memory write
(MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 14)
td(CLKH-A)
td(CLKL-A)
PARAMETER
Delay time, CLKOUT high to address valid‡
MIN
MAX
UNIT
–2
3
ns
Delay time, CLKOUT low to address valid§
–2
3
ns
td(CLKL-MSL)
td(CLKL-D)W
Delay time, CLKOUT low to MSTRB low
–1
3
ns
0
6
ns
td(CLKL-MSH)
td(CLKH-RWL)
Delay time, CLKOUT low to MSTRB high
–1
3
ns
Delay time, CLKOUT high to R/W low
–1
3
ns
td(CLKH-RWH)
td(RWL-MSTRBL)
Delay time, CLKOUT high to R/W high
–1
3
ns
H–2
H+1
ns
th(A)W
Hold time, address valid after CLKOUT high‡
1
3
ns
H+6§
ns
Delay time, CLKOUT low to data valid
Delay time, R/W low to MSTRB low
th(D)MSH
tw(SL)MS
Hold time, write data valid after MSTRB high
Pulse duration, MSTRB low
2H–2
H–3
tsu(A)W
tsu(D)MSH
Setup time, address valid before MSTRB low
2H–2
Setup time, write data valid before MSTRB high
ten(D–RWL)
Enable time, data bus driven after R/W low
tdis(RWH–D)
Disable time, R/W high to data bus high impedance
† Address, PS, and DS timings are all included in timings referenced as address.
‡ In the case of a memory write preceded by a memory write
§ In the case of a memory write preceded by an I/O cycle
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
2H–6
ns
ns
2H+5§
H–5
ns
ns
0
ns
41
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
CLKOUT
td(CLKH-A)
td(CLKL-A)
th(A)W
A[19:0]
td(CLKL-D)W
th(D)MSH
tsu(D)MSH
D[15:0]
td(CLKL-MSL)
tsu(A)W
tdis(RWH-D)
td(CLKL-MSH)
MSTRB
td(CLKH-RWL)
ten(D-RWL)
td(CLKH-RWH)
tw(SL)MS
td(RWL-MSTRBL)
R/W
PS, DS
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 14. Memory Write (MSTRB = 0)
42
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 15)
MIN
MAX
UNIT
ta(A)IO
ta(ISTRBL)IO
Access time, read data access from address valid
3H–7
ns
Access time, read data access from IOSTRB low
2H–7
ns
tsu(D)IOR
th(D)IOR
Setup time, read data before CLKOUT high
6
ns
Hold time, read data after CLKOUT high
0
ns
0
ns
th(ISTRBH-D)R
Hold time, read data after IOSTRB high
† Address and IS timings are included in timings referenced as address.
switching characteristics over recommended operating conditions for a parallel I/O port read
(IOSTRB = 0)† (see Figure 15)
PARAMETER
td(CLKL-A)
td(CLKH-ISTRBL)
MIN
MAX
Delay time, CLKOUT low to address valid
–2
3
ns
Delay time, CLKOUT high to IOSTRB low
–2
3
ns
–2
3
ns
0
3
ns
td(CLKH-ISTRBH) Delay time, CLKOUT high to IOSTRB high
th(A)IOR
Hold time, address after CLKOUT low
† Address and IS timings are included in timings referenced as address.
UNIT
CLKOUT
th(A)IOR
td(CLKL-A)
A[19:0]
tsu(D)IOR
ta(A)IO
th(D)IOR
D[15:0]
th(ISTRBH-D)R
td(CLKH-ISTRBH)
ta(ISTRBL)IO
td(CLKH-ISTRBL)
IOSTRB
R/W
IS
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 15. Parallel I/O Port Read (IOSTRB = 0)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
43
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port write
(IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 16)
PARAMETER
MIN
MAX
UNIT
td(CLKL-A)
td(CLKH-ISTRBL)
Delay time, CLKOUT low to address valid
–2
3
ns
Delay time, CLKOUT high to IOSTRB low
–2
3
ns
td(CLKH-D)IOW
td(CLKH-ISTRBH)
Delay time, CLKOUT high to write data valid
H–5
H+8
ns
Delay time, CLKOUT high to IOSTRB high
–2
3
ns
td(CLKL-RWL)
td(CLKL-RWH)
Delay time, CLKOUT low to R/W low
–1
3
ns
Delay time, CLKOUT low to R/W high
–1
3
ns
th(A)IOW
Hold time, address valid after CLKOUT low
0
3
ns
th(D)IOW
Hold time, write data after IOSTRB high
H–3
H+7
ns
tsu(D)IOSTRBH
Setup time, write data before IOSTRB high
H–7
H+1
ns
H–2
H+2
ns
tsu(A)IOSTRBL
Setup time, address valid before IOSTRB low
† Address and IS timings are included in timings referenced as address.
CLKOUT
tsu(A)IOSTRBL
td(CLKL-A)
th(A)IOW
A[19:0]
td(CLKH-D)IOW
th(D)IOW
D[15:0]
td(CLKH-ISTRBL)
td(CLKH-ISTRBH)
tsu(D)IOSTRBH
IOSTRB
td(CLKL-RWH)
td(CLKL-RWL)
R/W
IS
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 16. Parallel I/O Port Write (IOSTRB = 0)
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
ready timing for externally generated wait states
timing requirements for externally generated wait states [H = 0.5 tc(CO)]† (see Figure 17, Figure 18,
Figure 19, and Figure 20)
MIN
tsu(RDY)
th(RDY)
tv(RDY)MSTRB
th(RDY)MSTRB
tv(RDY)IOSTRB
th(RDY)IOSTRB
MAX
UNIT
Setup time, READY before CLKOUT low
6
ns
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low‡
0
ns
Hold time, READY after MSTRB low‡
Valid time, READY after IOSTRB low‡
4H
Hold time, READY after IOSTRB low‡
5H
4H–8
ns
ns
5H–8
ns
ns
tv(MSCL)
Valid time, MSC low after CLKOUT low
–1
3
ns
tv(MSCH)
Valid time, MSC high after CLKOUT low
–1
3
ns
† The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using
READY, at least two software wait states must be programmed.
‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
CLKOUT
A[19:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait States
Generated Internally
Wait State
Generated
by READY
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 17. Memory Read With Externally Generated Wait States
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
45
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[19:0]
D[15:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait States
Generated Internally
Wait State Generated
by READY
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 18. Memory Write With Externally Generated Wait States
46
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[19:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait
States
Generated
Internally
Wait State Generated
by READY
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 19. I/O Read With Externally Generated Wait States
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
47
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[19:0]
D[15:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait States
Generated
Internally
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 20. I/O Write With Externally Generated Wait States
48
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Wait State Generated
by READY
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
HOLD and HOLDA timings
timing requirements for memory control signals and HOLDA, [H = 0.5 tc(CO)] (see Figure 21)
MIN
tw(HOLD)
tsu(HOLD)
Pulse duration, HOLD low
Setup time, HOLD low/high before CLKOUT low
MAX
UNIT
4H+7
ns
7
ns
switching characteristics over recommended operating conditions for memory control signals
and HOLDA, [H = 0.5 tc(CO)] (see Figure 21)
MAX
UNIT
tdis(CLKL-A)
tdis(CLKL-RW)
Disable time, address, PS, DS, IS high impedance from CLKOUT low
PARAMETER
5
ns
Disable time, R/W high impedance from CLKOUT low
5
ns
tdis(CLKL-S)
ten(CLKL-A)
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
5
ns
Enable time, address, PS, DS, IS from CLKOUT low
2H+5
ns
ten(CLKL-RW)
ten(CLKL-S)
Enable time, R/W enabled from CLKOUT low
2H+5
ns
tv(HOLDA)
tw(HOLDA)
MIN
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
2
2H+5
ns
Valid time, HOLDA low after CLKOUT low
–1
2
ns
Valid time, HOLDA high after CLKOUT low
–1
2
ns
Pulse duration, HOLDA low duration
2H–1
ns
CLKOUT
tsu(HOLD)
tsu(HOLD)
tw(HOLD)
HOLD
tv(HOLDA)
tv(HOLDA)
tw(HOLDA)
HOLDA
tdis(CLKL-A)
ten(CLKL-A)
A[19:0]
PS, DS, IS
D[15:0]
tdis(CLKL-RW)
ten(CLKL-RW)
tdis(CLKL-S)
ten(CLKL-S)
tdis(CLKL-S)
ten(CLKL-S)
R/W
MSTRB
IOSTRB
Figure 21. HOLD and HOLDA Timings (HM = 1)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
49
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
reset, BIO, interrupt, and MP/MC timings
timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 tc(CO)] (see Figure 22, Figure 23,
and Figure 24)
MIN
MAX
UNIT
th(RS)
th(BIO)
Hold time, RS after CLKOUT low
0
ns
Hold time, BIO after CLKOUT low
0
ns
th(INT)
th(MPMC)
Hold time, INTn, NMI, after CLKOUT low†
0
ns
0
ns
tw(RSL)
tw(BIO)S
Hold time, MP/MC after CLKOUT low
Pulse duration, RS low‡§
4H+5
ns
Pulse duration, BIO low, synchronous
2H+2
ns
tw(BIO)A
tw(INTH)S
Pulse duration, BIO low, asynchronous
4H
ns
Pulse duration, INTn, NMI high (synchronous)
2H
ns
tw(INTH)A
tw(INTL)S
Pulse duration, INTn, NMI high (asynchronous)
4H
ns
Pulse duration, INTn, NMI low (synchronous)
2H+2
ns
tw(INTL)A
tw(INTL)WKP
Pulse duration, INTn, NMI low (asynchronous)
4H
ns
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
Setup time, RS before X2/CLKIN low¶
10
ns
5
ns
tsu(RS)
tsu(BIO)
Setup time, BIO before CLKOUT low
7
10
ns
tsu(INT)
Setup time, INTn, NMI, RS before CLKOUT low
7
10
ns
tsu(MPMC)
Setup time, MP/MC before CLKOUT low
5
ns
† The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure
synchronization and lock-in of the PLL.
§ Note that RS may cause a change in clock frequency, therefore changing the value of H.
¶ Divide-by-two mode
50
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
reset, BIO, interrupt, and MP/MC timings (continued)
X2/CLKIN
tsu(RS)
tw(RSL)
RS, INTn, NMI
tsu(INT)
th(RS)
CLKOUT
tsu(BIO)
th(BIO)
BIO
tw(BIO)S
Figure 22. Reset and BIO Timings
CLKOUT
tsu(INT)
tsu(INT)
th(INT)
INTn, NMI
tw(INTH)A
tw(INTL)A
Figure 23. Interrupt Timing
CLKOUT
RS
th(MPMC)
tsu(MPMC)
MP/MC
Figure 24. MP/MC Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
51
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings
switching characteristics over recommended operating conditions for IAQ and IACK
[H = 0.5 tc(CO)] (see Figure 25)
PARAMETER
MIN
MAX
UNIT
td(CLKL-IAQL)
td(CLKL-IAQH)
Delay time, CLKOUT low to IAQ low
–1
3
ns
Delay time, CLKOUT low to IAQ high
–1
3
ns
td(A)IAQ
td(CLKL-IACKL)
Delay time, address valid to IAQ low
1
ns
Delay time, CLKOUT low to IACK low
–1
3
ns
td(CLKL-IACKH)
td(A)IACK
Delay time , CLKOUT low to IACK high
–1
3
ns
3
ns
th(A)IAQ
th(A)IACK
Hold time, IAQ high after address invalid
tw(IAQL)
tw(IACKL)
Pulse duration, IAQ low
Pulse duration, IACK low
2H–2
ns
Delay time, address valid to IACK low
Hold time, IACK high after address invalid
–2
ns
–2
ns
2H–2
ns
CLKOUT
A[19:0]
td(CLKL-IAQH)
td(CLKL-IAQL)
th(A)IAQ
td(A)IAQ
tw(IAQL)
IAQ
td(CLKL-IACKL)
th(A)IACK
td(A)IACK
tw(IACKL)
IACK
MSTRB
Figure 25. IAQ and IACK Timings
52
POST OFFICE BOX 1443
td(CLKL-IACKH)
• HOUSTON, TEXAS 77251–1443
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings
(continued)
switching characteristics over recommended operating conditions for XF and TOUT
[H = 0.5 tc(CO)] (see Figure 26 and Figure 27)
PARAMETER
td(XF)
MIN
MAX
Delay time, CLKOUT low to XF high
–1
3
Delay time, CLKOUT low to XF low
–1
3
UNIT
ns
td(TOUTH)
td(TOUTL)
Delay time, CLKOUT low to TOUT high
0
4
ns
Delay time, CLKOUT low to TOUT low
0
4
ns
tw(TOUT)
Pulse duration, TOUT
2H
ns
CLKOUT
td(XF)
XF
Figure 26. XF Timing
CLKOUT
td(TOUTH)
td(TOUTL)
TOUT
tw(TOUT)
Figure 27. TOUT Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
53
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing
timing requirements for McBSP [H=0.5tc(CO)]†(see Figure 28 and Figure 29)
MIN
MAX
UNIT
tc(BCKRX)
tw(BCKRX)
Cycle time, BCLKR/X
BCLKR/X ext
4H
ns
Pulse duration, BCLKR/X high or BCLKR/X low
BCLKR/X ext
2H–2
ns
tsu(BFRH-BCKRL)
Setup time,
time external BFSR high before BCLKR low
th(BCKRL-BFRH)
Hold time
time, external BFSR high after BCLKR low
tsu(BDRV-BCKRL)
Setup time,
time BDR valid before BCLKR low
th(BCKRL-BDRV)
Hold time
time, BDR valid after BCLKR low
tsu(BFXH-BCKXL)
Setup time,
time external BFSX high before BCLKX low
th(BCKXL-BFXH)
Hold time,
time external BFSX high after BCLKX low
BCLKR int
8
BCLKR ext
1
BCLKR int
0
BCLKR ext
3
BCLKR int
5
BCLKR ext
0
BCLKR int
0
BCLKR ext
4
BCLKX int
7
BCLKX ext
0
BCLKX int
0
BCLKX ext
3
ns
ns
ns
ns
ns
ns
tr(BCKRX)
Rise time, BCKR/X
BCLKR/X ext
8
ns
tf(BCKRX)
Fall time, BCKR/X
BCLKR/X ext
8
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
switching characteristics for McBSP [H=0.5tc(CO)]† (see Figure 28 and Figure 29)
PARAMETER
tc(BCKRX)
tw(BCKRXH)
Cycle time, BCLKR/X
Pulse duration, BCLKR/X high
tw(BCKRXL)
Pulse duration, BCLKR/X low
td(BCKRH-BFRV)
Delay time
time, BCLKR high to internal BFSR valid
td(BCKXH-BFXV)
Delay time,
time BCLKX high to internal BFSX valid
Disable time, BCLKX high to BDX high im
impedance
edance following last data
tdis(BCKXH-BDXHZ)
bit of transfer
td(BCKXH-BDXV)
td(BFXH-BDXV)
MIN
MAX
BCLKR/X int
4H
D – 2‡
D + 2‡
ns
BCLKR/X int
C – 2‡
C + 2‡
ns
BCLKR int
–2
2
ns
BCLKR ext
3
9
ns
BCLKX int
0
4
BCLKX ext
8
11
BCLKX int
–1
4
BCLKX ext
9
BCLKX int
3
0¶
BCLKX ext
3
11
BCLKR/X int
Delay time,
time BCLKX high to BDX valid
DXENA = 0§
UNIT
ns
ns
ns
7
Delay time, BFSX high to BDX valid
BFSX int
–1¶
3
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
BFSX ext
3
13
ns
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ T = BCLKRX period = (1 + CLKGDV) * 2H
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ The transmit delay enable (DXENA) and A–bis mode (ABIS) features of the McBSP are not implemented on the TMS320VC5402.
¶ Minimum delay times also represent minimum output hold times.
54
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
tc(BCKRX)
tw(BCKRXH)
tr(BCKRX)
tw(BCKRXL)
BCLKR
td(BCKRH–BFRV)
td(BCKRH–BFRV)
tr(BCKRX)
BFSR (int)
tsu(BFRH–BCKRL)
th(BCKRL–BFRH)
BFSR (ext)
th(BCKRL–BDRV)
tsu(BDRV–BCKRL)
BDR
(RDATDLY=00b)
Bit (n–1)
(n–2)
tsu(BDRV–BCKRL)
(n–3)
(n–4)
th(BCKRL–BDRV)
BDR
(RDATDLY=01b)
Bit (n–1)
(n–2)
tsu(BDRV–BCKRL)
BDR
(RDATDLY=10b)
(n–3)
th(BCKRL–BDRV)
Bit (n–1)
(n–2)
Figure 28. McBSP Receive Timings
tc(BCKRX)
tw(BCKRXH)
tw(BCKRXL)
tr(BCKRX)
tf(BCKRX)
BCLKX
td(BCKXH–BFXV)
td(BCKXH–BFXV)
BFSX (int)
tsu(BFXH–BCKXL)
th(BCKXL–BFXH)
BFSX (ext)
td(BDFXH–BDXV)
BDX
(XDATDLY=00b)
Bit 0
Bit (n–1)
td(BCKXH–BDXV)
(n–2)
(n–3)
(n–4)
td(BCKXH–BDXV)
BDX
(XDATDLY=01b)
Bit (n–1)
Bit 0
(n–3)
td(BCKXH–BDXV)
tdis(BCKXH–BDXHZ)
BDX
(XDATDLY=10b)
(n–2)
Bit 0
Bit (n–1)
(n–2)
Figure 29. McBSP Transmit Timings
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
55
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
timing requirements for McBSP general-purpose I/O (see Figure 30)
MIN
tsu(BGPIO-COH)
th(COH-BGPIO)
Setup time, BGPIOx input mode before CLKOUT high†
Hold time, BGPIOx input mode after CLKOUT high†
MAX
UNIT
9
ns
0
ns
† BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
switching characteristics for McBSP general-purpose I/O (see Figure 30)
PARAMETER
Delay time, CLKOUT high to BGPIOx output mode‡
td(COH-BGPIO)
‡ BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
tsu(BGPIO-COH)
td(COH-BGPIO)
CLKOUT
th(COH-BGPIO)
BGPIOx Input
Mode†
BGPIOx Output
Mode‡
† BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
‡ BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 30. McBSP General-Purpose I/O Timings
56
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
MIN
MAX
0
5
UNIT
ns
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 0†
(see Figure 31)
MASTER
MIN
SLAVE
MAX
MIN
MAX
UNIT
tsu(BDRV-BCKXL)
th(BCKXL-BDRV)
Setup time, BDR valid before BCLKX low
9
– 12H
ns
Hold time, BDR valid after BCLKX low
0
5 + 12H
ns
tsu(BFXL-BCKXH)
Setup time, BFSX low before BCLKX high
10
ns
32H
ns
tc(BCKX)
Cycle time, BCLKX
12H
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b,
CLKXP = 0† (see Figure 31)
MASTER‡
PARAMETER
MIN
th(BCKXL-BFXL)
td(BFXL-BCKXH)
Hold time, BFSX low after BCLKX low§
Delay time, BFSX low to BCLKX high¶
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX low
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
SLAVE
MAX
MIN
MAX
UNIT
T–3
T+4
ns
C–5
C+3
ns
–2
6
C–2
C+3
6H + 5
10H + 15
ns
ns
2H+ 4
6H + 17
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4H – 2
8H + 17
ns
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
LSB
tsu(BFXL-BCKXH)
tc(BCKX)
MSB
BCLKX
th(BCKXL-BFXL)
td(BFXL-BCKXH)
BFSX
tdis(BFXH-BDXHZ)
tdis(BCKXL-BDXHZ)
BDX
Bit 0
td(BFXL-BDXV)
td(BCKXH-BDXV)
Bit(n-1)
tsu(BDRV-BCLXL)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXL-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 31. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
57
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 0†
(see Figure 32)
MASTER
MIN
tsu(BDRV-BCKXH)
th(BCKXH-BDRV)
Setup time, BDR valid before BCLKX high
tsu(BFXL-BCKXH)
Setup time, BFSX low before BCLKX high
Hold time, BDR valid after BCLKX high
SLAVE
MAX
MIN
MAX
UNIT
12
2 – 12H
ns
4
5 + 12H
ns
10
ns
32H
ns
tc(BCKX)
Cycle time, BCLKX
12H
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b,
CLKXP = 0† (see Figure 32)
MASTER‡
PARAMETER
SLAVE
MIN
MAX
UNIT
MIN
MAX
C–3
C+4
ns
T–5
T+3
ns
th(BCKXL-BFXL)
td(BFXL-BCKXH)
Hold time, BFSX low after BCLKX low§
Delay time, BFSX low to BCLKX high¶
td(BCKXL-BDXV)
Delay time, BCLKX low to BDX valid
–2
6
6H + 5
10H + 15
ns
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX low
–2
4
6H + 3
10H + 17
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
D–2 D+4
4H – 2
8H + 17
ns
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
LSB
tc(BCKX)
MSB
tsu(BFXL-BCKXH)
BCLKX
td(BFXL-BCKXH)
th(BCKXL-BFXL)
BFSX
tdis(BCKXL-BDXHZ)
BDX
td(BCKXL-BDXV)
td(BFXL-BDXV)
Bit 0
Bit(n-1)
tsu(BDRV-BCKXH)
BDR
Bit 0
(n-2)
(n-3)
th(BCKXH-BDRV)
Bit(n-1)
(n-2)
(n-3)
Figure 32. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
58
POST OFFICE BOX 1443
(n-4)
• HOUSTON, TEXAS 77251–1443
(n-4)
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 1†
(see Figure 33)
MASTER
MIN
tsu(BDRV-BCKXH)
th(BCKXH-BDRV)
Setup time, BDR valid before BCLKX high
tsu(BFXL-BCKXL)
Setup time, BFSX low before BCLKX low
Hold time, BDR valid after BCLKX high
SLAVE
MAX
MIN
MAX
UNIT
12
2 – 12H
ns
4
5 + 12H
ns
10
ns
32H
ns
tc(BCKX)
Cycle time, BCLKX
12H
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b,
CLKXP = 1†‡ (see Figure 33)
MASTER
PARAMETER
MIN
th(BCKXH-BFXL)
td(BFXL-BCKXL)
Hold time, BFSX low after BCLKX high§
Delay time, BFSX low to BCLKX low¶
td(BCKXL-BDXV)
Delay time, BCLKX low to BDX valid
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX high
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
SLAVE
MAX
MIN
MAX
UNIT
T–3
T+4
ns
D–5
D+3
ns
–2
6
D–2
D+3
6H + 5
10H + 15
ns
ns
2H + 3
6H + 17
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4H – 2
8H + 17
ns
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
tsu(BFXL-BCKXL)
LSB
tc(BCKX)
MSB
BCLKX
th(BCKXH-BFXL)
td(BFXL-BCKXL)
BFSX
td(BFXL-BDXV)
tdis(BFXH-BDXHZ)
tdis(BCKXH-BDXHZ)
BDX
td(BCKXL-BDXV)
Bit 0
Bit(n-1)
tsu(BDRV-BCKXH)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXH-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
59
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 1†
(see Figure 34)
MASTER
MIN
SLAVE
MAX
MIN
UNIT
MAX
tsu(BDRV-BCKXL)
th(BCKXL-BDRV)
Setup time, BDR valid before BCLKX low
9
– 12H
ns
Hold time, BDR valid after BCLKX low
0
5 + 12H
ns
tsu(BFXL-BCKXL)
Setup time, BFSX low before BCLKX low
10
ns
32H
ns
tc(BCKX)
Cycle time, BCLKX
12H
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b,
CLKXP = 1†‡ (see Figure 34)
MASTER‡
PARAMETER
SLAVE
MIN
UNIT
MIN
MAX
MAX
D–3
D+4
ns
T–5
T+3
ns
th(BCKXH-BFXL)
td(BFXL-BCKXL)
Hold time, BFSX low after BCLKX high§
Delay time, BFSX low to BCLKX low¶
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
–2
6
6H + 5
10H + 15
ns
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX high
–2
4
6H + 3
10H + 17
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
C–2 C+4
4H – 2
8H + 17
ns
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
LSB
tsu(BFXL-BCKXL)
tc(BCKX)
MSB
BCLKX
th(BCKXH-BFXL)
td(BFXL-BCKXL)
BFSX
tdis(BCKXH-BDXHZ)
BDX
td(BCKXH-BDXV)
td(BFXL-BDXV)
Bit 0
Bit(n-1)
tsu(BDRV-BCKXL)
BDR
Bit 0
(n-2)
(n-3)
th(BCKXL-BDRV)
Bit(n-1)
(n-2)
(n-3)
Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
60
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(n-4)
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
HPI8 timing
switching characteristics over recommended operating conditions†‡§¶ [H = 0.5tc(CO)]
(see Figure 35, Figure 36, Figure 37, and Figure 38)
PARAMETER
ten(DSL-HD)
Enable time, HD driven from DS low
MIN
MAX
UNIT
2
16
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) < 18H
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) ≥ 18H
td(DSL-HDV1)
d(DSL HDV1)
Delay time, DS low to HDx valid for
first byte of an HPI read
26H+16 – tw(DSH)
ns
16
Case 2a: Memory accesses when
DMAC is inactive and tw(DSH) < 10H
10H+16 – tw(DSH)
Case 2b: Memory accesses when
DMAC is inactive and tw(DSH) ≥ 10H
16
Case 3: Register accesses
16
Delay time, DS low to HDx valid for second byte of an HPI read
tv(HYH-HDV)
td(DSH-HYL)
Valid time, HDx valid after HRDY high
Hold time, HDx valid after DS high, for a HPI read
3
16
ns
5
ns
9
Delay time, DS high to HRDY low (see Note 1)
time DS high to HRDY high
Delay time,
16
Case 1c: Memory access when
DMAC is active in 32-bit mode and
tw(DSH) < 26H
Case 1d: Memory access when
DMAC is active in 32-bit mode and
tw(DSH) ≥ 26H
td(DSL-HDV2)
th(DSH-HDV)R
td(DSH-HYH)
18H+16 – tw(DSH)
16
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode
18H+16
ns
Case 1b: Memory accesses when
DMAC is active in 32-bit mode
26H+16
ns
Case 2: Memory accesses when
DMAC is inactive
10H+16
Case 3: Write accesses to HPIC
register (see Note 2)
6H+16
ns
td(HCS-HRDY)
td(COH-HYH)
Delay time, HCS low/high to HRDY low/high
16
ns
Delay time, CLKOUT high to HRDY high
3
ns
td(COH-HTX)
Delay time, CLKOUT high to HINT change
5
ns
td(COH-GPIO)
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output.
6
ns
NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.
2. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronoulsy, and do not cause HRDY to be deasserted.
† DS refers to the logical OR of HCS, HDS1, and HDS2.
‡ HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
§ DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
¶ GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
HPI8 timing (continued)
timing requirements†‡§ (see Figure 35, Figure 36, Figure 37, and Figure 38)
MIN
MAX
UNIT
tsu(HBV-DSL)
th(DSL-HBV)
Setup time, HBIL and HAD valid before DS low or before HAS low¶#
Hold time, HBIL and HAD valid after DS low or after HAS low¶#
5
ns
5
ns
tsu(HSL-DSL)
tw(DSL)
Setup time, HAS low before DS low
10
ns
Pulse duration, DS low
20
ns
tw(DSH)
tsu(HDV-DSH)
Pulse duration, DS high
10
ns
Setup time, HDx valid before DS high, HPI write
2
ns
th(DSH-HDV)W
tsu(GPIO-COH)
Hold time, HDx valid after DS high, HPI write
3
ns
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
6
ns
th(GPIO-COH)
Hold time, HDx input valid after CLKOUT high, HDx configured as general-purpose input
0
ns
† DS refers to the logical OR of HCS, HDS1, and HDS2.
‡ HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
§ GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
¶ HAD refers to HCNTL0, HCNTL1, and H/RW.
# When the HAS signal is used to latch the control signals, this timing refers to the falling edge of the HAS signal. Otherwise, when HAS is not used
(always high), this timing refers to the falling edge of DS.
62
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
HPI8 timing (continued)
Second Byte
First Byte
Second Byte
HAS
tsu(HBV-DSL)
tsu(HSL-DSL)
th(DSL-HBV)
HAD†
Valid
Valid
tsu(HBV-DSL)‡
th(DSL-HBV)‡
HBIL
HCS
tw(DSH)
tw(DSL)
HDS
td(DSH-HYH)
td(DSH-HYL)
HRDY
ten(DSL-HD)
td(DSL-HDV2)
td(DSL-HDV1)
th(DSH-HDV)R
HD READ
Valid
Valid
tsu(HDV-DSH)
Valid
tv(HYH-HDV)
th(DSH-HDV)W
HD WRITE
Valid
Valid
Valid
td(COH-HYH)
CLKOUT
† HAD refers to HCNTL0, HCNTL1, and HR/W.
‡ When HAS is not used (HAS always high)
Figure 35. Using HDS to Control Accesses (HCS Always Low)
POST OFFICE BOX 1443
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63
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
HPI8 timing (continued)
First Byte
Second Byte
Second Byte
HCS
HDS
td(HCS-HRDY)
HRDY
Figure 36. Using HCS to Control Accesses
CLKOUT
td(COH-HTX)
HINT
Figure 37. HINT Timing
CLKOUT
tsu(GPIO-COH)
th(GPIO-COH)
GPIOx Input Mode†
td(COH-GPIO)
GPIOx Output Mode†
† GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
Figure 38. GPIOx† Timings
64
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°–7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
PARAMETER
°C/W
RΘJA
56
RΘJC
5
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
65
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
MECHANICAL DATA
GGU (S-PBGA-N144)
PLASTIC BALL GRID ARRAY PACKAGE
12,10
SQ
11,90
9,60 TYP
0,80
0,80
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13
0,95
0,85
1,40 MAX
Seating Plane
0,12
0,08
0,55
0,45
0,08 M
0,45
0,35
0,10
4073221-2/B 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Thermal Resistance Characteristics
66
PARAMETER
°C/W
RΘJA
38
RΘJC
5
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DSG5402PGE100
ACTIVE
LQFP
PGE
144
Lead/Ball Finish
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
MSL Peak Temp (3)
Level-2-260C-1YR
TMS320VC5402GGU100
ACTIVE
BGA
GGU
144
160
TBD
SNPB
Level-3-220C-168HR
TMS320VC5402GGUR10
ACTIVE
BGA
GGU
144
1000
TBD
SNPB
Level-3-220C-168HR
TMS320VC5402PGE100
ACTIVE
LQFP
PGE
144
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YR
TMS320VC5402PGER10
ACTIVE
LQFP
PGE
144
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TMS320VC5402ZGU100
ACTIVE
BGA
ZGU
144
160
Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168HR
TMS32C5402PGER10G4
ACTIVE
LQFP
PGE
144
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TMX320VC5402GGU100
OBSOLETE
BGA
GGU
144
TBD
Call TI
Call TI
TMX320VC5402PGE100
OBSOLETE
LQFP
PGE
144
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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