Hynix HY5V66EF6P-P 64mb synchronous dram based on 1m x 4bank x16 i/o Datasheet

64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O
Document Title
4Bank x 1M x 16bits Synchronous DRAM
Revision History
Revision No.
0.01
History
Initial Draft
Draft Date
Remark
Dec. 2004
Preliminary
June. 2005
Preliminary
1. Editorial chage
0.80Typ --> 0.45 +/-0.05 (page12, Ball Dimension)
Before dimension :
0.80 Typ.
0.2
0.65 Typ.
After dimension :
0.450 +/- 0.05
0.65 Typ.
2. Added
Speed Product(100MHz CL2) (see to Page 02)
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.2 / June. 2005
1
11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
DESCRIPTION
The Hynix HY5V66E(L)F6(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V66E(L)F6(P) is organized as 4banks of 1,048,576 x 16.
HY5V66E(L)F6(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)
FEATURES
•
Voltage: VDD, VDDQ 3.3V supply voltage
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 Refresh cycles / 64ms
•
60 Ball FBGA (Lead or Lead Free Package)
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of
system clock
•
Data mask function by UDQM, LDQM
•
Internal four banks operation
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency; 2, 3 Clocks
•
Burst Read Single Write operation
ORDERING INFORMATION
Part No.
Clock Frequency
HY5V66E(L)F6(P)-5
200MHz
HY5V66E(L)F6(P)-6
166MHz
HY5V66E(L)F6(P)-7
143MHz
HY5V66E(L)F6(P)-H
133MHz
HY5V66E(L)F6(P)-P
100MHz
CL
Organization
Interface
Package
3
4Banks x 1Mbits
x16
LVTTL
60 Ball FBGA
2
Note:
1. HY5V66EF6 Series: Normal power, Leaded.
2. HY5V66ELF6 Series: Low power, Leaded.
3. HY5V66EF6P Series: Normal power, Lead Free.
4. HY5V66ELF6P Series: Low power, Lead Free.
Rev. 0.2 / June. 2005
2
11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
BALL CONFIGURATION
VDD
A1
A10
BA0
/CS
/CAS
/WE
NC
DQ7
DQ6
DQ5
DQ3
DQ2
DQ1
VDD
7
A3
A2
A0
BA1
NC
/RAS
LDQM
VDD
NC
VSSQ
VDDQ
DQ4
VSSQ
VDDQ
DQ0
6
5
Bottom View
4
3
A4
A5
A7
A9
NC
CLK
UDQM
VSS
NC
VDDQ
VSSQ
DQ11
VDDQ
VSSQ
DQ15
2
VSS
A6
A8
A11
CKE
NC
NC
NC
DQ8
DQ9
DQ10
DQ12
DQ13
DQ14
VSS
1
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
BALL DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
CLK
INPUT
Clock: The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE
INPUT
Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among (deep) power down, suspend or self refresh
CS
INPUT
Chip Select: Enables or disables all inputs except CLK, CKE, UDQM and LDQM
BA0, BA1
INPUT
Bank Address: Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
INPUT
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
RAS, CAS, WE
INPUT
Command Inputs: RAS, CAS and WE define the operation
Refer function truth table for details
UDQM, LDQM
INPUT
Data Mask: Controls output buffers in read mode and masks input data in write
mode
DQ0 ~ DQ15
I/O
VDD/VSS
SUPPLY
Power supply for internal circuits
VDDQ/VSSQ
SUPPLY
Power supply for output buffers
NC
-
Rev. 0.2 / June. 2005
Data Input / Output: Multiplexed data input / output pin
No connection : These pads should be left unconnected
3
11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Internal Row
Counter
Self refresh
logic & timer
1Mx16 BANK 3
CLK
CAS
Column Active
U/LDQM
A0
Address Buffers
BA1
DQ0
DQ15
Y-Decoder
Column Add
Counter
Bank Select
A11
Memory
Cell
Array
Column
Pre
Decoder
WE
A1
1Mx16 BANK 0
I/O Buffer & Logic
Refresh
1Mx16 BANK 1
Sense AMP & I/O Gate
State Machine
RAS
1Mx16 BANK 2
X-Decoder
X-Decoder
X-Decoder
X-Decoder
CKE
CS
Row
Pre
Decoder
Row Active
Address
Register
Mode Register
Burst
Counter
CAS Latency
Data Out Control
Pipe Line
Control
BA0
Rev. 0.2 / June. 2005
4
11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1
BA0
A11
A10
A9
A8
A7
0
0
0
0
OP Code
0
0
A6
A5
A4
CAS Latency
A3
A2
BT
A1
A0
Burst Length
OP Code
A9
Write Mode
0
Burst Read and Burst Write
1
Burst Read and Single Write
CAS Latency
Burst Type
A3
Burst Type
0
Sequential
1
Interleave
Burst Length
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
0
1
0
1
1
0
1
0
Burst Length
A2
A1
A0
1
0
0
0
2
0
0
1
3
0
1
0
4
4
0
Reserved
0
1
1
8
8
1
Reserved
1
0
0
Reserved
Reserved
Reserved
A3 = 0
A3=1
0
1
1
1
2
2
1
1
0
Reserved
1
0
1
Reserved
1
1
1
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
Rev. 0.2 / June. 2005
5
11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
ABSOLUTE MAXIMUM RATING
Parameter
Symbol
Rating
Ambient Temperature
TA
0 ~ 70
Storage Temperature
TSTG
-55 ~ 125
oC
VIN, VOUT
VDD, VDDQ
IOS
PD
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
V
V
mA
W
TSOLDER
260 . 10
Voltage on Any Pin relative to VSS
Voltage on VDD supply relative to VSS
Short Circuit Output Current
Power Dissipation
Soldering Temperature . Time
Unit
o
C
oC . Sec
DC OPERATING CONDITION (TA= 0 to 70oC)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VDD, VDDQ
VIH
VIL
Min
3.0
2.0
-0.3
Typ
3.3
3.0
-
Max
3.6
VDDQ+0.3
0.8
Unit
V
V
V
Note
1
1, 2
1, 3
Note: 1. All voltages are referenced to VSS = 0V
2. VIH (max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3. VIL (min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA= 0 to 70 oC, VDD=3.3±0.3V, VSS=0V)
Parameter
AC Input High / Low Level Voltage
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
Symbol
VIH / VIL
Vtrip
tR / tF
Voutref
CL
Value
2.4 / 0.4
1.4
1
1.4
30
Unit
V
V
ns
V
pF
Note
1
Note 1.
Vtt=1.4V
Vtt=1.4V
RT=500 Ω
Output
Output
RT=50 Ω
Z0 = 50Ω
30pF
DC Output Load Circuit
Rev. 0.2 / June. 2005
30pF
AC Output Load Circuit
6
11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
CAPACITANCE (TA= 0 to 70 oC, f=1MHz, VDD=3.3V)
Parameter
Pin
Symbol
Min
Max
Unit
CLK
CI1
2.0
4.0
pF
Input capacitance
A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS,
WE, LDQM, UDQM
CI2
2.0
4.0
pF
Data input / output capacitance
DQ0 ~ DQ15
CI/O
3.0
5.5
pF
DC CHARACTERRISTICS I (TA= 0 to 70oC)
Parameter
Symbol
Min
Max
Unit
Note
Input Leakage Current
ILI
-1
1
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IOH = -2mA
Output Low Voltage
VOL
-
0.4
V
IOL = +2mA
Note:
1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 3.6
Rev. 0.2 / June. 2005
7
11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
DC CHARACTERISTICS II (TA= 0 to 70oC)
Parameter
Operating Current
Symbol
IDD1
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
5
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
6
7
120 110
H
100
P
Unit Note
mA
CKE ≤ VIL(max), tCK = 15ns
2
mA
CKE ≤ VIL(max), tCK = ∞
2
mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCK
= 15ns
Input signals are changed one time
during 2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
18
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
18
IDD3P
CKE ≤ VIL(max), tCK = 15ns
3
IDD3PS
CKE ≤ VIL(max), tCK = ∞
3
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK
= 15ns
Input signals are changed one time
during 2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
40
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
35
Precharge Standby Current IDD2P
in Power Down Mode
IDD2PS
Precharge Standby Current
in Non Power Down Mode
Speed
Test Condition
IDD2N
IDD3NS
1
mA
mA
mA
Burst Mode Operating CurIDD4
rent
tCK ≥ tCK(min), IOL=0mA
All banks active
120 110
100
mA
1
Auto Refresh Current
IDD5
tRC ≥ tRC(min), All banks active
210 195
180
mA
2
Self Refresh Current
IDD6
CKE ≤ 0.2V
Normal
1
mA
Low power
400
uA
3
Note :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. HY5V66EF6(P) Series : Normal Power / HY5V66ELF6(P) Series : Low Power
Rev. 0.2 / June. 2005
8
11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
Symbol
5
6
7
H
P
Min Max Min Max Min Max Min Max Min Max
Unit Note
CAS
Latency=3
tCK3
5.0
CAS
Latency=2
tCK2
10
Clock High Pulse Width
tCHW
2.0
-
2.5
-
3.0
-
3.0
-
3.0
-
ns
1
Clock Low Pulse Width
tCLW
2.0
-
2.5
-
3.0
-
3.0
-
3.0
-
ns
1
CAS
Latency=3
tAC3
-
4.5
-
5.5
-
5.5
-
5.5
-
5.5
ns
CAS
Latency=2
tAC2
-
6.0
-
6.0
-
6.0
-
6.0
-
6.0
ns
Data-out Hold Time
tOH
2.0
-
2.0
-
2.0
-
2.0
-
2.0
-
ns
Data-Input Setup Time
tDS
1.5
-
1.5
-
1.5
-
1.5
-
2.0
-
ns
1
Data-Input Hold Time
tDH
0.8
-
0.8
-
0.8
-
0.8
-
1.0
-
ns
1
Address Setup Time
tAS
1.5
-
1.5
-
1.5
-
1.5
-
2.0
-
ns
1
Address Hold Time
tAH
0.8
-
0.8
-
0.8
-
0.8
-
1.0
-
ns
1
CKE Setup Time
tCKS
1.5
-
1.5
-
1.5
-
1.5
-
2.0
-
ns
1
CKE Hold Time
tCKH
0.8
-
0.8
-
0.8
-
0.8
-
1.0
-
ns
1
Command Setup Time
tCS
1.5
-
1.5
-
1.5
-
1.5
-
2.0
-
ns
1
Command Hold Time
tCH
0.8
-
0.8
-
0.8
-
0.8
-
1.0
-
ns
1
1.0
-
1.0
-
1.5
-
1.5
-
2.0
-
ns
System Clock
Cycle Time
Access Time
From Clock
1000
7.0
1000
10
7.5
1000
10
10
1000
10
ns
1000
10
ns
2
CLK to Data Output in Low-Z
tOLZ
Time
CLK to
Data Output
in High-Z Time
6.0
CAS
Latency=3
tOHZ3
-
4.5
-
5.5
-
5.5
-
6.0
-
6.0
ns
CAS
Latency=2
tOHZ2
-
6.0
-
6.0
-
6.0
-
6.0
-
6.0
ns
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Rev. 0.2 / June. 2005
9
11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
RAS
Cycle Time
Operation
RAS
Cycle Time
Auto Refresh
Symbol
5
6
7
H
P
Min Max Min Max Min Max Min Max Min Max
Unit Note
tRC
55
-
60
-
63
-
63
-
70
-
ns
tRRC
55
-
60
-
63
-
63
-
70
-
ns
RAS to CAS Delay
tRCD
15
-
18
-
20
-
20
-
20
-
ns
RAS Active Time
tRAS
42
100K
42
100K
42
120
K
50
120
K
ns
RAS Precharge Time
tRP
15
-
18
-
20
-
20
-
20
-
ns
RAS to RAS Bank Active
Delay
tRRD
20
-
20
-
20
-
20
-
20
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
1
-
1
-
1
-
CLK
Write Command to
Data-In Delay
tWTL
0
-
0
-
0
-
0
-
0
-
CLK
Data-in to Precharge
Command
tDPL
2
-
2
-
2
-
2
-
2
-
CLK
Data-In to Active Command
tDAL
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
0
-
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
2
-
2
-
2
-
CLK
CAS
Latency=3
tPROZ3
3
-
3
-
3
-
3
-
3
-
CLK
CAS
Latency=2
tPROZ2
2
-
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
tDPE
1
-
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1
-
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
-
64
-
64
-
64
ms
Precharge to
Data Output
High-Z
38.7 100K
tDPL + tRP
1
Note :
1. A new command can be given tRRC after self refresh exit.
Rev. 0.2 / June. 2005
10
11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
COMMAND TRUTH TABLE
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
No Operation
H
X
H
X
X
X
L
H
H
H
X
X
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
CA
H
X
L
H
L
L
X
CA
H
X
L
L
H
L
X
X
Burst Stop
H
X
L
H
H
L
X
X
DQM
H
V
X
Auto Refresh
H
H
L
L
L
H
X
X
Burst-Read-Single-WRITE
H
X
L
L
L
L
X
A9 ball High
(Other balls OP code)
Entry
H
L
L
L
L
H
X
Exit
L
H
H
X
X
X
L
H
H
H
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Self Refresh1
X
Precharge
power down
Clock
Suspend
Exit
L
H
Entry
H
L
Exit
L
H
Rev. 0.2 / June. 2005
X
X
ADDR
A10/AP
BA
RA
Note
V
L
H
L
H
V
V
H
X
L
V
MRS
Mode
X
X
X
X
X
X
X
11
11Preliminary
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
PACKAGE INFORMATION
60 Ball FBGA 10.1mm x 6.4mm
Unit
[mm]
10.10
+/-0.10
0.500
± 0.10
9.10 REF
1.1MAX
0.65 Typ.
6.40
± 0.10
Bottom View
1.80 ± 0.10
0.450 +/- 0.05
3.90
RFF
1.30
Typ.
0.65 Typ.
0.280 ± 0.05
Rev. 0.2 / June. 2005
12
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