L6491
High voltage high and low-side 4 A gate driver
Datasheet - production data
Applications
Motor driver for home appliances, factory
automation, industrial drives and fans
HID ballasts
Power supply unit
SO-14
Induction heating
Wireless chargers
Features
Industrial inverters
UPS
High voltage rail up to 600 V
dV/dt immunity ± 50 V/ns in full temperature
range
Description
Driver current capability: 4 A source/sink
The L6491 is a high voltage device manufactured
with the BCD6 “OFF-LINE” technology. It is
a single-chip half-bridge gate driver for N-channel
power MOSFET or IGBT.
Switching times 15 ns rise/fall with 1 nF load
3.3 V, 5 V TTL/CMOS inputs with hysteresis
Integrated bootstrap diode
Comparator for fault protections
Smart shutdown function
Adjustable deadtime
Interlocking function
Compact and simplified layout
The high-side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
interfacing microcontroller/DSP.
An integrated comparator is available for fast
protection against overcurrent, overtemperature,
etc.
Bill of material reduction
Table 1. Device summary
Effective fault protection
Flexible, easy and fast design
March 2015
This is information on a product in full production.
Order code
Package
Packaging
L6491D
SO-14
Tube
L6491DTR
SO-14
Tape and reel
DocID024832 Rev 1
1/24
www.st.com
Contents
L6491
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6
Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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DocID024832 Rev 1
L6491
1
Block diagram
Block diagram
Figure 1. Block diagram
VCC
PGND
DocID024832 Rev 1
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24
Pin connection
2
L6491
Pin connection
Figure 2. Pin connection (top view)
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Table 2. Pin description
Pin
number
Pin name
Type
1
LIN
I
2
SD/OD(1)
I/O
3
HIN
I
High-side driver logic input (active high)
4
VCC
P
Lower section supply voltage
5
DT
I
Deadtime setting
6
SGND
P
Signal ground
7
PGND
P
Power ground
8
(1)
LVG
O
Low-side driver output
9
CP-
I
Comparator negative input
10
CP+
I
Comparator positive input
11
NC
12
OUT
P
High-side (floating) common voltage
13
HVG(1)
O
High-side driver output
14
BOOT
P
Bootstrapped supply voltage
Function
Low-side driver logic input (active low)
Shutdown logic input (active low)/open-drain
comparator output
Not connected
1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This
allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low.
When the SD is set low, gate driver outputs are forced low and assure low impedance.
4/24
DocID024832 Rev 1
L6491
3
Truth table
Truth table
Table 3. Truth table
Input
Output
SD
LIN
HIN
LVG
HVG
L
X(1)
X(1)
L
L
H
H
L
L
L
H
L
H
L
L
H
L
L
H
L
H
H
H
L
H
1. X: don't care.
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Electrical data
L6491
4
Electrical data
4.1
Absolute maximum ratings
Table 4. Absolute maximum ratings(1)
Value
Symbol
Parameter
Unit
Min.
Max.
-0.3
21
V
Low-side driver ground
VCC - 21
VCC + 0.3
V
Vout
Output voltage
Vboot - 21
Vboot + 0.3
V
Vboot
Bootstrap voltage
-0.3
620
V
Vhvg
High-side gate output voltage
Vout - 0.3
Vboot + 0.3
V
Vlvg
Low-side gate output voltage
PGND - 0.3
VCC + 0.3
V
-0.3
5.5
V
-0.3
5.5
V
VCC
VPGND
VcpVcp+
Supply voltage
Comparator negative input
Comparator positive input
voltage(2)
voltage(2)
Vi
Logic input voltage
-0.3
15
V
VOD
Open-drain voltage
-0.3
15
V
50
V/ns
dvout / dt Allowed output slew rate
Ptot
Total power dissipation (TA = 25 °C)
1.0
W
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
ESD
Human body model
-50
2
kV
1. Each voltage referred to SGND unless otherwise specified.
2. Spikes up to 20 V can be tolerated if the duration is shorter than 50 ns (fSW = 120 kHz).
4.2
Thermal data
Table 5. Thermal data
Symbol
Rth(JA)
6/24
Parameter
Thermal resistance junction to ambient
DocID024832 Rev 1
SO-14
Unit
120
°C/W
L6491
4.3
Electrical data
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol
Pin
VCC
4
VPS(1)
7-6
VBO(2)
1.
Parameter
Test conditions
Min.
Max.
Unit
10
20
V
Low-side driver ground
-1.5
+1.5
V
14 - 12 Floating supply voltage
9.3
20
V
580
V
Supply voltage
(3)
Vout
12
DC output voltage
-9
VCP-
9
Comparator negative
input pin voltage
VCP+ 2.5 V
5(4)
V
VCP+
10
Comparator positive
input pin voltage
VCP- 2.5 V
5(4)
V
fsw
Switching frequency
HVG, LVG load CL = 1 nF
800
kHz
TJ
Junction temperature
125
°C
-40
VPS = VPGND - SGND.
2. VBO = Vboot - Vout.
3. LVG off. VCC = 12.5 V. Logic is operational if Vboot > 5 V.
4. At least one of the comparator's inputs must be lower than 2.5 V to guarantee proper operation.
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24
Electrical characteristics
L6491
5
Electrical characteristics
5.1
AC operation
Table 7. AC operation electrical characteristics (VCC = 15 V; PGND = SGND; TJ = +25 °C)
Symbol
ton
toff
tsd
Pin
Parameter
Test conditions
High/low-side driver turn-on
OUT = 0 V
1 vs. 8 propagation delay
3 vs 13 High/low-side driver turn-off BOOT = VCC
CL = 1 nF
propagation delay
Vi = 0 to 3.3 V
2 vs. Shutdown to high/low-side see Figure 3
8, 13 driver propagation delay
tisd
Comparator triggering to
Measured applying a voltage step from
high/low-side driver turn-off
0 V to 3.3 V to pin CP+; CP- = 0.5 V
propagation delay
MT
Delay matching, HS and LS
turn-on/off(1)
DT
Deadtime setting range
see Figure 4
5
MDT
tr
tf
Matching
8,13
deadtime(2)
85
120
ns
85
120
ns
85
120
ns
175
220
ns
30
ns
RDT = 0 , CL = 1 nF
0.12 0.18 0.24
µs
RDT = 100 k, CL = 1 nF, CDT = 100 nF
1.2
1.4
1.6
µs
RDT = 200 k, CL = 1 nF, CDT = 100 nF
2.2
2.6
3
µs
RDT = 0 , CL = 1 nF
50
ns
RDT = 100 k, CL = 1 nF, CDT = 100 nF
165
ns
RDT = 200 k, CL = 1 nF, CDT = 100 nF
260
ns
Rise time
CL = 1 nF
15
40
ns
Fall time
CL = 1 nF
15
40
ns
1. MT = max. (|ton(LVG) - toff(LVG)|, |ton(HVG) - toff(HVG)|, |toff(LVG) - ton(HVG)|, |toff(HVG) - ton(LVG)|).
2. MDT = | DTLH - DTHL | (see Figure 5 on page 14).
8/24
Min. Typ. Max. Unit
DocID024832 Rev 1
L6491
Electrical characteristics
Figure 3. Timing
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Electrical characteristics
L6491
Figure 4. Typical deadtime vs. DT resistor value
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L6491
5.2
Electrical characteristics
DC operation
Table 8. DC operation electrical characteristics
(VCC = 15 V; PGND = SGND; TJ = + 25 °C)
Symbol
Pin
Min.
Typ.
Max.
Unit
VCC UV hysteresis
0.5
0.6
0.72
V
Vcc_thON
VCC UV turn-ON threshold
8.7
9.3
9.8
V
Vcc_thOFF
VCC UV turn-OFF threshold
8.2
8.7
9.2
V
Undervoltage quiescent
supply current
VCC = 8 V
SD = 5 V; LIN = 5 V;
HIN = SGND;
RDT = 0 ;
CP+ = SGND; CP- = 5 V
160
210
A
Quiescent current
VCC = 15 V
SD = 5 V; LIN = 5 V;
HIN = SGND;
RDT = 0 ;
CP+ = SGND; CP- = 5 V
540
700
A
0.48
0.6
0.7
V
Vcc_hys
Iqccu
Iqcc
4
Parameter
Test conditions
Bootstrapped supply voltage section(1)
VBO_hys
VBO UV hysteresis
VBO_thON
VBO UV turn-ON threshold
8
8.6
9.1
V
VBO_thOFF
VBO UV turn-OFF threshold
7.5
8.0
8.5
V
IQBOU
VCC = VBO = 7 V
SD = 5 V; LIN and
Undervoltage VBO quiescent
HIN = 5 V;
14-12 current
RDT = 0 ;
CP+ = SGND; CP- = 5 V
20
30
A
IQBO
VBO = 15 V
SD = 5 V; LIN and
HIN = 5 V;
RDT = 0 ;
CP+ = SGND; CP- = 5 V
90
120
A
8
A
ILK
RDS(on)
VBO quiescent current
High voltage leakage current BOOT = HVG = OUT = 600 V
Bootstrap driver on
resistance(2)
175
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Electrical characteristics
L6491
Table 8. DC operation electrical characteristics
(VCC = 15 V; PGND = SGND; TJ = + 25 °C) (continued)
Symbol
Pin
Parameter
Test conditions
Min.
Typ.
LVG/HVG ON
TJ = 25 °C
3.5
4
Full temperature range
2.5
LVG/HVG OFF
TJ = 25 °C
3.5
Full temperature range
2.5
Max.
Unit
Driving buffer section
High/low-side source peak
current
Iso
8, 13
High/low-side sink peak
current
Isi
A
A
4
A
A
Logic inputs
Vil
Low level logic threshold
Vih
1, 2, 3 High level logic threshold
voltage
VSSD
2
1, 3
LIN and HIN connected
together and floating
HIN logic “1” input bias
current
HIN = 15 V
IHINl
HIN logic “0” input bias
current
HIN = 0 V
ILINl
LIN logic “0” input bias
current
LIN = 0 V
ILINh
LIN logic “1” input bias
current
LIN = 15 V
ISDh
SD logic “1” input bias
current
SD = 15 V
SD logic “0” input bias
current
SD = 0 V
IHINh
3
1
2
ISDl
1.45
V
2
2.5
V
0.8
V
0.8
V
260
A
1
A
15
A
1
A
60
A
1
A
SmartSD unlatch threshold
Single input voltage
Vil_S
0.95
120
5
20
200
10
40
1. VBO = Vboot - Vout.
2. RDS(on) is tested in the following way:
RDS(on) = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1(VCC, VBOOT1) - I2(VCC, VBOOT2)] where I1 is pin 14 current when
VBOOT = VBOOT1, I2 when VBOOT = VBOOT2.
12/24
DocID024832 Rev 1
L6491
Electrical characteristics
Table 9. Sense comparator(1) (VCC = 15 V, TJ = +25 °C)
Symbol
Pin
Parameter
Vio
9, 10 Input offset voltage
Iib
9, 10 Input bias current
IOD
2
td_comp
SR
2
Test conditions
Min.
Typ.
Max.
Unit
15
mV
1
A
20
27
mA
155
ns
-15
VCP+ = 1 V, VCP- = 1 V
Open-drain low level sink
current
SD\OD = 400 mV, VCP+ = 1
V; VCP - = 0.5 V;
Comparator delay
Rpu = 100 k to 5 V;
VCP - = 0.5 V;
voltage step on CP+ = 0 to
3.3 V; 50% CP+ to 90% SD
100
Slew rate
CL = 10 nF;
Rpu = 5 k to 5 V;
90% SD to 10% SD
10
13
V/s
1. Comparator is disabled when VCC is in UVLO condition.
DocID024832 Rev 1
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Waveform definitions
6
L6491
Waveform definitions
Figure 5. Deadtime and interlocking waveform definitions
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14/24
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L6491
7
Smart shutdown function
Smart shutdown function
The L6491 device integrates a comparator committed to the fault sensing function. The
comparator input can be connected to an external shunt resistor in order to implement
a simple overcurrent detection function.
The output signal of the comparator is fed to an integrated MOSFET with the open-drain
output available on pin 2, shared with the SD input. When the comparator triggers, the
device is set in shutdown state and both its outputs are set to low level leaving the halfbridge in 3-state.
Figure 6. Smart shutdown timing waveforms
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Smart shutdown function
L6491
In common overcurrent protection architectures, the comparator output is usually connected
to the SD input and an RC network is connected to this SD/OD line in order to provide
a monostable circuit, which implements a protection time following the fault condition.
Differently from the common fault detection systems, the L6491 smart shutdown
architecture allows immediate turn-off of the output gate driver in case of fault, by minimizing
the propagation delay between the fault detection event and the current output switch-off. In
fact the time delay between the fault and the output turn-off is no longer dependent on the
RC value of the external network connected to the SD/OD pin. In the smart shutdown
circuitry, the fault signal has a preferential path which directly switches off the outputs after
the comparator triggering. At the same time, the internal logic turns on the open-drain output
and holds it on until the SD voltage goes below the smartSD unlatch threshold VSSD. When
such threshold is reached, the open-drain output is turned off, allowing the external pull-up
to recharge the capacitor. The driver outputs restart following the input pins as soon as the
voltage at the SD/OD pin reaches the higher threshold of the SD logic input. The smart
shutdown system gives the possibility to increase the time constant of the external RC
network (that determines the disable time after the fault event) up to very large values
without increasing the delay time of the protection.
Any external signal provided to the SD pin is not latched and can be used as control signal
in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal
is applied to the SD input and the logic inputs of the gate driver are stable, the outputs
switch from the low level to the state defined by the logic inputs and vice versa.
16/24
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L6491
Typical application diagram
8
Typical application diagram
Figure 7. Typical application diagram
VCC
VCC
BOOTSTRAP DRIVER
FLOATING STRUCTURE
4
14
BOOT
+
CVCC1
H.V.
Cboot
HVG
DRIVER
FROM CONTROLLER
HIN
3
LEVEL
SHIFTER
Rfilt
Cfilt
13
HVG
12
OUT
Rg
5V
LOGIC
LIN
FROM CONTROLLER
SHOOT
THROUGH
PREVENTION
1
Rfilt
Cfilt
VCC
Vpu
FROM/TO
CONTROLLER
RSD
SD/OD
TO LOAD
LVG
DRIVER
8
LVG
10
CP+
2
PGND
5V
SMART
SD
CSD
COMPARATOR
+
-
CP9
DT
Rg
DEAD
5
RLP
CLP
Vpu
VCC
Rp1
CVCC2
TIME
RDT
CDT SGND
Rshunt
7
6
Cp2
Rp2
PGND
System power ground
Figure 8. Suggested PCB layout
Vpu
SD/OD
CBOOT
LIN
Rfilt
HIN
Rfilt
Cfilt
CVCC1
RDT CDT
Cfilt
RSD
CSD
SGND
plane
CLP
Cp2
Cp+
VCC
Rg
Vpu
CVCC2
Rp2
Rp1
RLP
uC Signal GROUND
Rshunt
BOTTOM layer
TOP layer
POWER GROUND
DocID024832 Rev 1
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24
Bootstrap driver
9
L6491
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is usually
accomplished by a high voltage fast recovery diode (Figure 9). In the L6491 an integrated
structure replaces the external diode.
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Equation 1
Q gate
C EXT = -------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
Equation 2
C BOOT >>>C EXT
if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop is 300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has also to take into account
the leakage and quiescent losses.
HVG steady-state consumption is lower than 120 A, so if HVG TON is 5 ms, CBOOT has to
supply CEXT with 0.6 C. This charge on a 1 F capacitor means a voltage drop of 0.6 V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to SGND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDS(on) (typical value:
175 ). At low frequency this drop can be neglected. Anyway, the rise of frequency has to
take into account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 3
Q gate
V drop = I ch arg e R DS on V drop = ------------------R DS on
T ch arg e
where Qgate is the gate charge of the external power MOS, RDS(on) is the on resistance of
the bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor.
18/24
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L6491
Bootstrap driver
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact:
Equation 4
30nC
V drop = --------------- 175 1V
5s
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 9. Bootstrap driver with external high voltage fast recovery diode
DBOOT
VCC
BOOT
H.V.
HVG
CBOOT
OUT
TO LOAD
LVG
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Package information
10
L6491
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
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Package information
Figure 10. SO-14 package outline
B(
Table 10. SO-14 package mechanical data
Dimensions (mm)
Symbol
Min.
Typ.
Max.
A
1.35
1.75
A1
0.10
0.25
A2
1.10
1.65
B
0.33
0.51
C
0.19
0.25
D
8.55
8.75
E
3.80
4.00
e
1.27
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
k
0
8
ddd
0.10
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Figure 11. SO-14 package suggested land pattern
0.60
1.27
4.0
6.7
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Revision history
Revision history
Table 11. Document revision history
Date
Revision
11-Mar-2015
1
Changes
Initial release.
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