Sample & Buy Product Folder Technical Documents Support & Community Tools & Software LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 LMZ12001EXT 1-A SIMPLE SWITCHER® Power Module with 20-V Maximum Input Voltage for Demanding Environments and Rugged Applications 1 Features 2 Applications • • • • • 1 • • • • • • • • Junction Temperature Range –55°C to 125°C Integrated Shielded Inductor Simple PCB Layout Flexible Startup Sequencing Using External SoftStart Capacitor and Precision Enable Protection Against Inrush Currents and Faults such as Input UVLO and Output Short Circuit Single Exposed Pad and Standard Pinout for Easy Mounting and Manufacturing Fast Transient Response for FPGAs and ASICs Low Output Voltage Ripple Pin-to-Pin Compatible With Family Devices: – LMZ14203EXT/2EXT/1EXT (42-V Maximum 3 A, 2 A, 1 A) – LMZ14203/2/1 (42-V Maximum 3 A, 2 A, 1 A) – LMZ12003/2/1 (20-V Maximum 3 A, 2 A, 1 A) Fully WEBENCH® Power Designer Enabled Performance Benefits – Low Radiated Emissions / High Radiated Immunity – Passes Vibration Standard MIL-STD-883 Method 2007.2 Condition A JESD22–B103B Condition 1 – Passes Drop standard MIL-STD-883 Method 2002.3 Condition B JESD22–B110 Condition B Electrical Specifications – 6-W Maximum Total Power Output – Up to 1-A Output Current – Input Voltage Range 4.5 V to 20 V – Output Voltage Range 0.8 V to 6 V – Efficiency up to 92% Simplified Application Schematic • • • Point-of-load Conversions from 5-V and 12-V Input Rail Time-Critical Projects Space-Constrained High Thermal Requirement Applications Negative Output Voltage Applications (See AN-2027 SNVA425) 3 Description The LMZ12001EXT SIMPLE SWITCHER® power module is an easy-to-use step-down DC-DC solution capable of driving up to 1-A load with exceptional power conversion efficiency, line and load regulation, and output accuracy. The LMZ12001EXT is available in an innovative package that enhances thermal performance and allows for hand or machine soldering. The LMZ12001EXT can accept an input voltage rail between 4.5 V and 20 V, and can deliver an adjustable and highly accurate output voltage as low as 0.8 V. The LMZ12001EXT only requires three external resistors and four external capacitors to complete the power solution. The LMZ12001EXT is a reliable and robust design with the following protection features: thermal shutdown, input undervoltage lockout, output overvoltage protection, short circuit protection, output current limit, and the device allows start-up into a prebiased output. A single resistor adjusts the switching frequency up to 1 MHz. Device Information(1)(2) PART NUMBER PACKAGE LMZ12001EXT BODY SIZE (NOM) NDW (7) 10.16 mm × 9.85 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Peak reflow temperature equals 245°C. See SNAA214 for more details. Efficiency 5-V Input at 25°C 100 LMZ12001EXT VOUT 90 VOUT @ 1A CFF RON RFBT Enable EFFICIENCY (%) FB EN SS GND VIN RON 95 VIN 1.8 1.5 1.2 0.8 85 80 75 70 65 60 CIN CSS RFBB COUT 55 50 25°C 0 0.2 0.4 0.6 0.8 1 OUTPUT CURRENT (A) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 3 4 4 4 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics ............................................. Detailed Description ............................................ 12 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 12 13 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application .................................................. 14 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 20 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Examples................................................... Power Dissipation and Thermal Considerations ... Power Module SMT Guidelines ............................ 20 21 22 22 11 Device and Documentation Support ................. 24 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 24 24 24 24 24 24 12 Mechanical, Packaging, and Orderable Information ........................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (October 2013) to Revision G • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 Changes from Revision E (April 2013) to Revision F Page • Changed 10 mils................................................................................................................................................................... 20 • Changed 10 mils................................................................................................................................................................... 22 • Added Power Module SMT Guidelines................................................................................................................................. 22 2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 5 Pin Configuration and Functions NDW Package 7-Pin Top View Pin Functions PIN NAME NO. TYPE DESCRIPTION EN 3 Analog Enable — Input to the precision enable comparator. Rising threshold is 1.18-V nominal; 90mV hysteresis nominal. Maximum recommended input level is 6.5 V. EP — Ground Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package during operation. Must be electrically connected to pin 4 external to the package. FB 6 Analog Feedback — Internally connected to the regulation, overvoltage, and short circuit comparators. The regulation reference point is 0.8 V at this input pin. Connected the feedback resistor divider between the output and ground to set the output voltage. GND 4 Ground Ground — Reference point for all stated voltages. Must be externally connected to EP. RON 2 Analog ON-Time Resistor — An external resistor from VIN to this pin sets the ON-time of the application. Typical values range from 25 kΩ to 124 kΩ. SS 5 Analog Soft-Start — An internal 8-µA current source charges an external capacitor to produce the soft-start function. This node is discharged at 200 µA during disable, overcurrent, thermal shutdown and internal UVLO conditions. VIN 1 Power Supply input — Nominal operating range is 4.5 V to 20 V. A small amount of internal capacitance is contained within the package assembly. Additional external input capacitance is required between this pin and exposed pad. VOUT 7 Power Output Voltage — Output from the internal inductor. Connect the output capacitor between this pin and exposed pad. 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) (3) MIN MAX UNIT VIN, RON to GND –0.3 25 V EN, FB, SS to GND –0.3 7 V 150 °C 245 °C 150 °C Junction Temperature Peak Reflow Case Temperature (30 sec) Storage Temperature, Tstg (1) (2) (3) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. For soldering specifications, refer to the following document: SNOA549 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2) VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. Test method is per JESD-22-114. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT 3 LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN 4.5 20 EN 0 6.5 V –55 125 °C Operation Junction Temperature V 6.4 Thermal Information LMZ12001EXT THERMAL METRIC (1) NDW UNIT 7 PINS RθJA Junction-to-ambient thermal resistance RθJC(top) (1) (2) (2) Junction-to-case (top) thermal resistance 4-layer JEDEC Printed-Circuit-Board, 100 vias, No air flow 19.3 2-layer JEDEC Printed-Circuit-Board, No air flow 21.5 No air flow 1.9 °C/W °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RθJA measured on a 1.705” x 3.0” four layer board, with one ounce copper, thirty five thermal vias, no air flow, and 1W power dissipation. Refer to PCB layout diagrams 6.5 Electrical Characteristics Limits are for TJ = 25°C unless otherwise specified. Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V, VOUT = 1.8 V (1). PARAMETER MIN (2) TYP (3) TEST CONDITIONS MAX (2) UNIT SYSTEM PARAMETERS ENABLE CONTROL 1.18 VEN EN threshold trip point VEN rising VEN-HYS EN threshold hysteresis VEN falling over the junction temperature (TJ) range of –55°C to +125°C 1.1 1.26 90 V mV SOFT-START 8 ISS SS source current ISS-DIS SS discharge current VSS = 0 V over the junction temperature (TJ) range of –55°C to +125°C 4.9 11 –200 µA µA CURRENT LIMIT 2 ICL Current limit threshold d.c. average over the junction temperature (TJ) range of –55°C to +125°C 1.4 3 A ON/OFF TIMER tON-MIN ON timer minimum pulse width 150 ns tOFF OFF timer pulse width 260 ns (1) (2) (3) 4 EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2024 SNVA422 and layout for information on device under test. Minimum and Maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Typical numbers are at 25°C and represent the most likely parametric norm. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 Electrical Characteristics (continued) Limits are for TJ = 25°C unless otherwise specified. Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V, VOUT = 1.8 V(1). PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT REGULATION AND OVERVOLTAGE COMPARATOR VFB In-regulation feedback voltage VSS >+ 0.8 V, TJ = –55°C to 125°C over the junction temperature (TJ) IO = 1 A range of –55°C to +125°C VSS >+ 0.8 V, TJ = 25°C, IO = 10 mA VFB-OV Feedback over-voltage protection threshold IFB Feedback input bias current IQ Non-switching input current VFB= 0.86 V ISD Shutdown quiescent current VEN= 0 V 0.798 0.777 0.786 0.818 0.802 V 0.818 0.92 V 5 nA 1 mA 25 μA THERMAL CHARACTERISTICS TSD Thermal shutdown Rising 165 °C TSD-HYST Thermal shutdown hysteresis Falling 15 °C 8 mVPP PERFORMANCE PARAMETERS ΔVO Output voltage ripple ΔVO/ΔVIN Line regulation VIN = 8 V to 20 V, IO= 1 A ΔVO/ΔVIN Load regulation VIN = 12 V η Efficiency VIN = 12 V, VO = 1.8 V, IO = 1 A .01% 1.5 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT mV/A 85% 5 LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com 6.6 Typical Characteristics Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 10-µF X7R Ceramic; CO = 100-µF X7R Ceramic; TA = 25°C for efficiency curves and waveforms. 100 0.3 95 80 DISSIPATION (W) EFFICIENCY (%) 1.8 1.5 1.2 0.8 85 75 70 65 60 1.5 0.2 0.15 1.2 0.8 0.1 0.05 55 50 1.8 0.25 90 25°C 25°C 0 0.2 0.4 0.6 0.8 0 1 0 0.2 OUTPUT CURRENT (A) 0.4 0.6 Figure 1. Efficiency 4.5-V Input at 25°C Figure 2. Dissipation 4.5-V Input at 25°C 0.3 1.8 95 0.25 1.8 1.5 1.2 0.8 85 80 DISSIPATION (W) EFFICIENCY (%) 90 75 70 65 60 1.5 0.2 0.15 1.2 0.8 0.1 0.05 55 25°C 0 0 0.2 0.4 0.6 0.8 1 25°C 0.2 0 Figure 3. Efficiency 5-V Input at 25°C 0.3 95 3.3 2.5 1.8 1.5 1.2 0.8 85 80 75 70 65 60 25°C 0.2 1.2 0.8 0.15 0.1 0 0.2 0.4 0.6 0.8 1 1.8 1.5 25°C 0.05 0 0.8 3.3 2.5 0.25 DISSIPATION (W) EFFICIENCY (%) 90 50 0.6 Figure 4. Dissipation 5-V Input at 25°C 100 55 0.4 OUTPUT CURRENT (A) OUTPUT CURRENT (A) 6 1 OUTPUT CURRENT (A) 100 50 0.8 1 0 0.2 0.4 0.6 0.8 1 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 5. Efficiency 6-V Input at 25°C Figure 6. Dissipation 6-V Input at 25°C Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 10-µF X7R Ceramic; CO = 100-µF X7R Ceramic; TA = 25°C for efficiency curves and waveforms. 100 0.35 95 5.0 3.3 2.5 1.8 1.5 1.2 0.8 85 80 0.3 0.25 DISSIPATION (W) EFFICIENCY (%) 90 5.0 3.3 2.5 1.8 1.5 75 70 65 0.2 1.2 0.15 0.8 0.1 60 25°C 0.05 55 50 25°C 0 0.4 0.2 0.6 0.8 0 1 0.4 Figure 7. Efficiency 8-V Input at 25°C Figure 8. Dissipation 8-V Input at 25°C 0.45 6.0 5.0 3.3 2.5 1.8 1.5 1.2 0.8 85 80 75 70 65 3.3 2.5 0.3 1.8 1.5 0.225 1.2 0.8 0.15 25°C 60 0.075 55 50 6.0 5.0 0.375 DISSIPATION (W) 90 25°C 0 0 0.2 0.4 0.6 0.8 1 0 0.2 OUTPUT CURRENT (A) 0.6 0.4 Figure 10. Dissipation 12-V Input at 25°C 0.6 100 6.0 5.0 95 6.0 5.0 3.3 2.5 1.8 85 80 0.5 DISSIPATION (W) 90 1 0.8 OUTPUT CURRENT (A) Figure 9. Efficiency 12-V Input at 25°C EFFICIENCY (%) 1 OUTPUT CURRENT (A) 95 75 70 65 60 3.3 2.5 0.4 0.3 1.8 0.2 0.1 55 50 0.8 0.6 OUTPUT CURRENT (A) 100 EFFICIENCY (%) 0.2 0 25°C 25°C 0 0.2 0.4 0.6 0.8 1 0 0 0.2 0.4 0.6 0.8 1 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 11. Efficiency 20-V Input at 25°C Figure 12. Dissipation 20-V Input at 25°C Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT 7 LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 10-µF X7R Ceramic; CO = 100-µF X7R Ceramic; TA = 25°C for efficiency curves and waveforms. 100 0.45 95 0.375 1.8 1.5 1.2 85 80 DISSIPATION (W) EFFICIENCY (%) 90 75 70 65 0.225 1.2 0.15 85°C 60 0.075 55 50 1.8 1.5 0.3 85°C 0 0 0.2 0.4 0.6 0.8 1 0.2 0 OUTPUT CURRENT (A) 0.4 0.6 0.8 1 OUTPUT CURRENT (A) Figure 13. Efficiency 4.5-V Input at 85°C Figure 14. Dissipation 4.5-V Input at 85°C 0.45 100 95 0.375 1.8 1.8 1.5 1.2 85 80 DISSIPATION (W) EFFICIENCY (%) 90 75 70 65 0.3 0.225 1.2 0.15 85°C 60 0.075 55 50 1.5 85°C 0 0 0.2 0.4 0.6 0.8 1 0 0.2 OUTPUT CURRENT (A) 0.4 0.6 1 0.8 OUTPUT CURRENT (A) Figure 15. Efficiency 5-V Input at 85°C Figure 16. Dissipation 5-V Input at 85°C 100 0.45 95 85 80 DISSIPATION (W) EFFICIENCY (%) 0.375 3.3 2.5 1.8 1.5 1.2 90 75 70 65 0.3 0.225 1.2 0.15 85°C 60 0.075 55 50 85°C 0 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 17. Efficiency 6-V Input at 85°C 8 3.3 2.5 1.8 1.5 Figure 18. Dissipation 6-V Input at 85°C Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 10-µF X7R Ceramic; CO = 100-µF X7R Ceramic; TA = 25°C for efficiency curves and waveforms. 100 0.45 95 5.0 3.3 2.5 1.8 1.5 1.2 85 80 0.375 DISSIPATION (W) EFFICIENCY (%) 90 75 70 65 0.3 0.225 1.2 0.15 85°C 60 0.075 55 50 5.0 3.3 2.5 1.8 1.5 85°C 0 0.2 0.4 0.6 0.8 0 1 0 0.2 OUTPUT CURRENT (A) Figure 19. Efficiency 8-V Input at 85°C Figure 20. Dissipation 8-V Input at 85°C 0.6 95 6.0 5.0 3.3 2.5 1.8 1.5 1.2 85 80 0.5 DISSIPATION (W) EFFICIENCY (%) 90 75 70 65 60 6.0 5.0 3.3 2.5 0.4 0.3 1.8 1.5 1.2 0.2 0.1 55 85°C 0 85°C 0 0.2 0.4 0.6 0.8 0 1 0.2 0.4 0.6 0.8 1 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 21. Efficiency 12-V Input at 85°C Figure 22. Dissipation 12-V Input at 85°C 0.7 100 95 85 80 DISSIPATION (W) 6.0 5.0 3.3 2.5 90 EFFICIENCY (%) 1 0.8 OUTPUT CURRENT (A) 100 50 0.6 0.4 1.8 75 70 65 0.6 6.0 5.0 3.3 0.5 2.5 0.4 0.3 1.8 1.5 0.2 1.2 60 0.1 55 50 85°C 0 85°C 0 0.2 0.4 0.6 0.8 0 1 OUTPUT CURRENT (A) 0.2 0.4 0.6 0.8 1 OUTPUT CURRENT (A) Figure 23. Efficiency 20-V Input at 85°C Figure 24. Dissipation 20-V Input at 85°C Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT 9 LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) 1.808 1.815 1.804 1.812 1.800 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 10-µF X7R Ceramic; CO = 100-µF X7R Ceramic; TA = 25°C for efficiency curves and waveforms. 6 5 1.796 12 1.792 20 25°C 1.788 0 0.2 0.4 0.8 0.6 6 1.809 5 12 1.806 20 1.803 85°C 1.800 1 0 0.2 0.4 0.6 0.8 1 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 25. Line and Load Regulation at 25°C Figure 26. Line and Load Regulation at 85°C 1.808 OUTPUT VOLTAGE (V) 1.804 1.800 1.796 1.792 6 5 4.5 12 1.788 1.784 20 -55°C 1.780 0 0.2 0.4 0.6 0.8 1 12 VIN 3.3 VO 1 A OUTPUT CURRENT (A) Figure 27. Line and Load Regulation at –55°C Figure 28. Output Ripple 2.4 CURRENT (A) 2.3 2.2 SHORT CIRCUIT 2.1 2.0 ONSET 1.9 25°C 1.8 0 12 VIN 3.3 VO 0.6-A to 1-A Step 5 10 15 20 25 INPUT VOLTAGE (V) Figure 29. Transient Response 10 Figure 30. Current Limit 1.8 VOUT at 25°C Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 10-µF X7R Ceramic; CO = 100-µF X7R Ceramic; TA = 25°C for efficiency curves and waveforms. 2.4 2.4 2.3 OUTPUT CURRENT (A) 2.3 CURRENT (A) SHORT CIRCUIT 2.2 2.1 2.0 ONSET SHORT CIRCUIT 2.2 2.1 2 ONSET 1.9 1.9 85C 25°C 1.8 1.8 0 5 10 15 20 25 0 5 INPUT VOLTAGE (V) 20 25 Figure 32. Current Limit 1.8 VOUT at 85°C 1.2 2.3 1 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 31. Current Limit 3.3 VOUT at 25°C 2.2 SHORT CIRCUIT 2.0 1.9 4.5Vin 0.8 12Vin 0.6 20Vin 0.4 0.2 -55°C 1.8 15 INPUT VOLTAGE (V) 2.4 2.1 10 1.8Vout ONSET 0 5 10 15 20 25 0 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (°C) INPUT VOLTAGE (V) Figure 33. Current Limit 1.8 VOUT at –55°C Figure 34. Thermal Derating VOUT = 1.8 V Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT 11 LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The LMZ12001EXT power module is an easy-to-use step-down DC-DC solution capable of driving up to 1-A load with exceptional power conversion efficiency, line and load regulation, and output accuracy. 7.2 Functional Block Diagram Vin VIN 1 Linear reg Cvcc 5 CIN SS Css CBST 3 EN RON 2 VOUT 7 RON Timer CFF 6 6.8 éH VO Co FB RFBT RFBB 0.47 éF Regulator IC Internal Passives GND 4 7.3 Feature Description 7.3.1 COT Control Circuit Overview Constant ON-Time control is based on a comparator and an ON-time one-shot, with the output voltage feedback compared with an internal 0.8-V reference. If the feedback voltage is below the reference, the main MOSFET is turned on for a fixed ON-time determined by a programming resistor RON. RON is connected to VIN such that ONtime is reduced with increasing input supply voltage. Following this ON-time, the main MOSFET remains off for a minimum of 260 ns. If the voltage on the feedback pin falls below the reference level again the ON-time cycle is repeated. Regulation is achieved in this manner. 7.3.2 Output Overvoltage Comparator The voltage at FB is compared to a 0.92-V internal reference. If FB rises above 0.92 V the ON-time is immediately terminated. This condition is known as overvoltage protection (OVP). It can occur if the input voltage is increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top MOSFET ON-times will be inhibited until the condition clears. Additionally, the synchronous MOSFET will remain on until inductor current falls to zero. 7.3.3 Current Limit Current limit detection is carried out during the OFF-time by monitoring the current in the synchronous MOSFET. Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 1.5 A (typical) the current limit comparator disables the start of the next ON-time period. The next switching cycle will occur only if the FB input is less than 0.8 V and the inductor current has decreased below 1.5 A. Inductor current is monitored during the period of time the synchronous MOSFET is conducting. So long as inductor current exceeds 1.5 A, further ON-time intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due to the longer OFF-time. NOTE Current limit is dependent on both duty cycle and temperature as illustrated in the graphs in the Typical Characteristics sections. 12 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 Feature Description (continued) 7.3.4 Thermal Protection The junction temperature of the LMZ12001EXT must not be allowed to exceed its maximum ratings. Thermal protection is implemented by an internal Thermal Shutdown circuit which activates at 165°C (typical) causing the device to enter a low power standby state. In this state the main MOSFET remains off causing VO to fall, and additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for accidental device overheating. When the junction temperature falls back below 145°C (typ Hyst = 20 °C) the SS pin is released, VO rises smoothly, and normal operation resumes. Applications requiring maximum output current especially those at high input voltage may require application derating at elevated temperatures. 7.3.5 Zero Coil Current Detection The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which inhibits the synchronous MOSFET when its current reaches zero until the next ON-time. This circuit enables the DCM operating mode, which improves efficiency at light loads. 7.3.6 Prebiased Start-Up The LMZ12001EXT will properly start up into a prebiased output. This start-up situation is common in multiple rail logic applications where current paths may exist between different power rails during the start-up sequence. The following scope capture shows proper behavior during this event. Figure 35. Prebiased Start-Up 7.4 Device Functional Modes 7.4.1 Discontinuous Conduction and Continuous Conduction Modes At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the critical conduction point, it will operate in continuous conduction mode (CCM). When operating in DCM the switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to zero before the end of the OFF-time. Note that during the period of time that inductor current is zero, all load current is supplied by the output capacitor. The next ON-time period starts when the voltage on the at the FB pin falls below the internal reference. The switching frequency is lower in DCM and varies more with load current as compared to CCM. Conversion efficiency in DCM is maintained since conduction and switching losses are reduced with the smaller load and lower switching frequency. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT 13 LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMZ12001EXT is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 1 A. The following design procedure can be used to select components for the LMZ12001EXT. Alternately, the WEBENCH software may be used to generate complete designs. When generating a design, the WEBENCH software utilizes iterative design procedure and accesses comprehensive databases of components. Please go to www.ti.com for more details 8.2 Typical Application U1 EP VIN Enable VOUT FB 1.8VO @ 1A 7 GND SS 6 5 VIN EN 4 3 2 1 RON LMZ12001EXTTZ-ADJ 4.5V to 20V RENT 32.4k CFF 0.022 PF RON 32.4k RENB 11.8k D1 OPT CIN2 10 PF RFBT 1.37k CIN1 1 PF CSS 0.022 PF RFBB 1.07k CO1 1 PF CO2 100 PF Figure 36. Evaluation Board Schematic Diagram 8.2.1 Design Requirements For this example the following application parameters exist. • VIN Range = Up to 20 V • VOUT = 0.8 V to 6 V • IOUT = 1 A 8.2.2 Detailed Design Procedure The LMZ12001EXT is fully supported by WEBENCH and offers the following: component selection, electrical and thermal simulations as well as the build-it board for a reduction in design time. The following list of steps can be used to manually design the LMZ12001EXT application. 14 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 Typical Application (continued) 1. 2. 3. 4. 5. 6. Select minimum operating VIN with enable divider resistors Program VO with divider resistor selection Program turnon time with soft-start capacitor selection Select CO Select CIN Set operating frequency with RON 8.2.2.1 Enable Divider, RENT and RENB Selection The enable input provides a precise 1.18-V band-gap rising threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as Vin. The enable input also incorporates 90 mV (typical) of hysteresis resulting in a falling threshold of 1.09 V. The maximum recommended voltage into the EN pin is 6.5 V. For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to limit this voltage. The function of this resistive divider is to allow the designer to choose an input voltage below which the circuit will be disabled. This implements the feature of programmable undervoltage lockout. This is often used in battery-powered systems to prevent deep discharge of the system battery. It is also useful in system designs for sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at powerup. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems where a lower boundary of operation must be established. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ12001EXT output rail. The two resistors must be chosen based on the following ratio: RENT / RENB = (VIN UVLO / 1.18 V) – 1 (1) The LMZ12001EXT demonstration and evaluation boards use 11.8 kΩ for RENB and 32.4 kΩ for RENT resulting in a rising UVLO of 4.5 V. This divider presents 5.34 V to the EN input when the divider input is raised to 20 V. 8.2.2.2 Output Voltage Selection Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of the divider is connected to the FB input. The voltage at FB is compared to a 0.8-V internal reference. In normal operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The main MOSFET ONtime cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the voltage at FB is above 0.8 V, ON-time cycles will not occur. The regulated output voltage determined by the external divider resistors RFBT and RFBB is: VO = 0.8 V × (1 + RFBT / RFBB) (2) Rearranging terms; the ratio of the feedback resistors for a desired output voltage is: RFBT / RFBB = (VO / 0.8 V) – 1 (3) These resistors must be chosen from values in the range of 1.0 kΩ to 10.0 kΩ. For VO = 0.8 V the FB pin can be connected to the output directly so long as an output preload resistor remains that draws more than 20 µA. Converter operation requires this minimum load to create a small inductor ripple current and maintain proper regulation when no load is present. A feed-forward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for best transient response and minimum output ripple. Table 1 lists the values for RFBT , RFBB , CFF and RON. Table 1. Bill of Materials REF DES DESCRIPTION CASE SIZE MANUFACTURER MANUFACTURER P/N U1 SIMPLE SWITCHER PFM Texas Instruments LMZ12001EXTTZ-ADJ Cin1 1 µF, 50 V, X7R 1206 Taiyo Yuden UMK316B7105KL-T Cin2 10 µF, 50 V, X7R 1210 Taiyo Yuden UMK325BJ106MM-T Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT 15 LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com Typical Application (continued) Table 1. Bill of Materials (continued) REF DES DESCRIPTION CASE SIZE MANUFACTURER MANUFACTURER P/N CO1 1 µF, 50 V, X7R 1206 Taiyo Yuden UMK316B7105KL-T CO2 100 µF, 6.3 V, X7R 1210 Taiyo Yuden JMK325BJ10CR7MM-T RFBT 1.37 kΩ 0603 Vishay Dale CRCW06031K37FKEA RFBB 1.07 kΩ 0603 Vishay Dale CRCW06031K07FKEA RON 32.4 kΩ 0603 Vishay Dale CRCW060332K4FKEA RENT 32.4 kΩ 0603 Vishay Dale CRCW060332K4FKEA RENB 11.8 kΩ 0603 Vishay Dale CRCW060311k8FKEA CFF 22 nF, ±10%, X7R, 16 V 0603 TDK C1608X7R1H223K CSS 22 nF, ±10%, X7R, 16 V 0603 TDK C1608X7R1H223K D1 5.1 V SOD-23 — Optional 8.2.2.3 Soft-Start Capacitor Selection Programmable soft-start permits the regulator to slowly ramp to its steady-state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot. Upon turnon, after all UVLO conditions have been passed, an internal 8-µA current source begins charging the external soft-start capacitor. The soft-start time duration to reach steady state operation is given by the formula: tSS = VREF × CSS / Iss = 0.8 V × CSS / 8 µA (4) This equation can be rearranged as follows: CSS = tSS × 8 μA / 0.8 V (5) Use of a 0.022-μF capacitor results in 2.2-ms soft-start interval which is recommended as a minimum value. As the soft-start input exceeds 0.8 V the output of the power stage will be in regulation. The soft-start capacitor continues charging until it reaches approximately 3.8 V on the SS pin. Voltage levels between 0.8 V and 3.8 V have no effect on other circuit operation. Note that the following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal 200-μA current sink. • The enable input being pulled low • Thermal shutdown condition • Overcurrent fault • Internal VCC UVLO (Approx 4-V input to VIN) 8.2.2.4 CO Selection None of the required CO output capacitance is contained within the module. At a minimum, the output capacitor must meet the worst case minimum ripple current rating of 0.5 × ILR P-P, as calculated in Equation 16 below. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10 μF is generally required. Experimentation will be required if attempting to operate with a minimum value. Ceramic capacitors or other low ESR types are recommended. See AN-2024 SNVA422 for more detail. The following equation provides a good first pass approximation of CO for load transient requirements: CO ≥ ISTEP × VFB × L × VIN/ (4 × VO × (VIN – VO) × VOUT-TRAN) (6) Solving: CO ≥ 1 A × 0.8 V × 10 μH × 12 V / (4 × 3.3 V × ( 12 V – 3.3 V) × 33 mV) ≥ 25 μF The LMZ12001EXT demonstration and evaluation boards are populated with a 100-µF 6.3-V X5R output capacitor. Locations for other output capacitors are provided. 16 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 8.2.2.5 CIN Selection The LMZ12001EXT module contains an internal 0.47-µF input ceramic capacitor. Additional input capacitance is required external to the module to handle the input ripple current of the application. This input capacitance must be located in very close proximity to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Worst case input ripple current rating is dictated by the equation: I(CIN(RMS)) ≊ 1 /2 × IO × √ (D / 1-D) where • D ≊ VO / VIN (7) As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when VIN = 2 × VO. Recommended minimum input capacitance is 10-µF X7R ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. TI recommends to pay attention to the voltage and temperature deratings of the capacitor selected. NOTE Ripple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating. If the system design requires a certain minimum value of input ripple voltage ΔVIN be maintained then the following equation may be used. CIN ≥ IO × D × (1 – D) / fSW-CCM × ΔVIN (8) If ΔVIN is 1% of VIN for a 20-V input to 3.3-V output application this equals 200 mV and fSW = 400 kHz. CIN ≥ 1A × 3.3 V / 20 V × (1 – 3.3 V / 20 V) / (400000 × 0.200 V) ≥ 1.7 μF Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines. 8.2.2.6 RON Resistor Selection Many designs will begin with a desired switching frequency in mind. For that purpose the following equation can be used. fSW(CCM) ≊ VO / (1.3 × 10-10 × RON) (9) This can be rearranged as RON ≊ VO / (1.3 × 10 -10 × fSW(CCM) ) (10) The selection of RON and fSW(CCM) must be confined by limitations in the ON-time and OFF-time for the COT control section. The ON-time of the LMZ12001EXT timer is determined by the resistor RON and the input voltage VIN. It is calculated as follows: tON = (1.3 × 10-10 × RON) / VIN (11) The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. RON must be selected such that the ON-time at maximum VIN is greater than 150 ns. The ON-timer has a limiter to ensure a minimum of 150 ns for tON. This limits the maximum operating frequency, which is governed by the following equation: fSW(MAX) = VO / (VIN(MAX) × 150 ns) (12) This equation can be used to select RON if a certain operating frequency is desired so long as the minimum ONtime of 150 ns is observed. The limit for RON can be calculated as follows: RON ≥ VIN(MAX) × 150 ns / (1.3 × 10 -10) (13) If RON calculated in Equation 10 is less than the minimum value determined in Equation 13 a lower frequency must be selected. Alternatively, VIN(MAX) can also be limited in order to keep the frequency unchanged. Additionally, consider the minimum OFF-time of 260 ns limits the maximum duty ratio. Larger RON (lower FSW) must be selected in any application requiring large duty ratio. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT 17 LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com 8.2.2.7 Discontinuous Conduction and Continuous Conduction Modes Selection Operating frequency in DCM can be calculated as follows: fSW(DCM) ≊ VO × (VIN – 1) × 10 μH × 1.18 × 1020 × IO / (VIN –VO) × RON2 (14) In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the OFF-time. The switching frequency remains relatively constant with load current and line voltage variations. The CCM operating frequency can be calculated using Equation 9 above. Figure 37 is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes. VIN = 12 V, VO = 3.3 V, IO = 1 A/0.25 A Figure 37. CCM and DCM Operating Modes The approximate formula for determining the DCM/CCM boundary is as follows: IDCB ≊ VO × (VIN – VO) / (2 × 10 μH × fSW(CCM) × VIN) (15) Figure 38 is a typical waveform showing the boundary condition. VIN = 12 V, VO = 3.3 V, IO = 0.29 A Figure 38. Transition Mode Operation The inductor internal to the module is 10 μH. This value was chosen as a good balance between low and high input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple current (ILR). ILR can be calculated with: ILR P-P = VO × (VIN – VO) / (10 µH × fSW × VIN) where • VIN is the maximum input voltage and fSW is determined from Equation 9. (16) If the output current IO is determined by assuming that IO = IL, the higher and lower peak of ILR can be determined. Be aware that the lower peak of ILR must be positive if CCM operation is required. 18 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 8.2.3 Application Curves 100 1.2 1 OUTPUT CURRENT (A) EFFICIENCY (%) 90 80 70 60 0.8 0.6 0.4 0.2 25°C 50 0 0.2 0.4 0.6 0 50 1 0.8 OUTPUT CURRENT (A) 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (°C) VIN = 12 V, VOUT = 5 V VIN = 12 V, VOUT = 5 V Figure 40. Thermal Derating Curve Figure 39. Efficiency RADIATED EMISSIONS (dBµV/m) 80.0 70.0 60.0 50.0 EN 55022 CLASS B LIMIT 40.0 30.0 20.0 10.0 0.0 0 200 400 600 800 1000 FREQUENCY (MHz) Figure 41. Radiated Emissions (EN 55022 Class B) from Evaluation Board Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT 19 LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com 9 Power Supply Recommendations The LMZ12001EXT device is designed to operate from an input voltage supply range between 4.5 V and 20 V. This input supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the LMZ12001EXT supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is more than a few inches from the LMZ12001EXT, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF electrolytic capacitor is a typical choice. 10 Layout 10.1 Layout Guidelines PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths during PCB layout. The high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input capacitor CIN1 is placed a distance away for the LMZ12001. Therefore physically place CIN1 as close as possible to the LMZ12001EXT VIN and GND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor must consist of a localized top side plane that connects to the GND exposed pad (EP). 2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components must be routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP. 3. Minimize trace length to the FB pin. Both feedback resistors, RFBT and RFBB, and the feed forward capacitor CFF, must be located close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The trace are from RFBT, RFBB, and CFF must be routed away from the body of the LMZ12001EXT to minimize noise. 4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and provide optimum output accuracy. 5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with a minimum via diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C. 20 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 10.2 Layout Examples VIN LMZ12001EXT VIN VO VOUT High di/dt Cin1 CO1 GND Loop 2 Loop 1 Figure 42. Critical Current Loops to Minimize Top View Thermal Vias GND GND EPAD 1 2 3 4 5 6 7 VIN EN RON SS GND VOUT FB CIN VIN COUT VOUT RON RENT RFBT CSS RENB CFF RFBB GND Plane Figure 43. PCB Layout Guide Figure 44. Top View of Evaluation PCB Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT 21 LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com Layout Examples (continued) Figure 45. Bottom View of Evaluation PCB 10.3 Power Dissipation and Thermal Considerations For the design case of VIN = 12 V, VO = 1.8 V, IO = 1 A, TAMB(MAX) = 85°C , and TJUNCTION = 125°C, the device must see a thermal resistance from case to ambient of: RθCA< (TJ-MAX – TAMB(MAX)) / PIC-LOSS – RθJC (17) Given the typical thermal resistance from junction to case to be 1.9°C/W .Use the 85°C power dissipation curves in the Typical Characteristics section to estimate the PIC-LOSS for the application being designed. In this application it is 0.4W RθCA< (125 – 85) / 0.4 W – 1.9 = 98.1 (18) To reach RθCA = 98.1, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a good estimate of the required board area covered by 1 oz. copper on both the top and bottom metal layers is: Board Area_cm2 = 500°C × cm2/W / RθJC (19) As a result, approximately 5 square cm of 1-oz. copper on top and bottom layers is required for the PCB design. The PCB copper heat sink must be connected to the exposed pad. Approximately thirty six, 8 mils thermal vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an example of a high thermal performance PCB layout, refer to the Evaluation Board application note AN–2024 SNVA422. For more information on thermal design see AN–2020 and AN–2026. 10.4 Power Module SMT Guidelines The recommendations below are for a standard module surface mount assembly • Land Pattern — Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads • Stencil Aperture – For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern – For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation • Solder Paste — Use a standard SAC Alloy such as SAC 305, type 3 or higher • Stencil Thickness — 0.125 to 0.15 mm • Reflow — Refer to solder paste supplier recommendation and optimized per board size and density • Refer to Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information. • Maximum number of reflows allowed is one 22 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 Power Module SMT Guidelines (continued) Figure 46. Sample Reflow Profile Table 2. Sample Reflow Profile Table PROBE MAX TEMP (°C) REACHED MAX TEMP TIME ABOVE 235°C REACHED 235°C TIME ABOVE 245°C REACHED 245°C TIME ABOVE 260°C REACHED 260°C 1 242.5 6.58 0.49 6.39 2 242.5 7.10 0.55 6.31 0.00 – 0.00 – 0.00 7.10 0.00 – 3 241.0 7.09 0.42 6.44 0.00 – 0.00 – Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT 23 LMZ12001EXT SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Development Support For developmental support, see the following: WEBENCH Tool, http://www.ti.com/webench 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: • AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, (SNVA425) • Absolute Maximum Ratings for Soldering, (SNOA549) • AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422) • AN-2085 LMZ23605/03, LMZ22005/03 Evaluation Board (SNVA457) • AN-2054 Evaluation Board for LM10000 - PowerWise AVS System Controller (SNVA437) • AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419) • AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules (SNVA424) • Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. SIMPLE SWITCHER is a registered trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Insturments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 24 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT LMZ12001EXT www.ti.com SNVS661G – JUNE 2010 – REVISED SEPTEMBER 2015 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: LMZ12001EXT 25 PACKAGE OPTION ADDENDUM www.ti.com 9-Jul-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMZ12001EXTTZ/NOPB ACTIVE TO-PMOD NDW 7 250 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -55 to 125 LMZ12001 EXT LMZ12001EXTTZE/NOPB ACTIVE TO-PMOD NDW 7 45 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -55 to 125 LMZ12001 EXT LMZ12001EXTTZX/NOPB ACTIVE TO-PMOD NDW 7 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -55 to 125 LMZ12001 EXT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Jul-2015 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMZ12001EXTTZ/NOPB TOPMOD NDW 7 250 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2 LMZ12001EXTTZX/NOPB TOPMOD NDW 7 500 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMZ12001EXTTZ/NOPB TO-PMOD NDW 7 250 367.0 367.0 45.0 LMZ12001EXTTZX/NOPB TO-PMOD NDW 7 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NDW0007A BOTTOM SIDE OF PACKAGE TOP SIDE OF PACKAGE TZA07A (Rev D) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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