SUTEX HV312 Sequencing hotswap controller Datasheet

HV302
HV312
__________________________________________________________________________________________________________________
Initial Release
Sequencing Hotswap Controllers
(Negative Supply Rail)
Features
General Description
-10V to 90V or +10V to +90V Operation
Four PWRGD Flags with Programmable Delays
Integrated “normally-on” Gate Clamp eliminates components
UV/OV Lock Out & Power-On-Reset (POR) for Debouncing
Sense resistor programmed Circuit Breaker & Servo Limit
Programmable Circuit Breaker Delay
Inrush control using either: Servo or Feedback Capacitor
Feedback to RAMP pin saves gate protection components
100ms Start Up Timeout Protection for Output Overload
Programmable Inrush Current di/dt Control
Programmable Auto-Retry (tens of seconds if desired)
Auto-Retry or Latched Operation
Application solution for input voltage step (diode “ORing”)
Enable through Open Drain interface to UV or OV
Low Power, 0.6mA Active Mode, 0.4mA Sleep Mode
Small SOIC-14 Package
The HV302 and HV312 Hotswap Controllers perform current
limiting, circuit breaker protection, over and under voltage
detection power management functions during insertion of cards or
modules into live backplanes and connectors. They may be used
in systems where active control is implemented in the negative
lead of supplies ranging from -10V to -90V or +10V to +90V.
During initial power application the external pass device is held off
by a “normally-on” circuit that clamps its gate low. Thereafter
UV/OV and power-on-reset work together to suppress gate turn on
due to contact bounce. When stable connection has been
established for the duration of a programmed time delay, the
inrush current is controlled and limited to a programmed level
using one of two possible methods; servo mode or drain to ramp
feedback capacitor mode. When charging of the load capacitor
is completed, the open drain PWRGD-A flag is asserted. Open
drain PWRGD-B, PWRGD-C and PWRGD-D flags are asserted
sequentially after the expiration of their respective programmed
time delays. Thereafter it transitions to a low power sleep mode
and continues to monitor current and input voltage. If full charging
of the load capacitor is not achieved within 100ms or the circuit
breaker is tripped at any time, the external pass device is turned
off and all four PWRGD flags are reset to the inactive state.
Thereafter a programmable auto-retry timer will hold the pass
device off to allow it to cool before resetting and initiating autoretry. The auto-retry can be disabled using a single resistor if
desired.
Applications
-48V Telecom and Networking
-24V Cellular and Fixed Wireless Systems
-24V PBX Systems
Power Over LAN (IEEE802.3)
Distributed Power Systems
Power Supply Control
+48V Servers and SANs
Hotswap Control of Diode ORed Multiple Power Sources
Cooling Fan Systems
Typical Application Circuit and Waveforms
GND
14
________
PWRGD-D / PWRGD-D
________
PWRGD-C /PWRGD-C
________
PWRGD-B / PWRGD-B
________
PWRGD-A / PWRGD-A
VDD
R1
487k
6
UV
R2
6.81k
5
OV
1
___
EN / EN
2
DC/DC PWM
CONVERTER
3
4
___
EN / EN
HV302 / HV312
R3
9.76k
Cload
DC/DC PWM
CONVERTER
-12V
COM
+12V
COM
-48V
TB
11
TC
12
TD
RAMP
VEE
10
7
13
SENSE
8
GATE
9
100uF
___
EN / EN
DC/DC PWM
CONVERTER
RTB
RTC
RTD
C1
10nF
NOTES:
1.
2.
3.
4.
Under Voltage Shutdown (UV) set to 35V.
Over Voltage Shutdown (OV) set to 65V.
Current Limit set to -1A.
Circuit Breaker set to 8A.
C2
0.75nF
R4
0.0125
Q1
IRF530
___
EN / EN
DC/DC PWM
CONVERTER
+5V
COM
+3.3V
COM
1
Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
HV302 / HV312
Absolute Maximum Ratings
Ordering Information
VEE reference to VDD pin
VPWRGD referenced to VEE Voltage
VUV and VOV referenced to VEE Voltage
Operating Ambient Temperature
Operating Junction Temperature
Storage Temperature Range
Active State of Power
Good Flags
HIGH
LOW
+0.3V to -100V
-0.3V to +100V
-0.3V to +12V
-40°C to +85°C
-40°C to +125°C
-65°C to +150°C
Electrical Characteristics (-10V
Symbol
VIN
-90V, -40°C
Parameter
Min
TA
Package Options
14 Pin SOIC
HV302NG
HV312NG
+85°C unless otherwise noted)
Typ
Max
Units
Conditions
600
400
-10
700
450
µA
µA
VEE = -48V, Mode = Limiting
VEE = -48V, Mode = Sleep
Low to High Transition
High to Low Transition
1.0
V
V
mV
nA
V
V
mV
nA
mV
mV
VUV = VEE + 1.9V, VOV = VEE + 0.5V
VUV = VEE + 1.9V, VOV = VEE + 0.5V
V
VUV = VEE + 1.9V, VOV = VEE + 0.5V
VUV = VEE + 1.9V, VOV = VEE + 0.5V
VUV = VEE, VOV = VEE + 0.5V
Supply (Referenced to VDD pin)
VEE
IEE
IEE
Supply Voltage
Supply Current
Sleep Mode Supply Current
-90
V
OV and UV Control
VUVH
VUVL
VUVHY
IUV
VOVH
VOVL
VOVHY
IOV
(Referenced to VEE pin)
UV High Threshold
UV Low Threshold
UV Hysteresis
UV Input Current
OV High Threshold
OV Low Threshold
OV Hysteresis
OV Input Current
1.26
1.16
100
1.0
1.26
1.16
100
VUV = VEE + 1.9V
Low to High Transition
High to Low Transition
VOV = VEE + 0.5V
Current Limit
VSENSE-CL
VSENSE-CB
(Referenced to VEE pin)
Current Limit Threshold Voltage
Circuit Breaker Current Limit Threshold Voltage
40
80
50
100
60
120
8.5
500
40
10
12
Gate Drive Output
VGATE
IGATEUP
IGATEDOWN
(Referenced to VEE pin)
Maximum Gate Drive Voltage
Gate Drive Pull-Up Current
Gate Drive Pull-Down Current
Ramp Timing Control
IRAMP
tPOR
tRISE
tLIMIT
tPWRGD-A
tPWRGD-B
tPWRGD-B
tPWRGD-C
tPWRGD-C
tPWRGD-D
tPWRGD-D
VRAMP
tSTARTLIMIT
tCBTRIP
tAUTO
µA
mA
-
Test Conditions: CLOAD=100µF, CRAMP=10nF, VUV = VEE + 1.9V, VOV = VEE + 0.5V, External MOSFET is IRF530*
Ramp Pin Output Current
10
VSENSE = 0V
µA
Time from UV to Gate Turn On
2.0
ms (See Note 1)
Time from Gate Turn On to VSENSE Limit
400
µs
Duration of Current Limit Mode
5.0
ms
Time from Current Limit to PWRGD-A
5.0
ms
Maximum Time from PWRGD-A to PWRGD-B
150
200
250
ms RTB = 120kΩ
Minimum Time from PWRGD-A to PWRGD-B
3.0
5.0
8.0
ms RTB = 3kΩ
Maximum Time from PWRGD-B to PWRGD-C
150
200
250
ms RTC = 120kΩ
Minimum Time from PWRGD-B to PWRGD-C
3.0
5.0
8.0
ms RTC = 3kΩ
Maximum Time from PWRGD-C to PWRGD-D
150
200
250
ms RTD = 120kΩ
Minimum Time from PWRGD-C to PWRGD-D
3.0
5.0
8.0
ms RTD = 3kΩ
Voltage on Ramp Pin in Current Limit Mode
3.6
V
(See Note 2)
Start up Time Limit
80
100
120
ms
Circuit Breaker Delay Time
2.0
5.0
May be extended by external RC circuit
µs
Automatic Retry Delay
16
s
2
Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
Power Good Outputs
VPWRGD-x(hi)
VPWRGD-x(lo)
IPWRGD-x(lk)
(Referenced to VEE pin)
Power Good Pin Breakdown Voltage
Power Good Pin Output Low Voltage
Maximum Leakage Current
90
0.5
<1.0
V
V
0.8
10
µA
500
500
ns
ns
PWRGD-x = HI Z
IPWRGD = 1mA, PWRGD-x = LOW
VPWRGD = 90V, PWRGD-x = HI Z
Dynamic Characteristics
tGATEHLOV
tGATEHLUV
OV Comparator Transition
UV Comparator Transition
Note 1: This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing.
Note 2: This voltage depends on the characteristics of the external N-Channel MOSFET. Vto = 3V for an IRF530.
*IRF530 is a registered trademark of International Rectifier.
Pinout
Pin Description
PWRGD-D (HV302)
________
PWRGD-D (HV312)
1
PWRGD-C (HV302)
________
PWRGD-C (HV312)
2
13
TD
PWRGD-B (HV302)
________
PWRGD-B (HV312)
3
12
TC
PWRGD-A (HV302)
________
PWRGD-A (HV312)
4
11
TB
OV
5
10
RAMP
UV
6
9
GATE
VEE
7
14
8
PWRGD-D – This Power Good Output Pin is held inactive on initial
power application and goes active a programmed time delay after
PWRGD-C goes active.
VDD
PWRGD-C – This Power Good Output Pin is held inactive on initial
power application and goes active a programmed time delay after
PWRGD-B goes active.
PWRGD-B – This Power Good Output Pin is held inactive on initial
power application and goes active a programmed time delay after
PWRGD-A goes active.
PWRGD-A – This Power Good Output Pin is held inactive on initial
power application and goes active when the external MOSFET is
fully turned on.
OV – This Over Voltage (OV) sense pin, when raised above its
high threshold will immediately cause the GATE pin to be pulled
low. The GATE pin will remain low until the voltage on this pin falls
below the low threshold limit, initiating a new start-up cycle.
UV – This Under Voltage (UV) sense pin, when below its low
threshold limit will immediately cause the GATE pin to be pulled
low. The GATE pin will remain low until the voltage on this pin
rises above the high threshold limit, initiating a new start-up cycle.
SENSE
VEE – This pin is the negative terminal of the power supply input to
the circuit.
PWRGD Logic
Model
HV302
HV312
Condition
INACTIVE (Not Ready)
ACTIVE (Ready)
INACTIVE (Not Ready)
ACTIVE (Ready)
VDD – This pin is the positive terminal of the power supply input to
the circuit.
PWRGD-A/B/C/D
0
VEE
1
HI Z
1
HI Z
0
VEE
TD – The resistor connected from this pin to VEE pin sets the time
delay from PWRGD-C going active to PWRGD-D going active.
TC – The resistor connected from this pin to VEE pin sets the time
delay from PWRGD-B going active to PWRGD-C going active.
TB – The resistor connected from this pin to VEE pin sets the time
delay from PWRGD-A going active to PWRGD-B going active.
RAMP – This pin provides a current output so that a timing ramp
voltage is generated when a capacitor is connected.
GATE – This is the Gate Driver Output for the external N-Channel
MOSFET.
SENSE – The current sense resistor connected from this pin to VEE
Pin programs the servo control current limit and the circuit breaker
trip limit.
3
Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
HV302 / HV312
Functional Block Diagram
Vint
VDD
Internal
Supply
Regulator
PWRGD-D
UVLO
and
POR
Band Gap
Reference
PWRGD-C
Vbg
PWRGD-B
Programmable
Timer
UV
LOGIC
C
Vbg
OV
PWRGD-A
555 type
Auto-Retry
Timer
C
Vint
10uA
Latch High & Sleep
Vint-1.2V
Transconductor
C
100mV
C
2Vbg
Transconductor
1:2
Mirror
gm
Selector
Switch
Buffer
Circuit Breaker
gm
Selector
Switch
5k
VEE
5k
Clamp Mechanism
SENSE
RAMP
GATE
TB TC TD
Functional Description
Insertion into Hot Backplanes
In Servo Mode operation, assuming the UV and OV limits are
satisfied and while continuing to hold the PWRGD flags inactive
and the external MOSFET GATE voltage low, the current source
feeding the RAMP pin is turned on. The external ramp capacitor
connected to it begins to charge, thus starting an initial time delay
determined by the value of the capacitor and the 2Vbg threshold
voltage of the RAMP pin. During this time if the OV or UV limits
are exceeded, an immediate reset occurs and the capacitor
connected to the RAMP pin is discharged.
Telecom, Networking, SAN and Server applications require the
ability to insert and remove circuit cards from systems without
powering down the entire system. All circuit cards have some filter
capacitance on the power rails, which is especially true in circuit
cards or network terminal equipment utilizing distributed power
systems. The insertion can result in high inrush currents that can
cause damage to connector and circuit cards and may result in
unacceptable disturbances on the system backplane power rails.
The HV302 and HV312 are designed to facilitate the insertion of
these circuit cards or connection of terminal equipment by
eliminating these inrush currents and powering up these circuits in
a controlled manner after full connector insertion has been
achieved
When the voltage on the RAMP pin exceeds the 2Vbg threshold
voltage, the gate drive circuit begins to apply voltage to the gate of
the external MOSFET, which begins to turn on when its gate
threshold voltage is reached.
The resulting output current
generates a voltage drop on the sense resistor connected between
the SENSE and VEE pins, causing a decrease in the available
current charging the capacitor on the RAMP pin. This continuous
feedback mechanism allows the output current to rise inverse
exponentially over a period of a few hundred microseconds to the
sense resistor programmed current limit set point.
Description of Operation
During initial power application, a “normally-on” circuit holds off the
external MOSFET, preventing an input glitch while an integrated
regulator establishes an internal operating voltage of
approximately 10V. Until the proper internal voltage is achieved all
circuits are held reset, the PWRGD flags are inactive and the gate
to source voltage of the external MOSFET is clamped low.
When the voltage drop on the sense resistor reaches 50mV the
RAMP pin current is reduced to zero and the voltage on the RAMP
pin will be fixed, indicating that the circuit is in current limit mode.
Depending on the value of the load capacitor and the programmed
current limit, charging may continue for some time, but may not
exceed a nominal 100ms preset time limit. Once the load
capacitor has been charged, the output current will drop, reducing
the voltage on the SENSE pin, which in turn will increase the
RAMP pin current, thus causing the voltage on the capacitor
connected to the RAMP pin to continue rising, thereby providing
yet another programmed delay.
Once the internal under voltage lock out (UVLO) has been
satisfied, the circuit checks the input supply under voltage (UV)
and over voltage (OV) sense circuits to ensure that the input
voltage is within programmed limits. These limits are determined
by the selected values of resistors R1, R2 and R3, which form a
voltage divider.
4
Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
HV302 / HV312
Functional Description - continued
In Feedback Capacitor Mode operation, assuming the UV and
OV limits are satisfied and while continuing to hold the PWRGD
flags inactive and the external MOSFET GATE voltage low, the
current source feeding the RAMP pin is turned on. The external
ramp capacitor (CRAMP) begins to charge and the feedback
capacitor (CFB) begins to discharge, thus starting an initial time
delay determined by the equivalent value of the capacitors and the
2Vbg threshold voltage of the RAMP pin. During this time if the
OV or UV limits are exceeded, an immediate reset occurs, the
ramp capacitor is discharged and the feedback capacitor is
recharged.
Whether operating in Servo Mode or Feedback Capacitor Mode,
when the ramp voltage is within 1.2V of the regulated internal
supply voltage, the controller will force the GATE terminal to a
nominal 10V, the PWRGD-A pin will change to an active state and
the Circuit Breaker is enabled. PWRGD-B will change to an active
state a programmed delay time after PWRGD-A went active,
PWRGD-C will change to an active state a programmed delay time
after PWRGD-B went active, PWRGD-D will change to an active
state a programmed delay time after PWRGD-C went active and
the circuit transitions to a low power sleep mode. While in sleep
mode the circuit continues to monitor the current and the OV and
UV status.
When the voltage on the RAMP pin exceeds the 2Vbg threshold
voltage, the gate drive circuit begins to apply voltage to the gate of
the external MOSFET, which begins to turn on when its gate
threshold voltage is reached. However, the source current from
the RAMP pin limits the dv/dt of the feedback capacitor (CFB)
which, in turn, programs the inrush current limit (ICL) in accordance
with the relationship ICL= IRAMP x CLOAD/CFB and thus the dv/dt of the
load capacitor. At this point essentially all available current from
the RAMP pin flows into the feedback capacitor, thus the voltage
on the ramp capacitor and the RAMP pin remains essentially
constant, thereby limiting and controlling the gate voltage of the
external MOSFET (See Programming Current Limit and Circuit
Breaker in Design Information section). When the load capacitor is
fully charged the current flowing into the feedback capacitor is
reduced and the voltage drop across the MOSFET essentially
drops to zero, effectively connecting the feedback capacitor in
parallel with the ramp capacitor. Now the current from the RAMP
pin flows into the parallel-connected capacitors and the voltage on
the RAMP pin begins to rise, thereby providing yet another
programmed delay.
When the voltage on the SENSE pin rises to 100mV, indicating an
over current condition, the circuit breaker will trip in less than 5µs.
This time may be extended by the addition of external
components.
If due to output overload conditions during startup full charging of
the load is not achieved within 100ms or a load fault occurs at any
time the circuit breaker is tripped, the MOSFET is turned off by
pulling down the GATE to VEE and all four PWRGD flags are reset.
Thereafter an auto-retry timer, programmed by the capacitor
connected to the RAMP pin, will hold the pass device off to allow it
to cool before resetting and restarting. The auto-retry can be
disabled using a single resistor if desired (See Auto-Retry and
Auto-Retry Disable in Design Information section).
At any time during the start up cycle or thereafter, crossing the UV
and OV limits (including hysteresis) will cause an immediate reset
of all internal circuitry. When the input supply voltage returns to a
value within the programmed UV and OV limits a new start up
sequence will be immediately initiated.
5
Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
HV302 / HV312
Design Information
Programming Under and Over Voltage Shut Down
Under Voltage/Over Voltage Operation
The UV and OV pins are connected to comparators with nominal
1.21V thresholds and 100mV of hysteresis (1.21V ± 50mV). They
are used to detect under voltage and over voltage conditions at the
input to the circuit. Whenever the OV pin rises above its high
threshold (1.26V) or the UV pin falls below its low threshold
(1.16V) the GATE voltage is immediately pulled low, the PWRGD
pin changes to its inactive state and the external capacitor
connected to the RAMP pin is discharged.
Calculations can be based on either the desired input voltage
operating limits or the input voltage shutdown limits. In the
following equations the shutdown limits are assumed.
From the calculated resistor values the OV and UV start up
threshold voltages can be calculated as follows:
The under voltage and over voltage shut down thresholds can be
programmed by means of the three resistor divider formed by R1,
R2 and R3. Since the input currents on the UV and OV pins are
negligible the resistor values may be calculated as follows:
R2 + R3
R1 + R2 + R3
R3
OVOFF = VOVH = 1.26 = VEEOV(off) ×
R1 + R2 + R3
Where VEEUV(off) and VEEOV(off) are Under & Over Voltage Shut
Down Threshold points.
UVON = VUVH = 1.26 = VEEUV(on) ×
R2 + R3
R1 + R2 + R3
OVON = VOVL = 1.16 = VEEOV(on) ×
R3
R1 + R2 + R3
UVOFF = VUVL = 1.16 = VEEUV(off) ×
Where VEEUV(on) and VEEOV(on) are Under & Over Voltage Start
Up Threshold points.
Then
If we select a divider current of 100µA at a nominal operating input
voltage of 50 Volts then
50V
R1 + R2 + R3 =
= 500kΩ
100uA
From the second equation for an OV shut down threshold of 65V
the value of R3 may be calculated.
OVOFF
R3 =
1.26 × 500KΩ
= 9.69kΩ
65
The closest 1% value is 9.76kΩ
VEEUV(on) = 1.26 ×
487kΩ + 6.81kΩ + 9.76kΩ
= 38.29V
6.81kΩ + 9.76kΩ
VEEOV(on) = 1.16 ×
R1 + R2 + R3
R3
VEEOV(on) = 1.16 ×
487kΩ + 6.81kΩ + 9.76kΩ
= 59.85V
9.76kΩ
Therefore, the circuit will start when the input supply voltage is in
the range of 38.29V to 59.85V.
From the first equation for a UV shut down threshold of 35V the
value of R2 can be calculated.
R2 =
R1 + R2 + R3
R2 + R3
And
65 × R3
= 1.26 =
500kΩ
UVOFF = 1.16 =
VEEUV(on) = 1.26 ×
35 × (R2 + R3)
500KΩ
1.16 × 500kΩ
− 9.76kΩ = 6.81kΩ
35
The closest 1% value is 6.81kΩ
Then
R1 = 500KΩ − R2 − R3 = 483kΩ
The closest 1% value is 487kΩ
6
Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
HV302 / HV312
Design Information- continued
Calculate C2 (feedback capacitor) discharge current
Programming Current Limit and Circuit Breaker
IC2 = 10µA − ISINK = 10µA − 2.5µA = 7.5µA
Feedback Capacitor Mode Operation
In this operating mode the circuit breaker trip current and the
inrush current limit can be independently programmed. In fact the
circuit breaker can be completely disabled by setting RSENSE = 0Ω.
If Auto-Retry is disabled an adjustment must be made to IC2
IAUTO =
The circuit breaker will trip in less than 5µs when the voltage on
the SENSE pin is raised 100mV above the VEE pin and the value of
the sense resistor may be calculated from the following equation:
R SENSE =
Where Vt is the maximum threshold voltage of the MOSFET.
Therefore, the adjusted value of IC2 is:
VSENSE-CB
100mV
=
ICB
ICB
IC2 = 10µA − ISINK − IAUTO
For an 8A circuit breaker:
R SENSE =
Vt
4V
=
= 1.6µA
RDISABLE 2.5MΩ
IC2 = 10µA − 2.5µA − 1.6µA = 5.9µA
100mV
= 12.5mΩ
8A
In this example we assume that Auto-Retry is enabled and
therefore use IC2 = 7.5µA.
The power rating of the sense resistor must be greater than or
equal to ICB x VSENSE-CB.
dv
dv
and
ICL = CLOAD ×
dt
dt
Since VIN is fixed and VRAMP is constant during limiting, then
dv
dv
across CLOAD =
across C2 as they share a common node
dt
dt
and their other terminals are at fixed voltages during inrush current
I
I
I × CLOAD
limiting. Therefore, C2 = CL
or C2 = C2
.
C2 CLOAD
ICL
As previously calculated and by conservation of charge on RAMP
node IC2=7.5µA based on the chosen inrush current limit of ICL=1A.
Given that CLOAD=100µF the required value for C2 can be
calculated.
The following diagrams depict the equivalent circuitry to clarify the
feedback capacitor operation for programming the inrush current
limit.
Note that
IC2 = C2 ×
Therefore
C2 =
IC2 × CLOAD 7.5µA × 100µF
=
= 0.75nF
ICL
1A
Note that during initial power application the RAMP pin is voltage
protected by the capacitive AC voltage divider consisting of CLOAD,
C2 and CRAMP and the GATE pin is internally clamped.
Servo Control Mode Operation
The circuit breaker will trip in less than 5µs when the voltage on
the SENSE pin is raised 100mV above the VEE pin and the value of
the sense resistor may be calculated from the following equation:
R SENSE =
The inrush current limit may be programmed as follows:
For a 2A circuit breaker:
Choose inrush current limit, for example ICL = 1A
Calculate ISINK =
VSENSE-CB
100mV
=
ICB
ICB
R SENSE =
ICL × R SENSE 1A × 12.5m Ω
= 2.5µA
=
5kΩ
5kΩ
100mV
= 50mΩ
2A
The power rating of the sense resistor must be greater than or
equal to ICB x VSENSE-CB.
If the Circuit Breaker function is disabled by setting RSENSE = 0Ω,
then ISINK = 0A. However, in this example we assume that the
Circuit Breaker function is enabled and therefore use ISINK = 2.5µA.
7
Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
HV302 / HV312
Design Information- continued
The timing functions are defined by the following equations:
The inrush current limit can be calculated as follows:
ICL =
VSENSE-CL
50mV
=
R SENSE
R SENSE
Thus the inrush current limit for a 2A circuit breaker:
ICL
50mV
=
= 1A
50mΩ
t START = 2.4
CRAMP
IRAMP
t TH = VGS( th )
CRAMP
IRAMP
t POR = t START + t TH
Compensation components from gate to source of the external
MOSFET may be required to reduce peaking of the inrush current.
t RISE ≈
CRAMP
 I
R
gfs  RAMP − SENSE
0
.
9
I
RFB
LIMIT

t LIMIT ≈ VIN




CLOAD
ILIMIT
(
t PWRGD − A = VINT − VGS(LIMIT ) − 1.2
) CI
RAMP
RAMP
These equations assume that the load is purely capacitive and the
following definitions apply.
CRAMP is the external capacitor connected to the RAMP pin.
IRAMP is the output current from the RAMP pin, nominally
10µA, when the voltage drop on RSENSE resistor is zero.
Compensation can be accomplished as follows:
1. Start with a 2nF capacitor from gate to source.
2. Increase capacitor value up to 10nF if needed.
3. If needed, add a 1kΩ resistor in series with the above
capacitor.
VINT is the internally regulated supply voltage and can range
from 9V to 11V.
VGS(th) is the gate threshold voltage of the external pass
transistor and may be obtained from its datasheet.
Servo Mode Timing
VGS(limit) is the external pass transistor gate-source voltage
required to obtain the limit current. It is dependent on the
pass transistor’s characteristics and may be obtained from
the transfer characteristics on the transistor datasheet.
gfs is the transconductance of the external pass transistor and
may be obtained from its datasheet.
RFB is the internal feedback resistor and is nominally 5KΩ.
ILIMIT is the load current when the voltage drop on RSENSE
resistor is 50mV.
These equations may be used to calculate the minimum value of
CRAMP for the most critical system performance characteristics.
For maximum contact bounce duration protection choose a value
for tPOR and use the following equation:
CRAMP =
t POR × IRAMP
2.4 + VGS(limit )
If control of PWRGD active delay is the critical system parameter,
then choose a value for tPWRGD-A and use the following equation:
CRAMP =
8
t PWRGD − A × IRAMP
VINT − VGS(limit ) − 1.2
Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
HV302 / HV312
Design Information - continued
The following waveforms demonstrate the sequencing of the
PWRGD flags. These results were obtained with RTB = 120kΩ, RTC
= 60kΩ and RTD = 3kΩ
Start up Overload Protection
Start up must be achieved within a nominal 100ms as indicated by
the PWRGD-A pin transition to the active state or the circuit will
reset and an Auto-Retry will initiate. If there is an output overload
or short circuit during start up, the circuit will be in current limit
mode for the 100ms time limit (in servo mode). In feedback
capacitor mode the circuit breaker will shutdown the MOSFET
before 100ms.
Circuit Breaker Delay
The circuit breaker will trip in less than 5µs when the voltage on
the SENSE pin reaches a nominal 100mV. A resistor in series with
the SENSE pin and a capacitor connected between the SENSE
and VEE pins may be added to delay the rate of voltage rise on the
SENSE pin, thus permitting a current overshoot and delaying
Circuit Breaker activation. This method is particularly useful when
operating in Feedback Capacitor Mode. However, in Servo Mode
operation it will result in a current limit leading edge overshoot.
Auto-Retry and Auto-Retry Disable
The Auto-Retry delay time is directly proportional to the
capacitance at the RAMP pin. Auto-Retry sequence is activated
whenever the 100ms timeout is reached during start up or the
Circuit Breaker is tripped.
The value of the resistors determines the capacitor charging and
discharging current of a triangle wave oscillator. The oscillator
output is fed to an 8-bit counter to generate the desired time delay.
The respective delay time is defined by the following equation:
Auto-Retry can be approximated as a 555-timer with 2.5µA charge
up and charge down currents through 8V, to a count of 256.
255 × 2 × C OSC × VPP
ICD
t TX =
and
ICD =
Where
Therefore,
t Auto−Re try =
2 × 8 × 256
× CRAMP
2.5µA
For CRAMP = 10nF
t Auto−Re try =
2 × 8 × 256
× 10nF = 16.4s
2.5µA
Vbg
4R TX
tTX = Delay Time between respective PWRGD flags
COSC = 120pF (Internal oscillator capacitor)
VPP = 8.2V (Peak-to-Peak voltage swing of oscillator)
ICD = Charge and Discharge current of oscillator
Vbg = 1.2V (Internal Band Gap Reference)
RTX = Programming resistor at TB, TC or TD pin
Combining the above two equations and solving for RTX yields:
R TX =
Due to the 2.5µA maximum charge current a resistor which draws
more than 2.5µA below 8V will disable Auto-Retry. Try to keep this
resistor as big as possible, e.g. 2.5MΩ. For most MOSFETs with
maximum Vt of 4V, this will vary the 10µA RAMP current source by
4V
= 1.6µA
only
2.5MΩ
B bg × t TX
2040 × CPP × VPP
=
1.2V × t TX
2040 × 120pF × 8.2V
R TX = 0.6 × 10 6 × t TX
For a delay time of 200ms we get:
(
) (
)
R TX = 0.6 × 10 6 × 200 × 10 −3 = 120kΩ
PWRGD Flag Delay Programming
For a delay time of 5ms we get:
Shortly after current limiting ends, PWRGD-A becomes active
indicating successful completion of the Hotswap operation.
PWRGD-B will change to an active state a programmed delay time
after PWRGD-A went active, PWRGD-C will change to an active
state a programmed delay time after PWRGD-B went active and
PWRGD-D will change to an active state a programmed delay time
after PWRGD-C went active. Resistors connected from the
respective TB, TC and TD pins to VEE pin are used to program the
delay times between the PWRGD flags sequentially going active.
(
) (
)
R TX = 0.6 × 10 6 × 5 × 10 −3 = 3kΩ
9
Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
HV302 / HV312
Design Information - continued
Supported External Pass Devices
The HV302 and HV312 are designed to support N-Channel
MOSFETs and IGBTs.
Selection of External Pass Devices
The RDS(ON) of the device is likely to be selected based on
allowable voltage drop at maximum load (ILOAD(MAX)) after the
Hotswap action has been completed.
Thus the required
continuous power dissipation rating (PCONT) of the device can be
determined from the following equation:
PCONT = RDS( ON) × I2LOAD(MAX )
The peak power rating (PPEAK) should be based on the highest
current level, which is always the circuit breaker trip set point (ICB),
and on the assumption that a output is shorted. The peak power
rating may be calculated from the following equation:
PPEAK = VIN × ICB
Given these values an external pass transistor may be selected
from the manufacturers data sheet.
Paralleling External Pass Transistors
Due to variations in threshold voltages and transconductance
characteristics between samples of MOSFETs, reliable 50%
current sharing is not achievable. Some measure of paralleling
may be accomplished by adding resistors in series with the source
of each device; however, it will cause increased voltage drop and
power dissipation.
Paralleling of external Pass devices is not recommended!
If a sufficiently high current rated external pass transistor cannot
be found then increased current capability may be achieved by
connecting independent Hotswap circuits in parallel, since they act
as current sources during the load capacitor charging time when
the circuits are in current limit. For this application the HV302 with
active high PWRGD is recommended where the PWRGD pins of
multiple Hotswap circuits can be connected in a wired OR
configuration.
Kelvin Connection to Sense Resistor
Physical layout of the printed circuit board is critical for correct
current sensing. Ideally trace routing between the current sense
resistor and the VEE and SENSE pins should be direct and as short
as possible with zero current in the sense traces. The use of
Kelvin connection from SENSE pin and VEE pin to the respective
ends of the current sense resistor is recommended.
To
To
VEE SENSE
Pin Pin
To Negative
Terminal of
Power Source
To Source
of MOSFET
Sense Resistor
10
Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
Similar pages