LTC3569 Triple Buck Regulator With 1.2A and Two 600mA Outputs and Individual Programmable References DESCRIPTION FEATURES n n n n n n n n n n n n n Three Independent Current Mode Buck DC/DC Regulators (1.2A and 2x 600mA) Single Pin Programmable VFB Servo Voltages from 800mV Down to 425mV (in 25mV Steps) Pull VFB High to Make Each 600mA Buck a Slave for Higher Current Operation Pulse Skip or Burst Mode® Operation Programmable Switching Frequency (1MHz to 3MHz) or Fixed 2.25MHz Synchronizable (1.2MHz to 3MHz) VIN Range 2.5V to 5.5V All Regulators Internally Compensated PGOOD Output Flag Quiescent Current <100μA (All Regulators in Burst Mode Operation) Zero Shutdown Current Overtemperature and Short-Circuit Protection Tiny 3mm × 3mm 20-Lead QFN and Thermally Enhanced TSSOP FE-16 Packages The LTC®3569 contains three monolithic, synchronous step-down DC/DC converters. Intended for medium power applications, it operates over a 2.5V to 5.5V input voltage range. The operating frequency is adjustable from 1MHz to 3MHz, allowing the use of tiny, low cost capacitors and inductors. The three output voltages are independently programmable by toggling the EN pins up to 15 times, lowering the 800mV FB references by 25mV per cycle. The first buck regulator sources load currents up to 1200mA. The other two buck regulators each provide 600mA. The two 600mA buck regulators can also be configured to operate as slave power stages, running in parallel with another internal buck regulator to supply higher load currents. When operating as parallel, slave output stages, discrete external components are shared and available output currents sum together. L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6127815, 6304066, 6498466, 6580258, 6611131, 7170195. APPLICATIONS n n n Portable Applications with Multiple Supply Rails General Purpose Step-Down DC/DC Dynamic Voltage Scaling Applications TYPICAL APPLICATION VIN Efficiency vs Load Current 2.2μH 22μF SVIN PVIN OUT1 = 2.5V 1200mA SW1 20pF EN1 EN3 10μF 90 FB1 2.5μH SW2 MODE 20pF RT 300k OUT2 = 1.8V 600mA 4.7μF FB2 60 50 40 20 2.5μH SW3 20pF 150k OUT3 = 1.2V 600mA 4.7μF FB3 PGND VIN = 5V 70 30 240k PGOOD SGND VIN = 3V 80 240k LTC3569 EFFICIENCY (%) EN2 510k 100 300k BURST PULSE SKIP OUT1 = 2.5V 10 0 0.01 0.1 1 10 100 ILOAD (mA) 1000 10000 3569 TA01b 3569 TA01a 3569f 1 LTC3569 ABSOLUTE MAXIMUM RATINGS (Notes 1, 6) SVIN Voltage.......................... –0.3V to 6V (7V Transient) PVINX Voltage .........................SVIN – 0.3V to SVIN + 0.3V ENx, MODE, PGOOD, SWx, FBx ......–0.3V to SVIN + 0.3V RT Voltage .................................................... –0.3V to 6V ISW1 (DC) .................................................................2.5A ISW2, ISW3 (DC) ........................................................1.3A Operating Temperature Range.................. –40°C to 85°C Storage Temperature Range................... –65°C to 125°C Maximum Junction Temperature (Note 6) ............ 125°C Peak Reflow Temperature ..................................... 260°C PIN CONFIGURATION EN2 EN1 4 5 6 17 PVIN1 8 9 PVIN3 13 EN1 12 EN2 MODE 4 11 PVIN2 10 SW2 14 PGND3 21 PGOOD 3 12 PGOOD 7 15 SW3 PVIN2 2 13 MODE SW3 PVIN1 20 19 18 17 16 SW2 1 11 EN3 RT 5 SW1 FE PACKAGE 16-LEAD PLASTIC TSSOP 6 7 8 9 10 SGND EN3 SW1 14 RT SVIN 3 FB3 15 FB2 SGND PGND2 16 FB1 2 FB1 1 FB2 FB3 SVIN PGND1 TOP VIEW TOP VIEW UD PACKAGE 20-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 125°C, θJA = 38°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 68°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3569EUD#PBF LTC3569EUD#TRPBF LDQF 20-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C LTC3569IUD#PBF LTC3569IUD#TRPBF LDQF 20-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C LTC3569EFE#PBF LTC3569EFE#TRPBF 3569FE 16-Lead Plastic TSSOP –40°C to 85°C LTC3569IFE#PBF LTC3569IFE#TRPBF 3569FE 16-Lead Plastic TSSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3569f 2 LTC3569 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise noted (Notes 2, 7). SYMBOL PARAMETER SVIN Input Supply Voltage CONDITIONS IVIN Input Current Pulse Skip Mode Input Current Burst Mode Operation EN1 = SVIN, EN2, EN3 = 0, IOUT1, = 0A, FB1 = 0.9V (Note 3) IQX Additional Input Current per Buck, Pulse Skip Burst Mode Operation IQSHDN Quiescent Current at SGND Pin in Shutdown Mode IPK1 Peak Inductor Current SW1 IPK2, IPK3 Peak Inductor Current SW2, SW3 VFBX(MAX) Maximum Feedback Voltage VFBX(STEP) Feedback Reference Step Size Each Toggle on ENx VFBX(MIN) Minimum Feedback Voltage VPROGFBX Feedback Programming Range IFBX MIN l TYP 2.5 MAX UNITS 5.5 V 230 47 365 82 μA μA (Note 3) VFB = 0.9V 140 22 225 36 μA EN1, EN2, EN3 = 0V VSW1 = VSW2 = VSW3 = 0V 0.1 1 μA 1.8 2.0 2.5 A 0.780 1.0 1.3 A l 0.784 0.8 0.816 V ENx Toggle 15 Times l 0.405 0.425 Feedback Pin Input Current VFB = 0.8V l ILKSWX Switch Pin Leakage Current VSWX = 0V or SVIN, VENX = SVIN, VFBX = 0.9V DX Maximum Duty Cycle FBx = 0V 25 0.425 mV 0.44 V 0.8 V ±0.2 μA ±1 μA 100 % RP1 RDSON of PSW for SW1 ISW1 = 100mA (Note 5) 195 mΩ RN1 RDSON of NSW for SW1 ISW1 = –100mA (Note 5) 180 mΩ RP2, RP3 RDSON of PSW for SW2, SW3 ISW2, ISW3 = 100mA (Note 5) 265 mΩ RN2, RN3 RDSON of NSW for SW2, SW3 ISW2, ISW3 = –100mA (Note 5) 250 mΩ RSWx_PD SWx Pull-Down in Shutdown ENx = 0V, VSWX = 1.2V, (FBx < SVIN ) 2.3 kΩ ΔVLINEREG Reference Voltage Line Regulation SVIN = 2.5V to 5.5V 0.04 ΔVLOADREG Output Voltage Load Regulation Pulse Skip Mode (Note 4) 0.5 tSS Soft Start Reference Ramp Rate tEN Enable Turn-On Delay From Last ENx Rise to Begin of Soft Start Ramp From ENx Fall to Shutdown 0.2 %/V % 0.75 V/ms 125 240 μs 170 330 μs 55 μs tOFF Enable Turn-Off Delay tPW Enable Pulse Width IENX Enable Leakage Current VENX = 3.6V 0.02 μA IMODE Mode Leakage Current VMODE = 3.6V 0.02 μA VIL Input Low Voltage MODE, ENx VIH Input High Voltage MODE, ENx TMODEPW Pulse Width Applied to MODE Pin for Synchronizing 0.06 0.4 V 1.2 V 100 ns 3569f 3 LTC3569 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise noted (Notes 2, 7). SYMBOL PARAMETER CONDITIONS PGOOD Power Good Threshold VFBX Ramping Up VFBX Ramping Down TPGOOD PGOOD Delay RPGOOD PGOOD Pull-Down On-Resistance MIN VFBX < 0.4V Undervoltage Lockout Fixed Oscillator Frequency VRT = SVIN l 1.9 fCLK(MAX) Maximum Programmable Oscillator Frequency RT = 100k l 3.0 fCLK(MIN) Minimum Programmable Oscillator Frequency RT = 453k l fSYNC Sync Frequency RT = 100k Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Current into a pin is positive and current out of a pin is negative. All voltages referenced to SGND. Note 3: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 4: Specification is guaranteed by design and not 100% tested in production. Note 5: Switch on-resistance verified by correlation to wafer level measurements. 100 150 100 VIN = 5V 60 50 40 3569 G01 1.0 MHz 3 MHz VIN = 3V 70 VIN = 5V 60 50 40 30 20 10 0 0.01 MHz 80 70 20 SLOPE ≅ 132nA/°C NO LOAD 0 50 –50 0 100 150 TEMPERATURE (°C) V 2.8 MHz 90 30 BUCK1 ONLY Burst Mode OPERATION VIN = 3.5V 2.5 100 EFFICIENCY (%) SLOPE ≅ 185nA/°C Ω Efficiency vs Load Current OUT3 = 1.2V 80 EFFICIENCY (%) ISVIN (μA) BUCK1 ONLY PULSE SKIP VIN = 3.5V 2.25 525 TA = 25°C, unless otherwise noted. VIN = 3V 90 50 μs Note 6: This IC includes over-temperature protection that is intended to protect the device during momentary overload conditions. Junction temperature exceeds 125°C when over-temperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7: The LTC3569E is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design characterization and correlation with statistical process controls. The LTC3569I is guaranteed to meet specified performance over the full –40°C to 85°C operating temperature range. Efficiency vs Load Current OUT2 = 1.8V 300 200 2 1.2 TYPICAL PERFORMANCE CHARACTERISTICS ISVIN vs Temperature UNITS % % l UVLO MAX –8 –12 380 fOSC 250 TYP BURST PULSE SKIP 0.1 1 10 ILOAD (mA) 100 1000 3569 G02 10 0 0.01 BURST PULSE SKIP 0.1 1 10 ILOAD (mA) 100 1000 3569 G03 3569f 4 LTC3569 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs VSUPPLY OUT1 = 1.8V Efficiency vs VSUPPLY OUT2 = 1.2V 95 BUCK1 ONLY Efficiency vs VSUPPLY OUT3 = 1.5V 90 85 85 85 80 75 65 80 75 ILOAD = 270mA ILOAD = 220mA ILOAD = 170mA ILOAD = 120mA 2 ILOAD = 210mA ILOAD = 170mA ILOAD = 110mA ILOAD = 70mA 70 4 3 EFFICIENCY (%) 90 70 5 65 6 2 5 75 ILOAD = 210mA ILOAD = 170mA ILOAD = 110mA ILOAD = 70mA 2 3 VSUPPLY (V) 5 6 3569 G06 RDS(ON) SW1 vs VSUPPLY and Temperature 2.40 0.35 VIN = 5.5V RDS(ON) SW2 and SW3 vs VSUPPLY and Temperature 0.50 NSW1 PSW1 100°C 0.40 RDS(ON) (Ω) RDS(ON) (Ω) 25°C 0.25 0.20 NSW2 & 3 PSW3 & 3 100°C 0.45 0.30 VIN = 3.5V VIN = 2.5V 4 VSUPPLY (V) 3569 G05 Oscillator Frequency vs Temperature 2.20 80 65 6 3569 G04 2.30 BUCK3 ONLY 70 4 3 VSUPPLY (V) fCLK (MHz) 95 BUCK2 ONLY 90 EFFICIENCY (%) EFFICIENCY (%) 95 TA = 25°C, unless otherwise noted. 25°C 0.35 0.30 0.25 –50°C 0.20 2.10 0.15 VRT = SVIN 2.00 –50 0 100 50 TEMPERATURE (°C) 150 0.10 –50°C 0.15 0.10 2 4 3 5 6 2 3 VSUPPLY (V) 3569 G07 4 VSUPPLY (V) 5 3569 G09 3569 G08 VFB vs Temperature ISVIN vs VSUPPLY Burst Mode Operation ISVIN vs VSUPPLY Pulse Skip 0.3 6 120 700 VREF SET TO MAX 600 ALL 3 80 2 BUCKS ENABLED ISVIN (μA) 0.0 400 300 ALL 3 100 500 0.1 ISVIN (μA) VFB ERROR (%) 0.2 1 BUCK ENABLED 2 BUCKS ENABLED 60 1 BUCK ENABLED 40 –0.1 200 VFB1 VFB2 VFB3 –0.2 –0.3 –50 0 100 50 TEMPERATURE (°C) 150 3569 G10 20 100 0 NO LOAD 2 3 4 5 0 6 NO LOAD 2 3 4 5 6 VSUPPLY (V) VSUPPLY (V) 3569 G11 3569 G12 3569f 5 LTC3569 TYPICAL PERFORMANCE CHARACTERISTICS Buck1 Load Regulation 0.6 Buck2 Load Regulation 0.6 BUCK2, 3 OFF VIN = 5.5V 0.2 VIN = 4.5V PULSE SKIP VOUT ERROR (%) VOUT ERROR (%) BUCK1, 3 OFF 0.4 0.4 0.0 –0.2 VIN = 2.5V VIN = 3.5V 0.2 VIN = 5.5V PULSE SKIP VIN = 4.5V 0.0 –0.2 VIN = 2.5V VIN = 3.5V –0.4 –0.4 –0.6 TA = 25°C, unless otherwise noted. –0.6 0 0.2 0.4 0.8 0.6 ILOAD (A) 1 1.2 0 0.1 0.2 0.4 0.3 ILOAD (A) 0.5 3569 G14 3569 G13 Line Regulation Buck3 Load Regulation 0.6 0.6 0.15 BUCK1, 2 OFF EACH BUCK TESTED INDIVIDUALLY 0.10 0.4 VOUT ERROR (%) VOUT ERROR (%) BUCK2 = 1.2V 0.2 0.0 PULSE SKIP 0.00 BUCK3 = 1.5V –0.05 –0.2 PULSE SKIP MODE ILOAD1 = 200mA ILOAD2, 3 = 150mA –0.10 –0.4 –0.6 BUCK1 = 1.8V 0.05 VOUT3 = 1.5V 0 0.1 0.2 0.4 0.3 ILOAD (A) 0.5 0.6 –0.15 2 3 4 VSUPPLY (V) 5 3569 G16 3569 G15 FB Pin Leakage IQSD vs Temperature 1000 10000 VIN = 5.5V SLAVE DETECTOR = 250nA 100 6 VIN = 5.5V 1000 ISVIN (nA) IFB (nA) 10 IFB2,3 1 10 IFB1 0.1 1 0.01 0.001 100 0 1 2 3 VFB (V) 4 5 6 3569 G17 0.1 –50 0 50 100 TEMPERATURE (°C) 150 3569 G18 3569f 6 LTC3569 TYPICAL PERFORMANCE CHARACTERISTICS Load Step Cross Talk, Pulse Skip, VIN = 3.6V, CH1 = VOUT1, CH2 = VOUT2, CH3 = VOUT3, CH4 = ILOAD1 Load Step Cross Talk, Pulse Skip, VIN = 3.6V, CH1 = VOUT1, CH2 = VOUT2, CH3 = VOUT3, CH4 = ILOAD2 100mV/DIV CH1 310mVP-P CH1 9.6mVP-P 20mV/DIV CH2 246mVP-P 100mV/DIV CH2 16.8mVP-P 20mV/DIV CH3 12mVP-P 20mV/DIV CH3 8mVP-P 500mA/DIV CH4 600mA CH4 1.2A 20μs/DIV TA = 25°C, unless otherwise noted. 20mV/DIV 500mA/DIV 3569 G19 Load Step Cross Talk, Pulse Skip, VIN = 3.6V, CH1 = VOUT1, CH2 = VOUT2, CH3 = VOUT3, CH4 = ILOAD3 ISW Leakage vs VSUPPLY Buck 1 10000 20mV/DIV CH2 11.2mVP-P 20mV/DIV 100mV/DIV CH4 600mA VIN = 3.6V VFB = 0.9V BUCK2, BUCK3 OFF 1000 100 ISW (nA) CH1 11.6mVP-P CH3 266mVP-P 3569 G20 20μs/DIV 85°C 10 1 25°C 0.1 500mA/DIV 20μs/DIV 3569 G21 –50°C 0.01 0.001 0 1 2 VSW (V) 3 3.6 3569 G22 Soft-Start Into Heavy Load, PS, VIN = 3.6V, CH1 = VOUT1, CH2 = VOUT2, CH3 = VOUT3, CH4 = IIN, R2 = PGOOD Soft-Start Into Light Load, PS, VIN = 3.6V, CH1 = VOUT1, CH2 = VOUT2, CH3 = VOUT3, CH4 = IIN, R3 = PGOOD CH1 500mV/DIV CH3 500mV/DIV CH2 500mV/DIV CH1 500mV/DIV CH3 500mV/DIV CH2 500mV/DIV R2 2V/DIV R3 2V/DIV CH4 500mA/DIV 400μs/DIV 3569 G23 CH4 50mA/DIV 400μs/DIV 3569 G24 3569f 7 LTC3569 PIN FUNCTIONS (QFN/TSSOP) SW2 (Pin 1/Pin 10): Buck 2 Switch. Connect to the Inductor for Buck 2. This pin swings from PVIN2 to PGND2. SVIN (Pin 9/Pin 2): Main Supply Pin. Decouple to SGND with a low ESR 1μF capacitor. PVIN2 (Pin 2/Pin 11): Main Supply Pin for Buck 2. Decouple to PGND2 with a low ESR 4.7μF capacitor. SGND (Pin 10/Pin 3): Main Ground Pin. Decouple to SVIN. PGOOD (Pin 3/Pin 12): The Power Good Pin. This opendrain output is released when an enabled output has risen to within 8% of the regulation voltage. When multiple outputs are enabled, PGOOD is the AND of each internal PGOOD. EN3 (Pin 11/Pin 4): Enable Pin for Buck 3. Toggle up to 15 times to program reference feedback level from 800mV down to 425mV. MODE (Pin 4/Pin 13): Combination Mode Selection and Oscillator Synchronization Pin. This pin controls the operating mode of the device. When tied to SVIN, Burst Mode operation is selected. When tied to SGND, pulseskipping mode is selected. The internal clock frequency synchronizes to an external oscillator applied to this pin. When synchronizing to an external clock, drive this pin with a logic-level signal with high and low pulse widths of at least 100ns. When synchronizing to an external clock, pulse skip mode is automatically selected. RT (Pin 5/Pin 14): Timing Resistor Pin. The free-running oscillator frequency is programmed by connecting a resistor from this pin to ground. Tie to SVIN to get a fixed 2.25MHz operating frequency. FB2 (Pin 6/Pin 15): Receives the feedback voltage from the external resistive divider across the output of Buck 2. Nominal voltage for this pin is programmed with the EN2 pin from 800mV down to 425mV. When pulled to SVIN, Buck 2 is put into slave mode, following Buck 1. FB1 (Pin 7/Pin 16): Receives the feedback voltage from the external resistive divider across the output of Buck 1. Nominal voltage for this pin is programmed with the EN1 pin from 800mV down to 425mV. FB3 (Pin 8/Pin 1): Receives the feedback voltage from the external resistive divider across the output of Buck 3. Nominal voltage for this pin is programmed with the EN3 pin from 800mV down to 425mV. When pulled to SVIN, Buck 3 is put into slave mode, following Buck 2. EN2 (Pin 12/Pin 5): Enable Pin for Buck 2. Toggle up to 15 times to program reference feedback level from 800mV down to 425mV. EN1 (Pin 13/Pin 6): Enable Pin for Buck 1. Toggle up to 15 times to program reference feedback level from 800mV down to 425mV. PGND3 (Pin 14/NA): Main Power Ground Pin for Buck 3. Connect to the (–) terminal of COUT3, and (–) terminal of CIN3. SW3 (Pin 15/Pin 7): Buck 3 Switch. Connect to the Inductor for Buck 3. This pin swings from PVIN3 to PGND3. PVIN3 (Pin 16/NA): Main Supply Pin for Buck 3. Decouple to PGND3 with a low ESR 4.7μF capacitor. PVIN1 (Pin 17/Pin 8): Main Supply Pin for Buck 1. Decouple to PGND1 with a low ESR 4.7μF capacitor. SW1 (Pin 18/Pin 9): Buck 1 Switch. Connect to the Inductor for Buck 1. This pin swings from PVIN1 to PGND1. PGND1 (Pin 19/NA): Main Power Ground Pin for Buck 1. Connect to the (–) terminal of COUT1, and (–) terminal of CIN1. PGND2 (Pin 20/NA): Main Power Ground Pin for Buck 2. Connect to the (–) terminal of COUT2, and (–) terminal of CIN2. Exposed Pad (Pin 21/Pin 17): Exposed paddle must be connected to PCB ground for rated thermal performance and electrical connection of the TSSOP package. 3569f 8 LTC3569 BLOCK DIAGRAM SVIN PVIN1 EN1 ON1 REF1 DAC1 PG1 P-CHANNEL + SW1 BUCK 1.2A EA1 FB1 – NG1 N-CHANNEL PGND1 OFF PGOOD1 PON1 NOFF1 PVIN2 EN2 ON2 REF2 DAC2 PG2 P-CHANNEL + SW2 BUCK 0.6A EA2 FB2 – NG2 N-CHANNEL OFF BG PGND2 PGOOD2 PON2 NOFF2 PVIN3 EN3 ON3 REF3 DAC3 PG3 SW3 EA3 FB3 BUCK 0.6A – MODE/SYNC OSC P-CHANNEL + NG3 CLK ISLOPE1 ISLOPE2 ISLOPE3 N-CHANNEL RPGOOD PGND3 OFF PGOOD3 PGOOD 800mV RT PGOOD1 PGOOD2 PGOOD3 PGOODB RT GND 3569BD Figure 1. Detailed Block Diagram 3569f 9 LTC3569 OPERATION Introduction Each of the buck regulators supports 100% duty cycle operation (low dropout mode) when their input voltage drops very close to their output voltage. The switching regulators also include soft-start to limit inrush current when powering on, and short circuit current protection. The LTC3569 contains three constant-frequency, currentmode buck DC/DC regulators. Both the P-channel and synchronous rectifier (N-channel) switches are internal to each buck. The operating frequency is determined by the value of the RT resistor, or is fixed to 2.25MHz by pulling the RT pin to SVIN, or is synchronized to an external oscillator tied to the MODE pin. Users may select pulse skip or Burst Mode operation to trade-off output ripple for efficiency. Independent programmable reference levels allow the LTC3569 to suit a variety of applications. Main Control Loop During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle. The P-channel current ramps up as the inductor charges. The peak inductor current is controlled by the internally compensated error amplifier output, ITH. The current comparator (PCOMP) turns off the P-channel and turns on the N-channel synchronous rectifier when the inductor current reaches the ITH level minus the offset of the slope compensation ramp. The energy stored in the inductor continues to flow through the bottom switch (N-channel) and into the load until either the inductor current approaches zero, or the next clock cycle begins. If the inductor current approaches zero the N compara- The LTC3569 offers different power levels, a single 1.2A buck as well as two 600mA bucks. These three bucks may be configured in different parallel configurations, for versatile high-current operation. The power stage of buck 2 can be configured as a slave to buck 1, by pulling FB2 to SVIN. The power stage of buck 3, can be configured to be a slave to buck 2, by pulling the FB3 pin to SVIN. To enable the slave power stage, pull the respective EN pin high. However if the master is disabled, the slave power stage is Hi-Z. VREF SLOPE + – + BURST CLAMP P COMP SOFT START ILIM ON PVIN SLAVE CLK SD ITH EA EA NOR NAND GATE S Q R SLAVE SLAVE SLEEP VREF ILIM P-LATCH VFB SVIN – MODE FROM MASTER P-CHANNEL SWITCHING LOGIC, BLANKING, ANTI SHOOT-THRU SW N-CHANNEL PON NOFF PGND PGOOD ON SLAVE NCOMP – NOR + 3569 F02 Figure 2. Buck Block Diagram 3569f 10 LTC3569 OPERATION tor (NCOMP) signals to turn-off the N-channel switch, so that is does not discharge the output capacitor. When a rising clock edge occurs, the P-channel switch turns on repeating the cycle. The peak inductor current is controlled by the error amplifier (EA) and is influenced by the slope compensation. The error amplifier compares the FB pin voltage to the programmed internal reference (REF). When the load current increases, the FB voltage decreases. When the FB voltage falls below the reference voltage, the error amplifier output rises to increase the peak inductor current until the average inductor current matches the new load current. With the inductor current equal to the load current, the duty cycle will stabilize to a value equal to VOUT/VIN. Pulse skip mode is intended for lower output voltage ripple at light load currents. Here, the peak P-channel current is compared with the value determined by the error amplifier output. Then, the P-channel is turned off and the N-channel switch is turned on until either the next cycle begins or the N-channel comparator (NCOMP) turns off the N-channel switch. If the NCOMP trips, the SW node goes Hi-Z and the buck operates discontinuously. In pulse skip mode the LTC3569 continues to switch at a constant frequency down to very low currents; where it eventually begins skipping pulses. Because the LTC3569 remains active at lighter load currents in pulse skip mode, the efficiency performance is traded off against output voltage ripple and electromagnetic interference (EMI). Low Current Operation Dropout Operation At light loads, the FB voltage may rise above the reference voltage. If this occurs the error amplifier signals the control loop to go to sleep, and the P-channel turns off immediately. The inductor current then discharges through the N-channel switch until the inductor current approaches zero; whereupon the SW goes Hi-Z, and the output capacitor supplies power to the load. When the load discharges the output capacitor the feedback voltage falls and the error amp wakes up the buck, restarting the main control loop as if a clock cycle has just begun. This sleep cycle helps minimize the switching losses which are dominated by the gate charge losses of the power devices. Two operating modes are available to control the operation of the LTC3569 at low currents, Burst Mode operation and pulse skip mode. When the input supply voltage decreases towards the output voltage the duty cycle automatically increases to 100%; which is the dropout condition. In dropout, the P-channel switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drop across the internal P-channel switch and the inductor. Select Burst Mode operation to optimize efficiency at low output currents. In Burst Mode operation the inductor current reaches a fixed current before the P-channel switch compares inductor current against the value determined by ITH. This burst clamp causes the output voltage to rise above the regulation voltage and forces a longer sleep cycle. This greatly reduces switching losses and average quiescent current at light loads, at the cost of higher ripple voltage. When the FB pin of one of the two 600mA regulators is tied to SVIN that regulator’s control circuits are disabled and the regulator’s switch pin is configured to follow a master regulator; either the first 600mA regulator (regulator 2) or the 1.2A regulator (regulator 1). In this way, two regulator power stages are ganged together (e.g. switch pins shorted together to a single inductor) to support higher current levels. This permits three permutations of power levels: three independent regulators at 1.2A, 600mA and 600mA; Low Supply Operation The LTC3569 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below 2.5V to prevent unstable operation. The UVLO function does not reset the reference voltage DAC. (See Programming the Reference.) Slave Power Stage 3569f 11 LTC3569 OPERATION two independent regulators at 1.2A each, where regulator 3 is placed in slave mode to regulator 2 and regulator 1 operates independently; or one 1.8A regulator and a second 600mA regulator, where regulator 2 is placed in slave mode to regulator 1, and regulator 3 is independent. PGOOD Pin When regulator 2 is operating as a slave, pull pins EN2 and FB2 up to SVIN to enable the slave power stage. Likewise when regulator 3 is operated as a slave, pull pins EN3 and FB3 up to SVIN to enable the slave power stage. If the EN pin of the slave device is pulled low, then the slave power stage is disabled and that SW pin is Hi-Z. The PGOOD pin is an open-drain output that indicates when all of the enabled regulator’s output voltages have risen to within 92% of their programmed levels. The three bucks each have separate PGOOD comparators with hysteresis. The PGOOD flag drops if one of the enabled regulator’s output voltages drops below 88% of the programmed level. Output voltage transient drops of duration less than 2μs are blanked and not reported at the PGOOD pin. The PGOOD pin open-drain driver is disabled if PGOOD is pulled up to a voltage above SVIN. Shutdown And Soft-Start Programming the Reference The main control loop is shut down after pulling the ENx pin to ground and waiting for the tOFF delay period to expire. When in shutdown, but not in slave mode, a 2k resistor to PGND discharges the output capacitor. When all three regulators are turned off the LTC3569 enters low power shutdown where all functions are disabled, and quiescent current drops to below 1μA. The full-scale reference voltage for each regulator is 0.8V. The reference can be programmed in –25mV steps by toggling the respective EN pin up to 15 times for a range from 800mV down to 425mV. This is illustrated in Figure 3. The EN pins require a minimum pulse width of 60ns, but no more than 55μs, as the toggle counter times out after the EN pin remains high for around 125μs (tEN). After the tEN timeout, the counter state is latched and sent on to the reference voltage DAC, and the counter is reset to full-scale. If the EN pin begins to toggle again, the counter decrements on each falling edge. If the EN pin is toggled more than 15 times, the counter remains fixed at the lowest DAC reference level. To reprogram the DAC to full-scale, hold the EN pin low for 170μs (tOFF), turning off the buck, and then pull EN high once. The buck then initiates a softstart as VREF ramps up to the full-scale value. A soft-start is enabled when any buck is initially turned on, or following a thermal shutdown. Soft-start ramps the programmed internal reference at a rate of about 0.75V/ms. The output voltage follows the internal reference voltage ramp throughout the soft-start period. While in soft-start, the LTC3569 is forced into pulse skip mode until the PGOOD flag indicates that the output voltage is nearing the programmed regulation voltage. Once the PGOOD flag has tripped, if the MODE pin is high the regulator then operates in Burst Mode, otherwise the LTC3569 continues to operate in pulse skip mode. Thermal Protection If the die junction temperature exceeds 150°C, a thermal shutdown circuit disables all functions in the LTC3569, and the SW nodes will be pulled low with 2k pull-downs. After the die temperature drops below 125°C the LTC3569 restarts without changing the programmed reference voltage DAC; but a soft-start is initiated upon exiting thermal shutdown. If the DAC is reprogrammed without forcing a shutdown, the soft start ramp is not engaged and the reference steps to the new value. Avoid using the full-scale 0.8V reference in programmable output voltage applications if the application cannot tolerate the transition through shutdown and soft-start when switching between different reference levels. 3569f 12 LTC3569 OPERATION 60ns < WIDTH < 55μs tEN tEN = 125μs (TYP) tOFF 170μs (TYP) tEN EN COUNTER INCREMENTS ON COUNTER RESETS TO FULL-SCALE IF EN FALLING EDGES OF EN STAYS HIGH FOR MORE THAN 125μs VREF COUNTER (15:0) DAC (15:0) 15 15 14 15 13 14 15 13 12 COUNTER RESETS TO FULL-SCALE IF EN STAYS LOW FOR MORE THAN 170μs 14 15 11 10 9 DAC LOADS COUNTER VALUE IF EN STAYS HIGH FOR MORE THAN 125μs 13 15 9 COUNT15 = 800mV COUNT13 = 750mV VREF SHUTDOWN 0mV BUCK OFF COUNT9 = 650mV SOFT-START BUCK ON SOFT-START 0mV BUCK OFF BUCK ON 3569 TD Figure 3. VREF and ENx Timing Diagram 3569f 13 LTC3569 APPLICATIONS INFORMATION Operating Frequency Minimum On-Time And Duty-Cycle Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows for smaller inductor and capacitor values. Operation at lower frequencies improves the efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The maximum usable operating frequency is limited by the minimum on-time and the required duty cycle. In buck regulators, the duty cycle (DC) is the ratio of output to input voltage: DC = VOUT/VIN = tON/(tOFF + tON). At low duty cycles, the SW node is high for a small fraction of the total clock period. As this time period approaches the speed of the gate drive circuits and the comparators internal to the LTC3569, the dynamic loop response suffers. To avoid minimum on-time issues it is recommended to adjust the operating frequency down so as to keep the minimum duty cycle pulse width above 80ns. Thus, the maximum operating frequency should be selected such that the duty cycle does not demand SW pulse widths below the minimum on-time. The maximum clock frequency, fCLKMAX, is selected from either the internal fixed frequency clock, or a timing resistor at the RT pin, or synchronizing clock applied to the MODE pin. The minimum on-time requirement is met by adhering to the following formula: The operating frequency, fCLK, of the LTC3569 is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that charges and discharges an internal timing capacitor within the oscillator. The relationship between oscillator frequency and RT is calculated by the following equation: RT = (5.1855e11)•(fCLK)–1.027 Or may be selected following the graph in Figure 4. 4.1 VIN = 3.6V TA = 25°C 3.6 For example, if VOUT is 0.8V and VIN ranges up to 5.5V, the maximum clock frequency is limited to no more than 1.8MHz. 3.1 fCLK (MHz) fCLKMAX = (VOUT/VIN(MAX))/tMIN-ON 2.6 2.1 Mode Selection And Frequency Synchronization 1.6 1.1 0.6 0.1 0 0.1 0.2 0.4 0.3 RT (MΩ) 0.5 0.6 3569 F04 Figure 4. fCLK vs RT The minimum frequency is limited by leakage and noise coupling due to the large resistance of RT. If the RT pin is tied to SVIN the oscillation frequency is fixed at 2.25MHz. Keep excess capacitance and noise (e.g. from the SW pins) away from the RT pin. It is recommended to remove the GND plane beneath the RT pin trace, and to route the RT pin PCB trace away from the SW pins. The MODE pin is a multi-purpose pin which provides mode selection and frequency synchronization. Connecting this pin to SVIN enables Burst Mode operation, which provides the best low current efficiency at the cost of a higher output voltage ripple. When this pin is connected to ground, pulse skipping operation is selected which provides the lowest output voltage and current ripple at the cost of low current efficiency. Synchronize the LTC3569 to an external clock signal by tying a clock source to the MODE pin. Select the RT pin resistance so that the internal oscillator frequency is set to 20% lower than the applied external clock frequency to ensure adequate slope compensation, since slope compensation is derived from the internal oscillator. During synchronization, the mode is set to pulse skipping. 3569f 14 LTC3569 APPLICATIONS INFORMATION The external clock source applied to the MODE pin requires minimum low and high pulse widths of about 100ns. Setting the Output Voltages The LTC3569 develops independent internal reference voltages for each of the feedback pins. These reference voltages are programmed from 0.8V down to 0.425V in –25mV increments by toggling the appropriate EN pin. The output voltage is set by a resistive divider according to the following formula (refer to Figure 9 for resistor designations): VOUT1 = VREF1(1 + R1/R2), where VREF1 is programmed by toggling the EN1 pin. VOUT2 = VREF2(1 + R3/R4), where VREF2 is programmed by toggling the EN2 pin. VOUT3 = VREF3(1 + R5/R6), where VREF3 is programmed by toggling the EN3 pin. Keeping the current small (<5μA) in these resistors maximizes efficiency, but making the current too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. To improve the frequency response, use a feedforward capacitor, CF, on the order of 20pF across the leading feedback resistor (R1, R3, and R5). Take care to route each FB line away from noise sources, such as the inductor or the SW line. Remove the ground plane from below the FB PCB routes to limit stray capacitance to GND on these pins. Inductor Selection Although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple current. The inductor ripple current ΔIL decreases with higher inductance and increases with higher VIN or VOUT: ΔIL = VOUT/(fCLK •L )•(1–VOUT/VIN) Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. A reasonable starting point for setting ripple current is ΔIL = 0.3•IOUT(MAX), where IOUT(MAX) is the maximum load current. The largest ripple current ΔIL occurs at the maximum input voltage. To guarantee that the ripple current stays below a specified maximum, choose the inductor value according to the following equation: L = VOUT/(fCLK •ΔIL)•(1 – VOUT/VIN(MAX)) The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values increase the burst frequency and reduces efficiency. Choose an inductor with a DC current rating at least 1.5 times larger than the maximum load current to ensure that the inductor core does not saturate during normal operation. If an output short circuit is a possible condition, select an inductor that is rated to handle the maximum peak current specified for the regulators. To maximize efficiency, choose an inductor with a low DC resistance; as power loss in the inductor is due to I2R losses. Where I2 is the square of the average output current and R is the ESR of the inductor. 3569f 15 LTC3569 APPLICATIONS INFORMATION Input/Output Capacitor Selection Use low equivalent series resistance (ESR) ceramic capacitors at the switching regulator outputs as well as at the input supply pins. It is recommended to use only X5R or X7R ceramic capacitors because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. For good transient response and stability the input and output capacitors should retain at least 50% of rated capacitance value over temperature and bias voltage. Check with capacitor data sheets to ensure that bias voltage and temperature derating is taken into account when selecting capacitors. In continuous mode, the input supply current is a square wave of duty cycle VOUT/VIN. The maximum input capacitor ripple current is approximated by: CIN required IRMS ≈ IOUT(MAX)(VOUT(VIN–VOUT))1/2/VIN This formula’s maximum is approximately IRMS=IOUT(MAX)/2. In an output short circuit situation, the input capacitor ripple current is approximately: CIN required IRMS ≈ IPK /√3 Thus, the ripple current in an output short circuit is about 2.5 times larger than for nominal operation. Take care in selecting the input capacitor so as not to exceed the capacitor manufacturer’s specification for self heating due to the ripple current. Two factors influence the selection of the output capacitor. The first is load voltage droop, VDROOP, the second is the output capacitor ESR effect on ripple voltage. Load voltage droops on a load current step, ΔIOUT, where the output capacitor supports the output voltage for typically 2 to 3 clock cycles until the inductor current charges up to the load step current level. A good estimate of output capacitor value required to maintain a droop of less than VDROOP is given by: The second factor that influences the selection of the output capacitor is the effect of output capacitor ESR on the output voltage ripple as a result of the inductor ripple current. The amplitude of voltage ripple, ΔVOUT, is determined by: ΔVOUT ≈ ΔIL(ESR + 1/(8•fCLK •COUT)) Where ΔIL is the ripple current in the inductor, and ESR is the equivalent series resistance of the output capacitor. Using ceramic capacitors, this voltage ripple is usually negligible. Printed Circuit Board Layout Considerations There are three main considerations to take into account while designing a PCB layout for the LTC3569. The first consideration is regarding switching noise coupling onto the FB pin traces and the RT pin trace, or causing radiated electromagnetic induction (EMI). The noise is mitigated by placing the inductors and input decoupling capacitors as close as possible to the LTC3569. Furthermore, careful placement of a contiguous ground plane directly under the high-frequency switching node traces of the LTC3569 mitigates EMI; since high-frequency eddy currents follow the ground plane in loops. The larger the area of the current return loops the larger EMI that is radiated. Placing input decoupling capacitors close to the corresponding PVIN/PGND pins directly reduces the area (and therefore the inductance) of ground returns. Also, place a group of vias directly under the grounded backside of the package leading to an internal ground plane. Place the ground plane on the second layer of the PCB to minimize parasitic inductance. The second consideration is stray capacitance on the FB pin traces and the RT pin trace to GND. This is taken into account by cutting the ground plane beneath these traces. However, wherever the ground plane is cut, add additional decoupling capacitors across the break to provide a path for high-frequency ground return currents to flow. COUT ≈ 2.5•ΔIOUT/(fCLK •VDROOP) 3569f 16 LTC3569 APPLICATIONS INFORMATION Finally, the third consideration is stray impedance between the SW node and the inductor when operating with a slave power stage. It is important to keep the stray inductance of the slave power device to a minimum, by keeping the trace from slave SW to the main SW as short as possible. This requirement is necessary to ensure that the slave power device’s share of the inductor current does not exceed that of the master as well as to keep the current density in the slave device under control. The inductor should be placed close to the master SW pin to minimize stray impedance and allow the master to control the inductor current. Thermal Considerations In the majority of applications, the LTC3569 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3569 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, the LTC3569 will be turned off and 2k resistive pull-downs are tied to all the SW nodes. To prevent the LTC3569 from exceeding maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. Temperature rise is: tRISE = PD •θJA Where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = tRISE + TA. Where TA is the ambient temperature. As an example, consider the case when the LTC3569 is in dropout at an input voltage of 2.7V with load currents of 1000mA, 500mA and 500mA for bucks 1, 2 and 3 respectively, at an ambient temperature of 85°C. From the Typical Performance Characteristics, the RDS(ON) of buck1 is 0.190Ω, and for buck2 and buck3 it is 0.265Ω. Therefore, power dissipated by the LTC3569 is: PD = I12 RDS(ON)1 + I22 RDS(ON)2 + I32 RDS(ON)3 = 190mV + 66.25mW + 66.25mV = 322.5mW At 85°C ambient the junction temperature is: TJ = 322.5mW•68°C/W + 85°C = 106.9°C. This junction temperature is below the absolute maximum junction temperature of 125°C. Design Example 1: 2.5V, 1.8V and 1.2V From a Li-Ion Battery As a design example, consider using the LTC3569 in a portable application with a Li-Ion battery source. The battery provides an SVIN from 2.9V to 4.2V. The loads require 2.5V, 1.8V and 1.2V with current requirements of up to 800mA, 400mA and 400mA respectively when active. The first load, with the 2.5V rail has no standby requirements, however loads 2 and 3 each require a current of 1mA in standby. Since two of the loads require low current operation, Burst Mode operation is selected. With VIN(MAX) at 4.2V and VOUT(MIN) = 1.2V, the maximum clock frequency is 3.57MHz based on minimum on-time requirements. To simplify the board layout, the fixed 2.25MHz internal frequency is selected. 3569f 17 LTC3569 APPLICATIONS INFORMATION Selecting The Inductors The output capacitor values are calculated as: Calculating the inductor values for 30% ripple current at maximum SVIN: COUT1 = 2.5•800mA/(2.25MHz•125mV) = 7.1μF COUT2 = 2.5•400mA/(2.25MHz•90mV) = 4.9μF L1 = 2.5V/(2.25MHz •240mA)•(1–2.5V/4.2V)= 1.9μH L2 = 1.8V/(2.25MHz •120mA)•(1–1.8V/4.2V)= 3.8μH L3 = 1.2V/(2.25MHz •120mA)•(1–1.2V/4.2V)= 3.1μH COUT3 = 2.5•400mA/(2.25MHz•60mV) = 7.4μF Choosing the closest standard values gives, COUT1 = 10μF, COUT2 = 4.7μF and COUT3 = 10μF. Choosing a vendor’s closest values gives L1 = 2.2μH, L2 = L3 = 3.3μH. These values result in the maximum ripple currents of: A 22μF input capacitor is selected since the Li-Ion battery has sufficiently low output impedance. ΔIL1 = 2.5V/(2.25MHz•2.2μH)•(1–2.5V/4.2V) = 204mA Setting The Output Voltages ΔIL2 = 1.8V/(2.25MHz•3.3μH)•(1–1.8V/4.2V) = 139mA ΔIL3 = 1.2V/(2.25MHz•3.3μH)•(1–1.2V/4.2V) = 115mA Without toggling the EN pins the LTC3569 develops a 0.8V reference voltage for each of the feedback pins. The output voltages are set by a resistive divider as follows: VOUT = 0.8•(1 + R2/R1) Selecting The Output Capacitors The value of the output capacitors are calculated based on a 5% load droop for maximum load current step. The output droop is usually about 2.5 times the linear drop of the first cycle and is estimated based on the following formula: The resistors in Figure 5 are selected as the nearest 1% standard resistor values. To improve frequency response feedforward capacitors of 10pF and 20pF are used. COUT = 2.5•IOUT(MAX)/(fCLK •VDROOP) VIN 2.9V TO 4.2V 2.2μH 22μF SVIN PVIN OUT1 2.5V AT 800mA SW1 243k EN1 EN3 Design Example 1: Burst Mode Operation 10μF 100 FB1 VIN = 2.9V TO 4.2V 115k LTC3569 90 3.3μH OUT2 1.8V AT 400mA SW2 RT 187k MODE 20pF 4.7μF FB2 470k 150k PGOOD 3.3μH OUT3 1.2V AT 400mA SW3 187k 20pF PGND 80 70 60 BUCK1 = 2.5V BUCK2 = 1.8V BUCK3 = 1.2V 10μF FB3 SGND EFFICIENCY (%) EN2 10pF 50 0.1 374k 1 3569 F05a 10 100 ILOAD (mA) 1000 10000 3569 F05b Figure 5. Triple Buck DC/DC Regulators: 800mA, 400mA, 400mA 3569f 18 LTC3569 APPLICATIONS INFORMATION Calculating the value of the output capacitors: Design Example 2: Dual Bucks, 1.8V at 1.8A and 1.5V at 600mA COUT1 = 2.5•1800mA/(2.25MHz•90mV) = 22μF For this example, the LTC3569 is configured to deliver two fixed voltages of 1.8V and 1.5V from a generic supply over the full operating range, 2.5V to 5.5V. The load requirements range from <1mA in standby mode up to 1.8A for the 1.8V supply and 600mA for the 1.5V supply. An input capacitor of 22μF is selected to support the maximum ripple current of 1.2A. An additional 0.1μF low ESR capacitor is placed between SVIN and SGND. The fixed internal clock frequency of 2.25MHz meets the minimum on-time requirements. Burst Mode operation is selected for high efficiency at the low standby current level. Calculating the inductor values for 30% ripple current at max SVIN: The resistor values shown in Figure 6 are selected as the closest standard 1% resistors to obtain the correct output voltages with the full-scale reference voltages of 0.8V. And 20pF feedforward capacitors are placed across the leading feedback resistors. COUT2 = 2.5•600mA/(2.25MHz•75mV) = 8.9μF L1 = 1.8V/(2.25MHz•540mA)•(1–1.8V/5.5V) = 1.0μH L2 = 1.5V/(2.25MHz•180mA)•(1–1.5V/5.5V) = 2.2μH VIN 2.5V TO 5.5V 1μH PVIN 22μF 187k SW2 EN1 EN2 EN3 22μF 150k FB2 VIN 2.2μH 511k OUT3 1.5V AT 600mA SW3 PGOOD 174k SVIN 20pF 10μF FB3 200k SGND Design Example 2: 1.8A Load Step on Buck1 with Buck2 Slave, Burst Mode Operation CH1 SW1/2 2V/DIV CH3 VOUT1 336mVP-P LTC3569 RT 0.1μF 20pF FB1 MODE VIN OUT1 1.8V AT 1.8A SW1 200mV/DIV CH2 ILOAD 1.8A 1A/DIV CH4 IL1 1.94A 1A/DIV 10μs/DIV PGND 3569 F06b 3569 F06a Figure 6. Dual Buck DC/DC Regulators: 1.8V at 1800mA, and 1.5V at 600mA 3569f 19 LTC3569 APPLICATIONS INFORMATION Design Example 3: Dual Programmable Bucks In this example consider two buck regulators operating from a 2.5V to 5.5V unregulated supply that are required to generate two independently programmable supplies that must step from 1.2V in standby up to 1.8V when active, with a maximum load current of 1.2A when active and 1mA in standby. Additionally, this application anticipates possible output short circuits, and is required to operate without damage in such a situation. Buck 1 is selected for the first regulator, and buck 3 is configured as a slave power stage in parallel with buck 2 by pulling FB3 up to VIN to obtain the required current level for the second regulator. Burst Mode operation is selected to achieve high efficiency during standby operation. The internal 2.25MHz clock frequency is selected, as it satisfies the minimum on-time requirement. Next, two reference voltages are selected to match the ratio of the active to standby voltages: 1.8V/1.2V = 1.5. The 0.75V and 0.5V reference levels mach this ratio. The resistors shown in Figure 7 are selected to obtain the correct feedback ratio from standard 1% resistors. Calculating the inductor values for 30% ripple current at maximum SVIN: L = 1.8V/(2.25MHz•360mA)•(1–1.8V/5.5V)= 1.5μH. The output capacitor values are selected as the nearest standard value to obtain 5% voltage droop at maximum load current step. COUT = 2.5•1200mA/(2.25MHz•90mV) ≈ 15μF. Select an output capacitor with an ESR of less than 50mΩ to obtain an output voltage ripple of less than 30mV. Finally select an input capacitor rated for the worst-case short-circuit ripple current of 2 IPK /√3 ≈ 2.5A, when both outputs are shorted to GND. VIN 2.5V TO 5.5V Design Example 3: Soft-Start to Standby (1.2V) 1.5μH 22μF SVIN PVIN SW1 EN1 FB1 294k DIGITAL CONTROL EN2 VIN EN3 20pF OUT1 1200mA 1.2V STANDBY 15μF 1.8V ACTIVE 500mV/DIV 500mV/DIV 210k LTC3569 1.5μH MODE SW2 RT SW3 294k 20pF OUT2 1200mA 1.2V STANDBY 15μF 1.8V ACTIVE FB2 511k 210k PGOOD FB3 SGND PGND VIN CH1 OUT1 CH2 OUT2 CH3 PGOOD CH4 EN1 = EN2 2V/DIV 2V/DIV 200μs/DIV 3569 F07b 3569 F07a Figure 7. Dual Programmable Buck DC/DC Regulators: 1200mA, 1200mA 3569f 20 LTC3569 APPLICATIONS INFORMATION Design Example 4: Dual Programmable Bucks In this example consider two buck regulators operating from a 2.5V to 5.5V unregulated supply that are required to generate two independently programmable supplies that must step from 1.2V in standby up to 1.6V when active, with a maximum load current of 0.8A when active and 1mA in standby. Furthermore, when switching between active and standby, the load voltage should not droop. Buck 1 is selected for the first regulator, and buck 3 is configured as a slave power stage in parallel with buck 2 by pulling FB3 up to VIN to obtain the required current level for the second regulator. Burst Mode operation is selected to achieve high efficiency during standby operation. The internal 2.25MHz clock frequency is selected, as it satisfies the minimum on-time requirement. Next, two reference voltages are selected to match the ratio of the active to standby voltages: 1.6V/1.2V = 1.3333. There are three reference value ratios that match this ratio: 0.8V and 0.6V, 0.7V and 0.525V, and 0.6V and 0.45V. As the load cannot tolerate a voltage droop when switching from standby to active, the 0.7V and 0.525V references are selected to match the ratio of output voltages. With this ratio, the buck does not need to be shutdown as it would if the full scale 0.8V reference level was chosen. The resistors shown in Figure 8 are selected to obtain the nearest feedback ratio from standard 1% resistors. Calculating the inductor values for 30% ripple current at maximum SVIN: L = 1.6V/(2.25MHz•240mA)•(1–1.6V/5.5V) ≈ 2.2μH. The output capacitor values are selected as the nearest standard value to obtain 5% voltage droop at maximum load current step. COUT = 2.5•800mA/(2.25MHz•90mV) ≈ 10μF. Select an output capacitor with an ESR of less than 50mΩ to obtain an output voltage ripple of less than 30mV. Finally select an input capacitor rated for the worst-case short-circuit ripple current of 2 IPK /√3 ≈ 2.5A, when both outputs are shorted to GND. Design Example 4: Dual 1A Bucks VOUT = 1.6V, Burst Mode Operation VIN 2.5V TO 5.5V 2.2μH 22μF SVIN PVIN SW1 EN1 FB1 210k EN2 VIN EN3 20pF 100 90 162k LTC3569 2.2μH MODE SW2 RT SW3 210k 20pF OUT2 800mA 1.2V STANDBY 10μF 1.6V ACTIVE FB2 511k VIN = 2.5V 80 VIN = 5.5V 70 60 162k PGOOD FB3 SGND EFFICIENCY (%) DIGITAL CONTROL OUT1 800mA 1.2V STANDBY 10μF 1.6V ACTIVE PGND 50 VIN 3569 F08 40 0.1 BUCK 1 BUCK 2, 3 1 10 100 ILOAD (mA) 1000 10000 3569 F08b Figure 8. Dual Programmable Buck DC/DC Regulators 3569f 21 LTC3569 PACKAGE DESCRIPTION UD Package 20-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1720 Rev A) 0.70 ±0.05 3.50 ± 0.05 (4 SIDES) 1.65 ± 0.05 2.10 ± 0.05 PACKAGE OUTLINE 0.20 ±0.05 0.40 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 0.75 ± 0.05 R = 0.05 TYP PIN 1 TOP MARK (NOTE 6) PIN 1 NOTCH R = 0.20 TYP OR 0.25 × 45° CHAMFER 19 20 0.40 ± 0.10 1 2 1.65 ± 0.10 (4-SIDES) (UD20) QFN 0306 REV A 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.20 ± 0.05 0.40 BSC 3569f 22 LTC3569 PACKAGE DESCRIPTION FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BB 4.90 – 5.10* (.193 – .201) 3.58 (.141) 3.58 (.141) 16 1514 13 12 1110 6.60 ±0.10 9 2.94 (.116) 4.50 ±0.10 2.94 6.40 (.116) (.252) BSC SEE NOTE 4 0.45 ±0.05 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 0.25 REF 1.10 (.0433) MAX 0° – 8° 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE16 (BB) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3569f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC3569 TYPICAL APPLICATION VIN 2.2μH 22μF SVIN PVIN SW1 EN1 FB1 OUT1 1200mA R1 DIGITAL CONTROL EN2 EN3 20pF 10μF R2 LTC3569 2.2μH OUT2 600mA SW2 MODE R3 RT 20pF 4.7μF FB2 511k R4 PGOOD 2.2μH OUT3 600mA SW3 R5 20pF 4.7μF FB3 SGND PGND R6 3569 TA02 Figure 9. Triple Programmable Buck DC/DC Regulators RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3406A/ LTC3406AB 600mA, 1.5MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA, ISD <1μA, ThinSOT™ Package LTC3407A/ LTC3407A-2 Dual 600mA/600mA 1.5MHz, Synchronous Step-Down DC/DC 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD <1μA, MS10E, 3mm × 3mm DFN-10 Package Converter LTC3411A 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD <1μA, MS10, 3mm × 3mm DFN-10 Package LTC3412A 2.5A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD <1μA, 4mm × 4mm QFN-16, TSSOP-16E Package LTC3417A-2 Dual 1.5A/1A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.3V to 5.5V, VOUT(MIN) = 0.8V, IQ = 125μA, ISD <1μA, TSSOP-16E, 3mm × 5mm DFN-16 Package LTC3419/LTC3419-1 Dual 600mA/600mA 2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 35μA, ISD <1μA, MS10, 3mm × 3mm DFN-10 Package LTC3544/LTC3544B Quad 100mA/200mA/200mA/300mA, 2.25MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.3V to 5.5V, VOUT(MIN) = 0.8V, IQ = 70μA, ISD <1μA, 3mm × 3mm QFN-16 Package LTC3545/LTC3545-1 Triple, 800mA × 3, 2.25MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.3V to 5.5V, VOUT(MIN) = 0.6V, IQ = 58μA, ISD <1μA, 3mm × 3mm QFN-16 Package LTC3547/LTC3547B Dual 300mA, 2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD <1μA, DFN-8 Package LTC3548/LTC3548-1/ Dual 400mA and 800mA IOUT, 2.25MHz, Synchronous StepDown DC/DC Converter LTC3548-2 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD <1μA, MS10E, 3mm × 3mm DFN-10 Package LTC3561 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 240μA, ISD <1μA, 3mm × 3mm DFN-8 Package LTC3562 Quad, I2C Interface, 600mA/600mA/400mA/400mA, 2.25MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.9V to 5.5V, VOUT(MIN) = 0.425V, IQ = 100μA, ISD <1μA, 3mm × 3mm QFN-20 Package ThinSOT is a trademark of Linear Technology Corporation. 3569f 24 Linear Technology Corporation LT 0109 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009