CY7C1370DV25 CY7C1372DV25 PRELIMINARY 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x 36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370DV25 and CY7C1372DV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370DV25 and CY7C1372DV25 are pin-compatible and functionally equivalent to ZBT devices. • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200, and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • Single 2.5V power supply • 2.5V I/O power supply All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 3.0 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Clock Enable (CEN) pin to suspend operation Write operations are controlled by the Byte Write Selects (BWa–BWd for CY7C1370DV25 and BWa–BWb for CY7C1372DV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. • Synchronous self-timed writes • Available in lead-free 100 TQFP, 119 BGA, and 165 fBGA packages Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. • IEEE 1149.1 JTAG Boundary Scan • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option Logic Block Diagram-CY7C1370DV25 (512K x 36) A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 S E N S E ADV/LD BWa BWb BWc BWd WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY A M P S WE O U T P U T R E G I S T E R S E INPUT REGISTER 1 OE CE1 CE2 CE3 ZZ Cypress Semiconductor Corporation Document #: 38-05558 Rev. *A E O U T P U T D A T A S T E E R I N G INPUT REGISTER 0 B U F F E R S DQs DQPa DQPb DQPc DQPd E E READ LOGIC SLEEP CONTROL • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 9, 2004 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Logic Block Diagram-CY7C1372DV25 (1M x 18) A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD BWa WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY BWb S E N S E A M P S WE O U T P U T R E G I S T E R S O U T P U T D A T A B U F F E R S S T E E R I N G E INPUT REGISTER 1 E OE CE1 CE2 CE3 ZZ DQs DQPa DQPb E INPUT REGISTER 0 E READ LOGIC Sleep Control Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current CY7C1370DV25-250 CY7C1372DV25-250 CY7C1370DV25-200 CY7C1372DV25-200 CY7C1370DV25-167 CY7C1372DV25-167 Unit 2.6 350 70 3.0 300 70 3.4 275 70 ns mA mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05558 Rev. *A Page 2 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPb DQb DQb VDDQ VSS NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ CY7C1372DV25 (1M × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-05558 Rev. *A A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A A A A A A A E(36) E(72) VSS VDD E(288) E(144) A A A A A A A E(36) E(72) VSS VDD 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQb DQb DQb DQb VSS VDDQ DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb NC DQa VSS VSS VDDQ VDDQ NC DQa DQa NC DQPa NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 CY7C1370DV25 (512K × 36) E(288) E(144) DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS DQc DQc DQc DQc VSS VDDQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 DQPc DQc DQc VDDQ A A A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A 100-pin TQFP Packages Page 3 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Pin Configurations (continued) 119-ball BGA Pinout CY7C1370DV25 (512K × 36) – BGA 1 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B C D E F G H J K L M N P NC NC DQc CE2 A DQPc A A VSS ADV/LD VDD NC A A VSS CE3 A DQPb NC NC DQb DQc DQc VSS CE1 VSS DQb DQb VDDQ DQc VSS DQb VDDQ DQc BWb DQb DQb DQc VDDQ DQc VDD BWc VSS NC OE A VSS DQc WE VDD VSS NC DQb VDD DQb VDDQ DQd DQd DQd DQd CLK NC VSS BWd BWa DQa DQa DQa DQa VDDQ DQd VSS DQa VDDQ DQd VSS CEN A1 VSS DQd VSS DQa DQa DQd DQPd VSS A0 VSS DQPa DQa NC A MODE VDD NC E(72) A A NC A A NC E(36) ZZ VDDQ TMS TDI TCK TDO NC VDDQ R T U VSS CY7C1372DV25 (1M x 18) – BGA A B C D E F G H J K L M N P R T U Document #: 38-05558 Rev. *A 1 2 3 4 5 6 7 VDDQ A A A A A VDDQ NC CE2 A A NC A VSS ADV/LD VDD NC A NC DQb A VSS CE3 A DQPa NC NC CE1 VSS NC DQa OE A VSS DQa VDDQ NC VSS NC NC DQa VDD DQa NC VDDQ DQa NC DQb VSS VDDQ NC VSS NC DQb VDDQ DQb NC VDD BWb VSS NC WE VDD NC NC DQb VSS CLK VSS NC DQb NC NC NC DQa NC VDDQ DQb VSS NC VDDQ DQb NC VSS CEN A1 BWa VSS VSS DQa NC NC DQPb VSS A0 VSS NC DQa NC NC A MODE VDD NC A E(72) A A E(36) A A ZZ VDDQ TMS TDI TCK TDO NC VDDQ Page 4 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Pin Configurations (continued) 165-Ball fBGA Pinout CY7C1370DV25 (512K × 36) – fBGA 4 5 6 7 1 2 3 A B C D E F G H J K L M N P E(288) A CE1 BWc BWb CE3 BWd VSS VDD BWa VSS R NC A CE2 DQPc DQc NC DQc VDDQ VDDQ 8 9 10 11 ADV/LD A A NC CLK CEN WE OE A A E(144) VSS VSS VSS VDD VDDQ VSS VSS VSS VDDQ NC DQb DQPb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc NC DQd DQc NC DQd VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQb NC DQa DQb ZZ DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQPd DQd NC VDDQ VDDQ VDD VSS VSS NC VSS NC VSS NC VDD VSS VDDQ VDDQ DQa NC DQa DQPa NC E(72) A A TDI A1 TDO A A A NC MODE E(36) A A TMS A0 TCK A A A A 8 9 10 11 A A A CY7C1372DV25 (1M × 18) – fBGA 1 2 3 4 5 6 A B C D E F G H J K L M N P E(288) A CE1 BWb NC CE3 CEN ADV/LD NC BWa CLK VSS VDD VSS VSS VSS VSS WE VSS VSS OE VSS R NC A CE2 NC NC NC DQb VDDQ VDDQ 7 A A E(144) VDD VDDQ VDDQ NC NC DQPa DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC NC DQb DQb NC NC VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQa DQa ZZ NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb DQPb NC NC VDDQ VDDQ VDD VSS VSS NC VSS NC VSS NC VDD VSS VDDQ VDDQ DQa NC NC NC NC E(72) A A TDI A1 TDO A A A NC MODE E(36) A A TMS A0 TCK A A A A Document #: 38-05558 Rev. *A Page 5 of 30 PRELIMINARY CY7C1370DV25 CY7C1372DV25 Pin Definitions I/O Type Pin Description A0 A1 A Pin Name InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. BWa BWb BWc BWd InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd. WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputAsynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQS I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX I/OSynchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQs. During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd. MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. TDO JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Synchronous TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. Synchronous TMS Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous TCK VDD VDDQ JTAG-Clock Power Supply Clock input to the JTAG circuitry. Power supply inputs to the core of the device. I/O Power Supply Power supply for the I/O circuitry. Document #: 38-05558 Rev. *A Page 6 of 30 PRELIMINARY CY7C1370DV25 CY7C1372DV25 Pin Definitions (continued) Pin Name I/O Type VSS NC E(36,72, 144, 288) Ground – – ZZ InputAsynchronous Pin Description Ground for the device. Should be connected to ground of the system. No connects. This pin is not connected to the die. These pins are not connected. They will be used for expansion to the 36M, 72M, 144M and 288M densities. ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to VSS or left floating. Introduction Functional Overview The CY7C1370DV25 and CY7C1372DV25 are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BWX can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one Document #: 38-05558 Rev. *A of the chip enable signals, its output will three-state following the next clock rise. Burst Read Accesses The CY7C1370DV25 and CY7C1372DV25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented is loaded into the Address Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b for CY7C1372DV25). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 & DQa,b/DQPa,b for CY7C1372DV25) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the write operation is controlled by BW (BWa,b,c,d for CY7C1370DV25 and BWa,b for CY7C1372DV25) signals. The CY7C1370DV25/CY7C1372DV25 provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly Page 7 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1370DV25 and CY7C1372DV25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b for CY7C1372DV25) inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/ DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b for CY7C1372DV25) are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1370DV25/CY7C1372DV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d for CY7C1370DV25 and BWa,b for CY7C1372DV25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address Second Address Third Address Fourth Address A1,A0 A1,A0 A1,A0 A1,A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address Second Address Third Address Fourth Address A1,A0 A1,A0 A1,A0 A1,A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit IDDZZ Sleep mode standby current ZZ > VDD − 0.2V 80 mA tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ active to sleep current This parameter is sampled tRZZI ZZ Inactive to exit sleep current This parameter is sampled Document #: 38-05558 Rev. *A 2tCYC ns 2tCYC 0 ns ns Page 8 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Truth Table[1, 2, 3, 4, 5, 6, 7] Operation Address Used CE ZZ ADV/LD WE BWx OE CEN CLK X X X L L-H DQ Deselect Cycle None H L L Three-State Continue Deselect Cycle None X L H X X X L L-H Three-State Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q) Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q) NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Three-State Dummy Read (Continue Burst) Next X L H X X H L L-H Three-State Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D) Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D) NOP/Write Abort (Begin Burst) None L L L L H X L L-H Three-State Write Abort (Continue Burst) Next X L H X H X L L-H Three-State Ignore Clock Edge (Stall) Current X L X X X X H L-H – Sleep Mode None X H X X X X X X Three-State Notes: 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWX. See Write Cycle Description table for details. 3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Three-state when OE is inactive or when the device is deselected, and DQs = data when OE is active. 8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05558 Rev. *A Page 9 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Partial Write Cycle Description[1, 2, 3, 8] Function (CY7C1370DV25) WE BWd BWc BWb BWa Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQa and DQPa) L H H H L Write Byte b – (DQb and DQPb) L H H L H Write Bytes b, a L H H L L Write Byte c – (DQc and DQPc) L H L H H Write Bytes c, a L H L H L Write Bytes c, b L H L L H Write Bytes c, b, a L H L L L Write Byte d – (DQd and DQPd) L L H H H Write Bytes d, a L L H H L Write Bytes d, b L L H L H Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L L WE BWb BWa Read H x x Write – No Bytes Written L H H Function (CY7C1372DV25) Write Byte a – (DQa and DQPa) L H L Write Byte b – (DQb and DQPb) L L H Write Both Bytes L L L IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1370DV25/CY7C1372DV25 incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V I/O logic levels. Document #: 38-05558 Rev. *A The CY7C1370DV25/CY7C1372DV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Page 10 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY TAP Controller State Diagram 1 TAP Controller Block Diagram TEST-LOGIC RESET 0 Bypass Register 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 1 2 1 0 0 1 CAPTURE-DR TDI CAPTURE-IR Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 0 Selection Circuitry TDO 0 Identification Register SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 Boundary Scan Register 1 0 PAUSE-DR 0 PAUSE-IR 1 0 TCK 1 EXIT2-DR 0 EXIT2-IR 1 TMS TAP CONTROLLER 1 UPDATE-DR 1 x . . . . . 2 1 0 1 EXIT1-DR 0 0 0 UPDATE-IR 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. Test Access Port (TAP) At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. Test Clock (TCK) TAP Registers The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see figure. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR Document #: 38-05558 Rev. *A Page 11 of 30 PRELIMINARY state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. CY7C1370DV25 CY7C1372DV25 the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. IDCODE Reserved The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 38-05558 Rev. *A Page 12 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY TAP Timing 1 2 3 Test Clock (TCK) t TH t TMSS t TMSH t TDIS t TDIH t TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[9, 10] Parameter Description Min. Max. Unit 20 MHz Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 25 ns tTL TCK Clock LOW time 25 ns 50 ns Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 5 ns 0 ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise 5 ns tTDIS TDI Set-up to TCK Clock Rise 5 ns tCS Capture Set-up to TCK Rise 5 Hold Times tTMSH TMS hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Notes: 9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document #: 38-05558 Rev. *A Page 13 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY 2.5V TAP AC Test Conditions 2.5V TAP AC Output Load Equivalent 1.25V Input pulse levels ............................................... .VSS to 2.5V Input rise and fall time..................................................... 1 ns 50Ω Input timing reference levels .........................................1.25V Output reference levels.................................................1.25V TDO Test load termination supply voltage.............................1.25V Z O= 50Ω 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[11] Parameter Description Test Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5V 2.0 V VOH2 Output HIGH Voltage IOH = –100 µA, VDDQ = 2.5V 2.1 V VOL1 Output LOW Voltage IOL = 8.0 mA, VDDQ = 2.5V IOL = 100 µA V VOL2 Output LOW Voltage 0.2 V VIH Input HIGH Voltage VDDQ = 2.5V 1.7 VDD + 0.3 V VIL Input LOW Voltage VDDQ = 2.5V –0.3 0.7 V IX Input Load Current –5 5 µA GND < VIN < VDDQ VDDQ = 2.5V 0.4 Note: 11.All voltages referenced to VSS (GND). Document #: 38-05558 Rev. *A Page 14 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Identification Register Definitions Instruction Field CY7C1370DV25 CY7C1372DV25 Description Revision Number (31:29) 000 000 Cypress Device ID (28:12) 01011001000100101 01011001000010101 Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 Indicate the presence of an ID register. Reserved for version number. Reserved for future use. Scan Register Sizes Bit Size (x18) Bit Size (x36) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 85 85 Boundary Scan Order (165-ball fBGA package) 89 89 Register Name Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05558 Rev. *A Page 15 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY 119-ball BGA Boundary Scan[12, 13] CY7C1370DV25 (1M x 36) Bit # Ball ID Bit # CY7C1370DV25 (1M x 36) Ball ID Bit # Ball ID 1 H4 37 B6 73 N2 2 T4 38 D4 74 P2 3 T5 39 B4 75 R3 4 T6 40 F4 76 T1 5 R5 41 M4 77 R1 6 L5 42 A5 78 T2 7 R6 43 K4 79 L3 8 U6 44 E4 80 R2 9 R7 45 G4 81 T3 10 T7 46 A4 82 L4 11 P6 47 G3 83 N4 12 N7 48 C3 84 P4 13 M6 49 B2 85 Internal 14 L7 50 B3 15 K6 51 A3 16 P7 52 C2 17 N6 53 A2 18 L6 54 B1 19 K7 55 C1 20 J5 56 D2 21 H6 57 E1 22 G7 58 F2 23 F6 59 G1 24 E7 60 H2 25 D7 61 D1 26 H7 62 E2 27 G6 63 G2 28 E6 64 H1 29 D6 65 J3 30 C7 66 2K 31 B7 67 L1 32 C6 68 M2 33 A6 69 N1 34 C5 70 P1 35 B5 71 K1 36 G5 72 L2 Notes: 12. Balls which are NC (No Connect) are pre-set LOW 13. Bit# 85 is pre-set HIGH Document #: 38-05558 Rev. *A Page 16 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY 119-ball BGA Boundary Scan Order[12, 13] CY7C1372DV25 (2M x 18) Bit # Ball ID Bit # CY7C1372DV25 (2M x 18) Ball ID Bit # Ball ID 1 H4 37 B6 73 N2 2 T4 38 D4 74 P2 3 T5 39 B4 75 R3 4 T6 40 F4 76 T1 5 R5 41 M4 77 R1 6 L5 42 A5 78 T2 7 R6 43 K4 79 L3 8 U6 44 E4 80 R2 9 R7 45 G4 81 T3 10 T7 46 A4 82 L4 11 P6 47 G3 83 N4 12 N7 48 C3 84 P4 13 M6 49 B2 85 Internal 14 L7 50 B3 15 K6 51 A3 16 P7 52 C2 17 N6 53 A2 18 L6 54 B1 19 K7 55 C1 20 J5 56 D2 21 H6 57 E1 22 G7 58 F2 23 F6 59 G1 24 E7 60 H2 25 D7 61 D1 26 H7 62 E2 27 G6 63 G2 28 E6 64 H1 29 D6 65 J3 30 C7 66 2K 31 B7 67 L1 32 C6 68 M2 33 A6 69 N1 34 C5 70 P1 35 B5 71 K1 36 G5 72 L2 Document #: 38-05558 Rev. *A Page 17 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY 165-ball fBGA Boundary Scan Order[12, 14] CY7C1370DV25 (1M x 36) CY7C1370DV25 (1M x 36) Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 37 A9 73 K2 2 N7 38 B9 74 L2 3 10N 39 C10 75 M2 4 P11 40 A8 76 N1 5 P8 41 B8 77 N2 6 R8 42 A7 78 P1 7 R9 43 B7 79 R1 8 P9 44 B6 80 R2 9 P10 45 A6 81 P3 10 R10 46 B5 82 R3 11 R11 47 A5 83 P2 12 H11 48 A4 84 R4 13 N11 49 B4 85 P4 14 M11 50 B3 86 N5 15 L11 51 A3 87 P6 16 K11 52 A2 88 R6 89 Internal 17 J11 53 B2 18 M10 54 C2 19 L10 55 B1 20 K10 56 A1 21 J10 57 C1 22 H9 58 D1 23 H10 59 E1 24 G11 60 F1 25 F11 61 G1 26 E11 62 D2 27 D11 63 E2 28 G10 64 F2 29 F10 65 G2 30 E10 66 H1 31 D10 67 H3 32 C11 68 J1 33 A11 69 K1 34 B11 70 L1 35 A10 71 M1 36 B10 72 J2 Note: 14. Bit# 89 is Pre-Set HIGH Document #: 38-05558 Rev. *A Page 18 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY 165-ball fBGA Boundary Scan Order[12, 14] CY7C1372DV25 (2M x 18) CY7C1372DV25 (2M x 18) Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 37 A9 73 K2 2 N7 38 B9 74 L2 3 10N 39 C10 75 M2 4 P11 40 A8 76 N1 5 P8 41 B8 77 N2 6 R8 42 A7 78 P1 7 R9 43 B7 79 R1 8 P9 44 B6 80 R2 9 P10 45 A6 81 P3 10 R10 46 B5 82 R3 11 R11 47 A5 83 P2 12 H11 48 A4 84 R4 13 N11 49 B4 85 P4 14 M11 50 B3 86 N5 15 L11 51 A3 87 P6 16 K11 52 A2 88 R6 89 Internal 17 J11 53 B2 18 M10 54 C2 19 L10 55 B1 20 K10 56 A1 21 J10 57 C1 22 H9 58 D1 23 H10 59 E1 24 G11 60 F1 25 F11 61 G1 26 E11 62 D2 27 D11 63 E2 28 G10 64 F2 29 F10 65 G2 30 E10 66 H1 31 D10 67 H3 32 C11 68 J1 33 A11 69 K1 34 B11 70 L1 35 A10 71 M1 36 B10 72 J2 Document #: 38-05558 Rev. *A Page 19 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V DC to Outputs in Tri-State ................... –0.5V to VDDQ + 0.5V DC Input Voltage....................................–0.5V to VDD + 0.5V Range Commercial Industrial Ambient Temperature VDD/VDDQ 0°C to +70°C 2.5V + _ 5% –40°C to +85°C Electrical Characteristics Over the Operating Range[15, 16] Parameter Description Test Conditions Min. Max. Unit VDD Power Supply Voltage 2.375 2.625 V VDDQ I/O Supply Voltage 2.375 VDD V VOH Output HIGH Voltage VDD = Min., IOH = −1.0 mA VOL Output LOW Voltage VDD = Min., IOL= 1.0 mA 2.0 V 0.4 V VIH Input HIGH Voltage[17] VDDQ = 2.5V 1.7 VDD + 0.3V V VIL Input LOW Voltage[17] VDDQ = 2.5V –0.3 0.7 V IX Input Load GND ≤ VI ≤ VDDQ –5 5 µA Input Current of MODE Input = VSS Input = VDD Input Current of ZZ 30 Input = VSS 5 µA 5 µA 4.0-ns cycle, 250 MHz 350 mA 5.0-ns cycle, 200 MHz 300 mA 6.0-ns cycle, 167 MHz 275 mA Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz VIN ≥ VIH or VIN ≤ VIL, f = fMAX = 5.0-ns cycle, 200 MHz 1/tCYC 6.0-ns cycle, 167 MHz 160 mA 150 mA 140 mA Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled IDD VDD Operating Supply Automatic CE Power-down Current—TTL Inputs µA µA –30 Input = VDD IOZ ISB1 µA –5 VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC –5 ISB2 Automatic CE Max. VDD, Device Deselected, All speed grades Power-down VIN ≤ 0.3V or VIN > VDDQ − 0.3V, Current—CMOS Inputs f = 0 70 mA ISB3 Automatic CE Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz Power-down VIN ≤ 0.3V or VIN > VDDQ − 0.3V, 5.0-ns cycle, 200 MHz Current—CMOS Inputs f = fMAX = 1/tCYC 6.0-ns cycle, 167 MHz 135 mA 130 mA 125 mA Automatic CE Power-down Current—TTL Inputs 80 mA ISB4 Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 All speed grades Shaded areas contain advance information. Notes: 15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2). 16. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 17. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05558 Rev. *A Page 20 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Capacitance[17] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TA = 25°C, f = 1 MHz, VDD = 2.5V. VDDQ = 2.5V TQFP Package BGA Package fBGA Package Unit 5 8 9 pF 5 8 9 pF 5 8 9 pF TQFP Package BGA Package fBGA Package Unit 31 45 46 °C/W 6 7 3 °C/W Thermal Resistance[17] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. AC Test Loads and Waveforms 2.5V I/O Test Load R = 1667Ω 2.5V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R = 1538Ω VT = 1.25V (a) Document #: 38-05558 Rev. *A ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE (b) 10% 90% 10% 90% ≤ 1 ns ≤ 1 ns (c) Page 21 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Switching Characteristics Over the Operating Range [22, 23] -250 Parameter tPower [18] Description VCC (typical) to the first access read or write Min. -200 Max. Min. -167 Max. Min. Max. Unit 1 1 1 ms 4.0 5 6 ns Clock tCYC Clock Cycle Time FMAX Maximum Operating Frequency tCH Clock HIGH 1.7 2.0 2.2 ns tCL Clock LOW 1.7 2.0 2.2 ns 250 200 167 MHz Output Times tCO Data Output Valid After CLK Rise tEOV OE LOW to Output Valid tDOH Data Output Hold After CLK Rise tCHZ Clock to High-Z[19, 20, 21] Clock to Low-Z[19, 20, 21] tCLZ 2.6 2.6 1.0 OE HIGH to Output tEOLZ OE LOW to Output Low-Z[19, 20, 21] 3.0 1.3 2.6 1.0 High-Z[19, 20, 21] tEOHZ 3.0 ns 3.4 ns 1.3 3.0 1.3 2.6 3.4 ns 3.4 1.3 3.0 ns ns 3.4 ns 0 0 0 ns Set-up Times tAS Address Set-up Before CLK Rise 1.2 1.4 1.5 ns tDS Data Input Set-up Before CLK Rise 1.2 1.4 1.5 ns tCENS CEN Set-up Before CLK Rise 1.2 1.4 1.5 ns tWES WE, BWx Set-up Before CLK Rise 1.2 1.4 1.5 ns tALS ADV/LD Set-up Before CLK Rise 1.2 1.4 1.5 ns tCES Chip Select Set-up 1.2 1.4 1.5 ns tAH Address Hold After CLK Rise 0.3 0.4 0.5 ns tDH Data Input Hold After CLK Rise 0.3 0.4 0.5 ns tCENH CEN Hold After CLK Rise 0.3 0.4 0.5 ns tWEH WE, BWx Hold After CLK Rise 0.3 0.4 0.5 ns tALH ADV/LD Hold after CLK Rise 0.3 0.4 0.5 ns tCEH Chip Select Hold After CLK Rise 0.3 0.4 0.5 ns Hold Times Shaded areas contain advance information. Notes: 18. This part has a voltage regulator internally; tPower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated. 19. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 21. This parameter is sampled and not 100% tested. 22. Timing reference 1.25V when VDDQ = 2.5V. 23. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05558 Rev. *A Page 22 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Switching Waveforms Read/Write/Timing[24, 25, 26] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BWx A1 ADDRESS A2 tCO tAS tDS tAH Data tDH D(A1) tCLZ D(A2) D(A2+1) tDOH Q(A3) tOEV Q(A4) tCHZ Q(A4+1) D(A5) Q(A6) In-Out (DQ) tOEHZ tDOH tOELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT UNDEFINED Notes: 24. For this waveform ZZ is tied LOW. 25. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document #: 38-05558 Rev. *A Page 23 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Switching Waveforms (continued) NOP,STALL and DESELECT Cycles[24, 25, 27] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BWx ADDRESS A5 tCHZ D(A1) Data Q(A2) D(A4) Q(A3) Q(A5) In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL DON’T CARE NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED ZZ Mode Timing[28, 29] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 27. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle 28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 29. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05558 Rev. *A Page 24 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Ordering Information Speed (MHz) 250 Ordering Code CY7C1370DV25-250AXC Package Name Package Type Operating Range A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial CY7C1372DV25-250AXC CY7C1370DV25-250BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-250BGC CY7C1370DV25-250BZC BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-250BZC CY7C1370DV25-250BGXC CY7C1372DV25-250BGXC CY7C1370DV25-250BZXC BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1372DV25-250BZXC 200 CY7C1370DV25-200AXC CY7C1372DV25-200AXC CY7C1370DV25-200BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-200BGC CY7C1370DV25-200BZC BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-200BZC CY7C1370DV25-200BGXC CY7C1372DV25-200BGXC CY7C1370DV25-200BZXC BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1372DV25-200BZXC 167 CY7C1370DV25-167AXC CY7C1372DV25-167AXC CY7C1370DV25-167BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-167BGC CY7C1370DV25-167BZC BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-167BZC CY7C1370DV25-167BGXC CY7C1372DV25-167BGXC CY7C1370DV25-167BZXC CY7C1372DV25-167BZXC Document #: 38-05558 Rev. *A BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Page 25 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Ordering Information (continued) Speed (MHz) 250 Ordering Code CY7C1370DV25-250AXI Package Name Package Type Operating Range A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial CY7C1372DV25-250AXI CY7C1370DV25-250BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-250BGI CY7C1370DV25-250BZI BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-250BZI CY7C1370DV25-250BGXI CY7C1372DV25-250BGXI CY7C1370DV25-250BZXI BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1372DV25-250BZXI 200 CY7C1370DV25-200AXI CY7C1372DV25-200AXI CY7C1370DV25-200BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-200BGI CY7C1370DV25-200BZI BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-200BZI CY7C1370DV25-200BGXI CY7C1372DV25-200BGXI CY7C1370DV25-200BZXI BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1372DV25-200BZXI 167 CY7C1370DV25-167AXI CY7C1372DV25-167AXI CY7C1370DV25-167BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-167BGI CY7C1370DV25-167BZI BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-167BZI CY7C1370DV25-167BGXI CY7C1372DV25-167BGXI CY7C1370DV25-167BZXI CY7C1372DV25-167BZXI BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-free BG packages(Ordering Code: BGX) will be available in 2005. Document #: 38-05558 Rev. *A Page 26 of 30 CY7C1370DV25 CY7C1372DV25 PRELIMINARY Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 16.00±0.20 DIMENSIONS ARE IN MILLIMETERS. 14.00±0.10 1.40±0.05 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 SEE DETAIL 50 0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 GAUGE PLANE R 0.08 MIN. 0.20 MAX. 0.10 0° MIN. 0°-7° A 51 31 R 0.08 MIN. 0.20 MAX. 12°±1° (8X) SEATING PLANE 51-85050-*A 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05558 Rev. *A A Page 27 of 30 PRELIMINARY CY7C1370DV25 CY7C1372DV25 Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Document #: 38-05558 Rev. *A Page 28 of 30 PRELIMINARY CY7C1370DV25 CY7C1372DV25 Package Diagrams (continued) 165 FBGA 13 x 15 x 1.40 MM BB165D 51-85180-** Document #: 38-05558 Rev. *A Page 29 of 30 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY7C1370DV25 CY7C1372DV25 Document History Page Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture (Preliminary) Document Number: 38-05558 REV. ECN No. Issue Date Orig. of Change ** 254509 See ECN RKF New data sheet *A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for non-compliance with 1149.1 Removed 225 Mhz Speed Bin Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA package Added comment of ‘Lead-free BG packages availability’ below the Ordering Information Document #: 38-05558 Rev. *A Description of Change Page 30 of 30