IS62WV25616ALL IS62WV25616BLL ISSI 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM ® MAY 2005 FEATURES DESCRIPTION • High-speed access time: 55ns, 70ns The ISSI IS62WV25616ALL/IS62WV25616BLL are highspeed, low power, 4M bit SRAMs organized as 256K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. • CMOS low power operation 36 mW (typical) operating 9 µW (typical) CMOS standby When CS1 is HIGH (deselected) or when CS1 is LOW and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. • TTL compatible interface levels • Single power supply 1.65V--2.2V VDD (IS62WV25616ALL) Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. 2.5V--3.6V VDD (IS62WV25616BLL) • Fully static operation: no clock or refresh required • Three state outputs The IS62WV25616ALL/IS62WV25616BLL are packaged in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin mini BGA (6mmx8mm). • Data control for upper and lower bytes • Industrial temperature available • Lead-free available FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CS1 OE WE UB LB CONTROL CIRCUIT Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 1 ISSI IS62WV25616ALL, IS62WV25616BLL PIN CONFIGURATIONS 48- ball mini BGA (6mm x 8mm) (Package Code B) ® 44-Pin mini TSOP (Type II) (Package Code T) 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CSI I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A17 PIN DESCRIPTIONS A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1 Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VDD Power GND Ground 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 ISSI IS62WV25616ALL, IS62WV25616BLL ® TRUTH TABLE I/O PIN I/O0-I/O7 I/O8-I/O15 WE CS1 OE LB UB Not Selected X X H X X X X H X H High-Z High-Z High-Z High-Z ISB1, ISB2 ISB1, ISB2 Output Disabled H H L L H H L X X L High-Z High-Z High-Z High-Z ICC ICC Read H H H L L L L L L L H L H L L DOUT High-Z DOUT High-Z DOUT DOUT ICC Write L L L L L L X X X L H L H L L DIN High-Z DIN High-Z DIN DIN ICC Mode VDD Current ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Related to GND Storage Temperature Power Dissipation Value –0.2 to VDD+0.3 –0.2 to VDD+0.3 –65 to +150 1.0 Unit V V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (VDD) Range Ambient Temperature IS62WV25616ALL IS62WV25616BLL 0°C to +70°C –40°C to +85°C 1.65V - 2.2V 1.65V - 2.2V 2.5V-3.6V 2.5V-3.6V Commercial Industrial DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions VDD Min. Max. Unit VOH Output HIGH Voltage IOH = -0.1 mA IOH = -1 mA 1.65-2.2V 2.5-3.6V 1.4 2.2 — — V V VOL Output LOW Voltage IOL = 0.1 mA IOL = 2.1 mA 1.65-2.2V 2.5-3.6V — — 0.2 0.4 V V VIH Input HIGH Voltage 1.65-2.2V 2.5-3.6V 1.4 2.2 VDD + 0.2 VDD + 0.3 V V VIL(1) Input LOW Voltage 1.65-2.2V 2.5-3.6V –0.2 –0.2 0.4 0.6 V V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Notes: 1. VIL (min.) = –1.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 3 ISSI IS62WV25616ALL, IS62WV25616BLL ® IS62WV25616ALL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ICC1 ISB1 Parameter Test Conditions VDD Dynamic Operating Supply Current Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX VDD = Max., CS1 = 0.2V WE = VDD-0.2V f=1MHZ VDD = Max., VIN = VIH or VIL CS1 = VIH , f = 1 MHZ TTL Standby Current (TTL Inputs) Unit Com. Ind. Com. Ind. Max. 70 25 30 10 10 Com. Ind. 0.35 0.35 mA 15 15 µA mA mA OR ULB Control ISB2 CMOS Standby Current (CMOS Inputs) ULB Control VDD = Max., VIN = VIH or VIL CS1 = VIL, f = 0, UB = VIH, LB = VIH VDD = Max., Com. CS1 ≥ VDD – 0.2V, Ind. VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 OR VDD = Max., CS1 = VIL, VIN ≤ 0.2V, f = 0; UB / LB = VDD – 0.2V IS62WV25616BLL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ICC1 ISB1 Parameter Test Conditions VDD Dynamic Operating Supply Current Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX VDD = Max., CS1 = 0.2V WE = VDD-0.2V f=1MHZ VDD = Max., VIN = VIH or VIL CS1 = VIH, f = 1 MHZ TTL Standby Current (TTL Inputs) Max. 70 35 40 15 15 Unit Com. Ind. Com. Ind. Max. 55 40 45 15 15 Com. Ind. 0.35 0.35 0.35 0.35 mA 15 15 15 15 µA mA mA OR ULB Control ISB2 CMOS Standby Current (CMOS Inputs) ULB Control 4 VDD = Max., VIN = VIH or VIL CS1 = VIL, f = 0, UB = VIH, LB = VIH VDD = Max., Com. CS1 ≥ VDD – 0.2V, Ind. VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 OR VDD = Max., CS1 = VIL, VIN ≤ 0.2V, f = 0; UB / LB = VDD – 0.2V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 ISSI IS62WV25616ALL, IS62WV25616BLL ® CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 8 pF VOUT = 0V 10 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load IS62WV25616ALL (Unit) 0.4V to VDD-0.2V 5 ns VREF IS62WV25616BLL (Unit) 0.4V to VDD-0.3V 5ns VREF See Figures 1 and 2 See Figures 1 and 2 IS62WV25616ALL 1.65V-2.2V IS62WV25616BLL 2.5V - 3.6V R1(Ω) Ω) 3070 3070 R2(Ω) Ω) 3150 3150 VREF 0.9V 1.5V VTM 1.8V 2.8V AC TEST LOADS R1 R1 VTM VTM OUTPUT OUTPUT 30 pF Including jig and scope Figure 1 5 pF Including jig and scope R2 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 R2 5 ISSI IS62WV25616ALL, IS62WV25616BLL ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter 55 ns Min. Max. 70 ns Min. Max. Unit tRC Read Cycle Time 55 — 70 — ns tAA Address Access Time — 55 — 70 ns tOHA Output Hold Time 10 — 10 — ns tACS1 CS1 Access Time — 55 — 70 ns OE Access Time — 25 — 35 ns OE to High-Z Output — 20 — 25 ns tLZOE(2) OE to Low-Z Output 5 — 5 — ns tHZCS1 CS1 to High-Z Output 0 20 0 25 ns tLZCS1 CS1 to Low-Z Output 10 — 10 — ns tBA LB, UB Access Time — 55 — 70 ns tHZB LB, UB to High-Z Output 0 20 0 25 ns tLZB LB, UB to Low-Z Output 0 — 0 — ns tDOE tHZOE (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to VDD-0.2V/VDD-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 ISSI IS62WV25616ALL, IS62WV25616BLL ® AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, WE = VIH, UB or LB = VIL) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) (CS1, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tDOE CS1 tHZOE tLZOE tACE1 tLZCE1 tHZCS1 LB, UB tBA tHZB tLZB DOUT HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = VIL. WE=VIH. 3. Address is valid prior to or coincident with CS1 LOW transition. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 7 ISSI IS62WV25616ALL, IS62WV25616BLL ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter Min. 55 ns Max. Min. 70 ns Max. Unit tWC Write Cycle Time 55 — 70 — ns tSCS1 tAW CS1 to Write End 45 — 60 — ns Address Setup Time to Write End 45 — 60 — ns tHA tSA Address Hold from Write End 0 — 0 — ns Address Setup Time 0 — 0 — ns tPWB tPWE LB, UB Valid to End of Write 45 — 60 — ns WE Pulse Width 40 — 50 — ns tSD tHD Data Setup to Write End 25 — 30 — ns Data Hold from Write End 0 — 0 — ns tHZWE(3) tLZWE(3) WE LOW to High-Z Output — 20 — 20 ns WE HIGH to Low-Z Output 5 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to VDD-0.2V/VDD-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 ISSI IS62WV25616ALL, IS62WV25616BLL ® AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tAW tPWE WE tPWB LB, UB tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tAW t PWE WE LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 tHD 9 ISSI IS62WV25616ALL, IS62WV25616BLL ® WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tAW t PWE WE LB, UB tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID WRITE CYCLE NO. 4 (UB/LB Controlled) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CS1 LOW t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CSWR4.eps 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 ISSI IS62WV25616ALL, IS62WV25616BLL ® DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR VDD for Data Retention See Data Retention Waveform 1.2 3.6 V IDR Data Retention Current VDD = 1.2V, CS1 ≥ VDD – 0.2V — 15 µA tSDR tRDR Data Retention Setup Time See Data Retention Waveform 0 — ns Recovery Time See Data Retention Waveform tRC — ns DATA RETENTION WAVEFORM (CS1 Controlled) tSDR Data Retention Mode tRDR VDD VDR CS1 GND CS1 ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 11 IS62WV25616ALL, IS62WV25616BLL ISSI ® ORDERING INFORMATION IS62WV25616ALL (1.65V-2.2V) Commercial Range: 0°C to +70°C Speed (ns) 70 Order Part No. Package IS62WV25616ALL-70T TSOP Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 70 IS62WV25616ALL-70TI TSOP 70 IS62WV25616ALL-70BI mini BGA (6mmx8mm) IS62WV25616BLL (2.5V - 3.6V) Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package 55 IS62WV25616BLL-55T TSOP 70 IS62WV25616BLL-70T TSOP Industrial Range: –40°C to +85°C Speed (ns) 12 Order Part No. Package 55 IS62WV25616BLL-55TI TSOP 55 IS62WV25616BLL-55TLI TSOP, Lead-free 55 IS62WV25616BLL-55BI mini BGA (6mmx8mm) 55 IS62WV25616BLL-55BLI mini BGA (6mmx8mm), Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 05/02/05 ISSI ® PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (48-pin) Top View Bottom View φ b (48x) 1 2 3 4 5 6 6 A 4 3 2 1 A e B B C C D D D 5 D1 E E F F G G H H e E E1 A2 Notes: 1. Controlling dimensions are in millimeters. A A1 SEATING PLANE mBGA - 6mm x 8mm mBGA - 8mm x 10mm MILLIMETERS INCHES MILLIMETER Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 48 Sym. Min. Typ. Max. N0. Leads 48 INCHES Min. Typ. Max. A — — 1.20 — — 0.047 A — — 1.20 — — 0.047 A1 0.24 — 0.30 0.009 — 0.012 A1 0.24 — 0.30 0.009 — 0.012 A2 0.60 — — 0.024 — — A2 0.60 — — 0.024 — — D 7.90 — 8.10 0.311 — 0.319 D 9.90 — 10.10 0.390 — 0.398 D1 E 5.25 BSC 5.90 — 6.10 0.207 BSC 0.232 — 0.240 D1 E 5.25 BSC 7.90 — 0.207 BSC 8.10 0.311 — 0.319 E1 3.75 BSC 0.148 BSC E1 3.75 BSC 0.148 BSC e 0.75 BSC 0.030 BSC e 0.75 BSC 0.030 BSC 0.012 0.014 0.016 b b 0.30 0.35 0.40 0.30 0.35 0.40 0.012 0.014 0.016 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 01/15/03 ISSI ® PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) N N/2+1 E1 1 Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. E N/2 D SEATING PLANE A ZD . b e Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD α Millimeters Min Max Inches Min Max (N) 32 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0° 5° 0° 5° L α A1 Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0° 5° 0° 5° Millimeters Min Max C Inches Min Max 50 — 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0° 5° — 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0° 5° Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 06/18/03