AKM AKD4632-A Ak4632 evaluation board rev.0 Datasheet

ASAHI KASEI
[AKD4632-A]
AKD4632-A
AK4632 Evaluation board Rev.0
GENERAL DESCRIPTION
AKD4632-A is an evaluation board for the AK4632, 16bit mono CODEC with MIC/SPK/VIDEO amplifier.
The AKD4632-A can evaluate A/D converter and D/A converter separately in addition to loopback mode
(A/D → D/A). AKD4632-A also has the digital audio interface and can achieve the interface with digital
audio systems via opt-connector.
„ Ordering guide
AKD4632-A
--- Evaluation board for AK4632
(Cable for connecting with printer port of IBM-AT, compatible PC and control
software are packed with this. This control software does not support Windows NT.)
FUNCTION
• DIT/DIR with optical input/output
• BNC connector for an external clock input
• 10pin Header for serial control mode
5V
AVDD DVDD SVDD VVDD GND
3.3V
Regulator
MIC-Jack
Control Data
MIC
10pin Header
DSP
BEEP/MIN/MOUT
AOUT
AK4632
10pin Header
SPK-Jack
VIN
AK4114
VOUT
Opt In
Opt Out
Clock
Gen
Figure 1. AKD4632-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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ASAHI KASEI
[AKD4632-A]
Evaluation Board Manual
„ Operation sequence
1) Set up the power supply lines.
1-1) When AVDD, DVDD, SVDD, VVDD and VCC are supplied from the regulator. (AVDD, DVDD, SVDD,
VVDD and VCC jack should be open.). See “Other jumper pins set up (page 10)”. <default>
[REG]
[AVDD]
[DVDD]
[SVDD]
[VVDD]
[VCC]
[AVSS]
[AGND]
[DGND]
(red )
(orange)
(orange)
(blue)
(blue)
(orenge)
(black)
(black)
(black)
= 5V
= open
= open
= open
= open
= open
= 0V
= 0V
= 0V
: 3.3V is supplied to AVDD of AK4632 from regulator.
: 3.3V is supplied to DVDD of AK4632 from regulator.
: 3.3V is supplied to SVDD of AK4632 from regulator.
: 3.3V is supplied to VVDD of AK4632 from regulator.
: 3.3V is supplied to logic block from regulator.
: for analog ground
: for analog ground
: for logic ground
1-2) When AVDD, DVDD, SVDD, VVDD and VCC are not supplied from the regulator. (AVDD, DVDD,
SVDD, VVDD and VCC jack should be junction.) See “Other jumper pins set up (page 10)”.
[REG]
[AVDD]
[DVDD]
[SVDD]
[VVDD]
[VCC]
[AVSS]
[AGND]
[DGND]
(red)
(orange)
(orange)
(blue)
(blue)
(orenge)
(black)
(black)
(black)
= “REG” jack should be open.
= 2.6 ∼ 3.6V : for AVDD of AK4632 (typ. 3.3V)
= 2.6 ∼ 3.6V : for DVDD of AK4632 (typ. 3.3V)
= 2.6 ∼ 5.25V : for SVDD of AK4632 (typ. 3.3V, 5.0V)
= 2.6 ∼ 5.25V : for VVDD of AK4632 (typ. 3.3V, 5.0V)
= 2.6 ∼ 3.6V : for logic (typ. 3.3V)
= 0V
: for analog ground
= 0V
: for analog ground
= 0V
: for logic ground
Each supply line should be distributed from the power supply unit.
AVDD and DVDD must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4632 and AK4114 should be reset once bringing SW1, 2 “L” upon power-up.
„ Evaluation mode
In case of AK4632 evaluation using AK4114, it is necessary to correspond to audio interface format for
AK4632 and AK4114. About AK4632’s audio interface format, refer to datasheet of AK4632. About
AK4114’s audio interface format, refer to Table 2 in this manual.
Applicable Evaluation Mode
(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI
pin)
(3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or
FCK pin)
(4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode
(5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode
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ASAHI KASEI
[AKD4632-A]
(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “0”.
X’tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set in X1. X’tal of 12.288MHz
(Default) is set on the AKD4632-A. Set “No.8 of SW3” to “H”.
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA
connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1)
and R26 should be properly selected in order to much the output impedance of the clock generator.
JP6
JP17
XTE
MCKI
JP18
MKFS
JP21
MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock
Output frequency (16fs/32fs/64fs) of BICK should be set by “BCKO1-0 bit” in the AK4632.
There is no necessity for set up JP19.
JP20
BICK
INV
JP29
BICK_INV
JP27
BICK
DIR ADC
THR
INV
THR
JP19
BICK_SEL
64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4632 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
JP26
4632_SDTI
SDTI
DIR
ADC
DAC/LOOP ADC
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[AKD4632-A]
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “0”.
X’tal of 12.288MHz (Default) is set on the AKD4632-A. In this case, the AK4632 corresponds to PLL reference
clock of 12.288MHz. In this evaluation mode, the output clock from MCKO-pin of the AK4632 is supplied to a
divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Then “MCKO bit” in the
AK4632 is set to “1”. When an external clock through a RCA connector (J8: EXT/BICK) is supplied, select
EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order
to much the output impedance of the clock generator.
JP17
XTE
JP6
MCKI
JP18
MKFS
JP21
MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock
JP20
BICK
INV
JP27
BICK
DIR ADC
THR
JP29
BICK_INV
INV
THR
JP19
BICK_SEL
64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4632 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
JP26
4632_SDTI
SDTI
DIR
ADC
DAC/LOOP ADC
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[AKD4632-A]
(3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK
pin)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “1”. JP6 (MCKI) should be open.
b) Set up jumper pins of BICK clock
When an external clock through a RCA connector J8 (EXT/BICK) is supplied, select EXT on JP19
(MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to much the
output impedance of the clock generator.
JP17
XTE
JP20
BICK
JP21
MCLK_SEL
XTL DIR EXT
INV
THR
JP29
BICK_INV
JP27
BICK
DIR ADC
INV
THR
In this evaluation mode, the selected clock from JP21 (MCLK_SEL) is supplied to a divider (U3: 74VHC4040),
BICK and FCK clocks are generated by the divider. Input frequency of master clock is set up in turn “256fs”,
“512fs”, “1024fs” from left.
JP18
MKFS
JP18
MKFS
JP18
MKFS
256fs 512fs 1024fs MCKO
256fs 512fs 1024fs MCKO
256fs 512fs 1024fs MCKO
And input frequency of BICK is set up in turn “16fs”, “32fs”, “64fs” from left.
JP19
BICK_SEL
JP19
BICK_SEL
JP19
BICK_SEL
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
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[AKD4632-A]
c) Set up jumper pins of FCK clock
When an external clock through a RCA connector J9 (FCK) is supplied, select EXT on JP22 (FCK_SEL). JP24
(EXT2) and R27 should be properly selected in order to much the output impedance of the clock generator.
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4632 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
JP26
4632_SDTI
SDTI
DIR
ADC
<KM075602>
DAC/LOOP ADC
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ASAHI KASEI
[AKD4632-A]
(4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “0”.
JP6
MCKI
JP21
MCLK_SEL
JP18
MKFS
XTL DIR EXT
256fs 512fs 1024fs
JP17
XTE
b) Set up jumper pins of BICK clock
JP20
BICK
INV
THR
JP29
BICK_INV
JP27
BICK
DIR ADC
INV
JP19
BICK_SEL
THR 64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP24 (EXT2) and R27 should be properly selected in order to much the output impedance of the clock generator.
JP28
FCK
DIR
JP22
FCK_SEL
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When D/A converter of the AK4632 is evaluated by using DIR of AK4114, the jumper pins should be set to the
following.
JP30
JP26
4632_SDTI
SDTI
DIR
ADC
DAC/LOOP ADC
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ASAHI KASEI
[AKD4632-A]
(5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “0”.
JP6
MCKI
JP21
MCLK_SEL
JP18
MKFS
XTL DIR EXT
256fs 512fs 1024fs
JP17
XTE
b) Set up jumper pins of BICK clock
JP20
BICK
INV
THR
JP27
BICK
DIR ADC
JP29
BICK_INV
INV
JP19
BICK_SEL
THR 64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP24 (EXT2) and R27 should be properly selected in order to much the output impedance of the clock generator.
JP28
FCK
DIR
JP22
FCK_SEL
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When A/D converter of the AK4632 is evaluated by using DIR of AK4114, the jumper pins should be set to the
following.
JP30
JP26
4632_SDTI
SDTI
DIR
ADC
DAC/LOOP ADC
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[AKD4632-A]
„ DIP Switch set up
[SW3] (MODE) : Mode Setting of AK4632 and AK4114
ON is “H”, OFF is “L”.
No.
Name
ON (“H”)
OFF (“L”)
1
DIF0
AK4114 Audio Format Setting
2
DIF1
See Table 2
3
CM2
Clock Operation Mode select
4
CM0
See Table 3
5
CM1
6
OCKS0
Master Clock Frequency Select
See Table 4
7
OCKS1
8
M/S
Master mode
Slave mode
Note. When the AK4632 is evaluated Master mode, “No.8 of SW3” is set to “H”.
Table 1. Mode Setting for AK4632 and AK4114
Register setting
for AK4632 Audio
Interface Format
Setting for AK4114 Audio Interface Format
DIF1 bit
DIF0 bit
DIF0
DIF1
DIF2
0
1
L
L
L
24bit, Left justified
16bit, Right justified
1
0
L
L
H
24bit, Left justified
24bit, Left justified
1
1
H
L
H
DAUX
SDTO
2
Default
2
24bit, I S
24bit, I S
Note. When the AK4632 is evaluated by using DIR/DIT of AK4114, “No.8 of SW3” is set to “L”.
Table 2. Setting for AK4114 Audio Interface Format
Mode
0
1
CM1
0
0
CM0
0
1
UNLOCK
PLL
X'tal
Clock source SDTO
ON
ON(Note)
PLL
RX
OFF
ON
X'tal
DAUX
0
ON
ON
PLL
RX
2
1
0
Default
1
ON
ON
X'tal
DAUX
3
1
1
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off.
Table 3. Clock Operation Mode select
No.
0
2
OCKS1
0
1
MCKO1
256fs
512fs
MCKO2
256fs
256fs
X’tal
256fs
512fs
Default
Table 4. Master Clock Frequency Select (Stereo mode)
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[AKD4632-A]
„ Other jumper pins set up
1. JP1 (GND)
OPEN
SHORT
: Analog ground and Digital ground
: Separated.
: Common. (The connector “DGND” can be open.) <Default>
2. JP2 (AIN)
OPEN
SHORT
: Connection between MICOUT pin and AIN pin of the AK4632.
: No connection.
: Connection. <Default>
3. JP3 (AVDD_SEL) : AVDD of the AK4632
REG
: AVDD is supplied from the regulator (“AVDD” jack should be open). < Default >
AVDD
: AVDD is supplied from “AVDD ” jack.
4. JP8 (VVDD_SEL) : VVDD of the AK4632
AVDD
: AVDD is supplied from “AVDD”. < Default >
VVDD
: VVDD is supplied from “VVDD ” jack.
5. JP9 (DVDD_SEL) : DVDD of the AK4632
AVDD
: DVDD is supplied from “AVDD”. < Default >
DVDD
: DVDD is supplied from “DVDD ” jack.
6. JP10 (LVC_SEL) : Logic block of LVC is selected supply line.
DVDD
: Logic block of LVC is supplied from “DVDD”. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
7. JP11 (VCC_SEL) : Logic block is selected supply line.
LVC
: Logic is supplied from supply line of LVC. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
8. JP4 (SVDD_SEL) : SVDD of the AK4632
REG
: SVDD is supplied from the regulator (“SVDD” jack should be open). < Default >
SVDD
: SVDD is supplied from “SVDD ” jack.
9. JP8 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114.
MCKO1
: The check from MCKO1 of AK4114 is provided to MCKI of the AK4632. < Default >
MCKO2
: The check from MCKO2 of AK4114 is provided to MCKI of the AK4632.
<KM075602>
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ASAHI KASEI
[AKD4632-A]
„ The function of the toggle SW
[SW1] (DIR)
: Power control of AK4114. Keep “H” during normal operation.
Keep “L” when AK4114 is not used.
[SW2] (PDN)
: Power control of AK4632. Keep “H” during normal operation.
„ Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
„ Serial Control
The AK4632 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2
(CTRL) with PC by 10 wire flat cable packed with the AKD4632-A
Connect
PC
10 wire
flat cable
10pin
Connector
CSN
CCLK
CDTI
AKD4632
10pin Header
Figure 2. Connect of 10 wire flat cable
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ASAHI KASEI
[AKD4632-A]
„ Analog Input / Output Circuits
(1) Input Circuits
a) MIC Input Circuit
J1
MIC-JACK
6
4
3
AVSS
JACK
JP12
MIC_SEL
INT
J3
MIC
RCA
2
3
1
MR-552LS
AVSS
Figure 3. MIC Input Circuit
(a-1) Analog signal is input to INT pin via J1 connector.
JP12
MIC_SEL
RCA JACK
(a-2) Analog signal is input to INT pin via J3 connector.
JP12
MIC_SEL
RCA JACK
b) VIN Input Circuit
J6
VIN
C29
2
3
1
VIN
0.1u
R23
75
MR-552LS
AVSS
AVSS
Figure 4. VIN Input Circuit
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ASAHI KASEI
[AKD4632-A]
(2) Output Circuits
a) AOUT Output Circuit
1
AOUT
+
C28
R20
220
2
1u
2
3
1
R21
20k
J5 AOUT
MR-552LS
AVSS
AVSS
Figure 5. AOUT Output Circuit
b) VOUT Output Circuit
C18 1u
2
+
VSAG
1
2
+
1
VSAG_SEL
R22
75
11
2
3
1
00
C17 47u
VOUT
JP7
R41
100k
11
00
JP5
J7 VOUT
MR-552LS
AVSS
VOUT_SEL
AVSS
Figure 6. VOUT Output Circuit
(b-1) “DC Output” is output from J7 connector.
JP5
VOUT_SEL
00
JP7
VSAG_SEL
11
00
11
(b-2) “SAG Trimming Circuit ” is output from J7 connector.
JP5
VOUT_SEL
00
JP7
VSAG_SEL
11
00
<KM075602>
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ASAHI KASEI
[AKD4632-A]
C) SPK Output Circuit
Note. When mini-jack is inserted or pulled out J2 (SPK-JACK) connector, JP13 (SPP_SEL) and JP14
(SPN_SEL) should be open, or “PMSPK bit” in the AK4632 should be set to “0”.
JP31
Dynamic
R15
10
J2
SPK-JACK
3
4
SVSS
SPP
6
JP13
D1
A
SVSS
K
DIODE ZENER
D2
SVSS
SPP_SEL
JP14
A
K
DIODE ZENER
Dynamic(EXT)
Piezo(EXT)
Dynamic
SPK1
CN5
Dynamic(EXT)
Piezo(EXT)
Dynamic
SPN_SEL
020S16
R
2
1
L
R17
10
SPN
Figure 7. SPK Output Circuit
(C-1) “Dynamic Speaker” of external is evaluated by using J2 (SPK-JACK) connector.
JP13
SPP_SEL
Dynamic
Dynamic(EXT)
Piezo(EXT)
JP14
SPN_SEL
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
(C-2) “Piezo (Ceramic) Speaker” of external is evaluated by using J2 (SPK-JACK) connector.
JP13
SPP_SEL
Dynamic
Dynamic(EXT)
Piezo(EXT)
JP14
SPN_SEL
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
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ASAHI KASEI
[AKD4632-A]
(C-3) Analog signal of SPP/SPN pins are output “Dynamic Speaker” on the evaluation (SPK1).
JP13
SPP_SEL
Dynamic
JP14
SPN_SEL
Dynamic(EXT)
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Piezo(EXT)
(3) BEEP/MIN/MOUT Input and Output Circuit
2
JP15
MIN/MOUT
OUT
IN
R16
20k
1
MOUT
+
J4
BEEP/MIN/MOUT
2
3
1
C24
1u
C25
0.1u
AVSS
MR-552LS
AVSS
2
C26
1u
JP16
1
+
R18
47k
MOUT
MIN
BEEP
MIN
R19
BEEP/MIN/MOUT
BEEP
20k
AVSS
Figure 8. BEEP/MIN/MOUT Input and Output Circuit
(3-1) Analog signal is input to MIN pin from J4 connector.
JP15
JP16
BEEP/MIN/MOUT
MIN/MOUT
IN
MOUT
MIN
BEEP
OUT
(3-2) Analog signal of MOUT pin is output from J4 connector.
JP15
MIN/MOUT
IN
JP16
BEEP/MIN/MOUT
MOUT
MIN
BEEP
OUT
<KM075602>
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ASAHI KASEI
[AKD4632-A]
(3-3) Analog signal of MOUT pin is input to MIN pin.
JP15
JP16
BEEP/MIN/MOUT
MIN/MOUT
IN
MOUT
MIN
BEEP
OUT
(3-4) Analog signal is input to BEEP pin from J4 connector.
JP15
JP16
BEEP/MIN/MOUT
MIN/MOUT
IN
MOUT
MIN
BEEP
OUT
∗ AKM assumes no responsibility for the trouble when using the above circuit examples.
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ASAHI KASEI
[AKD4632-A]
Control Software Manual
„ Set-up of evaluation board and control software
1. Set up the AKD4632-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4632-A by 10-line type flat cable (packed with AKD4632-A). Take care
of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AKD4632-A Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “akd4632.exe” to set up the control program.
5. Then please evaluate according to the follows.
„ Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
3. Click “Write default” button
„ Explanation of each buttons
1. [Port Reset] :
2. [Write default] :
3. [All Write] :
4. [Function1] :
5. [Function2] :
6. [Function3] :
7. [Function4] :
8. [Function5]:
9. [SAVE] :
10. [OPEN] :
11. [Write] :
Set up the USB interface board (AKDUSBIF-A) when using the board.
Initialize the register of the AK4632.
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
„ Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
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[AKD4632-A]
„ Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to the AK4632, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box:
Data Box:
Input registers address in 2 figures of hexadecimal.
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to the AK4632, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate DATT
There are dialogs corresponding to register of 09h and 0Ah.
Address Box:
Input registers address in 2 figures of hexadecimal.
Start Data Box:
Input starts data in 2 figures of hexadecimal.
End Data Box:
Input end data in 2 figures of hexadecimal.
Interval Box:
Data is written to the AK4632 by this interval.
Step Box:
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to the AK4632, click [OK] button. If not, click [Cancel] button.
<KM075602>
2005/04
- 18 -
ASAHI KASEI
[AKD4632-A]
4. [SAVE] and [OPEN]
4-1. [SAVE]
All of current register setting values displayed on the main window are saved to the file. The extension of file name is
“akr”.
<Operation flow>
(1) Click [SAVE] Button.
(2) Set the file name and click [SAVE] Button. The extension of file name is “akr”.
4-2. [OPEN]
The register setting values saved by [SAVE] are written to the AK4632. The file type is the same as [SAVE].
<Operation flow>
(1) Click [OPEN] Button.
(2) Select the file (*.akr) and Click [OPEN] Button.
<KM075602>
2005/04
- 19 -
ASAHI KASEI
[AKD4632-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [START] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.
This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file
name is “aks”.
Figure 1. Window of [F3]
<KM075602>
2005/04
- 20 -
ASAHI KASEI
[AKD4632-A]
6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed.
When [F4] button is clicked, the window as shown in Figure 2 opens.
Figure 2. [F4] window
<KM075602>
2005/04
- 21 -
ASAHI KASEI
[AKD4632-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3].
The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is
“DAC_Stereo_ON.aks”)
Figure 3. [F4] window(2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name
is “*.ak4”.
[OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the
change.
<KM075602>
2005/04
- 22 -
ASAHI KASEI
[AKD4632-A]
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to
buttons and then executed. When [F5] button is clicked, the window as shown in Figure 4 opens.
Figure 4. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 5. (In case that the selected file name is
“DAC_Output.akr”)
(2) Click [WRITE] button, then the register setting is executed.
<KM075602>
2005/04
- 23 -
ASAHI KASEI
[AKD4632-A]
Figure 5. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file
name is “*.ak5”.
[OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note
(1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be
loaded again in order to reflect the change.
<KM075602>
2005/04
- 24 -
ASAHI KASEI
[AKD4632-A]
MEASUREMENT RESULTS EXAMPLE
1.AK4632 Mode: EXT mode (Slave)
[Measurement condition]
• Measurement unit: ROHDE & SCHWARZ, UPD05
• MCKI: 256fs, 512fs
• BICK: 64fs
• Bit: 16bit
• Sampling Frequency: 8kHz & 16kHz
• Measurement Frequency: 20 ∼ 3.4kHz (fs=8kHz), 20 ∼ 8kHz (fs=16kHz)
• Power Supply: AVDD=DVDD=VVDD=3.3V,SVDD=3.3V/5.0V
• Temperature: Room
• Input Frequency: 1kHz
[Measurement Results]
1.ADC characteristics (MIC Gain = +20dB, IPGA=0dB, ALC1 = OFF, MIC Æ IPGA Æ ADC)
Result
MCKI clock
512fs
256fs
Sampling Frequency
8kHz
16kHz
8kHz
16kHz
S/(N+D) (-1dBFS)
84.3dB
84.1dB
84.4dB
84.0dB
D-Range (-60dBFS)
88.1dB
86.4dB
85.2dB
86.3dB
S/N
88.1dB
86.3dB
88.2dB
86.3dB
2. DAC characteristics (AOUT) (DAC Æ AOUT, DVOL = 0dB)
Result
MCKI clock
Sampling Frequency
S/(N+D) (0dBFS)
D-Range (-60dBFS)
S/N
512fs
8kHz
91.5dB
94.8dB
95.5dB
256fs
16kHz
89.6dB
92.0dB
93.5dB
8kHz
90.8dB
94.5dB
95.0dB
16kHz
89.5dB
92.1dB
93.5dB
3. Speaker-Amp characteristics (DAC Æ MOUT Æ MIN Æ SPP/SPN, ALC2=OFF)
S/(N+D)
S/N
SVDD=3.3V
RL=8Ω
SVDD=5.0V
RL=10Ω, CL=3uF
SVDD=3.3V
RL=8Ω
SVDD=5.0V
RL=10Ω, CL=3uF
Result
69.6dB
73.5dB
73.2dB
73.8dB
90.4dB
91.7dB
90.6dB
91.0dB
SPKG1-0 = “00” (-0.5dBFS)
SPKG1-0 = “01” (-0.5dBFS)
SPKG1-0 = “10” (-0.5dBFS)
SPKG1-0 = “11” (-0.5dBFS)
SPKG1-0 = “00”
SPKG1-0 = “01”
SPKG1-0 = “10”
SPKG1-0 = “11”
4. Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
Result
MCKI clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
512fs
8kHz
84.2dB
88.4dB
88.4dB
256fs
16kHz
83.2dB
85.9dB
86.0dB
<KM075602>
8kHz
84.2dB
87.0dB
87.0dB
16kHz
83.4dB
85.9dB
86.0dB
2005/04
- 25 -
ASAHI KASEI
[AKD4632-A]
2.AK4632 Mode: PLL SLAVE mode
[Measurement condition]
• Measurement unit: ROHDE & SCHWARZ, UPD05
• Bit: 16bit
• Sampling Frequency: 8kHz & 16kHz
• Measurement Frequency: 20 ∼ 3.4kHz (fs=8kHz), 20 ∼ 8kHz (fs=16kHz)
• Power Supply: AVDD=DVDD=SVDD=VVDD=3.3V
• Temperature: Room
• Input Frequency: 1kHz
[Measurement Results]
2-1. PLL Reference clock : BICK or FCK pin
Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
Result
PLL Reference clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
1fs (FCK pin)
8kHz
16kHz
75.3dB
78.6dB
86.5dB
86.0dB
86.5dB
85.9dB
16fs (BICK pin)
8kHz
16kHz
84.7dB
83.8dB
87.7dB
85.9dB
87.6dB
85.8dB
2-2. PLL Reference clock : MCKI pin
Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
PLL Reference clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
Result
12.288MHz
8kHz
16kHz
84.7dB
83.8dB
87.4dB
85.8dB
88.0dB
85.8dB
3.AK4632 Mode: PLL MASTER mode
[Measurement condition]
• Measurement unit: ROHDE & SCHWARZ, UPD05
• MCKI: 12.288MHz
• BICK: 16fs
• Bit: 16bit
• Sampling Frequency: 8kHz & 16kHz
• Measurement Frequency: 20 ∼ 3.4kHz (fs=8kHz), 20 ∼ 8kHz (fs=16kHz)
• Power Supply: AVDD=DVDD=SVDD=VVDD=3.3V
• Temperature: Room
• Input Frequency: 1kHz
[Measurement Results]
Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
Result
8kHz
S/(N+D) (-1dBFS)
84.2dB
D-Range (-60dBFS)
86.9dB
S/N
87.0dB
16kHz
83.3dB
85.0dB
85.0dB
<KM075602>
2005/04
- 26 -
ASAHI KASEI
[AKD4632-A]
4.PLOT DATA (EXT Slave mode)
4-1.ADC (MIC Æ ADC) PLOT DATA
Figure 1. THD+N vs. Input Level
Figure 2. THD+N vs. Input Frequency (Input Level = -1dBFS), C7: Ceramic Condenser
In this case, a ceramic condenser is used as C7 between MICOUT pin as AIN pin on the AKD4632-A.As the performance of
Ceramic condenser is not so good about low frequency signal. Refer to Figure 3 about the performance of AK4632.
<KM075602>
2005/04
- 27 -
ASAHI KASEI
[AKD4632-A]
Figure 3. THD+N vs. Input Frequency (Input Level = -1dBFS), C7: Film Condenser
Figure 4. Linearity
<KM075602>
2005/04
- 28 -
ASAHI KASEI
[AKD4632-A]
Figure 5. Frequency Response (by the board of AKD4632-A)
High pass filter is composed by the input impedance of AIN pin and C7 between MICOUT pin and AIN pin. Refer to
Figure 6 about frequency response of AK4632’s ADC.
Figure 6. Frequency Response (AIN Æ ADC)
<KM075602>
2005/04
- 29 -
ASAHI KASEI
[AKD4632-A]
Figure 7. FFT Plot ( Input level=-1.0dBFS)
Figure 8. FFT Plot ( Input level=-60.0dBFS )
<KM075602>
2005/04
- 30 -
ASAHI KASEI
[AKD4632-A]
Figure 9. FFT Plot ( “0” data input )
<KM075602>
2005/04
- 31 -
ASAHI KASEI
[AKD4632-A]
4-2. DAC (DAC Æ AOUT) PLOT DATA
Figure 10. THD+N vs. Input Level
Figure 11. THD+N vs. Input Frequency (Input Level = 0dBFS)
<KM075602>
2005/04
- 32 -
ASAHI KASEI
[AKD4632-A]
Figure 12. Linearity
Figure 13. Frequency Response
<KM075602>
2005/04
- 33 -
ASAHI KASEI
[AKD4632-A]
Figure 14. FFT Plot ( Input level=0dBFS )
Figure 15. FFT Plot ( Input level=-60.0dBFS )
<KM075602>
2005/04
- 34 -
ASAHI KASEI
[AKD4632-A]
Figure 16. FFT Plot ( “0” data input )
<KM075602>
2005/04
- 35 -
ASAHI KASEI
[AKD4632-A]
4-3. VIDEO PLOT DATA
[Measurement condition]
• Measurement unit: Tektronix VM700T Video Measurement set
• Power Supply: AVDD=DVDD=SVDD=3.3V,VVDD=3.3V
• Temperature: Room
• Input Frequency: 1kHz
4-3-1. S/N
• Measurement Frequency: 100kH ∼ 6MHz
Figure 1. Noise Spectrum
<KM075602>
2005/04
- 36 -
ASAHI KASEI
[AKD4632-A]
4-3-2. SAG
Figure 2. Field Time Distortion (DC Output, SAGC bits = “00”)
Figure 3. Field Time Distortion (SAG Trimming 47µF+ 1.0uF, SAGC bits = “10”)
<KM075602>
2005/04
- 37 -
ASAHI KASEI
[AKD4632-A]
Figure 4. Field Time Distortion (SAG Trimming 100µF+ 2.2uF, SAGC bits = “11”)
4-3-3. Vector
• Input signal: 75% color
Figure 5. 75% Color Vector (SAG Trimming 47µF+ 1.0uF, SAGC bits = “10”)
<KM075602>
2005/04
- 38 -
ASAHI KASEI
[AKD4632-A]
Revision History
Date
04/11/24
05/04/05
Manual
Revision
KM075601
KM075602
Board
Revision
0
0
Reason
First Edition
Change
Contents
“Control Software Manual” chapter is changed by version up
of control software.
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
<KM075602>
2005/04
- 39 -
A
T1
TA48033F
E
SVSS
MOUT
AVSS
AOUT
C3
+
47u
BEEP
1
C2
0.1u
INT
E
D
REG
OUT
C1
0.1u
2
IN
C
JP1
GND
GND
REG_IN
B
E
AVSS
DGND
T45_BK
T45_BK
REG_IN
AVDD
DVDD
VVDD
SVDD
+
5
JP5
VOUT_SEL
SAGC11
2
1
6
C17 47u
25
26
27
AOUT
MOUT
2
SVSS
JP4
REG
SVDD_SEL
L2
1
SVDD
21
R5 (short)
SPN
SVDD
23
22
R4
(open)
20
VOUT
MCKO
19
21
SPP
20
SPN
2
(short)
C16
+
47u
C
7
SAGC11 2
1
JP7
C18 1u
VSAG_SEL
MCKI
4632_MCKI
JP6 MCKI
18
AVSS
32pin_3
C20
0.1u
16
BICK
15
FCK
13
14
CDTI
10
9
17
DVDD
DVSS
SDTO
PDN
51
CSN
2
AVSS
4632_MCKO
18
17
8
R6
VSAG
19
SVSS
SAGC00
32pin_1
VVDD
SVSS
SAGC00
7
8
SPP
VIN
11
6
2
(short)
BEEP
AK4632
VVDD
CCLK
1
VOUT
C12
10u
22
R3 (short)
4
+
47u
+
5
PDN
L3
1
28
SVDD
C15
0.1u
+
VVDD
C19
VIN
JP8
AVDD VVDD_SEL
AIN
AVSS
4
AVDD
REG
MIN
24
1
AVSS
SVSS
23
C11
0.1u
3
C14
10u
AVDD
SDTI
AVSS
AVSS
24
2
3
C
29
30
MIC
MPI
MIN
12
AVDD
VCOC
1
2
+
2
1
+
AVDD
C10
0.1u
1
47u
(short)
2
C13
C9
10u
2
2
2
1
1
L1
1
D
AVSS
+
REG
JP2
AIN
+
AVDD
1
SVSS
CN3
CN2
JP3
AVDD_SEL
VCOM
C8
4.7n
REG
31
U1
10k
32
AVSS
R2
C7
0.22u
MICOUT
D
C6
1u
1
1
R1
2.2k
2
C5
0.1u
+
2
AVSS
C4
2.2u
1
SVSS
T45_BU
1
SVDD
T45_BK
1
AVSS
T45_BU
1
VVDD
T45_O
1
DVDD
T45_O
1
AVDD
T45_R
1
REG
1
25
26
27
28
29
30
32
CN1
32pin_4
31
AVSS
B
AVDD
R7
51
JP9
AVDD DVDD_SEL
DVDD
L4
R10
51
R11
51
R12
470
R13
470
1
2
AVSS
C21
10u
DVDD
2
14
15
16
4632_FCK
4632_BICK
DVDD
13
4632_SDTO
CN4
LVC
12
DVDD
JP10
LVC_SEL
11
R40
(short)
4632_SDTI
DVDD
10
(short)
9
47u
+
R9
51
R14 10
2
C22
1
1
R8
51
+
B
32pin_2
LVC
L5
1
47u
+
D3.3V
2
(short)
VCC
A
Title
2
C23
1
A
JP11
VCC_SEL
CDTI
VCC(3.3V)
CCLK
VCC
CSN
AVSS
Size
A3
Date:
A
B
C
D
AKD4632
Document Number
Rev
AK4632
Wednesday, August 18, 2004
Sheet
E
0
1
of
5
A
B
C
D
E
J1
MIC-JACK
6
JP31
Dynamic
4
3
E
AVSS
J3
MIC
JACK
JP12
MIC_SEL
R15
10
INT
J2
SPK-JACK
SVSS
RCA
2
3
1
6
JP13
D1
A
K
MR-552LS
AVSS
SVSS
DIODE ZENER
C24
1u
2
JP15
MIN/MOUT
OUT
R16
20k
1
SPK1
SPP_SEL
JP14
D2
MOUT
C25
0.1u
IN
Dynamic(EXT)
Piezo(EXT)
Dynamic
020S16
CN5
+
J4
BEEP/MIN/MOUT
2
3
1
A
SVSS
K
DIODE ZENER
Dynamic(EXT)
Piezo(EXT)
Dynamic
R
2
SPN_SEL
1
AVSS
L
MR-552LS
R17
10
AVSS
D
E
3
4
SPP
C26
1u
2
1
+
R18
47k
JP16
D
SPN
MOUT
MIN
BEEP
MIN
R19
BEEP/MIN/MOUT
BEEP
20k
AVSS
R20
220
+
C28
1
AOUT
J5 AOUT
2
3
1
2
1u
R21
20k
MR-552LS
AVSS
AVSS
C
J6
VIN
C
R22
75
C29
2
3
1
VIN
2
3
1
VOUT
0.1u
R23
75
MR-552LS
AVSS
R41
100k
J7 VOUT
MR-552LS
AVSS
AVSS
AVSS
B
B
A
A
Title
Size
A3
Date:
A
B
C
D
AKD4632
Document Number
Rev
Input/Output
Wednesday, August 18, 2004
Sheet
E
0
2
of
5
A
B
C
D
E
for
74HCU04,74AC74,74VHC4040,74HC14,74HC14,74HC541,74HCT04
E
C30
0.1u
C31
0.1u
C32
0.1u
C33
0.1u
C34
0.1u
C35
0.1u
C36
0.1u
2
2
1
1
D3.3V
12.288MHz
X1
E
+ C37
47u
R24
1M
U2A
1
U2B
2
3
74HCU04
JP17
XTE
C38
(open)
4
74HCU04
C39
(open)
D
D
EXT_MCLK
3
MCLK_SEL
C
10
5
12
11
CLK
Q
D
PR
Q
6
U4B
74AC74
Q
9
256fs
512fs
1024fs
MCKO
JP18
MKFS
Q
U3
10
11
CLK
CL
R25
short
CL
DIR_MCLK
JP21
U4A
74AC74
1
XTL
DIR
EXT
D
VCC
8
13
2
PR
4
VCC
CLK
RST
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
9
7
6
5
3
2
4
13
12
14
15
1
74VHC4040
JP19
BICK_SEL
64fs
32fs
16fs
EXT
B
JP20
BICK
EXT_BICK
2
INV
U5A
74HC14
C
JP22
2fs
1fs
EXT
EXT_FCK
FCK_SEL
MCKO
J8
EXT/BICK
THR
1
2
3
1
B
R26
51
MR-552LS
AVSS
JP23
EXT1
J9
FCK
2
3
1
R27
51
MR-552LS
AVSS
JP24
EXT2
A
A
Title
Size
A3
Date:
A
B
C
D
AKD4632
Document Number
Rev
CLOCK
Wednesday, August 18, 2004
Sheet
E
0
3
of
5
A
B
C
D
E
C40 C41
0.1u 0.1u
D3.3V
L6
(short)
R28
10k
3
2
1
VCC
GND
OUT
U5B
0.1u
C43
10u
R29
470
4
1
3
74HC14
D3.3V
+
TORX141
2
D3
HSU119
E
U5C
6
5
74HC14
L
C44
0.1u
H
SW1
DIR
2
C45
0.1u
1
C42
3
PORT1
A
2
E
K
1
D3.3V
1
37
INT1
38
AVDD
39
40
R
AVSS
R30
18k
VCOM
41
42
RX0
43
NC
44
RX1
46
45
TEST1
NC
RX2
U6
16
15
14
13
12
11
10
9
47
SW3
1
2
3
4
5
6
7
8
RX3
DIF0
DIF1
DIF2
CM0
CM1
OCKS0
OCKS1
M/S
D
48
C46
0.47u
D
R31
1k
U7A
INT0
IPS0
36
1
LED1
ERF
2
K
A
D3.3V
74HC04
2
NC
OCKS0
35
OCKS0
DIF0
OCKS1
34
OCKS1
TEST2
CM1
33
CM1
DIF1
CM0
32
CM0
PDN
31
XTI
30
IPS1
XTO
29
P/SN
DAUX
28
XTL0
MCKO2
27
XTL1
BICK
26
DIR_BICK
SDTO
25
DIR_SDTI
RP1
3
CM0
CM1
OCKS0
OCKS1
M/S
4
5
47k
AK4114
C
6
7
NC
DIF2
C
C47
(open)
1
9
8
7
6
5
4
3
2
1
9
10
11
C48
(open)
2
X2
11.2896MHz
8
DAUX
B
B
2
1
C51
10u
LRCK
24
MCKO1
23
22
C50
0.1u
+
+
C49
0.1u
1
DVSS
DVDD
21
20
VOUT
UOUT
19
COUT
18
BOUT
17
TX0
TX1
16
14
13
15
DVSS
VIN
TVDD
12
DIR_FCK
JP25
MCKO_SEL
MCKO2
MCKO1
DIR_MCLK
2
C52
10u
D3.3V
D3.3V
PORT2
A
IN
VCC
GND
3
2
1
A
D3.3V
C53
0.1u
TOTX141
Title
Size
A3
Date:
A
B
C
D
AKD4632
Document Number
Rev
DIR/DIT
Wednesday, August 18, 2004
Sheet
E
0
4
of
5
A
B
C
D
U8
U9
1
E
11
Y8
A8
12
Y7
A7
13
Y6
A6
DAUX
14
Y5
A5
4632_SDTI
15
Y4
A4
16
Y3
A3
17
Y2
A2
18
Y1
A1
10
GND
G2
9
M/S
LVC
DIR
20
VCC
E
C54
0.1u
19
MCKO
E
8
4632_MCKO
7
EXT_MCLK
6
4632_SDTO
G
10
GND
RP2
4632_MCKI
RP3
7
6
5
4
3
2
1
JP26
4632_SDTI DAC/LOOP
2
3
47k
4
5
5
ADC
4
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
18
7
6
5
4
3
2
1
17
47k
16
15
D
D
6
3
7
2
VCC
13
JP27
BICK
ADC
12
DIR
C55
0.1u
20
8
4632_BICK
19
14
4632_FCK
1
G1
9
A8
EXT_BICK
DIR_BICK
11
B8
JP28
FCK
ADC
74LVC245
DIR
74LVC541
EXT_FCK
DIR_FCK
C
C
1
LVC
JP29
U10A
+ C56
47u
2
1
INV
2
THR
74HC14
BICK_INV
R32
R34
R36
D3V
10k
10k
10k
R33
R35
R37
U11
470
470
470
2
3
4
5
6
7
8
9
PORT4
1
2
3
4
5
B
10
9
8
7
6
CSN
CCLK
CDTI
1
19
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
18
17
16
15
14
13
12
11
CSN
CCLK
CDTI
PDN
4632_MCKI
PORT3
MCLK
BICK
FCK
SDTI
VCC
10
9
8
7
6
ROM
G1
G2
B
R38
74HC541
CTRL
1
2
3
4
5
D3V
10k
ADC
DAUX
K
D3V
A
D4
HSU119
JP30
SDTI
R39
10k
U5E
8
74HC14
11
10
U2C
74HC14
5
U7D
U2F
6
13
12
9
H
74HCU04
1
3
L
SW2
PDN
C57
0.1u
U7B
8
3
11
10
74HCU04
5
U10C
10
5
13
6
U10E
11
74HC14
U7F
6
74HC04
4
74HC14
74HC04
U7C
U2E
11
3
U7E
4
74HC04
74HCU04
U10B
8
74HC04
74HCU04
U2D
9
2
A
U10D
12
74HC04
9
8
74HC14
10
A
74HC14
U10F
13
Title
12
74HC14
Size
A3
Date:
A
DIR_SDTI
DIR
U5D
9
B
C
D
AKD4632
Document Number
Rev
LOGIC
Wednesday, August 18, 2004
0
Sheet
E
5
of
5
AKD4632-A
L1
AKD4632-A
L2
AKD4632-A
L1̲SILK
AKD4632-A
L2̲SILK