ACE9050 System Controller and Data Modem Advance Information FEATURES ■ Low Power, Low Voltage (3·6 to 5·0 V) Operation ■ 3·0V Memory Interface ■ Power Down and Emulation Modes ■ 6303R-type Microcontroller ■ AMPS or TACS Modem ■ Watchdog and Power Control Logic ■ SAT Detection, Generation and Loopback ■ 6K bytes RAM ■ Interface to FLASH and EEPROM Memories ■ 512 byte ROM Boot Block ■ I/O Ports for Keyboard Scanning ■ I2C Controller ■ Small Outline 100-pin package APPLICATIONS ■ AMPS and ETACS Cellular Telephones ■ Two-way Radio Systems RELATED PRODUCTS The ACE9050 is part of Mitel Semiconductor's ACE chipset, together with the following: ACE9020 Receiver and Transmitter interface ACE9030 Radio Interface and Twin Synthesiser ACE9040 Audio Processor ORDERING INFORMATION Industrial temperature range. TQFP 100-lead 14314mm, 0·5mm pitch package (FP100) ACE9050D / IG / FP8N: trays and dry packed ACE9050D / IG / FP8Q: tape mounted and dry packed ABSOLUTE MAXIMUM RATINGS Supply voltages VDD, VDDM Storage temperature Operating temperature Voltage on any pin 20·5V to 16V 255°C to 1150°C 240°C to 185°C VSS20·5V to VDD10·5V OUTP2 [6] ICN LATCH1 OUTP2 [7] LATCH0 PWM2 DTFG EMUL IRQN POFFN VSS VSS VDD EXRESN C1008 MRN A15 A14 CPUCL R/W BAR DTMS PWM1 ECLK RXCD 75 76 51 50 BA17 BA16 BA15 BA14 A13 A12 A11 A10 A9 A8 A7 A6 VDDM VSS VSS A5 A4 A3 A2 A1 A0 CSE2N CSEPN WEN OEN ACE9050 100 1 26 25 TESTN XIN XOUT DFMS AS BAUDCLK P1 [7] P1 [6] SCL/P1 [4] VSS VDD P1 [5] SDA/P1 [3] P1 [2] P1 [1] P1 [0] VSS D7 D6 D5 D4 D3 D2 D1 D0 The ACE9050 provides the control and interface functions needed for AMPS or TACS analog cellular handsets. The device has been designed using Mitel Semiconductor submicron CMOS technology for low power and high performance. The ACE9050 contains an embedded microcontroller and peripheral functions. The controller is of the 6303 type with a Serial Communication Interface, Timer, ROM and RAM. The peripheral functions are: Data Modem, SAT Management, Serial Chip Interfaces, I 2C Interface, two Pulse Width Modulators, IFC Counter, Tone generator, I/O ports, Watchdog and Crystal Oscillator. Several power down modes are incorporated in the device as is a processor emulation mode for software and system development. An index to this data sheet is given on pages 49 and 50. DS4290 - 3.0 December 1997 LATC H3 SERV SYNTHCLK SYNTHDATA INRQ0 INRQ1 KPI [3] KPI [2] KPI [1] KPI [0] VDD VDD TXDATA TXSAT TXPOW AFC/RXDATA KPO [4] KPO [3] KPO [2] KPO [1] KPO [0] INP1[4] INP1[3] INP1[2] RXSAT Supersedes January edition, DS4290 - 2.3 FP100 Fig.1 Pin connections - top view. Pin 1 is identified by moulded spot and by coding orientation. See Table 1 for detailed pin descriptions. CLOCK & BAUD GENERATOR MEMORY INTERFACE WATCHDOG & POWER CONTROL I/O PORTS KEYPAD INTERFACE ACEBus INTERFACE 6303R MICROPROCESSOR UART (SCI) TIMER I/O PORTS 0·5K ROM 6K RAM I2C BUS INTERFACE 23PULSE WIDTH MODULATOR INTERRUPT CONTROL AMPS / TACS DATA MODEM IFC COUNTER TONE GENERATOR SAT MANAGEMENT Fig.2 ACE9050 simplified block diagram ACE9050 SYNTHDATA SYNTHCLK DTFG LATCH0 LATCH1 LATCH3 72 SYNTHDATA 73 SYNTHCLK 82 ACE SERIAL INTERFACE DTFG 80 ONRAD SINTSLEEP C1008 IRQSEND IRQREC PORT3[6] PORT4[7] }INTERRUPTS LSICOM0 LSICOM1 LATCH1 LSICOM2 LSICOM3 LATCH3 LSICOM4 LSICOM5 LATCH2 LSICOM6 MRI IRW ID[7:0] STR_WIDTH 78 75 83 PWM #2 PORT4 [7:0] 46-41 6 92,93 2 PORT3 PORT4 PORT4 TO MUX #1 MRI IRW ID[7:0] LVN1 OUT2 [0] TO CPUCL PIN INP1 [7] POWERDET INP1 [6] SERV I/P PORT1 IN_PORT1 INP1 [4:2] INTERNAL ADDRESS ID [7:0] IRQPRT4-RESET IRAM DECODER EPROM 27 IROM KEYP R/W TO PORT IRW KPOT O/P TRISTATE IROM IROME PORT4 [1] PORT3 [1] 6303 MICROPROCESSOR AND IRW READ/WRITE KERNEL AD15:O PORT2 [4] EMUL INTERRUPT IRQN PORT5 [2] 84 6 83BAUD I2C_ADDR I2C P1 [4] ISDA P1 [3] IRQTX I2C_INTERRUPT IRQWS INT IRQPRT2-READ IRQBISAT IRQRX IRQSEND 8·064MHz PORT3 [0] STIFCN (START/RESET) PORT3 [5] INTERRUPTS VDDM VSS IRQTO IRQRX MODPRT0 IRQBISAT CLOCK GENERATOR MODPRT1 IRQWS PORT5 [6] MODPRT2 IRQTX ID [7:0] 11, 64, 65, 68 PORT4 [4] NOMPLL 38 PORT3 [3] MDMSLP 10, 17, 36, 37, 86, 87 PORT3 [7] ENMOD IRW BARPORT TEST ACCESS ONLY MRN RXCD TXPOW PORT4 [2] REWD MASTER RESET 91 WATCHDOG AND RESET LOGIC MRI TURBO PORT3 [2] ENSIS 99 3 C1008 CLKBUS 1 SAT MUX LVN1 PORT5 P[1] CPUCL/ OUTP2 [0] C1008 ECLK XIN XOUT TESTN C1008 LVN1 TO WATCHDOG AND I2C 63 62 51 89 TXDATA TXSAT RXSAT EXRESN RESATO 100 FILTER 61 ATO LOGIC IRQTO 85 CLKBUS IRW TESTN INP1 [7] POWDET PORT3 [4] UPOFFN Fig. 3 detailed block diagram of ACE9050 2 PORT4 [3] 90 2 SELECT SAT GENERATOR 94 E (CPU CLOCK) SAT MANAGEMENT WATCHDOG AND ATO CPUCL OUT2 [0] MRI TXDATA 74 XOSC-PD CLKENAB INP1 [6] SERV INTERRUPT CONTROL INTERRUPT SOURCE MRI IRW ID[7:0] MODEM AFC/RXDATA 54kHz/450kHz VDD IRQPRT0-RESET IRQREQ 126kHz P1 [7:0] DFMS/P2 [4] DTMS/P2 [3] IRQN BAUDCLK IRQPRT1-MASK ISCL I2C_CCR IFFREQ (2432/256) KPI [3:0] IRQE (EXTERNAL INT.) MRI IRW ID[7:0] TESTN CLKBUS IRW ID[7:0] IFC COUNTER KPO [4:0] IRQN I2C INTERRUPT BRG BARLOW MRI ID[7:0] CLKBUS 60 7-9, 12-16 PORT2 [3] ENABLE RESET I2C I2C_STAT BARHIGH AFC/RXDATA 66-69 4 BAUD RATE CLOCK BARENABLE ICN 4 97 BAUDCLK I2C_CNTR 77 59-55 8 PORT1 [7:0] ID7:0 BEEP ALARM RING GENERATOR (BAR) ICN (EMUL) 5 INRQ [1:0] ISDA ISCL I2C_DATA TO 6303 70, 71 MRI IRW ID[7:0] RESET MRI CLOCK E MRI IRW AD[15:0] SLEEP BAR AD [8:0] ICN COUNTER I/P MEMORY SELECTS IRAM KEYPORT/CHIP ID ID [7:0] ROM 512 BYTES (IROM) BOOT BLOCK ACE9050 REGISTER SELECTS IRQPRT5 2 IRQPRT5-MASK IRQPRT6-READ BANK_SEL 26 INP1 [4:2] EXT. INTERRUPTS IRW MEMORY BANK SWITCHING EPROM MRI IRW ID[4:0] AD[15:14] 96 IRQE 54, 53, 52 3 INP1 [1:0] AD [12:0] OUTP2 [7] OUTP2 [6] NOT BONDED OUT2 [5:3] OUT_PORT2 TO MUX #2 RAM 6016 BYTES (IRAM) 28 76 OUT2 [1] EMUL IP 29 79 OUT2 [6] PORT5 EMUL IP IRQPRT4 BAR O/P PORT2 DATA AD15:0 4 50-47 PORT3 PORT5 OUTP2 [2]/ PWM2/ LATCH2 EXTERNAL PORTS O/P IN EMULATION ID7:0 EMUL DATA/AD 40,39,35-30 8 81 MUX #2 OUT2 [2] LATCH2 OUT2 [2] PORT5 [7:0] OUTP2 [1]/ PWM1 MUX CONTROL OUT2 [7] PORT3 [7:0] REFER TO TEXT FOR INDIVIDUAL BIT FUNCTIONS 98 MUX #1 PORT5 [0] } PORT5 [5:4] INTERNAL PORTS IRW EMUL IP 8 18-25 OUT2 [1] CONTROL EMUL ONLY 95 IN_PORT1 WEN DAC2 BUS INTERFACE 5 OUT_PORT2 OEN PWM #1 MRI IRW ID[7:0] TO 6303 BA [17:14] CSE2N CSEPN DAC1 LATCH0 TO MUX #2 EMUL AS R/W D [7:0] A [7:0] A [13:8] A [15:14] PULSE WIDTH MODULATOR POFFN ACE9050 FUNCTIONAL OVERVIEW MICROPROCESSOR UNIT The processor unit is program compatible with the standard 6303R. It contains the following hardware: 8-bit CPU Serial Communication Interface: SCI (UART) 16-bit timer/counter 8-bit l/O port (P1) 2-bit l/O port (P2) The processor bus speed can be either 1·008 MHz or 2·016 MHz. An Emulation mode is provided whereby the internal 6303 is bypassed to allow software development on a standard 6303 In-Circuit Emulator (ICE). MEMORY The ACE9050 contains 512 bytes ofROM and 6144 bytes of RAM internally. The ROM code facilitates system initiation after a reset and the programming of FLASH memory via the 6303 SCI (UART). The Internal RAM area represents the total RAM requirement anticipated for a cellular phone. BUS INTERFACE and MEMORY BANK SWITCHING These blocks create the Data, Address and Control lines for the external memory. The external address bus is expanded from the standard 16 bits up to 18 bits by a banked addressing scheme. This increases the memory address space from 64K to 256K. Two programmable Chip Selects (CSEPN and CSE2N) are generated. The Memory Interface will operate down to 13V, allowing the use of low voltage memory parts. In Emulation mode the external processor controls the ACE9050 via the Bus Interface block. EXTERNAL PORTS The ACE9050 contains two Keypad Interface ports, two maskable external interrupts, and both Input and Output ports. These are in addition to the 6303 bidirectional Port1 and Port2. The Output port provides two high current outputs for driving LEDs. DECODER and INTERRUPT CONTROL The Decoder block memory maps ACE9050 register locations onto the processor’s address space. The Interrupt Control block handles both internal and external interrupt sources. These are fed into control logic allowing individual masking and reset by software. The Interrupt control logic output is internally connected to the 6303 IRQ and also drives an external pin. ACE SERIAL INTERFACE (SINT) and I2C Three serial interface protocols are supported: UART, I2C and ACEBus. The 6303 provides a UART interface via the SCI block. The ACE9050 I2C block provides an I2C interface with both Master and Slave capability. The ACEBus is designed for use with the ACE Chipset and has a data rate of just over 1MBits/sec. Three Latch pulse are available to target data at the relevant IC and control the ACE9030 Synthesiser. BEEP, ALARM and RING TONE GENERATOR (BAR) The BAR Generator is intended to drive an acoustic tone transducer. It has a programmable single digital pulse train output. MODEM and SAT MANAGEMENT The Modem provides two way data transfer and SAT management over the radio link between a base station and phone handset. AMPS and TACS data rates are supported . The Modem block contains: Digital Discriminator, Data Decoder and Word Synchronising hardware. Various modes can be selected by software. A squelch level is also set by software so that the quality of each data byte can be assessed. SAT detection and generation at the standard three frequencies 5970Hz, 6000Hz and 6030Hz is included. WATCHDOG and POWER CONTROL (ATO) The Watchdog function will provide an internal and external Reset if the processor does not make a write access to a defined address every 4 seconds. An Autonomous Time Out circuit (ATO) will drive the POFFN output low if Transmitter power is detected without Receiver power, independent of any processor operation. POFFN must be used in conjunction with external regulators to control power to the mobile handset. IF CONTROL COUNTER (IFC) The Intermediate Frequency Control (IFC) Counter is used as part of an AFC Loop. The IFC Counter provides a pulse after a set number of IF input pulses. The IFC Counter output is connected to the 6303 timer input and an external pin (ICN). TWIN PULSE WIDTH MODULATORS Two independently programmable Pulse Width Modulators (PWMs) are available. These provide digital output pulse trains, controllable by software. The output can be filtered externally to provide a DAC function. Typical applications are battery charging control and LCD contrast control. CLOCK GENERATOR The Clock Generator provides all the various internal and external clocks from a single 8·064 MHz source. The source can either be an external crystal or the ACE9030. 3 ACE9050 PIN DESCRIPTIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Name TESTN XIN XOUT DFMS/P2 [4] AS BAUDCLK P1[7] P1[6] P1[4]/SCL VSS VDD P1[5] P1[3]/ SDA P1[2] P1[1] P1[0] VSS D7 D6 D5 D4 D3 D2 D1 D0 OEN WEN CSEPN CSE2N A0 A1 A2 A3 A4 A5 VSS VSS VDDM A6 A7 A8 A9 A10 A11 A12 A13 BA14 BA15 BA16 BA17 RXSAT INP1 [2] INP1 [3] INP1 [4] KPO [0] KPO [1] KPO [2] KPO [3] KPO [4] AFC/RXDATA TXPOW TXSAT TXDATA VDD VDD Type I I O I/O I O (I) I/O I/O I/O CLK/WDATO CLK CLK CPU BINT BAUD CPU CPU CPU / I2C I/O I/O I/O I/O I/O CPU CPU / I2C CPU CPU CPU I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O BINT BINT BINT BINT BINT BINT BINT BINT DEC DEC MEMB MEMB BINT BINT BINT BINT BINT BINT O O O (I) O (I) O (I) O (I) O (I) O (I) O O O O I I I I O O O O O I I O O Description Internal Connect to VDD Crystal connection CMOS input: 8·064 MHz Crystal connection CPU Port2 bit 4 or Serial interface (SCI) output Address strobe (Latch Address during Emulation) Baud Rate Gen. output for Emulation (lnput in test mode) PORT 1 of CPU PORT 1 of CPU PORT 1 of CPU/I2C SCL Ground Digital Supply PORT 1 of CPU PORT 1 of CPU/I2C SDA PORT 1 of CPU PORT 1 of CPU PORT 1 of CPU Ground Data bus (and Emulation Address A7 Input) Data bus (and Emulation Address A6 Input) Data bus (and Emulation Address A5 Input) Data bus (and Emulation Address A4 Input) Data bus (and Emulation Address A3 Input) Data bus (and Emulation Address A2 Input) Data bus (and Emulation Address A1 Input) Data bus (and Emulation Address A0 Input) Output Enable Write Enable C/S External EPROM C/S External EEPROM Address bus Address bus Address bus Address bus Address bus Address bus Ground Ground Digital Supply for Memory Interface (pins18-35, 38-50) Address bus Address bus Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Extended Address: From Bank Select Register) Address bus (Extended Address: From Bank Select Register) Address bus (Extended Address: From Bank Select Register) Address bus (Extended Address: From Bank Select Register) Received SAT input Bit 2 Input Port1 Bit 3 Input Port1 Bit 4 Input Port1 Keypad scan output/output port Keypad scan output/output port Keypad scan output/output pon Keypad scan output/output port Keypad scan output/output port 54/450kHz IF input fromACE9030 Power detect from transmitter SAT Output TACS / AMPS Modem Output Digital Supply Digital Supply PU None None PU PU None None None None None None None None None None None None None None None None None None None None None None None None None None None None - Block BINT BINT BINT BINT BINT BINT BINT BINT MEMB MEMB MEMB MEMB MODEM EPORT EPORT EPORT EPORT EPORT EPORT EPORT EPORT IFC/MODEM WDATO MODEM MODEM Table 1 4 Cont… ACE9050 Pin Name Type 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 KPI [3] KPI [2] KPI [1] KPI [0] INRQ1 INRQ0 SYNTHDATA SYNTHCLK SERV LATCH3 OUTP2 [6] ICN LATCH1 OUTP2[7] LATCH0 OUTP2[2]/PWM2/ LATCH2 DTFG EMUL IRQN POFFN VSS VSS VDD EXRESN C1008 MRN A15 A14 CPUCL/OUTP2 [0] R/W BAR DTMS OUTP2 [1]/PWM 1 ECLK RXCD I I I I I I O O I O O O (I) O O O O EPORT EPORT EPORT EPORT EPORT EPORT SINT SINT WDATO SINT EPORT IFC SINT EPORT SINT PWM I/O I O (I) O SINT BINT/CPU CPU WDATO O O I I I O O (I) O I/O O O (I) I WDATO CLK WDATO BINT BINT CLK/EPORT BINT BAR CPU PWM CLK WDATO 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Description Block Internal Keypad scan input/input port Keypad scan input/input port Keypad scan input/input port Keypad scan input/input port External Interrupt (also Bit1 Input Port1) External Interrupt (also Bit0 Input Port1) SynthBus Data Line SynthBus 126kHz Clock 1 = Service Mode Latch, programmable length. (To ACE9030, LATCHC pin) Output Port2 Bit 6: High Current Driver IF Counter Output for Emulation (input in Test mode) Latch O/P (To ACE9030 receiver Interface, LATCHB pin) Output Port2 Bit 7: High Current Driver Latch O/P (To ACE9040, LEN ) Output Port2 Bit 2/Pulse Width Modulator #2 Output/ SynthBus Latch O/P. Bidirectional serial inter-chip data, to/from the ACE9030 1 = CPU Emulation Mode CPU Interrupt for Emulation (input in Test mode) Power On/Off Ground Ground Digital Supply External reset output 1·008MHz Clock for ACEBus, ACE9030 and ACE9040 0 = Chip reset Address input for Emulation only Address input for Emulation only 8.064MHz clock/Out Port 2 bit 0 Read/Write (Input during Emulation) Beep, Alarm, Ring Tone Output CPU Port 2 bit 3 or Serial interface (SCI) input Output Port 2 Bit 1/Pulse Width Modulator #1 Output Processor Clock (Input during Emulation) Carrier detect from RX PD PD PD PD PD PD None PU None PD None PU PU None None None None Table 1 (continued) ABBREVIATIONS BAR Beep, Alarm and Ring tone generator BAUD Baud Rate generator BINT Bus Interface MEMB Memory Bank switching CLK Clock generator CPU 6303 microprocessor unit DEC Decoder EPORT External Port I2C IFC MODEM PWM SINT WDATO PU PD I2C interface IF Control counter AMPS/TACS Modem Pulse Width Modulator and MUX Serial Inter-chip interface Watchdog/Autonomous Time Out Internal Pullup resistor present Internal Pulldown resistor present UNUSED INPUTS Input or bidirectional pins must have a suitable pullup or pulldown reststor if they are configured as inputs, with no external drive. Some inputs have an internal pullup or pulldown resistor of the order of 100kΩ; this value is suitable if the pin is not subject to excessive noise or residual current greater than 15µA. If the pins shown in Table 2 are not used in the system, an external resistor will be required. Pin 4 7 8 9 12 13 14 Name DFMS P1 [7] P1 [6] P1 [5] P1 [4] P1 [3] P1 [2] Pin 15 16 51 52 53 54 60 Name P1 [1] P1 [0] RXSAT INP1 [2] INP1 [3] INP1 [4] AFC_IN/RXDATA Pin Name 61 74 82 TXPOW SERV DTFG (Requires programming resistor) MRN DTMS RXCD 91 97 100 NOTE: P1 [7:0], DFMS and DTMS are configured as inputs upon reset. Table 2 5 ACE9050 ELECTRICAL CHARACTERISTICS The Electrical Characteristics are guaranteed over the following range of operating conditions (unless otherwise stated): TAMB = 240°C to 185°C, VDD = 3·6V to 5·5V, VDDM = 3·0V to 5·5V (note 2) DC CHARACTERISTICS Value Characteristic Symbol Supply current (Normal clock) Supply current (Turbo clock) Supply current (Static) Input high voltage Input low voltage Output high voltage IDDNOR IDDTUR IDDSB VIH VIL VOH Output low voltage VOL High current drive O/P source (pins 76 & 79) IOHHI High current drive O/P sink (pins 76 & 79) IOLHI Tristate leakage current Input leakage current Pullup/down resistance IOZ IIN RIN Typ. Min. Max. 3·5 6·0 150 0·7VDD 20·5 0·8VDD 0·2VDD 0·92VDD 0·2 35 Units Conditions mA mA µA V V V 1·008MHz ECLK, VDD = 5V 2·016MHz ECLK, VDD = 5V No clock & osc. powered down 0·4 V 10 6 10 9 1 1 150 mA mA µA µA kΩ IOH = 2mA, VDD > 3·6V IOL = 1mA, VDD < 3·6V IOH = 2mA, VDD > 3·6V IOL = 1·5mA, VDD < 3·6V VDD > 3·6V VDD = 3·6V VDD > 3·6V VDD = 3·6V No Pullup/down cell No Pullup/down cell VDD = 5·5V, TAMB = 25°C NOTES 1. The DC Characteristics Min. and Max figures are guaranteed by test. 2. The voltage on VDDM must be less than or equal to VDD. AC CHARACTERISTICS (CLOCKS and CRYSTAL) Value Characteristic Oscillator frequency Oscillator external I/P AC coupling capacitor External resistor External capacitors Crystal ESR Startup time Radio serial control bus Microprocessor clock Microprocessor clock Clock output Watchdog time out Autonomous time out Symbol fOSC fIP CCOUPLE R1 C1, C2 XTALESR tSU C1008 ECLK1 ECLK2 CPUCL WDTO ATOTO NOTES 1. Refer to crystal manufacturer for exact deatils. 6 Min. 470 Typ. Max. 8·064 8·064 10 1000 22 120 5 1·008 1·008 2·016 8·064 4 30 Units Conditions MHz MHz nF kΩ pF Ω ms MHz MHz MHz MHz s s External crystal CMOS/800mV sine I/P AC coupled Sine input Crystal oscillator Crystal oscillator (note 1) Crystal oscillator Crystal oscillator Normal clock Turbo clock Output enabled Normal Mode Normal Mode ACE9050 TIMING DIAGRAMS NORMAL MODE PROCESSOR INTERFACE Read Cycle tECLK ECLK ADDR tCSLCLL tCLLADI tCLLCSH CS tADVCSL tCLLOEH tOELCLL OEN tCLLDAI tDAVCLL DATA Fig.4 ACE9050 6303 Read cycle timing diagram Timing Cycle Conditions Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 185°C, VDD = 13·6V to 15·5V Typical timings: TAMB = 125°C, VDD = 13·75V Normal clock Description Cycle time Address valid to CS low Chip Select set-up time OEN set-up time Data set-up time Data hold time OEN hold time CS hold time Address hold time Symbol tECLK tADVCSL tCSLCLL tOELCLL tDAVCLL tCLLDAI tCLLOEH tCLLCSH tCLLADI Min. 2 940 485 35 0 0 9 7 Turbo clock Typ. Max. Min. 992 4 972 492 9 985 495 1 24 18 4 45 42 2 445 240 35 0 0 9 7 Typ. Max. 496 4 480 245 9 490 248 1 24 18 4 45 42 Units ns ns ns ns ns ns ns ns ns Table 3 ACE9050 6303 Read cycle timing 7 ACE9050 Write Cycle (Normal Mode) tECLK ECLK ADDR tADVWEH tWEHADI CS tADVCSL tCSLWEH WEN tWEHCSH tWELWEH DATA tADVDALZ tWEHDAI tDAVWEH Fig. 5 ACE9050 6303 Write cycle timing diagram Timing Cycle Conditions Input clock frequency, XIN = 8·064MHz. Worst case timings: TAMB = 240°C to 185°C, VDD = 13·6V to 15·5V Typical timings: TAMB = 125°C, VDD = 13·75V Normal clock Description Cycle time Address valid to end of Write Address hold time Chip enable set-up time WE pulse width Data valid set-up time Data hold time Address valid to data low Z Address valid to chip select WE high to CS high Symbol tECLK tADVWEH tWEHADI tCSLWEH tWELWEH tDAVWEH tWEHDAI tADVDALZ tADVCSL tWEHCSH Min. 835 125 825 363 365 120 451 0 127 Turbo clock Typ. Max. Min. 992 853 140 840 364 368 862 151 860 371 371 473 5 140 487 10 163 395 63 390 173 177 60 203 0 66 Table 4 ACE9050 6303 Write cycle timing 8 Typ. Max. 496 420 72 415 181 183 427 93 425 184 192 225 4 72 239 9 105 Units ns ns ns ns ns ns ns ns ns ns ACE9050 EMULATION MODE PROCESSOR INTERFACE Read and Write Cycles tCYC ECLK AS tECLRWV R/W INVALID STABLE INVALID tECLADI tECLADV A[15:8] tADVASL tDAV tASLADI AD[7:0] A[7:0]/D[7:0] tDAI DA[7:0] Fig.6 ACE9050 6303 Emulation mode Read/Write cycles timing diagram Emulation Mode Timing Cycle Conditions Input clock ECLK frequency = 1·008MHz (Normal clock), 2·016MHz (Turbo clock), TAMB = 125°C, VDD = 15V 610% Normal clock Description Cycle time Read/Write settling time Address delay time Address hold time Address to latch set-up time Address to latch hold time Data set-up time - WRITE Data hold time - WRITE Data set-up time - READ Data hold time - READ Symbol tCYC tECLRWV tECLADV tECLADI tADVASL tASLADI tDAV-W tDAI-W tDAV-R tDAI-R Min. Typ. Turbo clock Max. Min. Max. 496 992 250 250 0 60 30 50 1 80 1 Typ. 160 160 0 20 20 50 1 80 1 Units ns ns ns ns ns ns ns ns ns ns Table 5 6303 Emulation Mode Read/Write cycles timing 9 ACE9050 SERIAL INTERFACE BLOCK ACEBus Read and Write Timings C1008 DATA1 DTFG 7 6 5 4 DATA2 3 2 1 0 7 6 5 4 DATA3 3 2 1 0 7 6 5 4 3 2 1 0 LATCH1 Fig.7 ACEBus Transmit Data flow C1008 1 2 DTFG 3 4 5 PREAMBLE DATA3 7 6 5 4 3 2 RESULT1 1 0 7 6 5 4 RESULT2 3 2 1 0 7 6 5 4 3 2 1 0 LATCH1 Fig.8 ACEBus Receive Data flow tDAVCLH tCLH tCLL tCLLDAZ tCLHDAI C1008 DTFG D1 [7] D1 [6] D3 [2] D3 [1] D3 [0] t CL H D A SYNTHDATA LATCH0/1/3 tCLHLAH tPW Fig.9 ACEBus Transmit timing diagram C1008 DTFG tDAVCLL Fig.10 ACEBus Receive timing diagram 10 tCLLDAI ACE9050 ACEBus Timing Cycle Conditions Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 1 85°C, VDD = 13·6V to 15·5V Typical timings: TAMB = 125°C, VDD = 13·75V Value Characteristic Symbol TRANSMIT Clock high to Data bus driven Data set-up time Data hold time Clock high to Latch high Latch width 0 and 1 Latch width 3 Clock low Clock high Clock high to data line tristate RECEIVE Data set-up time Data hold time Min. tCLHDA tDAVCLH tCLHDAI tCLHLAH tPW01 tPW3 tCLL tCLH tCLHDAZ 491 488 491 491 491 0·099 tDAVCLL tCLLDAI 14 14 Typ. Max. 496 12·59 496 496 0 5 Units ns ns ns ns ns ms ns ns ns Conditions Programmable width ns ns Table 6 ACEBus Read and Write timings SynthBus (Note: The SynthBus is not required when the ACE9050 is used as part of the ACE Chipset) tCLH tCLL tD17VCLH SYNTHCLK SYNTHDATA D1-7 D1-6 tDAVCLH D3-1 D3-0 tCLHDAI DTFG LATCH tLAH tCLHLAH Fig.11 SynthBus timing diagram SynthBus Timing Cycle Conditions Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 185°C, VDD = 13·6V to 15·5V Typical timings: TAMB = 125°C, VDD = 13·75V Value Characteristic Symbol First data bit set-up time Data bit set-up time (except first) Data hold time Clock high to latch high Latch width Clock low Clock high tD17VCLH tDAVCLH tCLHDAI tCLHLAH tLAH tCLL tCLH Min. Typ. >0 Max. 7·84 3·9 4·0 4·97 952 3·99 3·93 Units Conditions µs µs µs µs ns µs µs Table 7 SynthBus timing 11 ACE9050 INTERNAL REGISTERS AND RESET STATUS ACE9050 REGISTERS Name R/W Address IN_PORT1 OUT_PORT2 PORT3 BARPORT IRQPRT2 IRQPRT6 MODPRT0 MODPRT1 MODPRT2 KEYP LSICOM4 LSICOM5 LSICOM6 PORT4 PORT5 BANK_SEL RESERVED BARHIGH BARLOW BARENABLE BRG I2C_ADDR I2C_DATA I2C_CNTR I2C_STAT I2C_CCR DAC1 DAC2 LSICOM0 LSICOM1 LSICOM2 LSICOM3 STR_WIDTH KPOT REWD RESAT0 IRQPRT0 IRQPRT1 IRQPRT4 IRQPRT5 R R/W R/W 22-23 24-25 26-27 28-29 2C-2D 2E-2F 30-31 32-33 34-35 36-37 3A-3B 3C-3D 3E-3F 40-41 42-43 44 45 50 51 52 53 54 55 56 57 57 5B 5C 60-61 62-63 64-65 66 67 68-69 6A-6B 6C-6D 70-71 72-73 74-75 76-77 R R R/W R/W R/W R/W R R R R/W R/W W W W W W R/W R/W R/W R W W W W W W W W W W W W W W W Description External IP Port External OP Port Internal Port Test-Do Not Access Read Int Interrupts Read Ext Interrupts Modem Modem Modem Key Pad IP and Chip ID ACE Interface RX1 ACE Interface RX2 ACE Interface RX3 Internal Port Internal Port Bank Select Do Not Access BAR On BAR Off BAR OE UART Baud select I2C I2C I2C I2C I2C PWM 1 data PWM 2 Data ACE Interface TX1 ACE Interface TX2 ACE Interface TX3 ACE Interface Control Latch 3 Width O/P type for KPO Reset Watchdog Reset Time Out Reset Int Interrupts Mask Int Interrupts Reset Ext Interrupts Mask Ext Interrupts D7-0 reset condition Notes EE0EEE00 1, 6 00000000 00000000 2 111X111 XXXX1111 00000000 00000000 00000000 0010EEEE 3, 7 EEEEEEEE EEEEEEEE EEEEEEEE 6 4, 6 4, 6 4, 6 00000010 00000011 XXX00000 7 00000000 00000000 XXXXXX0 XXXXX000 00000000 00000000 00000000 11111000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 XXX11111 7 5, 7 XXXXXXXX XXXXXXXX 7 7 7 00000000 (Reset) 00000000 (Masked) XXXX0000 XXXX0000 7 7 Table 8 ACE9050 ports NOTES: 1. Bit 6 is set (1) in SERV mode. Bits 1 and 0 are set (1) if the corresponding interrupt is enabled (inverse of IRQPRT6). 2. Bit 4 (UPOFFN) is set (1) in SERV mode, but reset (0) in Normal mode. 3. Bit 4 is not used and should be treated as undetermined. 4. The LSICOM4, 5 and 6 ports values will depend on the DTFG input. 5. In SERV mode the Boot block will set up BRG to 00000100 (9600 Baud). 6. E = Depends on external input. 7. X = Not used or undetermined. 12 ACE9050 ACE9050 6303 REGISTERS Name R/W Address Description D7-0 reset condition Notes DDR1 DDR2 PORT1 PORT2 TCSR FRC_HIGH FRC_LOW OCR_HIGH OCR_LOW ICR_HIGH ICR_LOW RMCR TRCSR RDR TDR RAMCR W W R/W R/W R/W R/W R/W R/W R/W R R W R/W R W R 00 01 02 03 08 09 0A 0B 0C 0D 0E 10 11 12 13 14 Data Dir Register P1 Data Dir Register P2 Data Port 1 Data Port 2 Timer Control/Status Free Run Counter MSB Free Run Counter LSB O/P Compare Reg MSB O/P Compare Reg LSB I/P Capture Reg MSB I/P Capture Reg LSB Rate & Mode Control Tx/Rx Control and Status Rx Data Tx Data Not Used 00000000 00000000 1 1 2 3, 4 EEEEEEEE 010XXXXX 00000000 00000000 00000000 11111111 11111111 00000000 00000000 XXXX0000 00100000 00000000 00000000 00000000 4, 5 6 7 Table 9 6303 ports NOTES: 1. Both ports set to Input (0 = I/P, 1 = O/P) 2. E = external input 3. 6303 internally set to Multiplexed mode 4. X = Unused or undetermined 5. Set to 00001100 in SERV mode 6. Set to 00111010 in SERV mode 7. This register Read only in the ACE9050 MODES OF OPERATION The ACE9050 has three independent modes of operation: Normal, Emulation, Service. Mode Emulation Service Normal Pin EMUL SERV - Enabled High High Default mode Table 10 Modes of operation 1, NORMAL MODE This is intended to be the mode of operation when the ACE9050 is fully commissioned in the application. The internal 6303 Microprocessor is used and the Boot block ensures the program counter goes to the beginning of the ROM code area after initialisation. In Normal mode various blocks can be powered down to save current, and the processor can be programmed to run at 1·008MHz or 2·016MHz. 2. EMULATION MODE This mode is intended for system and software development work. In Emulation mode the Internal 6303 processor is made redundant and its function is replaced in the system by an external 6303 processor. This is to facilitate using a generic 6303 In-Circuit Emulator (ICE) for software development. Table 11 shows the functionality of external pins that change in this mode. This is to enable all of the internal functions of the ACE9050 to operate as they would in Normal mode. In Emulation mode the external processor or ICE must be set up to operate in Multiplexed mode. This mode is only intended for use at room temperature. Normal mode Emulation mode Function Type Pin D[7:0] A[13:8] A[15:14] ECLK R/W AS IRQN ICN Data Address Not used 6303 Clk Not used Not used Not used Not used I/O O I O O I O O Function Data and A[7:0] I/P Address I/P A[13:8] Address I/P A[15:14] ACE9050 Clock I/P Read/Write strobe Address Latch strobe 6303 Interrupt 6303 Timer P2 [0] Type I/O I I I I I O O Table 11 Normal and Emulation mode functions 3. SERVICE MODE This mode is intended for system development and phone service, where reprogramming of a FLASH ROM device is required. The two areas that are affected by Service mode are: 1. The Watchdog and Autonomous Time Out (ATO) resets are inhibited. This is intended for software development work. The POFFN pin (85) is initially programmed to be a 1 by the ROM code in this mode. 2. The internal ROM code facilitates loading of a program into the RAM area from the SCI. This program would normally be a FLASH loading program. The SCI may then be used to load new object code into the FLASH memory of a system. 13 ACE9050 The ROM code has a time out function so that if a valid start code is not detected on the SCI normal code operation will begin. The ROM code is fully described in the Internal ROM Boot Block section. 4. TEST MODE Test mode increases the efficiency of volume testing of the part. Pin 1, TESTN, should be hardwired to VDD. 5. POWER DOWN MODES To reduce overall power consumption, selective power down of various blocks is available under software control. In the power down state each block will go to a predetermined logic state. The following power reduction features are included: Bus Interface (CSEPN = 1 and Address = 3FFF) 8·064 MHz external Clock Off 1·008 MHz external Clock Off AMPS/TACS Modem power down ACE Serial Chip Interface Power down CPU Sleep Mode Crystal Oscillator Off 1MHz/2MHz Bus speed FUNCTIONAL DESCRIPTIONS 1. ACE9050 6303R DESCRIPTION General Description The embedded processor in the ACE9050 is functionally equivalent to a generic 6303R micro. This data sheet outlines the functionality of the embedded processor, detailing its operation with the internal peripheral circuitry. It is not intended as a programmers guide for a 6303. If further information is required the following publications are recommended: HITACHI 8-bit single-Chip Microcomputer Data Book Sept.1989 Motorola Microprocessors Data Manual Macro Assemblers Reference Manual, Motorola Semiconductors MC68MASR(D). The 6303 is an 8-bit processing unit which has a completely compatible instruction set with the 6301. It has object code upwardly compatible with the HD6300, HD6801 and HD6802. The ACE9050 has 6016 bytes of internal RAM (the 6303R has 128 bytes). Other features are: a Serial communications interface (SCI or UART), a 16-bit timer, 8-bit I/O port and a 5-bit I/O port (only 2 are bonded out from the ACE9050). The bus speed can be configured to 1·008 in Normal mode or 2·016MHz in Turbo mode. The ACE9050 has an Emulation mode whereby its internal 6303 is bypassed and the peripheral functions may be driven externally by a standard 6303 ICE. I/O Description VDD VSS XTAL External I I - E NMI IRQ I I Internal power supply Internal Ground Not connected Not Used (System Clock Driven into E directly) System Clock IP Not used: Tied to VDD Connected to Interrupt Control block and IRQN pin Connected to Internal Reset MRI Internally connected to IFC Counter Not connected Internally connect to Baud Clk External Pin (SCI I/P or Port2) External Pin (SCI O/P or Port2) External Pin (Port1 I/0 Access) Connected to internal address Bus Internally connected to Buses Connected to internal logic and R/W pin Connected to internal logic Standby mode disabled = VDD Name RES Port2 [0] Port2 [1] Port2 [2] Port2 [3] Port2 [4] Port1 [7:0] Addr [15:8] D/A [7:0] R/W AS STBY I I/O* I/O* I/O I/O I/O O I/O O O - *Port2 bits 0 and 1 must be configured as inputs in the 6303 to use the IFC and Baud rate generator functions. clocks. Table 12 Generic 6303 I/O mapping Port 1 This is an eight bit I/O port with the direction of each bit being defined by the data direction register DDR1 as given in Table 13. The Port can be accessed for read and write via the Port1 register. The output buffers have tristate capability, being high impedance when used as inputs. When the processor is reset these are high impedance. Two pins (Bits 3 and 4) associated with this port are also used as I/0 from the I2C interface on the ACE9050. This is configured by Port 5 bit 2. The 6303 is internally configured to mimic Multiplexed mode of operation, so this port cannot be configured to output the lower address bits. The ACE9050 has dedicated pins for this purpose. Associated Registers Name DDR1 Bits [7: 0] Description 1: Sets corresponding Port line to output 0: Sets corresponding Port line to input ACE9050 6303R Pin Description The ACE9050 6303 is embedded in a kernel which interfaces to the rest of the circuitry. Table 12 describes the internal connections to the ACE9050 6303. In Emulation mode, none of the output pins drive the internal buses. Clock The CPU Clock is provided from the Clock Generator Circuit in the ACE9050. This clock is either 1·008MHz or 2·016MHz. It is not further divided down in the 6303, so this clock frequency is the same as the processor bus speed. Refer to the Clock Generator section for details of how to configure the internal 14 Port 1 Bits [7:0] Read and Write access to Port 1 Table 13 Port 1 associated registers Port 2 This is a five-bit I/O port with the direction of each bit being defined by the data direction register DDR2. Only bit 3 and bit 4 are connected to external pins. This allows access to the I/O port and Serial Interface functions. Bit 0 and bit 2 are internally connected to the IFC and Baud clock. They must be configured as inputs to use these functions. Bit 0 and bit 2 are not externally accessible. ACE9050 The ACE9050 has an additional Output Port 2, which is separate from the 6303 Port 2. Associated Registers Name Description DDR2* Bits [4:0] 1: Sets corresponding Port line to output 0: Sets corresponding Port line to input Port 2* Bits [4:3] Read and Write access to Port 2 *The TRCSR register overrules these registers. Table 14 Port 2 associated registers Serial Communication Interface (SCI or UART) The processor contains a full-duplex asynchronous Serial Communications interface. It consists of a transmitter and receiver which operate independently but with the same data format and rate. Both parts communicate with the CPU via the data bus and to the outside world via Port 2. Interrupts generated can be individually masked. The receiver can be sent to ‘sleep’ by software. No receive interrupts are generated during a message in this state. The Baud rate can be generated within the ACE9050 6303 or the ACE9050 can provide a baud rate generator and selection register external to the processor block. This allows the following standard baud rates to be programmed: 600,1200. 2400, 4800 or 9600. The hardware consists of four registers: an 8-bit control/ status register, 4-bit mode select, an 8-bit receive data and an 8bit transmit data register. Programmable Timer Bit R/W Name The ACE9050 6303R contains a 16 bit programmable timer which may measure the period of an input waveform, as with a standard 6303R. This counter runs from the ECLK. The counter cannot generate an output waveform. The input to the timer is internally connected to the IFC counter for the AFC loop function. The timer hardware consists of an 8-bit status and control register, a 16-bit free running counter and a 16-bit input capture register. TCSR (Timer Control and Status Register) The Control and Status register has three flags: Input capture, Output Compare Match and Timer Overflow. Each flag has an associated interrupt enable. The other two bits in the register are for control of the output level and input edge select. The bits are described in Table 15. Bit R/W Name Description 7 R ICF Transition of appropriate type occurred on input (ICN). Cleared by read of Input Capture register 6 R OCF Match between Free Running Counter and Output Compare Register* 5 R TOF Timer overflow. Cleared by read of counter. Enable an ICF interrupt 4 R/W 3 R/W EOCI Enable an OCF interrupt* 2 R/W ETOI Enable Timer overflow interrupt 1 R/W IEDG 0 = Negative edge on ICN trigger ICR 1 = Positive edge on ICN trigger ICR 0 R/W OLVL Output level* EICI *As the timer cannot generate an output these bits are considered nonfunctional in the ACE9050. Table 15 TCSR bit descriptions FRC: Free Running Counter The FRC is a 16-bit ReadWrite counter; Data can be read from or written to it. The register has extra hardware to load and save both bytes of the counter simultaneously when a double byte store instruction is used. The counter is incremented by the processor clock. Reading from the counter does not affect it. ICR: Input Capture Register The ICR is a16-bit Read register which holds the value of the Free Running Counter when a transition is detected on ICN, i.e. the IFC Counter Output. Description 7 R RDRF RX Data Register Full* 6 R ORFE Overrun/Framing Error* 5 R TDRE TX Data Register Empty 4 R/W RIE RX Interrupt Enable: Enables an interrupt for both Bit 7 and Bit 6 3 R/W RE RX Enable. This sets Port2 bit 3 to Input regardless of the DDR2 2 R/W TIE TX Interrupt enable: Bit 5 will generate an Interrupt 1 R/W TE TX Enable: This sets Port2 bit 4 to Output regardless of DDR2 0 R/W WU Wake Up: Set by software and cleared by hardware.** * ** Overrun is where new data is placed in the Receive register before the old data has been read. Framing Error is where the bit counter is not synchronised with the boundary of the byte in the Received bit stream defined in Table 17. The Wake Up mode is intended for systems where more than one Processor is on the UART link, and is addressed by the first byte of data. If the address is incorrect the processor can disable the interrupts and effectively ignore the word. Table 16 TRCSR: Transmit/Receive Control Status Register bit descriptions Condition Bit 7 Bit 6 No Data Good Data RX Framing error Overrun error 0 1 0 1 0 0 1 1 NOTE: Bits 7 and 6 are cleared by reading the Status register, followed by reading the Received Data register Table 17 RMCR Transfer Rate/Mode Control Register The mode select register controls the clock source and setup. This is a write-only register. The processor can use an internally divided down processor clock to give the Baud clock. The Baud rate division ratio can be set to a value from 16 to 4096. However, this could lead to non-standard Baud rates so the ACE9050 provides a separate Baud rate generator.The bit functions of this register are described in Table 18. 15 ACE9050 Bits Description Value [7: 4] XXXX [3: 2] 00 01 10 11 [1: 0] 00 01 10 11 Not used Clock Control mode SCI disabled Use processor Clk for Baud rate Not used Use ACE 9050 Baud rate generator Speed Select (Bits 3: 2 = 01) E416 E4128 E41024 E44096 Table 18 RMCR Transfer Rate/Mode Control register Bits Description [7:0] (Data) RDR: Received Data Register Read received bits. First bit received is placed in bit 0, last in bit 7 [7:0] (Data) TDR: Transmit Data Register Write register to store bits before serial transfer from Transmit shift register, bit 0 first mode is fully supported by the ACE9050 6303. This mode is entered by execution of the SLP instruction. Escape is via an interrupt or reset . Address, Data and Memory Control The Address, Data and control lines from the ACE9050 6303 connect to a kernel which interfaces to the on chip bus structures. The Bus Interface block provides suitable buffering to drive required buses externally, and configure the I/0 for Emulation mode. Interrupt Processing The interrupt processing in the ACE9050 6303 is essentially the same as a generic 6303, the exception being NMI, which is not available. The IRQN is internally connected to the I2C interrupt, the External Interrupt and the Internal interrupt blocks. These blocks combine all the possible sources for interrupts into one line which is connected to IRQN. This is also connected to a pin for use in Emulation mode. The IRQN is maskable. The interrupt mask bit in the Condition Code Register must be zero for the CPU to respond to the Interrupt request, as with a generic 6303. The Interrupt Vector Memory map is shown in Table 20. Priority Table 19 Receive and Transmit Data registers In Normal Mode the SCI should be initialised before operation. This means writing to the mode select and the control/status register. In Service Mode the SCI is configured for 9600 baud, and the receive interrupt enabled. When the transmitter is first initialised it will send a ten-bit preamble of ‘1’s before being ready to transmit data. Once initialisation is complete data transmission enabled by writing to the transmit data register. TDRE is set to 0. A start bit is transmitted (0). Next the eight bit data starting at bit0 are transmitted followed by a single stop bit (1). The hardware sets the TDRE bit in the TRCSR register. If the CPU does not transfer another word the output goes high. The receiver is configured during initialisation. If enabled and a start bit is detected (0), the next nine bits will be sampled approximately at the centre of each bit. If the ninth bit is a 1 the data is transferred to the Receive data register. The RDFR bit is set in the TRCSR register. If the ninth bit is not a 1 or the receive data register is full then the ORFE bit is set to indicate an error. A read of the TRCSR register followed by a read of the Received data register (RDR) will clear these flags. RAM Control Register (RAMCR) This register is read only in the ACE9050. Bit 6 (RAME) is set to zero: this is because the RAM on the ACE9050 is external to the 6303 block. Bit 7 (STBY) is also set to zero by the ACE9050 because Standby mode is not supported. Operating Modes The Generic 6303R has two modes: Multiplexed and nonMultiplexed, where the mode is selected externally using P2[0], P2[1] and P2[2]. This is not required on the ACE9050, where the mode is set to mimic multiplexed internally when the reset (MRN) is released . The ACE9050 processor has two fundamental modes of operation: Emulation and Normal, which are described in the MODES OF OPERATION section. Low Power Consumption Modes The generic 6303 Standby mode is not supported by the ACE9050 6303. The STBY pin is not accessible. The Sleep 16 1 2 3 4 5 6 7 8 Vector MSB LSB FFFE FFEE FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFFF FFEF FFFB FFF9 FFF7 FFF5 FFF3 FFF1 Interrupt RES TRAP Software Interrupt (SWI) IRQN ICF (Timer Input Capture) OCF (Timer OP Compare) TOF (Timer Overflow) SCI (UART) Table 20 Interrupt vector memory map Error Processing An interrupt is generated when an undefined op-code is fetched, or when an instruction is fetched from an impossible address. This is in the range 0000- 007F for the ACE9050 (0000001F for a standard 6303). 2. INTERNAL ROM BOOT BLOCK The ROM code provides a boot block for the ACE9050. Following a reset condition code execution will always start in the internal ROM. The internal ROM data flow depends on the condition of the SERV Input and thus the mode of operation of the ACE9050. The operation flow of the IROM is shown in Fig. 12 and described in the following sections: Normal Mode 1. Read serial data on ACEBus DTFG line 2. Configure ACE9030 Reference dividers via ACEBus. 3. Set the program counter to the beginning of external ROM (1800H). Service Mode 1. 2. 3. 4. Read serial data on ACEBus DTFG line Configure ACE9030 Reference Dividers via ACEBus Configure the UART to RX Wait 2 seconds for special code on UART - if not found go to step 3 of Normal Mode 5. Load Data from UART into RAM ACE9050 6. Pass control to Program loaded in RAM 7. Map Interrupt Vectors to RAM space. 8. The RAM program can then Program a FLASH memory via the UART. Steps 1and 2 - Both Modes The ACE Chipset offers the flexibility of using one of three different crystal frequencies: 12·8, 14·85 or 15·36 MHz. The chosen crystal can be used to generate all the system clocks and local oscillator frequencies required in a cellular phone application. The ACE9050 must detect what crystal is being used and set up the correct value for the OSC8 dividers in the ACE9030. This is handled in the Internal ROM. Upon Reset the ACE9030 sets the OSC8 for a 15·36 MHz Crystal, so the ACE9050 is not clocked faster than 8·064 MHz. The system designer must set up the DTFG input (the Radio Serial Interface, pin 82), using an external resistor of approximately 10kΩ. The crystal frequency determines where the resistor is terminated, as shown in Table 21. Upon reset the ACE9050 Internal ROM reads the DTFG input and programs the ACE9030 OSC8 accordingly. Crystal Serial Data RXed Resistor from pin 82 to: 12·8MHz 14·85MHz 15·36MHz 000000 0 < Data < FFFFFF FFFFFF VSS (Gnd) A1 (pin 31) VDD Table 21 Step 3 - Normal Mode Program code in the external EPROM at address 1800H is started. The Internal ROM resides at the top of the processor address space FE00H - FFFFH. Obviously the main program requires access to this space for Interrupt vectors. The Internal ROM is deselected by setting PORT4 [1] to zero. It is recommended that any external program does this quickly and always before enabling any Interrupt sources. Step 3 - Service Mode The Internal ROM will initialise the 6303 SCI (UART) and set up the Baud rate generator to 9600 Baud. The SCI is initialised to the following: Receiver On Transmitter ON Receive Interrupt enabled 9600 Baud rate from ACE9050 Baud Rate Generator The Receive interrupt will remain enabled after the IROM code execution. The UART is always configured for 8-bit data transfer, no parity and one stop bit. Steps 4, 5 and 6 - Service Mode When in service mode the ACE9050 can download a program from the SCI to RAM. To achieve this the first code (start code) must be sent down to the SCI within 2 seconds of releasing Reset. The boot block code will write the subsequent code into RAM. Two code formats are supported: (a) Motorola S- Record format (b) Binary dump (a) Motorola S-Record Format The start code for this format is ‘OA’ in ASCII ( i.e. 30H, 41H). s0nnppppxxxxxxxxxcc First Record in file s1nnppppdddddddddddddcc Data record with 16-bit address · · s9nneeeecc End of file record (nn = 3) where: nn = Number of bytes ( xx1pp1dd1cc ) in record. pppp = Load address dd = data bytes, 1 to 16 xxxx = Name of proqram (ASCII coded) eeee = Program entry address cc = checksum calculated from [2552sum(pp)1sum (dd)1 sum (xx)1sum (ee)1nn)] MOD 256 When the ‘s9’ is read in from the End of File Record, the code will jump to the reset vector. This is mapped to 0FFE by the IROM. The RAM program will then begin execution as for a reset. The last 6 characters of the record file (nneeeecc) will be received while the program is running. (b) Binary dump file This format is for the binary representation of the code, not a proprietary binary format code. The start code for this format is ‘OB’ ASCII (ie 30H, 42H) . First two bytes are the start address pointer. The next two bytes are the end address pointer11. The next bytes are the data bytes. These are loaded consecutively from the start to the end address. When the last data byte is received the program counter will go to the loaded code start address pointer. Step7-Interrupt Vector table The Internal ROM will map the 6303 Interrupt vector table to an address space in RAM so the loaded program can deal with interrupts as shown in Table 22. In general only the SCI interrupt is required for a Flash Loading program. Interrupt Vector address 0FFE 0FEE 0FFC 0FFA 0FF8 0FF6 0FF4 0FF2 0FF0 Reset Trap Not Implemented SWI Software interrupt IRQN ICF Timer Input compare OCF Timer Output compare TOF Timer overflow SCI Table 22 RAM Area Reserved for IROM Operation The IROM code itself requires a small amount of RAM during its operation. This area must not be used for storage of the RAM program. RAM Reserved area: 080H to 100H Fig. 12 shows the data flow for the internal ROM. 3. DECODER The Decoder logic creates the memory map for system containing the ACE9050. Internally, it maps the ACE9050 registers, RAM and ROM onto the System Memory map. External ROM is also mapped onto the available address space by the Decoder, but the situation can be complicated by the Bank Address switching circuitry. Refer to Table 23 on the following page for details of memory mapping. Note that the ACE9050 contains Memory Banked Switching circuitry. Refer to the section 4 ‘BUS INTERFACE AND MEMORY BANKING’ below for details. The Decoder also creates suitably timed Output Enable and Write Enable signals (refer to Figs. 4 and 5) for parallel read and write cycles to external devices. 17 ACE9050 Description Address (hex) 0000-001F 0020-007F 0080-17FF 1800-7FFF 8000-BFFF C000-FDFF FE00-FFFF External Pins 6303 Registers Internal ACE9050 Registers RAM Non Banked external ROM Banked external ROM Non-Banked external ROM Internal / External ROM Table 23 WEN Write Enable, active low (pin 27) This output is used to latch data into external memory or other suitable devices. Associated Registers IROM Port 4 bit 1 The ACE9050 internal ROM (IROM) is mapped to the top 512 bytes of the address space allowing it to provide interrupt handler routines. Upon reset the IROM select is enabled. It can and should be disabled by software before the interrupts are enabled. RESET RELEASED PC TO 6303 RESET VECTOR FFFE OEN Output Enable, active low (pin 26) This signal is used when accessing external memory or other suitable devices. Driving the Output Enable input of external memory reduces the possibility of data bus contention conditions. ACE9050 RESET IROM SELECTED (PORT4 [1]–1) Bit 1 IROM START IROM CODE Description Address range FE00H-FFFFH: 0 = External ROM 1 = Internal ROM (reset state) Table 24 000000 READ DATA FROM DTFG SLEEP Port 3 Bit 1 If this bit is enabled then the CSEPN will become inactive during periods when the 6303 is in Sleep mode. When the 6303 Sleep mode is activated, the processor puts FFFFH on the address bus. The Decoder simply does not activate CSEPN for this address when the SLEEP bit is enabled. FFFFFF 0< DATA <FFFFFF SET UP ACE9030 FOR 12·8MHz XTAL SET UP ACE9030 FOR 14·85MHz XTAL SET UP ACE9030 FOR 15·36MHz XTAL Bit 1 SLEEP 0 1 SERV INPUT SET UP SCI (UART): 9600 BAUD; 8 BIT: NO PARITY. RECEIVE INTERRUPT ENABLED Description Address FFFFH: 0 = CSEPN active 1 = CSEPN inactive Table 25 4. BUS INTERFACE AND MEMORY BANKING The Bus interface logic is responsible for the following: NO JUMP TO 1800H (START OF EXT ROM) WAIT UP TO 2 SEC FOR 0A OR 0B YES MAIN PROGRAM IN EXTERNAL ROM RESET PORT4 [1] INTERRUPT VECTOR TABLE RESET TRAP NI * SWI IRQ ICF OCF TOF SCI 0FFE 0FEE 0FFC 0FFA 0FF8 0FF6 0FF4 0FF2 0FF0 LOAD EITHER MOTOROLA S-FORMAT OR BINARY FILE CODE INTO RAM AREA FROM SCI END FILE PASS CONTROL TO RAM PROGRAM * NI = NOT IMPLEMENTED Fig. 12 Data flow for the internal ROM 18 1. External Interface to ACE9050 Data and Address buses 2. Creating 2 chip selects for external memory parallel devices. 3. The logic for the external banked addressing 4. Emulation Mode: External control of internal buses Fig. 13 is the block diagram of the circuit. The ACE9050 memory interface can operate at a lower supply voltage than the rest of the chip. This allows the use of low voltage memory parts. The memory interface pads use a separate supply rail, which is connected to VDDM. External Pins EMUL Emulation mode (pin 83) This input changes the function of the external data and address buses. In Emulation mode (EMUL = 1), the internal Address and Data buses are constructed from external stimuli and not the internal 6303. ACE9050 INTERNAL DATA BUS [7:0] NORMAL: D[7:0] EMUL: D[7:0] & A[7:0] INPUT 8 ID[7:0] (DISABLED IN EMULATION MODE) NORMAL: NOT USED EMUL: AS INPUT A[7:0] NORMAL: A[13:8] OUTPUT EMUL: A[13:8] INPUT NORMAL: NOT USED EMUL: A[15:14] INPUT BA[17:14] CSEPN CSE2N ACE9050 6303 AND KERNEL TRANSPARENT LATCH LATCH ENABLE AD[15:0] (DISABLED IN EMULATION MODE) IRW 8 8 6 [7:0] 2 [13:8] 16 [15:14] [15:14] 4 MEMORY BANK SWITCHING 2 DATA BUS INTERNAL EPROM CHIP SELECT INTERNAL ADDRESS BUS [15:0] NORMAL: R/W NOT USED EMUL: R/W INPUT INTERNAL READ / NOT WRITE Fig. 13 Data and Address bus configuration AS Address Strobe (pin 5) This input is used in Emulation Mode only. Th external D [7:0] will contain both data and the lower 8 bits of the address bus.The Bus Interface provides the transparent latch required to hold the value of the address during the latter part of the cycle. The AS is provided to control the Latch Enable. In a typical system this will be directly connected to the emulating 6303 AS output. R/W Read/Not Write (pin 95) This is an output in Normal mode, but an input in Emulation Mode. It is the processor Read/Not Write line. The timing of this output is not guaranteed to be the same as a standard 6303 processor. In Emulation mode it will be directly connected to the Emulating 6303 R/W line. D [7:0] Data (and Address in Emulation mode) (Pins 18-25) In Normal mode these pins provide bidirectional data transfer between the ACE9050 6303 and external memory. In Emulation mode they provide the directional data and the lower 8 bits of the address bus into the ACE9050. A [7:0] Lower 8 address bits (Pins 40, 39, 35-30) These outputs provide the lower 8 bits of the address bus for external memory. This is the case for both Normal and Emulation modes. BA [17:14] Banked address (pins 50 to 47) The ACE9050 expands the external address bus to 18 bits. This allows up to 256K of memory space. BA [17:14] are the outputs from the bank select register. The operation of the refister is described further in ‘Memory Map and Banked Addressing’, below. CSEPN Chip Select (pin 28) This output provides active low chip select for accessing external program memory. On reset the entire external memory address space is mapped to CSEPN. In the Banked area of the memory map the programmer can select either CSEPN or CSE2N access via bit 4 of the Bank Select register. CSE2N Chip Select (pin 29) This output provides an active low chip select for accessing external memory or other suitable device. In the Banked area of the memory map the programmer can select either CSEPN or CSE2N access via bit 4 of the Bank Select register. VDDM Supply to Memory Interface (pin 38) The power supply pin for the memory interface, VDDM, provides the power supply for the following pads: A [13:0], BA [17:14], D [7:0], CSEPN, CSE2N, WEN and OEN Memory Map and Banked Addressing A [13:8] Address Bits 13 to 8 (pins 46-41) In Normal mode these provide the output of the ACE9050 6303 address bus bits 13 to 8, for addressing external devices. In Emulation mode, A[13:8] provide input for an external 6303 address bus, to address the ACE9050 functions excluding the 6303. A [15:14] Emulation Address bits 15 and 14 (pins 92 and 93) These inputs are only used in Emulation mode. The internal 6303 address A[15:14] are fed to the banked address logic and not to an external pin. In emulation mode the host processor must drive the complete 6303 internal address bus so A[15:14] inputs are provided. The host processor will then drive the entire internal bus and the bank select register, so the external memory access will be the same regardless of Emulation or Normal mode. The ACE9050 provides the circuitry to create a banked addressing system which will increase the size of the programming space from 16 bit (64K bytes) to 18 bit (256K Bytes) and enable two Chip Select lines to be programmed. This is achieved using an internal register to select the required page of memory and chip select line. The use of banked addressing and associated circuitry is not mandatory in a system using an ACE9050. When using banked addressing the external addresses generated and thus the system memory map are different from the 6303 memory map. The banked addressing functions in the same manner for both Normal and Emulation mode with a external processor. 19 ACE9050 Associated register The processor memory map is thus split into two distinct areas: Non Banked address (Root) and Banked address: BANK_SEL: Bank Select register (Write only) Bit Name [7:5] 4 CS 3 2 1 0 BA 17 BA 16 BA 15 BA 14 Non Banked address area (Root) A[17:14]: The address lines A[17:16] are set to 11. The address lines A[15:14] are identical to the corresponding processor address lines. This means the original area of the processor memory map is mapped to the top of the external memory address space. CSE2N is never active, regardless of the value of the Bank_Sel register bit 4. All access will be with CSEPN. Description Not used Chip Select: 1 = CSE2N 0 = CSEPN Banked Address A17 (see Table 27) Banked Address A16 (see Table 27) Banked Address A15 (see Table 27) Banked Address A14 (see Table 27) Table 26 Bank_Sel 3:0 Page Base Address (Hex) Bank_Sel 3:0 Page Base Address (Hex) 0000 0001 0010 0011 0100 0101 0110 0111 00000 04000 08000 0C000 10000 14000 18000 1C000 1000 1001 1010 1011 1100* 1101* 1110* 1111* 20000 24000 28000 2C000 30000 34000 38000 3C000 *Refer to System Memory Map section for more details Table 27 Banked Address area: A[17:14] These address lines are the same as Bank Sel register bits [3:0]. The programmer can in theory select up to 16 pages. This is discussed in more detail in System Memory Map section. CSE2N: The BANK SEL bit 4 determines whether this Chip select line is enabled or the CSEPN. Table 28 summarises operation in the two areas. Address area A[17:16] A[15:14] Chip Select Non-Banked Set to 11 Same as Micro Always CSEPN Banked Bank Select register bits [3:0] Bit 4 Table 28 Banked Address System Memory Map The processor and the system memory map become different because of the memory banking. The system memory map is spit into 16K pages and the original processor Memory map re-targeted. Refer to Fig. 15. The banking is configured to occupy a 16K byte area of the processor memory address space. It will thus create 16K byte pages. This is configured in hardware and cannot be altered. It is achieved by decoding the upper 2 bits of the processor Address bus. If the address is in the range 8000H to BFFFH which corresponds to A[15:14] = 10, the bank select circuit is invoked. The bank addressing circuit only affects the upper four bits of the external data bus. The top two A[17:16] are completely new, and the next two A[15:14] are replacements for the processor A[15: 14] bits. Fig. 14 is a block diagram of the Bank Select circuitry. SYSTEM ADDRESS 0XXXX BANK 1 BANK 2 BANK 3 BANK 4 1XXXX BANK 5 VDD 17 BANK 6 16 BANK 8 2XXXX 15 BANK 9 14 AD15 AD14 CONTROL 1 = A, 0 = B A[17:14] B MUX ID[3:0] ID [4:0] BANK 10 CPU ADDRESS 15:0 0000 REGISTERS 4 5 4 4 BA [17:14] BANK 11 3XXXX RAM 1000 A 8000 BANKED A MUX CSEPN C000 FE00 BOOT ROM B FFFF 64K CSE2N Fig. 14 Banked Addressing block diagram 20 BANK 12 A[17:14] BANK_SEL REGISTER ID4 EPROM SELECT BANK 7 PROCESSOR MEMORY MAP 256K ROM SYSTEM MEMORY MAP Fig. 15 Memory Map and Banked Addressing ACE9050 The page addressing can access up to 16316K pages per Chip Select line in theory; however the original 6303 memory map must also reside in the 256K of CSEPN memory space. This is put to the top of the system memory map by the ACE9050 and represents Pages 13 to 16. So, for example, the 6303 address range C000H to FFFFH will access the same memory location as 8000H to BFFFH with the bank select register set at 0FH. This is useful when programming a FLASH memory device, but care must be exercised in the addressing of run time code. For the top four pages the system designer must decide whether to access the area via its page address or its direct (Root) address. For the original 6303 4 pages: Page 1 (0000H-3FFFH) = Page 13 (30000H-33FFFH) This must be used for ROOT ROM, as the code will jump to 1800H after reset. This means the bottom 6K of the page (0000H-17FFH) cannot be used unless it is accessed via its banked address. It does allow the maximum possible (42K) memory area to be configured as Non Banked. Page 2 (40000H-7FFFH) = Page 14 (340000H-37FFFH) This page can either be used as Root, or banked. Page 3 (8000H-BFFFH) = Page 15 (38000H-3BFFFH) This page is banked by definition. Page 4 (C000H-FFFFH) = Page 16 (30000H-3FFFFH) The final page could either be accessed via it banked address or Root address, however as this contains the Interrupts it must be Root. The designer can also allocate any of these or further shadowed 16 pages to the CSE2N chip select. It is up to the system designer whether to use unique pages for CSE2N or shadow a ROM (CSEPN) page . processing, the first interrupt the 6303 will detect low IRQN line and re-enter the interrupt handler routine. This will continue until all pending interrup have been serviced when the IRQN line will remain high. If more than one pending interrupt occurs the software can prioritise its response, by the way the interrupt handler is written. The later interrupts must not be cleared in IRQPRT0, 1, 4 or 5 by the software until they have been serviced. The ACE9050 will not detect more that one pending interrupt from a given source, i.e. it will not tell that two IRQ-WS have been missed, only that an IRQ-WS interrupt has occured. Internal Interrupt Control Port The internal interrupt control port facilitates resetting, masking and reading of seven potential internal interrupt sources via three registers. Table 29 describes the possible sources. Bit 7 6 5 3 2 1 0 Name Description Modem: Data Transmitted Modem: Received Word synchronisation sequence IRQ-BI-SAT Modem: Busy Idle bit or SAT updated Modem: Rx Data registers updated IRQ-RX ACE Serial Interface Received data IRQ-REC IRQ-SEND ACE Serial Interface Sent data Time Out (ATO expired) IRQ-TO IRQ-TX IRQ-WS Table 29 Internal interrrupt sources 5. INTERRUPTS The ACE9050 contains one internal interrupt port, one external interrupt port and one I2C interrupt. This expands the one 6303 maskable interrupt (IRQN) into eight internal and two external interrupts. The Interrupt control logic enables masking, reading and resetting of the potential interrupt sources. Three registers are associated with each of the two interrupt control ports, IRQPRT 0, 1 and 2 for internal and IRQPRT 4, 5 and 6 for external interrupts. Each Interrupt control port will generate an Interrupt request line, as will the I2C interrupt. These three lines are NORed together to produce the 6303 IRQN input. Fig. 16 is a block diagram of the Interrupt Section. If a source is not masked an interrupt will be generated and the corresponding bit set in the Interrupt register. If it is masked no interrupt will be generated and the correspondincg bit will not get set in the interrupt register. Once an interrupt is generated, it can be read in IRQPRT2, 6 or the I2C section. If both internal and external interrupts are enabled the processor must read both IRQPRT2 and 6; however, if only external or internal interrupts are enabled the software need only read th corresponding register. To reset the interrupt, a write to IRQPRT0 or 4 is required with the correspondin bit set to 0. The interrupts sources are not prioritised in the ACE9050. Handling the I2C interrupt is covered separately in the I2C Interface description, Section 10. Associated Registers (Table 30) IRQPRT0: Internal Interrupt Reset Register Writing a zero in a data bit of this register will reset the corresponding interrupt source. IRQPRT1: Internal Interrupt Mask Register A write to this register will determine the possible source of interrupts. At reset all interrupts are masked IRQPRT2: Internal Interrupt Read register A Read from this register will determine the interrupts source. IRQPRT0 Bit Name Description [7: 0] Reset 0 = Reset 1 = No change Mask 0 = Reset and masked 1 = Enabled [7: 5] Source 4 [3:0] Source 0 = Interrupt 1 = No Interrupt Should be masked 0 = Interrupt 1 = No Interrupt IRQPRT1 [7: 0] Masking Interrupts IRQPRT2 The IRQN input to the 6303 is a level sensitive maskable interrupt line. This means that it is possible to enable and disable all interrupts from the ACE9050 in the 6303. This is useful to avoid nested interrupt situations. If several interrupts are unmasked in the ACE9050, the interrupt handler routine can disable all interrupt when it is dealing with an interrupt via the 6303. If another valid interrupt occurs during this time the IRQN line will be driven low by the ACE9050. When the IRQN is enabled in the 6303 at the end of Table 30 21 ACE9050 DATA BUS 8 IRQPRT0 RESET IRQPRT1 MASK 0 1 2 3 LATCHING 4 LOGIC 5 6 7 TIME OUT IRQSEND IRQREQ IRQRX IRQBISAT IRQWS IRQTX IRQPRT2 READ AND COMBINING LOGIC 7 DATA BUS IRQPRT4 RESET INRQ0 INRQ1 71 IRQPRT5 MASK 0 1 70 LATCHING LOGIC IRQPRT6 READ AND COMBINING LOGIC 2 84 IRQN TO 6303 DATA BUS INP1 [2] INP1 [3] INP1 [4] SERV TXPOW 0 1 2 3 PORT1 4 INPUT 5 6 7 52 53 54 74 61 I2C INTERRUPT ACE9050 Fig. 16 ACE9050 Interrupt configuration External Interrupt Control Port The external interrupt control port facilitates resetting, masking and reading of two potential external interrupt sources via three registers. The external interrupt inputs are edge sensitive. Table 31 describes the possible sources Bit 1 0 Name Description INRQ1 External Interrupt 1 (INRQ [1]) INRQ0 External Interrupt 0 (INRQ [0]) Table 31 External pins INRQ0 (pin 71) A rising edge (zero to one transition) on this line will generate an INRQ0 interrupt if the associated bit in the mask register is set to 1. The level of this input can also be read via Port1 bit 0 22 regardless of whether an interrupt is generated. INRQ1 (pin 70) A rising edge (zero to one transition) on this line will generate an INRQ1 interrupt if the associated bit in the mask register is set to 1. The level of this input can also be read via Port1 bit 1 regardless of whether an interrupt is generated. Associated Registers (Table 32)Bit7: 0 IRQPRT4: External Interrupt Reset Register. A write to this register will reset the interrupts corresponding to 0 written in the data field. IRQPRT5: External Interrupt Mask Register. A write to this register will determine the possible source of interrupts. After reset all interrupts are masked. IRQPRT6: External Interrupt Read register. A Read from this register will determine the interrupts source. ACE9050 Bit Name [1: 0] Reset [1: 0] Mask [1: 5] Read Description IRQPRT4 0 = Reset 1 = No change IRQPRT5 0 = Masked 1 = Enabled IRQPRT6 0 = Interrupted 1 = Not Interrupted Table 32 6. EXTERNAL PORTS AND MULTIPLEXER The ACE9050 contains 2 external ports, addition to the 6303 Port1 and Port2 which a described in section 1 ‘ACE9050 6303R Description’. One of the ports is an input register (IN_PORT1), the other an output (OUT_PORT2). Both are 8-bit, but not all bits are accessible from outside the ACE9050. Two bits from OUT_PORT2 are fed to a multiplexer. This enables multiple functions to share the same external pin, thus reducing the overall pin count. The functions multiplexed with the port are the Pulse Width Modulators and the ACE serial Interface Latch2. Selection is made via the ACE9050 control Port 5. Further I/O capability can be obtained by using the Keypad interface as standard ports. This is described in the ‘Keypad Interface’ section of the data sheet. External Pins INPUTS INRQ1, INRQ0: External Port and Interrupt Input (pins 70 & 71) The logic level of these external inputs are read via IN_ PORT1[1:0], regardless of whether these inputs are configured to generate interrupts or not. INP1[4], INP1[3], INP1[2]: External Port Inputs (pins 54,53,52) Uncommitted input. The logic level of these pins can be read via IN_PORT1[4:2]. SERV: Service Input (pin 74) The state of the mode select line SERV can be read by software via IN_PORT1. The function of SERV is described in ‘Modes Of Operation’ section. TXPOW: Power Detect input (pin 61) The TXPOW input goes to the Watchdog and ATO block, refer to ‘Autonomous Timeout’ section for more details. The state of the input can be read via IN_PORT1. OUTPUTS OUT 2[6] (pin 76), OUT2[7] (pin 79) Output pins High Current inverting output pins. May be used for LED or backlight drivers. Their state is set up via OUT_PORT2. Upon reset OUT_PORT 2[7:6] are reset low. Due to the inverting nature of the outputs this means OUT 2[7] and OUT 2[6] are high. Associated Registers IN_PORT1: ACE9050 Input Port: Read Only Bit Name Description 7 6 5 4 3 2 1 0 POWDET SERV INP1 [4] INP1 [3] INP1 [2] INRQ1 INRQ0 Logic Level of TXPOW Input pin Logic Level of SERV Input pin Read back as 0 Logic Level of INP1 [4] pin Logic Level of INP1 [3] pin Logic Level of INP1 [2] pin Logic Level of INRQ1 pin Logic Level of INRQ0 pin Table 33 OUT_PORT2: ACE9050 Output Port: Read and Write Bit Name Description 7 6 5 4 3 2 1 0 OUTP2 [7] OUTP2 [6] OUTP2 [5] OUTP2 [4] OUTP2 [3] OUTP2 [2] OUTP2 [1] High Current Inverting O/P* High Current Inverting O/P* Set to 0: Not used Set to 0: Not used Set to 0: Not used O/P to multiplexer with PWM2 and Latch2) O/P to multiplexer (with PWM1) O/P when CPUCL disabled *On reset, these bits are set low and the corresponding output pins driven high. Table 34 PORT5 [5:4]: OUTP2.2_SEL Bit 5 Bit 5 0 0 1 1 0 1 0 1 OUTP2 [2]/PWM2/LATCH2 pin function OUT_PORT2 [2] (Reset state) Pulse width modulator 2 ACE Serial Interface Latch 2 Not valid OUTP2 [0]/CPUCL OUT_PORT2[0] or CPUCL Clock (pin 94) When the CPUCL Clock Output is disabled in the Clock Generator this pin is driven by the OUT_PORT2 [0]. Refer to ‘Clock Generator’ section for details of the CPUCL function. OUTP2 [1]/PWM1 (pin 98) This pin can be either be driven from OUT_PORT2[1] or the Pulse Width Modulator 1. The selection is made via Port5[0]. OUTP2 [2]/PWM2/Latch2 (pin 81) This pin can be driven from: OUT_PORT 2[2], Pulse Width Modulator 2 or ACE Serial Interface Latch2. The selection is made via Port 5[5:4]. Table 35 PORT5 [0]: PWM 1 MUX Bit 0 0 1 OUT2 [1]/PWM1 pin function Pulse width modulator 1 OUT_PORT2 [1] (Reset state) Table 36 23 ACE9050 7. CLOCK GENERATOR Associated Registers The AC9050 provides a clock generator with crystal oscillator circuit. This circuit generates all of the chip clock frequencies to which the logic is synchronised. In Normal mode all the clocks are generated from one external source. In Emulation mode the Master clock is the ECLK which becomes an input. For AMP and TACS mobile handset applications the input frequency must be 8·064MHz. In Emulation Mode an input frequency of 1·008MHz, or 2·016MHz in Turbo mode, is required on the ECLK pin. Note that, although the ACE9050 will operate with lower frequencies, the radio functions such as the Modem would not then function correctly in a radio system. The clock generator has a built-in oscillator which requires an external crystal. Alternatively, the oscillator can be powered down and either a 800mv peak-to-peak AC-coupled sinewave or a CMOS logic level applied to XIN may be used. If the ACE9030 is being used this provides a suitable output via CLK8; AC coupling must be used. The main internal clock (1·008MHz) is derived from the CPU clock, or ECLK. This can either be 1·008 MHz or 2·016 MHz in Turbo mode. In Turbo mode ECLK is divided by 2 to generate the main 1·008MHz clock. This gives correct functionality when in Emulation mode, where the ECLK frequency is generated externally. The clock generator produces a clock bus with all of the internal clock frequencies required by the ACE9050. Various frequencies are also available externally . If an external crystal is used with the Crystal Oscillator, Fig. 17 shows the external components required. Careful layout rules should be applied to the external Crystal Circuit design. These include mounting the components as close as possible to the ACE9050 and avoiding running signal lines close to the oscillator circuit. Description TURBO: Port 4 bit 3 0 = 1·008MHz (Reset state) 1 = 2·016MHz (Turbo) ENSIS: Port 3 bit 2 0 = CPUCL pin: OUT2 [0] (Reset state) 1 = CPUCL pin: 8·064MHz CLKENAB: Port 5 bit 1 0 = C1008 pin = 0 1 = C1008 pin = 1·008MHz (Reset state) XOSC PD: Port 5 bit 6 0 = Oscillator active (Reset state) 1 = Oscillator power down Table 37 8. BAUD RATE GENERATOR The Baud Rate Generator provides standard baud rate clocks for the SCI in the 6303 block. It is internally connected to the 6303 Port2 bit 2. For Emulation mode the Baud Rate generator clock output is available to drive the shadow 6303. The Baud rate clock output is 8 times the baud rate. This is the requirement for a standard 6303. Baud rates available are shown in Table 38. For higher baud rates a 6303 transfer rate can be selected in the TRCSR register. As these are referenced to the ECLK they will be non-standard rates. External Pins 2 X1 R1 3 C1 XIN XOUT C2 R1 = 470kΩ to 1MΩ C1, C2 = 22pF typical (Refer to AC Characteristics) BAUDCLK: Baud rate clock output. (pin 6) This output is 83the baud rate. It is used in emulation mode only by the shadow 6303. Associated Registers BRG: Baud rate Select port - Write only Bits Fig. 17 External crystal components External Pins CPUCL 8·064 MHz Output (pin 94) This output is the buffered crystal or clock input frequency. After reset it is disabled, but can be enabled by software. Refer to Associated Registers. C1008 1·008 MHz Output (pln 90) This output is the main clock divided by eight. It must always be 1·008 MHz in a mobile phone application using the ACE chipset. It is intended to drive the ACE Serial interface clock. It is enabled after reset, but can be disabled by software. Description [7: 3] XXXX Unused [2: 0] 000 001 010 011 100 600 Baud (Reset state) 1200 Baud 2400 Baud 4800 Baud 9600 Baud Table 38 9. EXTERNAL RESET AND WATCHDOG FUNCTION ECLK Processor Clock (pin 99) This is the processor clock. It is an output in Normal mode, but an input in Emulation. The frequency is 1·008MHz, or 2·01 6MHz in Turbo mode. XIN Crystal or External source (pin 2) Input Crystal or external source input. External source must be AC-coupled or CMOS levels. XOUT Crystal Output (pin 3) If an external crystal is used connect between XIN and XOUT. If an external source is used this output should be left unconnected. 24 The ACE9050 contains a Master reset circuit. Upon a reset being applied, all the circuits are reset and the registers put into a known state. These are detailed in Tables 8 and 9 for the ACE9050 and 6303 registers respectively. The mode selection of the 6303 also occurs automatically upon Master reset. An external output (EXRESN) is also asynchronously driven low. The Master reset circuit is activated by one of two means: (a) The external pin MRN (Master Reset) being driven low. (b) Watchdog Time out. The Watchdog circuit provides an automatic means to reset the processor if it gets stuck in an infinite loop, which would be ACE9050 caused by the software code entering an illegal state. This could be due to an incorrect sequence being entered by the user or a glitch on either the data or address bus causing the wrong instruction to be executed. The Watchdog is a 4-second counter which is always counting and when it overflows a system reset is generated. This will reset the ACE9050 and drive the external reset low for 100ms. It will not reset POFFN, so the phone will not turn off. Refer to the ‘Autonomous Time Out (ATO)’ section for more details. To prevent the system reset the Watchdog counter must be cleared. This will prevent the system reset for 4 seconds. The following actions clear the Watchdog counter: 1. In service mode the counter is permanently cleared, preventing the system reset. 2. MRN low clears the Watchdog counter. The counter thus starts when MRN goes high. 3. The processor making a write access to the Watchdog register. Thus in normal operation the software code must be sure to access the Watchdog register once every 4 seconds to prevent a reset. External Pins MRN Master Reset (pin 91) This active low input completely resets the ACE9050 Inte~rated circuit. It prevents the Watchdog timer from counting. The ACE9050 will be reset for the duration of the MRN pulse plus an additional 100ms. The clock must be running for the device to reset correctly. EXRESN External Reset (pin 89) This active low output is provided for an external reset function. It is active for a minimum of 100ms in the case of a Watchdog reset. In the case of a MRN reset EXRESN will be low for the duration of MRN being low plus an additional 100ms, as shown in Fig. 18. MRN I/P EXRESN O/P 100ms Fig. 18 EXRESN reset Associated Registers REWD A write access to this address will clear the watchdog 4second counter. 10. I2C INTERFACE General The ACE9050 I2C provides an interface between an I2C bus and a microprocessor. Details of the I2C bus specification can be found in the Philips Components Technical Handbook. The I2C bus allows integrated circuits to communicate directly with each other via a bidirectional 2-wire bus. Interfacing the devices in an I2C system is very simple because they connect directly to the two bus lines: a serial data line (SDA) and a serial clock line (SCL). A prototype system or final product version can easily be modified by ‘clippinq’ or ‘unclipping’ ICs to or from the bus. The I2C is a reliable, multi-Master bus with integrated addressing and data transfer protocols. The multi-Master capability of the I2C is very important, although many designs do not require it. Both lines of the I2C bus are connected to a positive supply via a pull-up resistor, and remain high when the bus is not busy. Each device is recognised by a unique address, and can operate as either a transmitter or a receiver, depending upon the function of the device. When a data transfer takes place on the bus, a device can either be a Master or a Slave. The device which initiates the transfer, and generates the clock signals for this transfer, is the Master. At that time, any device addressed is considered to be a Slave. It is important to note that a Master could either be a transmitter or a receiver; a Master microcontroller may send data to an EEPROM acting as a transmitter, and then interrogate the EEPROM for its contents acting as a receiver, in both cases performing as the Master initiating the transfer. In the same manner, a Slave could be both a receiver and a transmitter. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse in order to be valid. Changes in the data line at this time will be interpreted as control signals. A high to low transition of SDA with SCL high indicates a Start condition, and a low to high transition of SDA whilst SCL is high defines a Stop condition. The bus is considered to be busy after a Start condition and free at a certain time interval after a Stop condition. These conditions are always generated by the Master. Each byte is transmitted serially with the MSB first. The byte is 8 bits long followed by an acknowledge bit. The clock pulse related to the acknowledge bit is generated by the Master. The device acknowledging must pull down the SDA line during this clock pulse, whilst the transmitting device releases the SDA line (pulled high) during this pulse. A Slave receiver must generate an acknowledge after the reception of each byte. If the receiving device cannot receive the data byte immediately, it can force the transmitter to wait by holding the SCL line low. Each device on the bus has its own unique address. The address of the microcontoller is fully programmable whereas peripheral devices usually have fixed and programmable portions. Before any data is transmitted on the bus, the Master transmits on the bus the address of the Slave to be accessed. The Slave should acknowledge the Master’s addressing. The addressing is done by the first byte transmitted by the Master after the start condition. An address on the network is seven bits long, appearing as the most significant bits of the address byte. The last bit is a direction (R/W) bit, with a 0 indicating that the Master is transmitting (WRITE) and a 1 indicates that the Master is requesting data (READ). When an address is sent, each device on the system compares the address with its own. If there is a match the device will consider itself addressed and send an acknowledge. In addition to the above ‘standard’ addressing, the I2C bus protocol allows for ‘general call’ addressing and interfacing to CBUS devices. Fig. 19 shows a complete data transfer, comprised of an address byte indicating a WRITE and two data bytes. It also indicates the Start and Stop conditions . 25 ACE9050 SDA D7· · · · ·D1 D0 1-7 8 D7· · · · ·D1 D0 1-7 8 SCL ACK DATA 9 R/W 9 ADDRESS START CONDITION 9 8 1-7 S DATA ACK ACK P STOP CONDITION Fig.19 I 2C Data transfer ACE9050 I2C The ACE9050 I2C can operate in one of four modes: 1. Master Transmit 2. Master Receive 3. Slave Transmit 4. Slave Receive The ACE9050 can operate in multi-Master systems (where there is more than Master on the bus). The ACE9050 I2C will perform bus arbitration and clock synchronisation. In a mobile handset where the I2C is used to interface to a serial PROM and/ or an LCD display it would be sufficient to have the ACE9050 as the sole Master. The I2C interface consists of the SCL (clock) and SDA (data) lines. These are multiplexed with the 6303 bidirectional Port1 pins to reduce the overall pin count. Selection is made via the ACE9050 Port5. The internal 6303 microprocessor interface consists of five 8bit memory mapped registers and a processor interrupt line. The interrupt is connected to the 6303 IRQN interrupt, as are the ACE9050 internal and external Interrupt ports. External Pins SCL/6303 Port 1 [4] (pin 9) Bi-directional pin, used for the I2C clock when selected. This pin requires an external pull up resistor when used as SCL.. The value of the pull up resistor depends on the system and I2C bus implementation. Refer to the I2C bus specification. In a typical system the resistor value would fall between 1kΩ and 20kΩ. SDA/6303 Port 1 [3] (pin 13) Bidirectional pin, used for the I2C data when selected. This pin requires an external pull up resistor when used as SDA. The value of the resistor should be the same as the SCL line. Associated Registers SEL_I2C Port 5 bit 2 Bit 2 Name Description SEL_I2C 0 = I2C Reset, P1 [4] and [3] selected 1 = I2C operational, SCL and SDA selected Table 39 I2C_CNTR Control Register Read/Write This register is used to control the ACE9050 I2C. The program can write and read from the register. The hardware can also change the status of the bits in this register (see Table 40). Note that this register is cleared to 00H when the I2C is reset. IEN Interrupt Enable When IEN is set to 1 an interrupt will occur when the IFLG bit is set. This will cause an interrupt on the 6303 IRQ. When IEN is cleared to zero the I2C interrupt will be disabled. 26 Position Bit Description D7 D6 D5 D4 D3 D2 D1 D0 IEN ENAB STA STP IFLG AAK - Interrupt Enable Bus Enable Master Mode Start Master Mode Stop Interrupt Flag Assert Acknowledge Read back only: 0 Read back only: 0 Table 40 ENAB Bus Enable When ENAB = 1 the ACE9050 I2C will respond to calls to its Slave address (SLA6-0) and to the general call address if bit GCE in the I2C_ADDR register is set. STA Start Master Mode When STA = 1 the ACE9050 I2C enters Master mode and will send a START condition on the bus when the bus is free. If the STA bit is set to 1 when already in Master mode and one or more bytes have been transmitted then a repeated START condition will be sent. If the STA bit is set to 1 when the ACE9050 I2C is being accessed in Slave mode then the ACE9050 I2C will complete the data transfer in Slave mode and then enter Master mode when the bus has been released. After the START condition has been sent this bit will be automatically cleared. STP Stop Master Mode When STP is set to 1 in Master mode then a STOP condition is transmitted on the I2C bus. If the STP bit is set to 1 in Slave mode then the ACE9050 I2C will behave as if a STOP condition has been received, but no STOP condition will be transmitted on the I2C bus. If both STA and STP bits are set the ACE9050 I2C will first transmit the STOP condition (if in Master mode) then transmit the START condition. The STP bit is automatically cleared: writing a zero to this bit has no effect. IFLG Interrupt Flag This bit gets set if an interrupt condition occurs in the I2C; however an interrupt will only be generated if the Interrupt Enable (IEN) is set. An interrupt condition is defined as one of 26 of the possible 27 ACE9050 I2C states being entered. The only state that does not set IFLG is state F8H. Refer to STAT register for more information on the I2C states. When IFLG is high then the low period of the I2C bus clock line, SCL, is stretched and the data transfer is suspended. When IFLG is reset to zero the interrupt is reset and the I2C clock line released. ACE9050 AAK Assert Acknowledge. This bit is used to determine whether an Acknowledge bit is sent when the I2C Receives data. It also indicates the last byte to transmit when the I2C is in Slave Transmit mode. AAK is set to one: An acknowledge (low level on SDA) will be sent during the acknowledge clock pulse on the I2C bus when: 1. The Slave address has been received. 2. The general call address has been received and the GCE bit in the I2C ADDR registers set to one. 3. A data byte has been received in Master or Slave mode. AAK is cleared to zero: When a data byte is received a Not Acknowledge (high level on SDA) will be sent, both in Master and Slave modes. In the Slave Transmitter mode then the byte in the I2C_DATA register is assumed to be the ‘last byte’. After this byte has been transmitted the I2C will enter state C8H then return to the idle state. I2C_STAT Status Register Read This read only register contains a 5-bit status code, as shown in Table 41. Code (Hex) 00 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78 80 88 90 98 A0 A8 B0 B8 C0 C8 F8 Bit Name Description [7:3] STATUS State code Read back as zero [2:0] Table 41 There are 27 possible status codes. When I2C_STAT contains the status code F8H no relevant status information is available and the IFLG bit in the I2C_CNTR register is not set. All other status codes correspond to a defined state of the ACE9050 I2C. When each of these states is entered the corresponding status code appears in this register and the IFLG bit in the I2C_CNTR register is set. When the IFLG bit is cleared the status code returns to F8H. The 27 possible status codes shown in Table 42 If an illegal condition occurs on the I2C bus then the bus error state is entered, status code 00H. To recover from this state the STP bit in the I2C_CNTR register must be set and the IFLG bit cleared. The I2C will then return to the idle state, no STOP condition will be transmitted on the I2C bus.. Status Bus error START condition transmitted Repeat START condition transmitted Address + write bit transmitted, ACK received Address + write bit transmitted, ACK not received Data byte transmitted in master mode, ACK received Data byte transmitted in master mode, ACK not received Arbitration lost in address or data byte Address + read bit transmitted, ACK received Address + read bit transmitted, ACK not transmitted Data byte received in master mode, ACK transmitted Data byte received in master mode, Not ACK transmitted Slave address + write bit received, ACK transmitted Arbitration lost in address as master, slave address + write bit received, ACK transmitted General call address received, ACK transmitted Arbitration lost in address as master, General call address received, ACK transmitted Data byte received after slave address received, ACK transmitted Data byte received after slave address received, Not ACK transmitted Data byte received after General Call received, ACK transmitted Data byte received after General Call received, Not ACK transmitted STOP or repeat START condition received in slave mode Slave address + read bit received, ACK transmitted Arbitration lost in address as master, slave address + read bit received, ACK transmitted Data byte transmitted in slave mode, ACK received Data byte transmitted in slave mode, ACK not received Last byte transmitted in slave mode, ACK received No relevant status information, IFLG =O Table 42 Possible values of I2C_STAT Register 27 ACE9050 I2C_CCR Clock Control Register: Write This register is write only, the seven LSBs control the clock frequency on the I2C bus when in master mode. The register is cleared to 0 when the I2C is reset. Position Bit D7 D6 D5 D4 D3 D2 D1 D0 m3 m2 m1 m0 n2 n1 n0 Clock Synchronisation If another device on the I2C bus drives the clock line when the ACE9050 I2C is in master mode the ACE9050 I2C will synchronise its clock to the I2C bus clock. The high period of the clock will be determined by the device that generates the shortest high clock period. The low period of the clock will be determined by the device that generates the longest low clock period. A slave may stretch the low period of the clock to slow down the bus Master. The low period may also be stretched for handshaking purposes. This can be done after each bit transfer or each byte transfer. The ACE9050 I2C will stretch the clock after each byte transfer until the IFLG bit in the I2C_CNTR register is cleared. Table 43 The frequency of the SCL clock is given by: fSCL = fCLK 103(m11)32n Where: fSCL is the I2C bus clock frequency, fCLK is 8·064 MHz, m is the value stored in CCR D[6: 3] and n is the value stored in CCR D[2:0] I2C_ADDR Slave Address: Read/Write This register sets the slave address of the ACE9050 I2C. This is only valid when the I2C is in Slave mode, allowing the system designer to select the required Slave address and prevent contentions. The register is cleared to 0 when the ACE9050 I2C is reset. Position D7 D6 D5 D4 D3 D2 D1 D0 Bit SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 GCE Bus Arbitration In master mode the ACE9050 I2C will check that each transmitted logic 1 appears on the I2C bus as a logic 1. If another device on the bus overrules and pulls the SDA line low arbitration is lost. If arbitration is lost during the transmission of a data byte or a not acknowledged bit is received the ACE9050 I2C will return to the idle state. If arbitration is lost during the transmission of an address the ACE9050 I2C will switch to slave mode so that it can recognise its own slave address or the general call address. Bus and Internal Clock Speeds The I2C bus is defined for bus clock speeds up to 100k bits/ s. The clock speed generated by the ACE9050 I2C in master mode is determined by the I2C_CCR register. All signals within the ACE9050 I2C are synchronised to an internal main clock (MCLK). The frequency of this clock is given by: Description Slave address 1st bit Slave address 2nd bit Slave address 3rd bit Slave address 4th bit Slave address 5th bit Slave address 6th bit Slave address 7th bit General Call address enable Table 44 SLA6 - SLA0 sets the 7-bit address. SLA6 corresponds to the first bit received from the I2C bus after a start condition. When the ACE9050 I2C receives this address after a START condition it will enter Slave mode. If GCE is set to one then the I2C will also recogonise the General Call Address.(00H). I2C_DATA Data Register: Read/Write This register contains the data byte to be transmitted or the data byte which has just been received. Bits Name [7:0] Read [7:0] Write RXData TXData Description Data received Data to transmit Table 45 28 In transmit mode the byte is sent MSB first, in receive mode the first bit received will be in the MSB of the register. After each byte is transmitted this register will contain the byte that was actually present on the bus. Therefore in the case of lost arbitration this register will contain the received byte. fMCLK = fCLK (m11) Where: fMCLK is the MCLK (main clock) clock frequency, fCLK is 8·064 MHz and m is the value stored in I2C_CCR D[6: 3] If the ACE9050 I2C is used in systems where there are other masters on the I 2C bus then the frequency of MCLK should not be less than 500 kHz to prevent the ACE9050 I2C from missing a START condition sent by another master. Modes of Operation The following section details the operation of the ACE9050 I2C in the four possible modes of I2C transfer, namely: Master Transmit, Master Receive, Slave Transmit and Slave Receive. Master Transmit In the master transmit mode the ACE9050 I2C will transmit a number of bytes to a slave receiver. Before the master transmit mode can be entered the I2C_CNTR register should be initialised as shown in Table 46, where X is either 0 or 1. ACE9050 Position Bit State If a repeated START condition has been transmitted then the status code will be 10H instead of 08H. D7 D6 D5 D4 D3 D2 D1 D0 IEN ENAB STA STP IFLG AAK - X 1 0 0 0 X 0 0 2. Transmit Slave Address and Write The I2C_DATA register should now be loaded, with the address of the slave to be written to in bits[7:1] and bit[0] cleared to zero to specify Write. The IFLG bit should now be cleared to zero before the transfer can continue. When the slave address and write bit have been transmitted and an acknowledqe bit received the IFLG will be set again. A number of status codes are now possible in the STAT register, as shown in Tables 47 and 48. 3. Transmit Data If the code 18H or 20H has been detected in the STAT, the next byte to be placed in the I2C_DATA register is the first data byte, or a word address in the case of some memory devices. The IFLG can then be cleared. After each additional data byte has been transmitted the IFLG will be set and one of three status codes will be in the START register, as shown in Tables 49 and 50. Table 46 1. Transmit Start Condition. The master transmit mode is entered by settinq the STA bit to one. The ACE9050 I2C will then test the I2C bus and will transmit a START condition when the bus is free. When a START condition has been transmitted the IFLG bit will be set and the status code in the STAT register will be 08H. Code 18H ACE9050 I2C state Micro response Addr and Write transmitted, ACK received Addr and Write transmitted, ACK not received 20H Next I2C action (a) WriteDATA, clear IFLG Transmit data byte,receive ACK (b) Set STA, clear IFLG Transmit repeated START (c) Set STP, clear IFLG Transmit STOP (d) Set STA and STP, clear IFLG Transmit STOP then START As for code 18H As for code 18H Table 47 Possible status codes after Slave address has been transmitted with the ACE9050 as the only bus Master Code 38H 68H ACE9050 I2C state Micro response Next I2C action (a) Clear IFLG Return to idle. (b) Set STA, clear IFLG Transmit START when bus free. Arbitration lost, Slave Addr and Clear IFLG: AAK = 0 Receive data byte, transmit Not ACK Arbitration lost Write received: ACK transmitted Clear IFLG: AAK = 1 Receive data byte, transmit ACK 78H Arbitration lost, GCA, ACK transmitted As for code 68H As for code 68H B0H Arbitration lost, Slave Addr and Write byte to DATA, clear IFLG, AAK = 0 Transmit last byte, receive ACK Read received: ACK transmitted Write byte to DATA, clear IFLG, AAK = 1 Transmit data byte, receive ACK Table 48 Possible status codes after Slave address has been transmitted with Multiple Bus Masters Code 28H 30H ACE9050 I2C state Data byte transmitted, ACK received Data byte transmitted, ACK not received Micro response Next I2C action (a) Write byte to DATA, clear IFLG Transmit data byte,receive ACK (b) Set STA, clear IFLG Transmit repeated START (c) Set STP, clear IFLG Transmit STOP (d) Set STA and STP, clear IFLG Transmit START then STOP As for code 28H As for code 28H Table 49 Possible status codes after Data has been transmitted with the ACE9050 as the only bus Master Code 38H ACE9050 I2C state Arbitration lost Micro response Next I2C action (a) Clear IFLG Return to idle (b) Set STA, clear IFLG Transmit START when bus free Table 50 Possible extra status codes after Data has been transmitted with multiple bus Masters 29 ACE9050 bit will be set and status code 08H will be in the I2C_STAT register. If a repeated START condition has been transmitted then the status code will be 10H instead of 08H . 4. Transmit Stop When all bytes have been transmitted the STP bit should be set. The ACE9050 I2C will then transmit a STOP condition, clear the STP bit and return to the idle state. If the Slave receiver cannot receive any more data it must indicate this to the Master by generating the Not Acknowledged condition. 2. Transmit Slave address and Read The I2C_DATA register should be loaded with the address of the Slave in bits[7:1] and bit[0] set to 1 to specify read. The IFLG bit should now be cleared to 0 before the transfer can continue. When the Slave address and read bit have been transmitted and an acknowledge bit received, the IFLG bit will be set again. A number of status codes are possible in the STAT register; these are shown in Tables 51 and 52. Master Receive In the Master receive mode the ACE9050 I2C will receive a number of bytes from a Slave transmitter. The sequence is not dissimilar to that for Transmit. For some memory devices a ‘dummy write’ may be required to transmit the word address before the read operation. Before the master receiver mode can be entered the I2C_CNTR register should be initialised as for enterinq master transmit mode. 3. Receive Data If the code 40H has been detected it can be assumed that a Slave has detected its address and when the IFLG is cleared the ACE9050 will begin to clock in valid data on the SDA line. After each data byte has been received the IFLG will be set, and require clearing. One of three status codes wil be in the I2C_STAT register, as shown in Tables 53 and 54. 1. Transmit Start Condition The master receive mode is entered by setting the STA bit to one. The ACE9050 I2C will then test the I2C bus and will transmit a START condition when the bus is free. After the START condition has been transmitted the IFLG Code ACE9050 I2C state Micro response 40H Addr and Read transmitted, ACK received 48H Addr and Write transmitted, ACK not received Next I2C action Clear IFLG, AAK = 0 Receive Data byte, transmit Not ACK Clear IFLG, AAK = 1 Receive Data byte, transmit ACK (a) Set STA, clear IFLG Transmit repeated START (b) Set STP, clear IFLG Transmit STOP (b) Set STA and STP, clear IFLG Transmit STOP then START Table 51 Possible status codes after Slave address has been transmitted with the ACE9050 as the only bus Master Code 38H ACE9050 I2C state As for Master transmit Micro response As for Master transmit Next I2C action As for Master transmit 68H 78H B0H Table 52 Possible extra status codes after Slave address has been transmitted with multiple bus Masters Code ACE9050 I2C state Micro response Next I2C action Read Data, clear IFLG, AAK = 0 ReceiveData byte, transmit Not ACK Read Data, clear IFLG, AAK = 1 Receive Data byte, transmit ACK 50H Data byte received, ACK transmitted 58H Data byte received, Not ACK transmitted (a) Read Data, set STA, clear IFLG Transmit repeated START (b) Read Data, set STP, clear IFLG Transmit STOP (b) Read Data, set STA and STP, Transmit STOP then START clear IFLG Table 53 Possible status codes after Data has been received in multi-Master system Code 38H ACE9050 I2C state Arbitration lost Micro response As for Master transmit Next I2C action As for Master transmit Table 54 Possible status codes after Data has been received in multi-Master system 30 ACE9050 4. Transmit Stop When the Master has finished receiving data it must signal the end of data to the Slave transmitter by generating a not acknowledge on the last byte that was clocked out by the Slave. The Slave transmitter must release the data line to allow the Master to generate the STOP condition. When all bytes have been received the I2C_STAT register should return a 58H. The microcontroller is then free to set the STP bit. The ACE9050 I2Cwill transmit a STOP condition, clear the STP bit and return to the idle state. Slave Transmit In the Slave transmit mode a number of bytes are transmitted to a Master receiver. The Slave transmitter has control of the SDA line and must ensure the bits are correctly acknowledged. Before the Slave transmit mode can be entered the CNTR register should be initialised as shown in Table 55, where X is either 0 or 1. Position Bit State D7 D6 D5 D4 D3 D2 D1 D0 IEN ENAB STA STP IFLG AAK - X 1 0 0 0 1 0 0 Table 55 1. Entering Stave Transmit Mode The ACE9050 I2C will enter Slave transmit mode when it receives its own Slave address (SLA6-0) and the read bit (bit 0 = 1 ) after a START condition. The ACE9050 I2C will then transmit an acknowledge bit and set the IFLG bit in the I2C_CNTR register and status code A8H (Slave address and read bit received, ACK transmitted) will be in the I2C_STAT register. Slave transmit mode can also be entered directly from a Master mode if arbitration was lost in Master mode during the address byte, and the Slave address and read bit were received. The status code in the I2C_STAT register will then be B0H. 2. Sending Data The data byte to be transmitted should then be loaded into the I2C_DATA register and the IFLG cleared. When the ACE9050 I2C has transmitted the byte and received an acknowledge the IFLG will be set and the STAT register will contain B8H. 3. Completing Transfer Slave Termination When the last byte to be transmitted is loaded into the DATA register the AAK bit should be cleared when, or immediately before the IFLG is cleared. After that last bit has been transmitted the IFLG will be set as usual but the STAT should contain C8H. When this IFLG flag is cleared the ACE9050 I2C will then return to the idle state. The AAK bit must be set to one before Slave mode can be entered again. 4. Master Termination If no acknowledge is received after transmitting any byte: the SDA line is released to allow the Master to generate, the Stop condition IFLG will be set and the STAT register will contain C0H. When the IFLG is cleared the ACE9050 I2C will return to the idle state. If the STOP condition is detected after an acknowledge bit then the ACE9050 I2C will return to the idle state. Slave Receive In the Slave receive mode a number of data bytes are received from a Master transmitter. Before the Slave receive mode can be entered the CNTR register should be initialised as for Slave transmit mode. 1. Entering Slave Receive Mode The ACE9050 I2C will enter Slave receive mode when it receives its own Slave address (SLA6-0) and the write bit (bit = 0) after the START condition. The ACE9050 I2C will then transmit an acknowledge bit and set the IFLG bit in the I2C_CNTR register and status code 60H (Slave address1write bit received, ACK Transmitted) will be in the STAT register. The ACE9050 I2C will also enter Slave receive mode when it receives the general call address 00H (if bit GCE in the ADDR register is set). The status code will then be 70H. Slave receive mode can also be entered directly from a Master mode if arbitration was lost in Master mode during the address byte, and the Slave address and write bit or general call address were received. (For the general call condition the GCE bit in the I2C_ADDR register must be set to one) The status code in the I2C_STAT register will then be 68H if the Slave address was received or 78H if the general call address was received. The IFLG bit must be cleared to zero to allow the data transfer to continue. 2. Receiving Data If the AAK bit in the I2C_CNTR register is set to 1 then after each byte is received an acknowledge bit (low level on SDA) is transmitted and the IFLG bit is set, the I2C_STAT register will contain status code 80H (or 90H if Slave receive mode was entered with the general call address). The received data byte can be read from the I2C_DATA register and the IFLG bit must be cleared to allow the transfer to continue. 3. Competing Transfer When the STOP condition or a repeated START condition is detected after the acknowledge bit, then the IFLG bit is set and the I2C_STAT register will contain status code A0H. If the AAK bit is cleared to 0 during a transfer then the ACE9050 I2C will transmit a not acknowledge bit (high level on SDA) after the next byte is received, and set the IFLG bit. The I2C_STAT register will contain status code 88H (or 98H if slave receive mode was entered with the general call address). When the IFLG bit has been cleared to 0 the ACE9050 I2C will return to the idle state. RADIO FUNCTIONS The ACE9050 provides the following Radio Functions, which will typically be required in a mobile phone implementation, all of which are controlled by internal configuration registers: Modem and SAT management, ACE Serial Interface, IFC counter, 2 pulse width modulators, Key pad interface and Tone generator. These functions are described in the following sections 1. INTERNAL CONFIGURATION REGISTERS The ACE9050 contains 3 internal configuration registers. These allow the hardware to be configured via software write instructions. The function of the bits is described in the relevant section in more detail. This section provides an overview of the 3 internal configuration registers. 31 ACE9050 Associated Registers PORT3 Read/Write Bit Name 7 ENMOD 6 ONRAD PORT5 Read/Write (continued) Block Logic state Bit Modem 0 = No action* 1 = Modem fully enabled 2 SEL_I2C I2C ACE serial interface 0 = Latch pulse 3 generated* 1 = Latch 3 set to 1 0 = I2C Reset* 1 = I2C Enabled, SCL and SDA selected 1 CLKENAB Clock Gen 0 = C1008 Low 1 = C1008 Enabled* 0 PWM1MUX Output Mux #1 Name Block Logic state 5 STIFC IFC counter 0 = IFC counter reset* 1 = Enable IFC counter 4 UPOFFN ATO and Watchdog 0 = POFFN set to 0* 1 = POFFN set to 1 3 MDMSLP Modem 0 = Active* 1 = Sleep 2. AMPS/TACS MODEM AND SAT CONTROLLER 2 ENSIS Clock Gen 0 = OUT2 [0]* 1 = 8·064MHz Clock General Description 1 SLEEP Decoder 0 = No action* 1 = CSEPN lnactive for address FFFFH 0 IFFREQ IFC counter 0 = 256 period count* 1 = 2432 period count *Reset state in Normal mode Table 58 (continued) The Modem function supports both AMPS and TACS mobile phone systems. Selection is made via software; no external component changes are necessary. The Modem provides the following hardware: CPU interface Data Receiver Data Transmitter SAT Decoder SAT Transmitter *Reset state in Normal mode Table 56 PORT4 Read/Write Bit Name 7 SINTSLP 6 - Not used 5 - Not used 4 NOMPLL Modem (Data Clk) 0 = Clk sync to data* 1 = Clk not sync to data 3 TURBO CPU clock 0 = 1·008MHz* 1 = 2·016MHz 2 SATMUX Modem (SAT Mux) 0 = TXSAT selected* 1 = RXSAT selected 1 IROM Decoder 0 = External ROM 1 = Internal ROM* 0 - Block ACE serial interface Logic state 0 = Active* 1 = Sleep Not used PORT5 Read/Write 7 - 6 XOSC_PD Block [5:4] OUT2.2_SEL Output Mux #2 3 - Not used Table 58 32 Logic state Not used Clock Gen AFC/RXDATA Data Input (pin 60) Data is fed into the digital Discriminator via this input pin. The data can be a composite Voice, Data and SAT modulated carrier mixed down to either 54kHz or 450 kHz. The signal must be of the CMOS input levels described in the AC Characteristics section. The ACE9030 provides such an output on its AFCOUT pin. The ACE9030 samples the 450kHz IF with a 504kHz clocked register to produce a 54kHz CMOS output. TXDATA Transmit Data Output (pin 63) When enabled this output generates Manchester encoded Data at the appropriate data rate. This produces a digital output which must be filtered and combined with the other sources of TX modulation. The ACE9040 provides these functions via the DATI input. Table 57 Name The Data Receiver contains a Digital Discriminator, Data Decoder and Word Sync Detector (see Fig. 20). The Transmitter generates Manchester encoded data. The SAT receiver measures the incoming SAT signal. The SAT transmitter can either retransmit the received SAT or generate one of the 3 standard SAT tones . External Pins *Reset state in Normal mode Bit 0 = PWM 1 1 = OUT_PORT2 [1]* 0 = Active Oscillator* 1 = Power down 00 = OUT2 [2]* 01 = PWM 2 10 = Latch 2 RXSAT Received SAT Input (pin 51) This input is for the received SAT which, must have been filtered to give the appropriate SAT tone with CMOS level swings. The ACE9040 provides the filtering and amplification to provide a suitable signal on the RSO output. TXSAT Transmit SAT output (pin 62) This output provides a CMOS level SAT frequency output. The source can either be the Received SAT, or a totally independent SAT tone generated locally in the ACE9050. This output which must be filtered and combined with the other source of TX modulation. The ACE9040 provides these functions via the TSI input. ACE9050 RXSAT ACE9040 AFCIN 450kHz SAT DECODER TXSAT MICRO DATA BUS AND CONTROL AUDIO DEMODULATOR SAT TRANSMITTER DATA RECEIVER AFC/RXDATA WORD SYNC DET DATA DECODER DISCRIMINATOR 54kHz 504kHz ACE9030 DATA TRANSMITTER TXDATA ACE9050 Fig.20 AMPS/TACS Modem and SAT Controller Associated Registers The Modem has 3 dedicated registers for control and data transfer. There are also bits in the general registers PORT3 and PORT4 which are used to set up the Modem. The bits are described in more detail in the relevant section. MDMSLP PORT3[3] (Table 59) This bit determines whether the modem is active or in sleep mode. The modem is put into sleep mode by turning off the clock to the Modem and associate circuitry. Modem mode MDMSLP MODPRT0 (Table 62) This is a dedicated read/write port used for controlling the Modem; Bit 7 MDRESN 0 = Reset Modem 1 = Modem enabled 6 A_TN 0 = TACS Modem 1 = AMPS Modem [5: 4] SCCTX [1:0] Active Sleep 0 1 Table 59 ENMOD PORT3[7] This bit is used to set up the Modem. It must be set to 1 by the software after a reset and before the Modem is used. It should then remain at 1. SATMUX PORT4[2] (Table 60) This bit is used to control the source of the Transmitted SAT signal. Function Name [5:4] bits: SAT generator 00 = 5·97kHz 01 = 6·00kHz 10 = 6·03kHz 11 = No SAT transmitted 3 ENAMPI 0 = TX output disabled 1 = TX output enabled 2 SYNDET 0 = Capture mode 1 = Sync mode 1 ENWS 0 = Word sync disabled 1 = Receiver will re-synchronise 0 VC_CCN 0 = Control channel 1 = Voice channel Table 52 SATMUX 0 1 Multiplexer output Locally generated SAT RXSAT Table 60 NOMPLL PORT4[4] (Table 61) In the Data Decoder the modem uses a locally generated clock to recover the data. NOMPLL selects whether this clock is forced to lock to the extract Data clock or not. Refer to Data Decoder section for more detail. NOMPLL Decoder clock 0 1 Normal mode: Data clock locked to incoming clock Free-running: Data clock unlocked Table 61 MODPRT1 This is a dedicated read/write port used for controlling the Modem. Write (Table 63) Bit Name Function 7 MDMTST Must always be set to 0 6 TXDINV 0 = TX Data not inverted 1 = TX Data inverted 5 RXDINV 0 = RX Data not inverted 1 = RX Data inverted 4 LF1_2 0 = Discriminator enabled 1 = Discriminator bypassed (Test) SQLEV [3: 0] Set the squelch threshold level 3: 0 Table 63 33 ACE9050 Interrupts MODPRT1 (continued) Read (Table 64) Bit Name 7 - The modem has 4 interrupt lines which feed into the Internal Interrupt Control block. The interrupts can be read, reset and individually masked in this block Function Not used IRQ-RX Bit3 This interrupt is generated every time the data (RXD [7:0]) and squelch values (SQRX [3:0]) are updated. This will be approximately every 800µs for AMPS and 1ms for TACS. If busy/ idle bits are extracted, these times will vary by a maximum of one bit period. B_I 0 = Busy/idle bit = 0 1 = Busy/idle bit = 1 [5:4] SCCRX [1:0] Bits [5:4]: SAT generator 00 = 5·97kHz 01 = 6·00kHz 10 = 6·03kHz 11 = No SAT received [3:0] SQRX [3:0] Number of Data bits in a word that have exceeded the pre-set Squelch threshold 6 Table 64 MODPRT2 This is a read/write port used for data transfer Write (Table 65) Bit Name [7:0] TXD [7:0] IRQ-WS Bit6 This interrupt occurs every time the 11-bit Barker code is detected in the incoming data stream. Refer the Word Sync Detector for more details. Function Data byte to transmit Table 65 Read (Table 66) Bit Name [7:0] RXD [7:0] IRQ-BI-SAT Bit5 This interrupt has a dual function, dependent on whether the Modem is set up for a control channel or a voice channel. On a control channel the interrupt occurs every time the busy/ idle bit B_I is updated in MODPORT1. This will occur nominally every 1ms in an AMPS system and 1·25ms in TACS. On a voice channel this interrupt indicates there is an updated SAT value present in SCCRX. This will occur every 10 to 12ms. Function Received Data byte (note 1) NOTE 1.When VC_CCN and ENWS = 0, busy/idle bits are extracted from the data stream and are not present in RXD. IRQ-TX Bit7 This interrupt occurs every time the first bit of a byte is transmitted from the Modem Transmitter. The software must ensure that the data in TXD is valid prior this interrupt. When enabled it will generate an interrupt every 800µs for AMPS and 1ms for TACS. The Data transmission sequence is discussed in more detail in the Modem Transmitter section. Table 66 MODEM BLOCK DESCRIPTIONS RE-SYNC D AFC/ RXDATA Q C Q C1008 42 MODPRT1 [4]: LF1_2 MODPRT1 [5]: RXDINV 2 1 D Q C Q D 12 11 Q C Q D Q C Q D Q C Q TO DATA DECODER 504kHz DISCRIMINATOR ENABLE/BYPASS RXDATA INVERT/NOT INVERT Fig. 21 Modem discriminator Control Block The Modem can be confiqured for either AMPS or TACS systems. Various clocks and timing blocks are configured depending on whether the data has a 10kHz or an 8kHz Bit rate for AMPS/TACS respectively. The Modem can also be entirely reset under software control. If the Modem is not required the clock to the associated circuitry can be stopped, thus reducing the current consumption of the ACE9050. Discriminator (Fig. 21) The Discriminator uses a digital delay technique. The incominq signal is first sampled at 504kHz. This means the input can either be the 450kHz IF at CMOS levels or the 54kHz output from the ACE9030; it makes no difference to the operation of the discriminator. 34 In the ACE9030 the signal is initially sampled at 504kHz, which is below the Nyquist frequency, so effectively a mixing function occurs. 504kHz mixed with 450kHz gives a frequency component at 54kHz. Further sampling of the signal at 504kHz in the ACE9050 then has no effect. The signal is then passed through a delay line of 12 D-type flip-flops, clocked at 504 kHz, giving a delay of 23·8µs, or 1·286 nominal 54kHz cycles. The non-delayed and delayed signals are then EXORed together, which produces a digital version of the analog equivalent FM demodulator: a 90 degree phase shifter and mixer. The ACE9030 contains a similar discriminator, optimised for the speech content of the signal. The ACE9030 data sheet contains a full description of the operation of such a circuit. ACE9050 Associated Register bits LF1_2 MODPRT 1[4] (Table 67) Bit 4 Function Name LF1_2 The digital tracking loop can be configured in two modes: Capture or Sync, as detailed in Table 70. 0 = Discriminator enabled 1 = Discriminator bypassed (test) Table 67 For test purposes the discriminator can be bypassed. This is achieved by setting LF1_2. In this case the Modem requires 10kHz or 8kHz Manchester encoded data, i.e. the baseband data signal. RXDINV MODPRT 1[5] (Table 68) Bit 5 Function Name RXDINV 0 = RX Data not inverted 1 = RX Data inverted Table 68 The phase of the Data from the Discriminator is determined by the RF architecture of the receiver. The data can be inverted to cater for both high side and low side VCO architectures. Data Decoder The Data Decoder is responsible for clock and data extraction from the discriminated baseband Manchester encoded data stream. Manchester encoded data inherently contains the clock. The Data Decoder extracts the clock timing from the incoming data stream and regenerates an appropriately phased clock. The circuit then EXORs the extracted clock with the data. This yields a 1 for the bit period if the data bit is in phase, or a 0 if the data is out of phase. It then samples the output from the EXOR at 504kHz. Thus, nominally 50·4 or 63 samples are taken per bit period for AMPS or TACS respectively. The data decoder will then decide if the bit is a 1 or a 0, on the state with the highest number of samples. If the number of ‘correct’ samples is over a certain threshold then a flag is set. The required threshold can be set by software and is referred to as the squelch level. The flag is passed to the Word Sync Detector along with the value of the bit. The Data Decoder uses a digital transition tracking loop to regenerate the correctly phased clock. A clock at 90 degrees to the data extraction clock and an integrate-and-dump function are used. This 90 degree clock is again EXORed with the incoming data stream. The result of this is fed into an up/down counter. The output of the counter, along with the bit value, will determine whether the phase of the incoming clock was early or late. The phase of the clock over the next bit period will be altered to pull the clock in the appropriate direction. This process repeats for every bit period. The amount the clock is pulled is determined by the SYNDET bit. Manchester encoded data transitions occur on the bit boundaries as well as in the centre of the bit. This is especially true for a string of 1s or 0s. There is a chance the clock will lock on to these, 180 degrees out of phase. The word structure contains a dotting sequence; this is a 1010… pattern which is devoid of incorrect transitions. The hardware can recognise the error condition during this time and automatically correct the clock phase. Associated Registers SYNDET MODPRT 0 [2] (Table 69) Bit 2 Name SYNDET Regenerated clock shift Mode Function 0 = Capture mode 1 = Sync mode Table 69 TACS (125µs) AMPS (100µs) 0 = Capture mode 64% (12µs) 65% (10µs) 1 = Sync mode 61% (2µs) 61·6% (4µs) Table 70 In Capture mode the regenerated clock is shifted by a greater percentage of the cycle than in Sync mode. This will allow the regenerated clock to slip over and then acquire the incoming clock phase faster. For example, to re-acquire phase in the AMPS system would take around 2ms with good signal levels. In Sync mode the regenerated clock is not shifted as much, allowing more accurate data extraction over the bit period. If the regenerated clock becomes out of phase in this mode it will of course take longer to re-acquire the correct phase. For example in the AMPS system, to re-acquire phase would take around 10ms. The clock rate for the circuit is 504kHz, hence the circuit works to a resolution which is a multiple of 2µs in all cases. In general, the SYNDET bit should be set to Capture mode until the system design is satisfied that the Modem is in Word Sync. Then the SYNDET should be switched to Sync mode before data reading begins. NOMPLL Nominal PLL Port 4 [5] The Digital Tracking loop’s operation can be turned on or off with the NOMPLL bit, as shown in Table 71. Mode NOMPLL 0 1 Data Clock synchronising enabled Data Clock free-running Table 71 The NOMPLL bit will generally be set to 0 to allow normal operation of the digital tracking loop and clock synchronisation circuit. With NOMPLL set to 1 the regenerated clock will not try to lock to the incoming data clock, but will keep its current phase. If there is a short period of time when data is not present it may be advantageous to set the NOMPLL bit. The Digital trackinq loop will then be prevented from ‘hunting’ for a non-existent data clock. When the data then reappears, the regenerated clock should still be in phase and data can be immediately decoded without the need to re-synchronise. This facility is of use in systems where the receiver can power down for short periods of time in Standby mode, thus reducing the overall current consumption of the phone unit. SQLEV [3: 0] MODPRT1 [3:0] The software can set a ‘squelch level’ for the incoming data. This sets the number of samples of a bit that have to be ‘correct’ for the bit to be approved. The Data Decoder sets a flag at the end of a bit period if the squelch level has been reached. The Word Sync Detector then sums the number of approved bits that occur in a byte and updates the SQRX register at the same time as the data register. Four bits are used to determine the squelch threshold, giving 16 different levels. The number of samples for AMPS and TACS systems is 50 and 63 respectively. Table 72 on the following page shows the number of samples required for a bit to meet the level set, and the percentage of the total number of samples for both AMPS and TACS settings that this represents. 35 ACE9050 SQLEV Samples [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AMPS % (50 samples) TACS % (63 samples) 100 96 92 88 84 80 76 72 68 64 98 95 92 89 86 83 79 76 73 70 67 63 60 57 54 51 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 Table 72 Squelch level settings Word Sync Detector The Word Sync Detector contains the hardware to detect the Barker code, synchronise the received bytes to the incoming data frame, extract Busy/Idle bits and update the RXD and SQRX registers. It also generates the IRQ-WS, IRQ-RX and IRQ-BI-SAT interrupts. The hardware has four modes of operation which can be selected by software. The Barker code sequence is used for achieving frame synchronisation to the incoming data word boundaries. It occurs in a message after the dotting sequence and before the first data word. The hardware detection circuit is an 11-bit serial shift register with appropriate asynchronous decode logic to detect the Barker code (11100010010). The action upon detecting word sync depends on the mode of the hardware. The Word Sync Detector contains a parallel register, into which the incoming data, RXD, is clocked. When the hardware is in the appropriate mode the Busy/Idle bits are removed from the data sequence before being fed to the Data Receive (RXD) register. The Word Sync Detector also tallies the number of times the Squelch level flag is set for an eight-bit byte and stores this in the SQRX register. The Word Sync Detector contains byte and frame counters which generate the IRQ-RX interrupt when the data and squelch registers are updated. The software must ensure these registers are read within the suitable time frame after IRQ-WS to avoid losing data. Associated Registers VC_CCN Voice/Control Channel MODPRT0 bit0 (Table 73) This bit allows the software to control the mode of the Word Sync Detector between Control channel and Voice channel. It also operates in conjunction with the ENWS bit; VC_CCN must be set to reflect the category of the current channel. VC_CCN 0 1 Mode Control channel Voice channel Table 73 ENWS Enable Word Sync MODPRT 0 [1] (Table 74) This bit allows the software to control the mode of the Word Sync Detector between ‘Sync on Barker’ and ‘ Not Sync on Barker’. It also operates in conjunction with the VC_CCN bit. 36 ENWS 0 1 Description Data will not reframe if a Barker code is detected Data will reframe if a Barker code is detected NOTE: Regardless of the setting of ENWS the IRQ-WS will be generated on detection of a Barker code. Table 74 RXD[7:0] MODPRT2 Read (Table 75) This register contains the data from a forward channel (FVC or FOCC) segmented into 8-bit chunks. Bit Name Function 7: 0 RXD[7:0] Data byte received Table 75 The first bit received goes to the most significant bit of the register. On a Control channel the Busy/Idle bits can be extracted. All other data on the Control channel and all data on the voice channel will be present in the registers. This includes the dotting and Barker sequences. The IRQ-RX interrupt occurs when the registers have been updated. SQRX[3:0] MODPRT1[3:0] Read (Table 76) These four bits contain the number of bits in the present received byte that have surpassed the Squelch threshold set. It will thus contain a number between 0 and 8. This register is updated at the same time as the RXD register. SQRX [3:0] Number of bits surpassing Squelch level 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 to 1111 0 1 2 3 4 5 6 7 8 Not valid Table 76 Possible Squelch readings B_I MODPRT1[6] Read (Table 77) This bit is the extracted Busy/Idle bit from a Control channel data stream. Note that an IRQ-BI-SAT interrupt occurs when this bit is updated. B_I Busy/Idle bit 0 1 0 1 Table 77 Modes of Operation The Word Sync Detector has four modes of operation. The modes affect how Busy/Idle bits a handled, the function of the IRQ-BI-SAT interrupt and the action of the Word Sync Detector upon finding a Barker code in the incoming data stream. The modes are selected via the VC_CCN and ENWS bits, as shown in Table 78. ACE9050 VC_CCN ENWS 0 0 Control channel syncronised Data reframe = disabled IRQ-BI-SAT = Busy/Idle Busy/Idle bits extracted 0 1 Control channel unsynchronised Data reframe = enabled IRQ-BI-SAT = Not Valid Busy/Idle bits not extracted 1 0 Voice channel Data reframe = disabled IRQ-BI-SAT = SAT update 1 1 Voice channel Data reframe = enabled IRQ-BI-SAT = SAT update Mode Description Table 78 Control Channel When on a Control channel the software must decide when to switch between the synchronised and unsynchronised modes. The Modem does not give any direct indication that bit synchronisation has been achieved; however, the IRQ-WS provides indication that a Barker code has been detected. The system designer can look for the IRQ-WS being generated regularly in a suitable time window corresponding to the frame time, RSSI levels and squelch levels, before determining the Modem is in synchronisation. Once the software has determined that the Modem is in synchronisation the ENWS bit must to be set to zero. The Word Sync Detector will then remove the Busy/Idle bits from the incoming data stream and not re-synchronise on Barker codes. The software must disable ENWS before the first Busy/Idle bit occurs after the Barker Code in the control channel frame. The time for this is 1ms on AMPS or 1·25ms on TACS systems. The software does not then have to re-enable ENWS unless synchronisation is lost. As the number of bits in a frame is not divisible by eight the Word Sync Detector circuit uses frame counters to realign the data on subsequent frames instead of Barker codes. This ensures spurious Barker codes occurring in the data do not upset the synchronisation of the Modem. Due to this action Barker codes will appear distorted when read in the RXD registers. The dotting and Barker code will appear as the following three consecutive bytes: AAH, B8H and 12H. Once in synchronisation, the software must ensure that the IRQ-WS still occur within the time window set up. If a number of IRQ-WS are missed, the software must assume the Modem has become unsynchronised and take appropriate action. It is up to the system designer to decide on the threshold for the number of IRQ-WS dropped, or any other type of software averaging . Table 79 shows a typical sequence for locking onto data when on a Control channel. Voice Channel Data is not a continuous stream on a Voice channel, as on a Control channel. The data sequence also does not contain Busy/ Idle bits. The software designer has to determine when valid data is present on the voice channel. The IRQ-WS interrupt timinq cannot be used for this purpose, as the data stream is not continuous. Also IRQ-WS interrupts will occur sporadically, even when no data is present, due to the probability of an incoming signal beinq decoded as a valid Barker code. The voice channel data sequence begins with a long dottinq sequence. The software can monitor the data present in the RXD registers, and when these reliably yield a pattern of AAH or 55H it can be assumed a data sequence is beinq transmitted. The software should then ensure an IRQ-WS occurs to indicate valid data is beinq received. Other system parameters such as RSSI, RX audio level and SAT can also be measured by the software. ENWS may be left enabled, or disabled after synchronisation. As there are no Busy/Idle bits and the frame is divisible by eight it is not critical to the hardware operation. Function Description 1 Set up ENMOD = 1 MDMSLP = 0 MDMRESN = 1 LF1_2 = 0 RXDINV = Setup to system NOMPLL = 0 SQLEV[3:0] = Set as required A_TN = Set as Required Disable all Modem Interrupts 2 Initialise VC_CCN = 0 SYNDET = 0 ENWS = 1 2 Acquire Enable IRQ-WS interrupt 5 Verify Ensure the IRQ-WS interrupts are occurring in the correct time window. It is up to the system designer to determine the exact criteria. 6 Lock When this occurs set: ENWS = 0 within 1ms SYNDET = 1 Enable IRQ-RX interrupt within 800µs. 7 Read Data Read and Squelch on interrupt 8 Check Ensure IRQ-WS occurs in correct time window. The data registers should contain AAH, B8H & 12H at the end of a frame. Table 79 Data sychronisation and acquisition sequence Data Transmitter The Modem transmitter is considerably simpler than the receiver. It contains a data register for writing data 8 bits at a time and Manchester encoding circuitry. It also contains timing and interrupt circuitry. Data to be transmitted is written one byte at a time to TXD[7:0]. This data is then transmitted on the next IRQ-TX interrupt, if the output is enabled. Bit 7 (most significant) is transmitted first. The Data Transmitter generates the IRQ-TX interrupts at the correct rate for the chosen system (800µs for AMPS or 1000µs for TACS) regardless of whether the transmitter is enabled or not. The Transmitter encodes the data into Manchester format before transmission. This is achieved by 37 ACE9050 IRQTX TXD REGISTER DATA BUS LOAD DATA 7:0 8-BIT SHIFT REGISTER Q7 C TXDATA AMPS 100µs TACS 125µs CLOCK TXDATIN MODPRT1 ENAMPI MODPRT0 Fig. 22 Modem Transmitter block diagram IRQTX ENABLE INTERRUPT IRQTX WRITE 1st DATA BYTE TO TXD REGISTER ENABLE ENAMPI (1st DATA BYTE TRANSMITTED) WRITE 2nd DATA BYTE TO TXD IRQTX IRQTX IRQTX WRITE 3rd DATA BYTE TO TXD (2nd DATA BYTE TRANSMITTED) WRITE LAST DATA BYTE TO TXD (LAST – 1 DATA BYTE TRANSMITTED) IRQTX IRQTX LAST DATA BYTE TRANSMITTED DISABLE ENAMPI Fig. 23 Modem transmission sequence generating a square wave at the bit rate and EXORing the generated clock with the relevant bit, for the bit period. The output can then be inverted, if this is required by the system designer. A block diagram is shown in Fig. 22. No data manipulation is made by the encoder hardware. The software must generate the dotting and Word sync patterns and the BCH coding. If the Transmitter is enabled the contents of the TXD register will be transmitted on an IRQ-TX interrupt, regardless of whether this register has been updated. This enables the generation of an ST tone with no overhead on the processor, other than timing the required duration. The software must simply write FFH or 00H to the TXD. Associated Registers (Tables 80, 81 and 82) MODPRT2 This is a read/write port used for data transfer Write Bit Name Function 7:0 TXD[7:0] Data byte to transmit (bit 7 transmitted first) Table 80 ENAMPI MODPRT 0 bit 3 Function Bit 0 1 TX output disabled TX output enabled Table 81 TXDINV MODPRT 1 bit 6 Function Bit 0 1 True Data output Inverse Data output Table 82 38 Data transmission sequence Table 83 and Fig. 23 describe the correct sequence for transmitting a Data message. Note that in the 5th step (Set ENAMPI high quickly) the latency between the IRQ-TX and setting ENAMPI will cause part of the first byte not to be transmitted. This byte will always be part of a dotting sequence, so this will not cause a degradation in data, however it is desirable to reduce this time to a minimum. Step 1 2 3 4 5 6 7 8 9 10 11 12 Action Enable IRQ-TX interrupt Wait for IRQ-TX interrupt Write Data byte to TXD Wait for IRQ-TX interrupt Set ENAMPI high quickly Write Data byte to TXD Wait for IRQ-TX interrupt Repeat steps 6 and 7 until last byte Write last byte Wait for IRQ-TX interrupt Wait for IRQ-TX interrupt Disable ENAMPI Table 83 Modem transmission sequence SAT MANAGEMENT The SAT Management circuitry consists of a SAT detector, SAT generator and a multiplexer. Refer to the External Pins section of the General Description for details of the two external pins: RXSAT and TXSAT . SAT Detector The SAT Detector measures the frequency of the signal on RXSAT input. When the Modem is configured for a Voice channel (VC_CCN high) a SAT measurement will occur every 10 to 12 ms. The SAT receiver measures the duration of 64 SAT cycles and depending on the result determines the SAT value. ACE9050 Further software filtering may be required. The result of the measurement will reside in MODPRT1 bits 5 and 6. If the IRQBI-SAT interrupt is not masked an IRQ-Bl-SAT interrupt will occur at the end of each measurement period, after the MODPRT1 has been updated. Associated Register SCCRX [1:0] MODPRT1 [5:4] Read SCCRX [1:0] SAT tone (Hz) 00 01 10 11 5970 6000 6030 No SAT Limits (Hz) 5955-5984 5985-6014 6015-6045 < 5955 > 6045 Table 84 SAT Transmitter The ACE9050 has an on-chip SAT generator which can generate 5·97kHz, 6kHz, or 6·03 kHz signals. The selection is made via bits SCCTX [1:0] in MODPRT0. Alternatively the received SAT can be looped around and re-transmitted. The ACE9050 provides a multiplexer so either source can be selected under software control via the SATMUX bit in PORT4. The generator circuit consists of a series of preset counters running from the system clock. The ACE9050 makes no allowance for varying the phase of the regenerated SAT tone as this not a requirement for current AMPS or TACS protocols. When the Received SAT is looped around the ACE9050 only buffers the incoming SAT signal on RXSAT before feeding it to the TXSAT output pin. Associated Registers SCCTX[1:01 MODPRT0 [5:4] Write SCCTX [1:0] Generated SAT tone (Hz) 00 01 10 11 5970 6000 6030 No SAT generated Table 85 SATMUX PORT 4[2] TX SAT source SATMUX 0 1 Internally generated SAT RX SAT Table 86 The buses can be used for data transfer between any ICs that have the appropriate interface logic; however, in a system using the ACE Chips the following words are valid on the ACEBus: ACE9030 Sleep Word Normal (ADC Values Read) Set-up Synth Word A Synth Word B Synth Word C Synth Word D Synth Dummy word (Low Noise Mode) ACE9040 Operating mode Initialising Mode 0 Initialising Mode 1 Handsfree For more information refer to the ACE9030 and ACE9040 data sheets. The ACEBus consists of a 1·008MHz clock, a bidirectional data line and 4 latch outputs. The clock and data lines are common, while the latch outputs are connected as follows: Latch 0: Control (ACE9040, LEN) Latch 1: Radio interface section (ACE9030, LATCHB) Latch 2: Internally connected to MUX #2 Latch 3: Synthesiser section (ACE9030, LATCHC) Valid data is transmitted in a stream of 24 continuous bits. At the end of the last bit the relevant latch is activated. This will latch the data into the target device. The data line will become tristate after the data transfer so that data may be received from a bus driver. The block contains eight ACE9050 registers. Three are for serial data transmit, three for receive and two are for bus control. The block also contains interrupt generating circuitry. The SynthBus contains a data line Synthdata, clock line Synthclk and associated Latch2, which is multiplexed with OUT2[2] and PWM2. The clock to ACE Serial Interface block can be disabled to reduce the overall power consumption of the ACE9050. Turning off this clock will disable the ACE Serial Interface but will not turn off the C1008 clock. External Pins C1008 (pin 90) Refer to Clock Generator Section. This clock is used for data transfer. In the ACE9030 and ACE9040 it is also used for clocking other functions so care must be exercised in turning this clock off. DTFG (pin 82) Bidirectional data line. The ACE9050 clocks out data loaded into the 3 registers. Data is clocked in and out of the ACE9050 on the falling edge of C1008. 3. ACE SERIAL INTERFACE BLOCK General Description The ACE Serial Interface contains two serial interfaces: The ACEBus and the SynthBus. The ACEBus is used to distribute data to and from ICs in the ACE chipset. The SynthBus is redundant when using the ACE chipset. The ACE9050 contains the Master Transmitter/Receiver unit for the ACEBus. The ACE9040 and ACE9030 contain slave units. The bus is used for programming the devices into the required state. This will be required when the phone is powered up, and during phone operation. The ACE9030 can also transmit ADCs values to the ACE9050 on the ACEBus. LATCH 0 (pin 80) Latch pulse used to target data transfer. In a system using the ACE chip set Latch0 is connected to the LEN input of the ACE9040. The latch is nominally a 500ns pulse. LATCH 1 (pin 78) Latch pulse used to target data transfer. In a system using the ACE chip set Latch1 is connected the ACE9030 Radio Interface (LATCHB). The latch is nominally a 500ns pulse. LATCH 3 (pin 75) Latch pulse used to target data transfer and optimise the performance of the synthesiser. In a system using the ACE chip 39 ACE9050 set Latch3 is connected to the LATCHC input of the ACE9030 Synthesiser. The lenqth of the latch can be varied and the latch can be set permanently high. Latch 3 can be used with the SynthBus, but is fixed at 500ns. SYNTHCL (pin 73) SynthBus clock line at nominally 126kHz. This is not a continuous clock. It is only activated when data transfer is required. SYNTHDAT (pin 72) SynthBus Data line. Contains valid data from the ACE9050, or is set to zero. LSICOM 3 (continued) Bit Name 3 2 1 0 Not used Not used Latch 1 Latch 0 Associated Registers Write Register Bits LSICOM 0 LSICOM 1 LSICOM 2 7:0 7:0 7:0 Bit Name 7 Go 0 = No data transfer 1 = Begin data transfer 6 CL Must be 0 Function Table 87 SINTSLEEP Port 4 [7] Bit 7 Function Name SINTSLEEP 0 = ACE Serial Interface enabled 1 = ACE Serial Interface powered down Table 88 STR_WIDTH Write The pulse width of Latch 3 is programmable between 99·2µs and 12·6ms, with 99·2µs increments. This register only works with the ACEBus, not the Synthbus. Bits Description 6:0 Pulse duration in increments of 100 C1008 periods. This register is decremented when a pulse is generated. Writing a value of 0 in this register terminates the pulse. Table 89 LSICOM 3 Write This register is the control register. This is used to define the mode of the data transfer, select which latch to activate and also is used to initiate the transfer. Bit Name 7 Go 0 = No data transfer 1 = Begin data transfer 6 CL Must be 1 5 ANS 4 Function 0 = No Answer request 1 = Answer request Not used Must be 0 Table 90 Valid bit fields for ACEBus data transfer 40 5 Not used Must be 0 4 Not used Must be 0 3 Latch 3 Latch 3 enabled for data transfer 2 Latch 2 Latch 2 enabled for data transfer 1 Not used Must be 0 0 Not used Must be 0 Description First byte to transmit Second byte to transmit Third byte to transmit Must be 0 Must be 0 Latch 1 enabled for data transfer Latch 0 enabled for data transfer Table 90 (continued) Transmitter Section The transmitter consists of five write registers, interrupt and latch generating logic, clock divider and timer, and three shift registers connected in series. These form the 24-bit message that is sent out on DTFG. The most significant bit of LSICOM 0 is transmitted first (refer to Fig. 7). Function Table 91 Valid bit fields for SynthBus Sending Data To begin the transmitting sequence the appropriate word has to be written to LSICOM 3. If a Latch 3 is required for the ACEBus a non-zero value must be written to STR_WIDTH prior to writing the control word in LSICOM 3. When LSICOM 3[7] (GO) is set, the clock to the serial shift registers is enabled. Data from LSICOM 0, 1 and 2 are clocked out on the falling edge of C1008. After the 24 data bits have been clocked out, the appropriate latch is generated on the next fallinq edge of C1008. At the same time as the latch the IRQ-SEND interrupt is generated internally. This is fed to the interrupt control block where it can be masked. The LSICOM 3 will then be reset, so as to be ready for the next data transfer. Receiver Section The receiver consists of three serial registers which can be read via LSICOM 4, 5 and 6. It also contains a counter, clocking and interrupt generating circuitry. Associated Registers Read Register Bits Description LSICOM 4 LSICOM 5 LSICOM 6 7:0 7:0 7:0 First byte received (ACE9030 preamble) Second byte received (ACE9030 result 1) Third byte received (ACE9030 result 2) Table 92 Receiving Data In order to receive, LSICOM 3[5] (ANS) must be set. After the transmission sequence, data on the DTFG line is clocked into the receiver on the falling edge of C1008. This process begins on the fifth negative clock edge after the latch pulse, to allow a response time from the slave (Fig. 8). After 24 clock cycles the complete word will have been clocked into the ACE9050. The data in the shift registers is latched into the three read registers. At the same time the IRQREC interrupt is generated. The IRQ-SEND interrupt is generated in the receive sequence with the relevant latch in the same way as for a transmit only sequence. ACE9050 PROGRAMMING Programming Constraints The programming of the interface is relatively straightforward when used with the ACE Chipset. However, the following constraints apply: (a) To activate a Latch 3 transfer on the ACEBus, the STR_WIDTH register must be written to with a non-zero value prior to writing to LSICOM3 [7] (GO) set. (b) After writing to LSICOM3 with the GO bit set, registers LSICOM0 to 3 must not be written for 25µs or until an IRQSEND Interrupt has been generated. (c) After writing to LSICOM3 with the GO and ANS bits set, LSICOM0 to 3 must not be written to until 6 clock cycles after an IRQ-SEND. LSICOM3 cannot be written to with bit 7 (GO) set until 55µs or the IRQ-REC interrupt has been generated. This is because the DTFG will contain the slave data until this time. (d) A value greater than 0 must not be written to the STR_WIDTH register preceding a LATCH0, 1, 2 transfer or a Latch3 transfer with the SynthBus. (e) The ACEBus and the SynthBus cannot be used simultaneously. ACEBus Transfers Latch 0 Data Transfer (1) Write Data to LSICOM0,1 and 2 (2) Write to LSICOM3 control word: CL ANS 1 1 0 0 0 SynthBus Transfers Latch 3 Data Transfer (1) Write Data to LSICOM 0 to 2 (2) Write LSICOM3 Control word: GO CL ANS 1 0 0 0 L3 L2 1 0 0 0 0 0 (3) Service IRQ-SEND interrupt if enabled Latch 2 Data Transfer (1) Write Data to LSICOM 0 to 2 (2) Write LSICOM 3 Control word: Programming Sequences GO The Strobe width will be a minimum of 100µs, However data can be transmitted to the other slave units during the Latch3 high time. Alternatively the Latch3 may be terminated prematurely by writing 0 into the STR_WIDTH register. This may only be done after the IRQ-SEND interrupt, to ensure the latch is not terminated prematurely. The ONRAD bit (PORT 3 [6]) can be used to keep the Latch 3 line high. Care must be taken when enabling Latch3 in this way so that spurious data is not clocked into the synthesiser. By setting the STR_WIDTH register to a suitably large value and enabling ONRAD before the STR_WIDTH time expires, the Latch 3 line can be permanently asserted. The STR_WIDTH time begins when the data transfer has completed. L1 L0 0 1 0 GO CL ANS 1 0 0 0 L3 L2 0 1 (3) Service IRQ-SEND interrupt if enabled 4. IFC COUNTER (3) Service IRQ-SEND interrupt if enabled Latch 1 Data Transfer (a) Without answer request (1) Write Data to LSICOM0, 1 and 2 (2) Write LSICOM3 Control word: GO CL ANS 1 1 0 0 0 L1 L0 1 0 0 (3) Service IRQ-SEND interrupt if enabled External Signals (b) With answer request (1) Write Data to LSICOM 0, 1 and 2 (2) Write LSICOM 3 Control word: GO CL ANS 1 1 1 0 0 L1 L0 1 0 0 (3) Service IRQ-SEND interrupt if enabled (4) Wait for IRQ-REC interrupt (5) Read data from LSICOM 4, 5 and 6 Latch 3 Data Transfer (ACEBus) (1) Write Data to LSICOM 0 to 2 (2) Write Strobe Width to STR_WIDTH(non-zero value) (3) Write LSICOM 3 Control word: GO CL ANS 1 1 0 0 0 The IFC counter is used as part of the Automatic Frequency Compensation loop, in conjunction with 6303 timer. The IFC counts a predetermined number of periods of the AFC_IN/ RXDATA signal. By timing this duration the frequency of the input can be determined. In a system using the ACE chipset this input frequency will be 54kHz. The Number of periods counted can be either 256 or 2432. This will give measurement times over a period of approximately 5ms or 45ms when using the ACE chipset. Other input frequencies are possible, but would give different time periods and thus accuracy could be affected. L1 L0 0 0 0 (4) Service IRQ-SEND interrupt if enabled AFC/RXDATA Input (pin 60) This signal also feeds to the AMPS/TACS modem. This pin can be directly connected to the AFCOUT pin of the ACE9030, when this device is being used. ICN Output (pin 77) This output is used in emulation mode only. It is output of the IFC counter, which should be connect to the Emulator 6303 PORT2 [0]. It is internally connected to the ACE9050 6303. Associated Registers Register Bit STIFCN PORT 3 [5] 0 1 0 1 IFFREQ P0RT 3 [0] Description Reset counter* Enable counter 2432 counts 256 counts *The counter must be reset before it can be enabled Table 93 41 ACE9050 TCSR 6303 Timer Control Status Register Register used to control and read the status of th 6303 Timer block. Refer to ‘6303 Processor Unit’ section of Hitachi or Motorola data book for full details . ICR 6303 Input Capture register 16 bit read only register used to hold the value of the free running counter captured when the proper transition of the ICN input occurred. Refer to ‘6303 Processor Unit’ section or Hitachi or Motorola data book for full details. Detailed Operation Once the IFC counter is set the next rising edge of the AFC/ RXDATA input pin will generate a negative transition on ICN. The IFC counter will then count the required number of transitions and create a positive edge on ICN at the end of the count period. The program has to control the 6303 timer in such a way that first the negative and then the positive transition of ICN is captured. The software can then calculate the difference between the two readings, which will give the elapsed time. Two Pulse Width Modulators are available in the ACE9050. These provide CMOS type outputs whose average high time can be set by software. External components can be used to filter the output and give a mean DC level. The values chosen for these components depend on the ripple and response time required in the application. Typical applications for such outputs are LCD contrast control and battery charging control. The PWM outputs are fed to output multiplexers; the corresponding external pin function is selected by software. The PWM circuits are designed to minimise the low frequency components of the output wave form. The PWM works on a 254µs cycle time, with 0·992µs pulse duration. The number of pulses is programmed using the appropriate register. The hardware ensures that the pulses are distributed as evenly as possible within a cycle. This is shown in Fig. 24 for some simple programming examples. With suitable external components the following formula can be used to obtain the mean DC level of a PWM output: VMEAN = (DAC[7:0]4256)3VDD Programming Example Initialise External Pins (a) Set IFFREQ to the determine the required Count (b) Reset STIFCN bit. This bit is reset by a hardware reset or by writing 0. It is not reset by the counter finishing execution. (c) Ensure the 6303 TCSR register is configured so as to capture a falling edge on ICN. OUT2[1]/PWM1 Output (pin 98) Selection for the source for this pin is made via the PWMlMUX bit in PORT5. This pin is also described in the External Ports and Multiplexer section. Begin Count (a) Write 1 to STIFCN (b) Read the ICR after the negative transition on ICN (c) Set TCSR register so as to capture a rising edge on ICN (Within 5 or 45 ms) End of Count (a) When a capture has occurred the ICR register can be read. Calculate From the difference between the two ICR values captured, the elapsed time for the count period can be calculated. It is then possible to estimate the offset of the system crystal and cancel out this error using the ACE9030 DACs. If the crystal is off frequency it will have little effect on the timer accuracy. It will however affect the main synthesiser as the error is multiplied by the divider ratio set in the main synthesiser. The absolute error is then mixed down to appear on the 54kHz directly. OUT[2]/PWM2/LATCH[2] Output (pin 81) Selection for the source for this pin is made via the OUT2.2_SEL bits in PORT5. This pin is also described in the External Ports and Multiplexer section. Associated Registers Write Register Bits DAC1 PORT 7:0 Number of output pulses in a cycle period DAC2 PORT 7:0 Number of output pulses in a cycle period 5. PULSE WIDTH MODULATOR NUMBER LOADED 32 64 128 1·008 MHz CLOCK Fig. 24 Pulse Width Generator output 42 Description Table 94 ACE9050 PORT5 Read/Write (Note 1) Bits Name 5:4 OUT2.2_SEL 00 = OUT_PORT2[2] (Note 2) 01 = PWM2 10 = Latch 2 11 = Not valid 0 DATA BUS Description PWM1MUX 5 DATA BUS NOTES 1. These register bits are also described in the External Ports and Multiplexer section. 2. Reset state. 4 6. BEEP ALARM RING (BAR) TONE GENERATOR BAR Output (Pin 96) CMOS output which is determined by the state of the registers in the BAR block (BARHIGH, BARLOW and BARENABLE). 5 59-55 KPO [4:0] KEYP READ Table 95 External Pin 5 KEYP WRITE 0 = PWM1 1 = OUT_PORT2[1] (note 2) The ACE9050 provides a Beep Alarm and Ring Tone generator unit. This provides a digital output pulse train. The high and low time can be programmed with software. It is thus possible to vary the output tone frequency, period and volume. The pulse train can also be disabled whereupon the output will be set low. Within the system this output can be used to control a buzzer driver. KPOT 66-69 [3:0] KPI INPUTS KPI [3:0] [7:4] IDENT 010 Fig. 25 Keyport configuration Output Port The output port has five individual outputs, which can be used as scanning outputs connected to a keyboard matrix, or can be used for other general purposes . External Pins KP0[4: 0] Outputs (Pins 59: 55) The state of these outputs are defined by the respective bits in the internal registers KEYP and KPOT. Associated Registers Write Register Bits BARHIGH 7:0 BAR ON time BARLOW 7:0 BAR OFF time BARENABLE 0 Description 0 = BAR output low 1 = BAR output pulsing Table 96 Programming The two programmable 8-bit registers determine the ON and OFF times in steps of approximately 8µs (7·9µs). The maximum ON and OFF times are approximately 2ms each (2·02ms). The following formula is used to calculate the actual times: BAR ON Time = (2562BARHIGH[7:0])37·93µs BAR OFF Time = (2562BARLOW[7:0])37·93µs 7. KEYPAD INTERFACE AND CHIP IDENTITY The Keyboard interface consists of a 5-bit output port, a 4-bit input port and associated registers to read, write and configure the ports (see Fig. 25). Alternatively these ports can be used for general I/O. The output port drive configuration can be set via software to provide the system designer with full flexibility. The port has tristate output buffers, controlled by the KPOT register. By programming KEYP and KPOT appropriately the outputs can be configured to drive in the following ways: High impedance Driving logic output (high or low) Open drain Open source. Associated Registers KEYP Write Keypad output port register Bits Description 4:0 Sets or clears associated bit in Output Port register Table 97 KPOT Write Output Port driver configuration Bits Description 4:0 0 = Output driven to level set by relevant KEYP bit 1 = Output tristate Table 98 Programming Examples The following bit patterns thus yield the following output configurations: KEYP Write KPOT Output 0 1 0 0 1 1 X 0 0 0 1 0 1 1 0 1 0 Z 1 Z Z Description Logic drive Logic drive Open drain Open drain Open source Open source High impedance Table 99 43 ACE9050 Input Port The Keyboard interface has four inputs. These inputs can also be used as general inputs. The upper four bits of this port are hard wired and provide a means of identifying the present variant of the ACE9050. Level 0 1 KPI[3:0] 4-bit Input port (pins 66 to 69) The state of this input port can be obtained by reading the respective bits in the internal register KEYP. Associated Registers KEYP [7:0] Read Keypad input port register Bits Description [7:4] [3:0] Chip Identity code (See Table 101) Reads the level of the associated input on KPI [3:0] A typical source for the receive signal strength would be the RSSI output from the IF Strip. However this will need to be compared to a predefined level and the logical output fed to the ACE9050. The ACE9030 provides an ADC, programmable threshold register and comparator for this purpose via RXCD. TXPOW TX power level input (pin 61) Digital input to monitor the presence of a Transmitted signal, as shown in Table 103. Level 0 1 Table 100 Identity code 7 6 5 4 Receive signal absent Receive signal present Table 102 External Pins Bits Description Table 101 Transmit signal absent Transmit signal present Table 103 Description Read back 0 Read back 0 Read back1 Read back 0 Description A typical source for the transmit signal presence would be a detector in the TX path. However this will need to be compared to a predefined level and the logical output fed to the ACE9050. The ACE9030 provides two Op Amps that may be used for this purpose. One may be used as a buffer/amp and the other as a comparator in conjunction with a DAC, which is also on the ACE9030. The level of TXPOW can be directly determined via IN Port1[7], POWDET. POFFN Power Off output (pin 85) This pin is intended to be used to control external power regulators for the phone. It is reset low by an MRN reset. The software and the ATO then control the state of POFFN: The software can set the state of POFFN directly via Port 3[4]. The ATO reset can only drive POFFN output low. 8. AUTONOMOUS TIMEOUT (ATO) The Autonomous Time Out circuit (ATO) is provided to facilitate an automatic power down of the phone in the event of the phone entering an illegal transmitting state. The ATO block requires external functions to implement its intended operation. The ATO monitors the status of the RXCD and TXPOW inputs; in a typical system these will indicate the presence of received and transmitted signals, respectively. If a transmitted signal is detected, without the presence of a received signal the ATO circuitry can change the state of the output pin, POFFN. This should be used to remove power from the phone system via external power control circuitry. The main block in the ATO is a 30-second counter. It is reset by an accepted processor write to the RESATO register. The state of the external inputs RXCD and TXPOW determine whether the processor access is accepted. If the processor does not attempt to access the register, or access is blocked for a period of 30 seconds, the ATO Timer expires and an ATO reset occurs. External Pins RXCD Receive Path Carrier Detect Input (pin 100) Digital input to indicate the presence of a carrier in the receiver part of the Radio as shown in Table 102. 44 POFFN is not cleared by a Watchdog reset, so that this type of reset will not power down the phone. When in Service mode the ATO Reset is disabled and the IROM code sets POFFN to logic 1. Associated Registers RESATO Reset ATO: Write Bit - Description Write access resets the 30s ATO timer. Table 104 UPOFFN Port 3 Bit 4 of this register sets the state of the POFFN output, as shown in Table 105. Bit Name 4 UPOFFN Description 0 = POFFN output set low 1 = POFFN output set high Table 105 ACE9050 Block Descriptions ATO Timer The ATO timer is a 30 second resetable counter. If the ATO counter reaches 30 seconds, an ATO Reset is generated. The counter is reset by the following actions: (a) External MRN Reset (b) Accepted Processor Write to the RESATO register The levels of the two external signals RXCD (pin 100) and TXPOW (pin 61) are used to determine whether a processor Write to RESATO is accepted or not, as shown in Table 106. RXCD TXPOW 0 0 1 1 0 1 0 1 RESATO access Accepted Denied Accepted Accepted NOTE: The CPU cannot tell whether a hardware access has been accepted or not. Table 106 The RXCD input is filtered prior to use in the ATO Timer logic by the RXCD Filter. The ATO timer is NOT reset by Watchdog reset. ATO Reset When the AT0 Times Out the ATO reset circuit is trigered and the following occurs: (a) A Time Out Interrupt is generated. (b) If the POFFN is high it will be driven low. The Time Out interrupt is generated at least 1 second before the POFFN is driven low. This is to give the processor time to clean up before power is removed. The processor cannot prevent the ATO reset at this stage. The ACE9050 design assumes that the ATO Reset will remove power from the phone system. If the system is designed in such away that power is not removed from the ACE9050 the POFFN pin is only guaranteed to stay low for approximately 1 second. The state of the internal circuitry is not guaranteed after an ATO Reset. RXCD Filter The purpose of the filter is to smooth out short glitches in the RXCD input. The filter waits for 1 second of RXCD becoming high before the filter output is asserted. Once the output has been asserted for more than 1 second, if the RXCD goes low for more that 1 second the filter output will go low. The filter hardware consists of a 10-bit up-down counter clocked at 492Hz. If the RXCD input is high the counter increments. If it is low the counter decrements. Thus, assuming the counter begins at zero, with a fixed high on the RXCD the counter’s MSB will assert after 1 second and will overflow after approximately 2 seconds. When the counter overflows and RXCD is high it will continue to hold the maximum count value and conversely, when it reaches zero and RXCD is low, it will contain zero. The MSB of the counter is the filter output which is fed to the ATO. Programming Guide Although the processor only needs to access the ATO register once every 30 seconds to prevent the reset, the access should occur more frequently. This would ensure a spurious error condition unfortunately timed would not cause an ATO turnoff. Servicing the ATO with the Watchdog would be the sensible approach. 45 ACE9050 PROGRAMMER’S GUIDE TO CONTROL PORTS AND REGISTERS IN_PORT 1 External Inputs PORT 4 ACE9050 Configuration Read/Write Bit Read Name Bit Name Description 7 SINTSLEEP 7 6 5 4 3 2 1 0 POWDET SERV 0 INP1 [4] INP1 [3] INP1 [2] INRQ [1] INRQ [0] Level of TXPOW pin Level of SERV pin Read back 0 Level of INP1 [4] pin Level of INP1 [3] pin Level of INP1 [2] pin Level of INRQ [1] pin (interrupt or INP1 [1]) Level of INRQ [0] pin (interrupt or INP1 [0]) 6 5 4 Not used Not used NOMPLL 3 TURBO 2 SATMUX 1 IROM 0 Not used Table 107 OUT_PORT 2 External Outputs Read Name Description 7 6 5 4 3 2 OUTP2 [7] OUTP2 [6] Reserved Reserved Reserved OUTP2 [2] 1 OUTP2 [1] 0 OUTP2 [0] Inverted drive to OUTP2 [7] pin Inverted drive to OUTP2 [6] pin Should be set to 0 Should be set to 0 Should be set to 0 Drive level of OUTP2 [2] pin when selec ted by Port 5 Drive level of OUTP2 [1] pin when selec ted by Port 5 Drive level to CPUCL pin when CPUCL is disabled in Port 3 Table 108 PORT 3 ACE9050 Configuration Table 110 PORT 5 ACE9050 Configuration Read/Write Bit Name 7 6 XOSC Name 3 2 1 7 ENMOD Modem on 6 ONRAD ACE serial interface STIFC Start IFC count UPOFFN Power control MDMSLP Modem mode ENSIS CPUCL pin 4 3 2 Logic state Description 1 SLEEP 0 IFFREQ IFC counter Sleep * Reset state in Normal mode 0 = No action* 1 = Modem fully enabled 0 = Latch 3 pulse generated* 1 = Latch 3 set to 1 0 = IFC counter reset* 1 = Enable IFC counter 0 = POFFN set to 0* 1 = POFFN set to 1 0 = Active* 1 = Sleep 0 = OUT2 [0]* 1= 8·064MHz Clk 0 = CSEPN active for address FFFFH* 1 = CSEPN inactive for address FFFFH 0 = 256 period count* 1 = 2432 period count Table 109 46 Logic state Description 0 = Active* 1 = Power down 00 = OUT2 [2]* 01 = PWM 2 10 = Latch 2* Not used SEL_I2C Select I2C 0 = I2C reset* 1 = I2C enabled CLKENAB CLK enable 0 = C1008 low 1 = C1008 enabled* PWM1MUX Multiplexer 0 = PWM 1 1= OUT_PORT 2 [1]* control Not used Power down oscillator [5:4] OUT2.2_SEL Multiplex control Read/Write 5 0 = ACE serial interface active* 1 = Sleep Read back 0 Read back 0 0 = Clock synchronised to data* 1 = Clock free running 0 = 1·008MHz processor bus* 1 = 2·016MHz processor bus 0 = TXSAT selected* 1 = RXSAT selected 0 = External ROM 1 = Internal ROM* - * Reset state in Normal mode Bit Bit Description 0 * Reset state in Normal mode Table 111 MODPRT 0 Modem Control Read/Write Bit Name 7 MDRESN 6 A_TN [5:4] SCCTX 1 [0] 3 ENAMI Function 0 = Reset Modem* 1 = Modem enabled 0 = TACS Modem* 1 = AMPS Modem Bits 5: 4 = SAT generator 00 = 5·97kHz* 01 = 6·00kHz 10 = 6·03kHz 11 = No SAT transmitted 0 = TX output disabled* 1 = TX output enabled * Reset state in Normal mode Table 112 Cont… ACE9050 MODPRT 0 Modem Control (continued) BANK_SEL Bank Select Register Write only Bit Name 2 SYNDET 1 ENWS 0 VC_CCN Function 0 = Capture mode* 1 = Sync mode 0 = Word sync disabled* 1 = Receiver will resynchronise 0 = Control channel* 1 = Voice channel * Reset state in Normal mode Bit Name [7:5] 4 3 2 1 0 CS BA17 BA16 BA15 BA14 Description Not used Chip Select: 1 = CSE2N, 0 = CSEPN Banked address A17 Banked address A16 Banked address A15 Banked address A14 Table 112 (continued) MODPRT 1 Modem Control Write Bit Name 7 6 MDMTST TXDINV 5 RXDINV 4 LF1_2 Function Table 116 ACE9050 REGISTERS BY BLOCK 6303 Name [3:0] SQLEV [3:0] Must always be set to 0 0 = TX data not inverted* 1 = TX data inverted 0 = RX data not inverted* 1 = RX data inverted 0 = Discriminator enabled* 1 = Discriminator bypassed (Test) Set the squelch threshold level * Reset state in Normal mode Table 113 MODPRT 1 Modem Status Read Bit Name Function 7 6 B_I Not used 0 = Busy/Idle bit = 0 1 = Busy/Idle bit = 1 Bits 5: 4 = SAT received 00 = 5·97kHz 01 = 6·00kHz 10 = 6·03kHz 11 = No SAT received Number of data bits in a word that have exceeded the preset Squelch threshold [5:4] SCCRX [1:0] [3:0] SQRX [3:0] Table 114 LSICOM 3 ACE Serial Interface Control Register DDR 1 DDR 2 PORT 1 PORT2 TCSR 1 FRC_HIGH FRC_LOW ICR_HIGH ICR_LOW RMCR TRCSR RDR TDR R/W Addr W W R/W R/W R/W R/W R/W R R W R/W R W 00 01 02 03 08 09 0A 0D 0E 10 11 12 13 Description Data Dir register P1 Data Dir register P2 Data Port 1 Data Port 2 Timer Control/Status Free run counter MSB Free run counter LSB IP Capture register MSB IP Capture register LSB Rate and mode control TX/RX Control and Status RX data TX data Table 117 ACE9050 Internal Ports Name PORT 3 PORT 4 PORT 5 R/W Addr R/W R/W R/W BANK_SEL ACE9050 configuration ACE9050 configuration ACE9050 configuration Table 118 Bus Interface Name 26 40 42 Description R/W Addr W 44 Description Bank select Table 119 Write External Ports Bit Name 7 GO Function Name 6 CL 5 ANS 4 3 2 1 0 Not used Latch 3 Latch 2 Latch 1 Latch 0 0 = No data transfer 1 = Begin data transfer 0 = SynthBus (126kHz) 1 = ACEBus (1·008MHz) 0 = No answer request 1 = Answer request Must be 0 SynthBus: Latch 3 SynthBus: Latch 2 Latch 1 enabled for data transfer Latch 0 enabled for data transfer Table 115 R/W Addr IN_PORT 1 R OUY_PORT 2 R/W KEYP R/W KPOT W 22 24 36 68 Description External I/P Port External O/P Port Keypad I/P and chip ID O/P type for KPO Table 120 Watchdog and ATO Name REWD RESATO R/W Addr W W 6A 6C Description Reset Watchdog Reset Time Out Table 121 47 ACE9050 I2C Interrupts Name IRQPRT0 IRQPRT1 IRQPRT2 IRQPRT4 IRQPRT5 IRQPRT6 R/W Addr W W R W W R 70 72 2C 74 76 2E Description Reset internal interrupts Mask internal interrupts Read internal interrupts Reset external interrupts Mask external interrupts Read exernal interrupts Table 122 LSICOM0 LSICOM1 LSICOM2 LSICOM3 LSICOM4 LSICOM5 LSICOM6 STR_WIDTH 60 62 64 66 3A 3C 3E 67 Description ACE interface TX1 ACE interface TX2 ACE interface TX3 ACE interface Control ACE interface RX1 ACE interface RX2 ACE interface RX3 Latch 3 width Table 123 DAC1 DAC2 I2C Slave address I2C Data Tx/Rx I2C Control I2C Status I2C Clock MODPRT0 MODPRT1 MODPRT2 R/W Addr R/W R/W R/W BARHIGH BARLOW BARENABLE Configuration Control/Status Data Tx/Rx Table 126 BAR Name 30 32 34 Description R/W Addr W W W 50 51 52 Description BAR on BAR off BAR Output Enable Baud Rate Generator R/W Addr W W 5B 5C Description PWM 1 data PWM 2 data Table 124 48 54 55 56 57 57 Table 127 PWM Name R/W R/W R/W R W Description Table 125 Name R/W Addr W W W W R R R W I2C_ADDR I2C_DATA I2C_CNTR I2C_STAT I2C_CCR R/W Addr Modem ACE Serial Interface Name Name Name BRG R/W Addr W 53 Description UART Baud select Table 128 ACE9050 INDEX FUNCTIONAL OVERVIEW Page 3 PIN DESCRIPTIONS 4 ELECTRICAL CHARACTERISTICS 6 DC Characteristics AC Characteristics 5. INTERRUPTS Masking Interrupts Internal Interrupt Control Port External Interrupt Control Port Page 21 21 21 22 6. EXTERNAL PORTS & MULTIPLEXER 23 7. CLOCK GENERATOR 24 8. BAUD RATE GENERATOR 24 9. EXTERNAL RESET 24 TIMING DIAGRAMS Normal Mode Processor Interface Read Cycle Write Cycle Emulation Mode Processor Interface Read and Write Cycles Serial Interface Block ACEBus Read and Write Timings SynthBus Timing 7 8 9 10,11 11 INTERNAL REGISTERS AND RESET STATUS ACE9050 Registers 6303 Registers 12 13 MODES OF OPERATION 1.Normal Mode 2.Emulation Mode 3.Service Mode 4.Test Mode 5.Power down Modes 13 13 13 14 14 FUNCTIONAL DESCRIPTIONS 1. ACE9050 6303 General Description Pin Description Clock I/O Port 1 I/O Port 2 Programmable Timer Serial Communication Interface SCI (UART) RAM Control Register Operating Modes Low Power Consumption Modes Address Data & Memory Control Interrupt Processing Error Processing 14 14 14 14 14 15 15 16 16 16 16 16 16 10. I2C INTERFACE General SEL_I2C Register I2C_CNTR Register I2C_STAT Register I2C_CCR Register I2C_ADDR Register I2C_DATA Register Clock Synchronisation Bus Arbitration Bus and Internal Clock Speeds Modes Of Operation Master Transmit 1. Transmit Start Condition 2. Transmit Slave Address and Write 3. Transmit Data 4. Transmit Stop Master Receive 1. Transmit Start Condition 2. Transmit Slave Address and Read 3. Receive Data 4. Transmit Stop Slave Transmit 1. Entering Slave Transmit Mode 2. Sending Data 3. Completing transfer Slave Receive 1. Entering Slave Receive Mode 2. Receiving Data 3. Completing transfer 25 26 26 27 28 28 28 28 28 28 28 29 29 30 30 30 30 31 31 31 31 31 31 31 RADIO FUNCTIONS 2. INTERNAL ROM BOOT BLOCK Normal Mode Service Mode Steps 1 and 2 Step 3 Normal Mode Step 3 Service Mode Steps 4,5 and 6 Motorola S Format Binary Dump Step 7 Interrupt Vector table RAM Area Reserved for IROM Operation 3. DECODER 4. BUS INTERFACE AND MEMORY BANKING Memory Map and Banked Addressing Non-Banked Area (Root) Banked Area Banked Address System Memory Map 16 16 17 17 17 17 17 17 17 17 17,18 18 19 20 20 20 1. INTERNAL CONFIGURATION REGISTERS 2. AMPS TACS MODEM AND SAT CONTROLLER General Description Interrupts Modem Block Descriptions Controller Discriminator Data Decoder Word Sync Detector Modes of Operation Control Channel Voice Channel Data Transmitter Data Transmission Sequence SAT Management SAT Detector SAT Transmitter 31 32 34 34 34 35 36 36 37 37 37 38 38 38 39 49 ACE9050 Page 3. ACE SERIAL INTERFACE BLOCK General Description Transmitter Section Sending Data Receiver Section Receiving Data Programming Programming Constraints Programming Sequences ACEBus Transfers SynthBus Transfers 39 40 40 40 40 41 41 41 41 41 4. IFC COUNTER Detailed Operation Programming Example 41 42 42 5.PULSE WIDTH MODULATOR 42 6. BEEP ALARM RING (BAR) TONE GENERATOR 43 7. KEYPAD INTERFACE AND CHIP IDENTITY Output Port Prograrnming Examples Input Port Identity Code 43 43 43 44 44 8. AUTONOMOUS TIMEOUT (ATO) Block Descriptions ATO Timer ATO Reset RXCD Filter 44 PROGRAMMER’S GUIDE TO CONTROL PORTS AND REGISTERS 46 ACE9050 REGISTERS BY BLOCK 47 50 45 45 45 LIST OF ILLUSTRATIONS Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 10 Fig. 11 Fig. 12 Fig. 13 Fig. 14 Fig. 15 Fig. 16 Fig. 17 Fig. 18 Fig. 19 Fig. 20 Fig. 21 Fig. 22 Fig. 23 Fig. 24 Fig. 25 Pin connections ACE implified block diagram Detailed block diagram ACE9050 6303 Read cycle timing diagram ACE9050 6303 Write cycle timing diagram ACE9050 6303 Emulation Mode Read/Write cycle timing diagram ACEBus Transmit Data flow ACEBus Receive Data flow ACEBus Transmit timing diagram ACEBus Receive timing diagram SynthBus timing diagram Data flow for the internal ROM Data and Address Bus configuration Banked Addressing block diagram Memory Map and Banked Addressing ACE9050 Interrupt configuration External crystal components EXRESN Reset I2C Data transfer AMPS/TACS Modem and SAT controller Modem discriminator Modem Transmitter block diagram Modem Transmission sequence Pulse Width Generator output Keyport configuration Page 1 1 2 7 8 9 10 10 10 10 11 18 19 20 20 22 24 25 26 33 34 38 38 42 43 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. 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