ON NCV7703BD2G Triple half-bridge driver with spi control Datasheet

NCV7703B
Triple Half-Bridge Driver
with SPI Control
The NCV7703B is a fully protected Triple Half−Bridge Driver
designed specifically for automotive and industrial motion control
applications. The three half−bridge drivers have independent control.
This allows for high side, low side, and H−Bridge control. H−Bridge
control provides forward, reverse, brake, and high impedance states.
The drivers are controlled via a standard Serial Peripheral Interface
(SPI). This device is fully compatible with ON Semiconductor’s
NCV7708 Double Hex Driver.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ultra Low Quiescent Current in Sleep Mode, 1 mA for VS and VCC
Power Supply Voltage Operation down to 5 V
3 High−Side and 3 Low−Side Drivers Connected as Half−Bridges
Internal Free−Wheeling Diodes
Configurable as H−Bridge Drivers
0.5 A Continuous (1 A peak) Current
RDS(on) = 0.8 W (typ)
5 MHz SPI Control with Daisy Chain Capability
Compliance with 5 V and 3.3 V Systems
Overvoltage and Undervoltage Lockout
Fault Reporting
1.4 A Overcurrent Threshold Detection with Optional Shutdown
3 A Current Limit with Auto Shutdown
Overtemperature Warning and Protection Levels
Internally Fused Leads in SOIC−14 Package for Better Thermal
Performance
ESD Protection up to 6 kV
These are Pb−Free Devices
MARKING
DIAGRAM
14
SOIC−14
D2 SUFFIX
CASE 751A
14
1
• Automotive
• Industrial
• DC Motor Management
VS
VS
NCV7703BG
AWLYWW
1
NCV7703B = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
GND
OUT3
VS
CSB
SI
SCLK
GND
GND
OUT1
OUT2
VCC
EN
SO
GND
ORDERING INFORMATION
Device
Typical Applications
VS
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Package
Shipping†
NCV7703BD2G
SOIC−14
(Pb−Free)
55 Units / Rail
NCV7703BD2R2G
SOIC−14
(Pb−Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
M
OUT1
OUT2
M
OUT3
Figure 1. Cascaded Application
© Semiconductor Components Industries, LLC, 2010
April, 2010 − Rev. 0
1
Publication Order Number:
NCV7703B/D
NCV7703B
VS
EN
ENABLE
VCC
Reference
& Bias
UVLO
OSC
DRIVE 1
VS
clk
clk
VS
Charge
Pump
Control
Logic
Fault
Detect
High−Side
Driver
Waveshaping
VS
OUT1
Low−Side
Driver
Channel Enable
Waveshaping
SI
SPI
SCLK
Fault
SO
16 Bit
Logic
and
Latch
CSB
VS
Undervoltage
Lockout
VS
Overvoltage
Lockout
Under−Load
Overcurrent
Thermal
Warning/Shutdown
VS
DRIVE 2
clk
Channel Enable
Fault
OUT2
VS
DRIVE 3
clk
Channel Enable
Fault
OUT3
Figure 2. Block Diagram
GND
PACKAGE PIN DESCRIPTION
Pin #
Symbol
1
GND*
Ground. Connect all grounds together.
2
OUT3
Half Bridge Output 3.
3
VS
4
CSB
5
SI
Serial Input
6
SCLK
Serial Clock
7
GND*
Ground. Connect all grounds together.
8
GND*
Ground. Connect all grounds together.
9
SO
Serial Output
10
EN
Enable. Logic high wakes the IC up from a sleep mode.
11
VCC
Power supply input for internal logic.
12
OUT2
Half Bridge Output 2.
13
OUT1
Half Bridge Output 1.
14
GND*
Ground. Connect all grounds together.
Description
Power Supply input for the output drivers and internal supply voltage.
Chip Select Bar. Active low serial port operation.
*Pins 1, 7, 8, and 14 are internally shorted together. It is recommended to also short these pins externally.
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2
NCV7703B
ENABLE
Wake Up
D1*
1N4001
NCV8518
RESET
+
WDI
VBAT
Vout
D2**
Delay
120k
22 mF
GND
VCC
10 mF
VS
OUT1
EN
microprocessor
M
OUT2
CSB
SI
NCV7703B
OUT3
SO
GND
M
SCLK
GND
GND
GND
GND
* D1 optional. For use where reverse battery protection is required.
** D2 optional. For use where load dump exceeds 40V.
Figure 3. Application Circuit
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3
−
NCV7703B
MAXIMUM RATINGS
Rating
Value
Unit
Power Supply Voltage (VS)
(DC)
(AC), t < 500 ms, Ivs > −2 A
−0.3 to 40
−1
V
Output Pin OUTx
(DC)
(AC), t < 500 ms, IOUTx > −2 A
−0.3 to 40
−1
V
Pin Voltage
(Logic Input pins, SI, SCLK, CSB, SO, EN, VCC)
−0.3 to 7
Output Current (OUTx)
(DC)
(AC) (50 ms pulse, 1 s period)
V
A
−1.8 to 1.8
Internally Limited
Electrostatic Discharge, Human Body Model,
VS, OUT1, OUT2, OUT3 (Note 3)
6
kV
Electrostatic Discharge, Human Body Model,
all other pins (Note 3)
2
kV
Electrostatic Discharge, Machine Model,
VS, OUT1, OUT2, OUT3 (Note 3)
300
V
Electrostatic Discharge, Machine Model,
all other pins (Note 3)
200
V
1
kV
Operating Junction Temperature
−40 to 150
°C
Storage Temperature Range
−55 to 150
°C
MSL3
−
Electrostatic Discharge, Charge Device Model (Note 3)
Moisture Sensitivity Level (MAX 260°C Processing)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Test Conditions (Typical Value)
Thermal Parameters
14 Pin Fused SOIC Package
Unit
min−pad board
(Note 1)
1″ pad board
(Note 2)
Junction−to−Lead (psi−JL8, YJL8) or Pins 1, 7, 8, 14
23
22
°C/W
Junction−to−Ambient (RqJA, qJA)
122
83
°C/W
mm2
1. 1−oz copper, 67
copper area, 0.062″ thick FR4.
2. 1−oz copper, 645 mm2 copper area, 0.062″ thick FR4.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A115)
ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model
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4
NCV7703B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ TJ ≤ 150°C, 5.5 V ≤ VS ≤ 40 V, 3 V ≤ VCC ≤ 5.25 V, EN = VCC, unless otherwise specified)
Conditions
Min
Typ
Max
Unit
VS = 13.2 V, OUTx = 0 V
EN = SI = SCLK = 0 V, CSB = VCC
0 V < VCC < 5.25 V
(TJ = −40°C to 85°C)
−
1.0
5.0
mA
VS = 13.2 V, OUTx = 0 V
EN = SI = SCLK = 0 V, CSB = VCC
0 V < VCC < 5.25 V, TJ = 25°C
−
−
2.0
Supply Current (VS)
Active Mode
EN = VCC, 5.5 V < VS < 35 V
No Load
−
2.0
4.0
mA
Supply Current (VCC)
Sleep Mode (Note 6)
VCC = CSB, EN = SI = SCLK = 0 V
(TJ = −40°C to 85°C)
−
0
2.5
mA
Supply Current (VCC)
Active Mode
EN = VCC
−
1.5
3.0
mA
Characteristic
GENERAL
Supply Current (VS)
Sleep Mode (Note 5)
VCC Power−On−Reset Threshold
2.60
2.80
3.00
V
VS Undervoltage Detection
Threshold VS decreasing
Hysteresis
4.3
100
4.7
−
5.1
400
V
mV
VS Overvoltage Detection
Threshold VS increasing
Hysteresis
34.0
1.5
37.5
3.5
40.0
5.5
V
Thermal Warning (Note 4)
Threshold
Hysteresis
120
−
145
30
170
−
°C
Thermal Shutdown (Note 4)
Threshold
Hysteresis
155
−
175
30
195
−
°C
1.05
1.20
−
°C/°C
VS = 13.2 V, TJ = 25°C
−
0.8
0.95
W
VS = 13.2 V
−
−
1.5
W
8 V ≤ VS ≤ 40 V
−
−
1.7
W
5.5 V ≤ VS ≤ 8 V, TJ = 25°C
−
1.3
−
W
5.5 V ≤ VS ≤ 8 V
−
−
2.0
W
VS = 13.2 V, TJ = 25°C
−
0.8
0.95
W
VS = 13.2 V
−
−
1.5
W
8 V ≤ VS ≤ 40 V
−
−
1.7
W
5.5 V ≤ VS ≤ 8 V, TJ = 25°C
−
1.3
−
W
5.5 V ≤ VS ≤ 8 V
−
−
2.0
W
OUTx = 0 V, VS = 40 V, EN = 0 V
CSB = VCC
0 V < VCC < 5.25 V
Sum(I(OUTx)
−5.0
−
−
mA
OUTx = 0 V, VS = 40 V, EN = 0 V
CSB = VCC
0 V < VCC < 5.25 V, TJ = 25°C
Sum(I(OUTx)
−1.0
−
−
Ratio of Thermal Shutdown to Thermal
Warning temperature (Note 4)
OUTPUTS
Output RDS(on) (Source)
Output RDS(on) (Sink)
Source Leakage Current
Sum of I(OUTx) x = 1, 2, 3
Iout = −500 mA
Iout = 500 mA
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NCV7703B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ TJ ≤ 150°C, 5.5 V ≤ VS ≤ 40 V, 3 V ≤ VCC ≤ 5.25 V, EN = VCC, unless otherwise specified)
Characteristic
Conditions
Min
Typ
Max
Unit
OUTx = VS = 40 V, EN = 0 V
CSB = VCC
0 V < VCC < 5.25 V
−
−
300
mA
OUTx = VS = 13.2 V, EN = 0 V
CSB = VCC
0 V < VCC < 5.25 V, TJ = 25°C
−
−
10
OUTPUTS
Sink Leakage Current
Over Current Shutdown Threshold
Source
Sink
−1.8
1.0
−1.4
1.4
−1.0
1.8
A
Current Limit
Source
Sink
−5.0
2.0
−3.0
3.0
−2.0
5.0
A
Under Load Detection Threshold
Source
Sink
−15
3.0
−7.0
7.0
−2.0
15
mA
−
0.9
1.3
V
Power Transistor Body Diode Forward Voltage If = 500 mA
4. Thermal characteristics are not subject to production test
5. For temperatures above 85°C, refer to Figure 4.
6. For temperatures above 85°C, refer to Figure 5.
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NCV7703B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ TJ ≤ 150°C, 5.5 V ≤ VS ≤ 40 V, 3 V ≤ VCC ≤ 5.25 V, EN = VCC, unless otherwise specified)
Conditions
Min
Typ
Max
Input Threshold
High
Low
−
30
−
−
70
−
Input Hysteresis
100
350
600
mV
Characteristic
Unit
LOGIC INPUTS (EN, SI, SCLK, CSB)
%VCC
Input Pulldown Current (EN, SI, SCLK)
EN = SI = SCLK = VCC
5.0
25
50
mA
Input Pullup Current (CSB)
CSB = 0 V
−50
−25
−5
mA
−
10
15
pF
VCC – 1.0
VCC – 0.7
−
V
−
0.2
0.4
V
−10
−
10
mA
−
10
15
pF
10
10
25
25
50
50
−
200
−
ms
200
350
600
ms
Input Capacitance (Note 7)
LOGIC OUTPUT (SO)
Output High
Iout = 1 mA
Output Low
Iout = −1.6 mA
Tri−state Leakage
CSB = VCC, 0 V v SO v VCC
Tri−state Input Capacitance (Note 7)
CSB = VCC
TIMING SPECIFICATIONS
Overcurrent Shutdown Delay Time
Source
Sink
Current Limit Fault Delay
ms
VS > 8 V
Under Load Detection Delay Time
High Side Turn On Time
VS = 13.2 V, Rload = 25 W
−
7.5
15
ms
High Side Turn Off Time
VS = 13.2 V, Rload = 25 W
−
3.0
6.0
ms
Low Side Turn On Time
VS = 13.2 V, Rload = 25 W
−
6.5
15
ms
Low Side Turn Off Time
VS = 13.2 V, Rload = 25 W
−
3.0
6.0
ms
High Side Rise Time
VS = 13.2 V, Rload = 25 W
−
5.0
10
ms
High Side Fall Time
VS = 13.2 V, Rload = 25 W
−
2.0
5.0
ms
Low Side Rise Time
VS = 13.2 V, Rload = 25 W
−
1.0
3.0
ms
Low Side Fall Time
VS = 13.2 V, Rload = 25 W
−
1.0
3.0
ms
NonOverlap Time
High Side Turn Off to Low Side Turn On
1.0
−
−
ms
NonOverlap Time
Low Side Turn Off to High Side Turn On
1.0
−
−
ms
7. Not production tested.
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NCV7703B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ TJ ≤ 150°C, 5.5 V ≤ VS ≤ 40 V, 3 V ≤ VCC ≤ 5.25 V, EN = VCC, unless otherwise specified)
SERIAL PERIPHERAL INTERFACE
Conditions
Timing Chart #
(See Figure 6)
Min
Typ
Max
Unit
VCC = 5 V
−
−
−
5
MHz
VCC = 5 V
VCC = 3.3 V
−
−
200
500
−
−
−
−
ns
SI, SCLK
−
−
−
15
pF
SCLK High Time
1
85
−
−
ns
SCLK Low Time
2
85
−
−
ns
SCLK Setup Time
3
4
85
85
−
−
−
−
ns
SI Setup Time
11
50
−
−
ns
SI Hold Time
12
50
−
−
ns
CSB Setup Time
5
6
100
100
−
−
−
−
ns
CSB High Time (Note 9)
7
200
−
−
ns
SO enable after CSB falling edge (Note 8)
8
−
−
50
ns
SO disable after CSB rising edge (Note 8)
9
−
−
50
ns
Characteristic
SCLK Frequency
SCLK Clock Period
Maximum Input Capacitance (Note 8)
SO Rise Time
VCC = 5 V, Cload = 40 pF
−
−
10
25
ns
SO Fall Time
VCC = 5 V, Cload = 40 pF
−
−
10
25
ns
SCLK ↑ to SO 50%
10
−
20
50
ns
SO Valid Time (Note 8)
8. Not tested in production.
9. Minimum high time of CSB between two successive SPI commands.
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NCV7703B
4.0
6.0
VS = 13.2 V
VCC = 0 V
3.5
VCC SLEEP CURRENT (mA)
VS SLEEP CURRENT (mA)
7.0
5.0
4.0
3.0
2.0
1.0
0
−40 −20
VCC = 5.25 V
0
20
40
60
80
VCC = 5.25 V
3.0
2.5
2.0
1.5
1.0
0.5
0
−40 −20
100 120 140 160
TJ, TEMPERATURE (°C)
0
20
40
100 120 140 160
Figure 5. VCC Sleep Supply Current vs. Temperature
Detailed SPI Timing
4
CSB
6
5
SCLK
1
80
TJ, TEMPERATURE (°C)
Figure 4. VS Sleep Supply Current vs. Temperature
3
60
2
CSB
SO
8
9
SI
12
SCLK
11
10
SO
Figure 6. SPI Timing Waveforms
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7
NCV7703B
TYPICAL CHARACTERISTICS
140
120
1 oz Cu
qJA (°C/W)
100
80
2 oz Cu
60
40
20
0
0
100
200
300
400
500
600
COPPER HEAT SPREADING AREA
700
800
(mm2)
Figure 7. qJA vs. Copper Spreader Area,
14 Lead SON (fused leads)
1000
Cu Area = 100 mm2 1.0 oz
R(t) (°C/W)
100
200 mm2 1.0 oz
10
300 mm2 1.0 oz
400 mm2 1.0 oz
500 mm2 1.0 oz
1
0.1
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
TIME (sec)
Figure 8. Transient Thermal Response to a
Single Pulse 1 oz Copper (Log−Log)
140
Cu Area = 100 mm2 1.0 oz
R(t) (°C/W)
120
200 mm2 1.0 oz
100
300 mm2 1.0 oz
80
400 mm2 1.0 oz
500 mm2 1.0 oz
60
40
20
0
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
TIME (sec)
Figure 9. Transient Thermal Response to a
Single Pulse 1 oz Copper (Semi−Log)
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10
10
100
1000
NCV7703B
SPI Communication
Frame Detection
Standard 16−bit communication has been implemented to
this IC to turn drivers on/off, and to report faults. (See
Figure 11). The LSB (Least Significant Bit) is clocked in
first.
Input word integrity (SI) is evaluated by the use of a frame
consistency check. The word frame length is compared to an
h x 16 bit acceptable word length before the data is latched
into the input register. This guarantees the proper word
length has been imported and allows for daisy chain
operation applications.
The frame length detector is enabled with the CSB falling
edge and the SCLK rising edge.
SCLK must be low during the CSB rising edge. The fault
register is cleared with a valid frame detection. Existing
faults are re−latched after the fault filter time.
Communication is Implemented as Follows:
1. CSB goes low to allow serial data transfer.
2. A 16 bit word is clocked (SCLK) into the SI
(Serial Input) pin.
3. CSB goes high to transfer the clocked in
information to the data registers.
NOTE: SO is tristate when CSB is high.
Frame detection starts
after the CSB falling edge
and the SCLK rising edge.
Frame detection mode ends with
CSB rising edge.
CSB
SCLK
SI
SRR
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
Internal Counter 1
2
3
4
5
6
X
X
7
8
9
X
X
X
X
10
11
12
13
OCD
14
X
OVLO
15
16
Valid 16 bits shown
Figure 10. Frame Detection
CSB
SI
SRR
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
X
X
X
X
X
X
OCD
X
OVLO
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
X
X
X
X
X
X
OLD
ULD
PSF
SCLK
SO
TW
Figure 11. SPI Communication Frame Format
clocked into the SI pin of the device. Daisy chain
communication between SPI compatible IC’s is possible by
connection of the Serial Output pin (SO) to the input of the
sequential IC (SI) (Reference the Daisy Chain Section).
Table 1 defines the programming bits and diagnostic bits.
Figure 11 displays the timing diagram associated with
Table 1. Fault information is sequentially clocked out the
SO pin of the NCV7703B as programming information is
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NCV7703B
Table 1. SPI BIT DESCRIPTION
Input Data
Output Data
Bit Number
Bit Description
Bit Status
Bit Number
Bit Description
Bit Status
15
Over Voltage Lock Out
Control (OVLO)
0 = Disable
15
Power Supply Fail Signal
(PSF for OVLO or UVLO)
0 = No Fault
Under Load Detect Signal (ULD)
0 = No Fault
14
1 = Enable
Not Used
14
1 = Fault
1 = Fault
13
Over Current Detection Shut
Down Control (OCD)
13
0 = Disable
Over Load Detect Signal (OLD)
1 = Enable
1 = Fault
12
Not Used
12
Not Used
11
Not Used
11
Not Used
10
Not Used
10
Not Used
9
Not Used
9
Not Used
8
Not Used
8
Not Used
7
Not Used
7
Not Used
6
OUTH3
6
OUTH3
0 = Off
1 = On
5
OUTL3
5
0 = Off
OUTH2
OUTL3
4
0 = Off
OUTL2
OUTH2
3
0 = Off
OUTH1
OUTL2
2
OUTH1
1 = On
OUTL1
0 = Off
0
Status Register Reset (SRR)
0 = No Reset
0 = Off
1 = On
0 = Off
1
0 = Off
1 = On
1 = On
2
0 = Off
1 = On
1 = On
3
0 = Off
1 = On
1 = On
4
0 = No Fault
0 = Off
1 = On
1
OUTL1
0 = Off
0
Thermal Warning (TW)
0 = Not in TW
1 = On
1 = On
1 = Reset
1 = In TW
DETAILED OPERATING DESCRIPTION
General
Power Up/Down Control
The NCV7703B Triple Half Bridge Driver provides drive
capability for 3 Half−Bridge configurations. Each output
drive is characterized for a 500 mA load and has a typical
1.4 A surge capability. Strict adherence to integrated circuit
die temperature is necessary, with a maximum die
temperature of 150°C. This may limit the number of drivers
enabled at one time. Output drive control and fault reporting
are handled via the SPI (Serial Peripheral Interface) port.
An Enable function (EN) provides a low quiescent sleep
current mode when the device is not being utilized. A pull
down is provided on the EN, SI and SCLK inputs to ensure
they default to a low state in the event of a severed input
signal. A pull−up is provided on the CSB input disabling SPI
communication in the event of an open CSB input.
A feature incorporated in the IC is an under voltage
lockout circuit that prevents the output drivers from turning
on unintentionally. VCC and VS are monitored for
undervoltage conditions supporting a smooth turn−on
transition. All drivers are initialized in the off (high
impedance) condition, and will remain off during a VCC or
VS undervoltage condition. This allows power up
sequencing of VCC, and VS up to the user. Once VCC is out
of UVLO, SPI communication can begin regardless of the
voltage on VS. However, drivers will remain off if VS is in
an undervoltage condition. Hysteresis in the UVLO circuits
results in glitch free operation during power up/down.
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NCV7703B
H−Bridge Driver Configuration
The NCV7703B has the flexibility of controlling each half
bridge driver independently. This allows for high side, low
side and H−bridge control. H−bridge control provides
forward, reverse, brake and high impedance states.
been exceeded for a duration greater than 200 ms, regardless
of the OLD input bit status. The OUTx output bit will report
a “0” indicating which driver encountered the hard short.
The OLD status bit will be set and will remain set until a new
SRR input SPI command is executed.
Overvoltage Clamping − Driving Inductive Loads
Under−Load Detection (Table 3)
Each output is internally clamped to ground and Vs by
internal free wheeling diodes. The diodes have ratings that
complement the FETs they protect.
The under−load detection circuit monitors the current
from each output driver. A minimum load current (this is the
maximum open circuit detection threshold) is required when
the drivers are turned on. If the under−load detection
threshold has been detected for more than the under−load
delay time, the ULD bit (output bit #14) will be set to a “1”.
The under load bit is reset with SRR.
Overcurrent Shutdown Threshold Detection (Table 2)
The state of input bit 13 (OCD) selects driver reaction
when reaching overcurrent shutdown threshold. With a “0”
for input bit 13, the OLD status bit will be set to “1” when
the level exceeds the overcurrent shutdown shut−down
threshold and the driver will remain on. With a “1” for input
bit 13, the output driver shuts off when the overcurrent
shutdown threshold is exceeded and can only be turned back
on via the SPI port with a SPI command that includes an SRR
= 1. Note: high currents could cause a high rise in die
temperature. Devices will not be allowed to turn on if the die
temperature exceeds the thermal shutdown temperature.
Overvoltage Shutdown (Table 4)
Overvoltage lockout circuitry monitors the voltage on the
VS pin. The response to an overvoltage condition is selected
by SPI input bit 15. PSF output bit 15 is set when a VS
overvoltage condition exists. If input bit 15 (OVLO) is set
to “1”, all outputs will turn off during this overvoltage
condition. Turn On/Off status is maintained in the logic
circuitry, so that when proper input voltage level is
reestablished, the programmed outputs will turn back on.
The PSF output bit is reset with SRR.
Current Limit Fault
The current limit fault circuit will shut down the offending
output driver when the Current Limit (Source or Sink) has
Table 2. INPUT BIT 13, OVERCURRENT DETECTION SHUT DOWN CONTROL AND RESPONSE
OLD Input
Bit 13 Set
Typical Load Current
Condition
Output Bit 13 OLD Status
OUTx Status
0
IL ≤ 1.4 A
0
Unchanged
0
1.4 A < IL ≤ 3 A
1 (Need SRR to reset)
Unchanged
0
IL ≥ 3 A, for 200 ms (typ)
1 (Need SRR to reset)
OUTx Latched Off (Need SRR to reset)
1
IL ≤ 1.4 A
0
Unchanged
1
IL > 1.4 A, for 25 ms (typ)
1 (Need SRR to reset)
OUTx Latched Off (Need SRR to reset)
Table 3. INPUT BIT 14, UNDER LOAD DETECTION SHUT DOWN
OUTx ULD Set
Output Data Bit 14, Under Load Detect (ULD) Status
OUTx Status
0
0
Unchanged
1
1 (Need SRR to reset)
Unchanged
Table 4. INPUT BIT 15, OVERVOLTAGE LOCK OUT (OVLO) SHUT DOWN
OVLO Input
Bit 15
VS OVLO
Condition
Output Data Bit 15 Power
Supply Fail (PSF) Status
OUTx Status
0
0
0
Unchanged
0
1
1 (Need SRR to reset)
Unchanged
1
0
0
Unchanged
1
1
1 (Need SRR to reset)
All Outputs Shut Off (Remain off until VS is out of OVLO)
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13
NCV7703B
Thermal Shutdown
software polling of this bit will allow for load control and
possible prevention of thermal shutdown conditions.
Thermal warning information can be retrieved
immediately without performing a complete SPI access
cycle. Figure 12 below displays how this is accomplished.
Bringing the CSB pin from a high to low condition
immediately displays the information on the Output Data Bit
0, thermal warning, even in the absence of an SCLK signal.
As the temperature of the NCV7703B changes from a
condition from below the thermal warning threshold to
above the thermal warning threshold, the state of the SO pin
changes and this level is available immediately when the
CSB goes low. A low on SO indicates there is no thermal
warning, while a high indicates the IC is above the thermal
warning threshold. This warning bit is reset by setting SRR
to “1”.
Three independent thermal shutdown circuits are featured
(one common sensor for each HS and LS transistor pair).
Each sensor has two temperature levels; Level 1, Thermal
Warning sets the “TW” status bit to a 1 and would have to
be reset with a command that includes the SRR after the IC
cools to a temperature below Level 1. The output will remain
on in this condition.
If the IC temperature reaches Level 2, Over Temperature
Shutdown, all drivers are latched off. It can be reset only
after the part cools below the shutdown temperature,
(including thermal hysteresis) with a turn−on command that
includes the SRR set bit.
The output data bit 0, Thermal Warning, will latch and
remain set, even after cooling, and is reset by sending a SPI
command to reset the status register (SRR, input 0 set to
“1”). Since thermal warning precedes a thermal shutdown,
CSB
CSB
SCLK*
SCLK*
SO
SO
TWH
Tristate Level
NTW
Tristate Level
Thermal Warning High
No Thermal Warning
*SCLK can be high or low in order to maintain the thermal information on SO. Toggling SCLK will cause other output bits to shift out.
TWH = Thermal Warning High
NTW = No Thermal Warning
Figure 12. Access to Temperature Warning Information
Applications Drawing
Daisy Chain
will be the Diagnostic Output Data. These are the bits
representing the status of the IC and are detailed in the SPI
Bit Description Table. Additional programming bits should
be clocked in which follow the Diagnostic Output bits. Word
length must be h x 16 due to the use of frame detection.
The NCV7703B is capable of being setup in a daisy chain
configuration with other similar devices which include
additional NCV7703B devices as well as the NCV7708
Double Hex Driver. Particular attention should be focused
on the fact that the first 16 bits which are clocked out of the
SO pin when the CSB pin transitions from a high to a low
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14
m icroprocessor
NCV7703B
CSB
SCLK
CSB
SCLK
CSB
SCLK
CSB
SCLK
NCV7703B
NCV7703B
NCV7708B
NCV7708B
SI
SI
SI
SI
SO
SO
SO
SO
Figure 13. Daisy Chain Operation
Parallel Control
A more efficient way to control multiple SPI compatible
devices is to connect them in a parallel fashion and allow
each device to be controlled in a multiplex mode. The
diagram below shows a typical connection between the
microprocessor or microcontroller and multiple SPI
compatible devices. In a daisy chain configuration, the
programming information for the last device in the serial
string must first pass through all the previous devices. The
parallel control setup eliminates that requirement, but at the
cost of additional control pins from the microprocessor for
each individual CSB pin for each controllable device. Serial
data is only recognized by the device that is activated
through its respective CSB pin.
VS
OUTx
NCV7703B
SI
SCLK
microprocessor
SO
CSB
chip1
CSB
chip2
CSB
chip3
SI
SCLK
CSB OUT1
SO
OUT2
OUT3
OUTx
NCV7703B
SI
SCLK
CSB OUT1
SO
OUT2
OUT3
GND
NCV7703B
Figure 14. Parallel Control
SI
SCLK
CSB OUT1
SO
OUT2
OUT3
Figure 15. High−Side / Low−Side Application Drawing
Any combination of H−bridge and high or low−side
drivers can be designed in. This allows for flexibility in
many systems.
Additional Application Setup
In addition to the cascaded H−Bridge application shown
in Figure 1, the NCV7703B can also be used as a high−side
driver or low−side driver (Figure 15).
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15
NCV7703B
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
0.25 (0.010)
M
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
D 14 PL
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCV7703B/D