TI1 MSP430G2955 Mixed signal microcontroller Datasheet

MSP430G2955
MSP430G2855
MSP430G2755
www.ti.com
SLAS800 – MARCH 2013
MIXED SIGNAL MICROCONTROLLER
Check for Samples: MSP430G2955, MSP430G2855, MSP430G2755
FEATURES
1
•
•
•
•
•
•
•
•
•
Low Supply-Voltage Range: 1.8 V to 3.6 V
Ultra-Low Power Consumption
– Active Mode: 250 µA at 1 MHz, 2.2 V
– Standby Mode: 0.7 µA
– Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequency
– Internal Very-Low-Power Low-Frequency
(LF) Oscillator
– 32-kHz Crystal
– High-Frequency (HF) Crystal up to 16 MHz
– External Digital Clock Source
– External Resistor
Two 16-Bit Timer_A With Three
Capture/Compare Registers
One 16-Bit Timer_B With Three
Capture/Compare Registers
Up to 32 Touch-Sense-Enabled I/O Pins
•
•
•
•
•
•
•
•
•
•
Universal Serial Communication Interface
(USCI)
– Enhanced UART Supporting Auto Baudrate
Detection (LIN)
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C™
On-Chip Comparator for Analog Signal
Compare Function or Slope Analog-to-Digital
(A/D) Conversion
10-Bit 200-ksps Analog-to-Digital (A/D)
Converter With Internal Reference, Sampleand-Hold, and Autoscan
Brownout Detector
Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security
Fuse
Bootstrap Loader
On-Chip Emulation Logic
Family Members are Summarized in Table 1
Package Options
– TSSOP: 38 Pin (DA)
– QFN: 40 Pin (RHA)
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430G2x55 series are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers, up to 32
I/O touch-sense-enabled pins, a versatile analog comparator, and built-in communication capability using the
universal serial communication interface. For configuration details, see Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
MSP430G2955
MSP430G2855
MSP430G2755
SLAS800 – MARCH 2013
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Table 1. Available Options (1) (2)
Device
BSL
EEM
Flash
(KB)
RAM
(B)
Timer_A
Timer_B
COMP_A+
Channels
ADC10
Channels
USCI_A0
USCI_B0
Clock
I/O
Package
Type
56
4096
8
12
1
HF, LF,
DCO,
VLO
38-TSSOP
1
2x TA3
1x TB3
32
1
32
40-QFN
32
38-TSSOP
1
HF, LF,
DCO,
VLO
32
40-QFN
32
38-TSSOP
1
HF, LF,
DCO,
VLO
32
40-QFN
MSP430G2955IDA38
MSP430G2955IRHA40
MSP430G2855IDA38
MSP430G2855IRHA40
1
1
48
4096
MSP430G2755IDA38
MSP430G2755IRHA40
(1)
(2)
1
1
32
4096
2x TA3
1x TB3
2x TA3
1x TB3
8
12
8
12
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Device Pinout, 38-Pin TSSOP (DA Package)
2
TEST/SBWTCK
1
38
P1.7/TA0.2/TDO/TDI
P1.6/TA0.1/TDI
DVCC
2
37
P2.5/TA1.0/ROSC
3
36
P1.5/TA0.0/TMS
DVSS
4
35
P1.4/SMCLK/TCK
XOUT/P2.7
5
34
P1.3/TA0.2
XIN/P2.6
6
33
P1.2/TA0.1
RST/NMI/SBWTDIO
7
32
P1.1/TA0.0
P2.0/TA1CLK/ACLK/A0
8
31
P1.0/TA0CLK/ADC10CLK
P2.1/TA0INCLK/SMCLK/A1
9
30
P2.4/TA0.2/A4/VREF+/VEREF+
P2.2/TA0.0/A2
10
29
P2.3/TA0.1/A3/VREF−/VEREF−
P3.0/UCB0STE/UCA0CLK/A5
11
28
P3.7/TA1.2/A7
P3.1/UCB0SIMO/UCB0SDA
12
27
P3.6/TA1.1/A6
P3.2/UCB0SOMI/UCB0SCL
13
26
P3.5/UCA0RXD/UCA0SOMI
P3.3/UCB0CLK/UCA0STE
14
25
P3.4/UCA0TXD/UCA0SIMO
AVSS
15
24
P4.7/TB0CLK/CA7
AVCC
16
23
P4.6/TB0OUTH/A15/CA6
P4.0/TB0.0/CA0
17
22
P4.5/TB0.2/A14/CA5
P4.1/TB0.1/CA1
18
21
P4.4/TB0.1/A13/CA4
P4.2/TB0.2/CA2
19
20
P4.3/TB0.0/A12/CA3
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P1.2/TA0.1
P1.3/TA0.2
P1.5/TA0.0/TMS
P1.4/SMCLK/TCK
P1.6/TA0.1/TDI/TCLK
P1.7/TA0.2/TDO/TDI
TEST/SBWTCK
DVCC
DVCC
P2.5/TA1.0/ROSC
Device Pinout, 40-Pin QFN (RHA Package)
39 38 37 36 35 34 33 32
DVSS
1
30
P1.1/TA0.0
XOUT/P2.7
2
29
P1.0/TA0CLK/ADC10CLK
XIN/P2.6
3
28
P2.4/TA0.2/A4/VREF+/VEREF+
DVSS
4
27
P2.3/TA0.1/A3/VREF−/VEREF−
RST/NMI/SBWTDIO
5
26
P3.7/TA1.2/A7
P2.0/TA1CLK/ACLK/A0
6
25
P3.6/TA1.1/A6
P2.1/TA0INCLK/SMCLK/A1
7
24
P3.5/UCA0RXD/UCA0SOMI
P2.2/TA0.0/A2
8
23
P3.4/UCA0TXD/UCA0SIMO
P3.0/UCB0STE/UCA0CLK/A5
9
22
P4.7/TB0CLK/CA7
10
21
P4.6/TB0OUTH/A15/CA6
P3.1/UCB0SIMO/UCB0SDA
P4.5/TB0.2/A14/CA5
P4.4/TB0.1/A13/CA4
P4.3/TB0.0/A12/CA3
P4.1/TB0.1/CA1
P4.2/TB0.2/CA2
P4.0/TB0.0/CA0
AVCC
AVSS
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
12 13 14 15 16 17 18 19
Functional Block Diagram
VCC
XIN
VSS
P1.x, P2.x
2x8
P3.x, P4.x
2x8
Ports P1, P2
Ports P3, P4
2x8 I/O,
Interrupt
capability,
Pullup or
pulldown
resistors
2x8 I/O,
Pullup or
pulldown
resistors
Timer0_B3
USCI_A0:
UART, LIN,
IrDA,SPI
XOUT
ACLK
Basic Clock
System+
SMCLK
MCLK
16MHz
CPU
incl. 16
Registers
ADC
10-Bit
Flash
RAM
COMP_A+
56 kB
48 kB
32 kB
4 kB
12
Channels,
Autoscan,
DTC
8
Channels
Watchdog
WDT+
Timer1_A3
Timer0_A3
MAB
MDB
Emulation
(2BP)
JTAG
Interface
Brownout
Protection
15 or 16 Bit
Spy-Bi-Wire
3 CC
Registers
3 CC
Registers
3 CC
Registers,
Shadow
Register
USCI_B0:
SPI,I2C
RST/NMI
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Table 2. Terminal Functions
TERMINAL
NAME
NO.
I/O
DA
RHA
31
29
P1.0/
DESCRIPTION
General-purpose digital I/O pin
TACLK/
I/O
ADC10CLK
P1.1/
TA0.0
P1.2/
TA0.1
P1.3/
TA0.2
Timer_A, clock signal TACLK input
ADC10, conversion clock
32
30
I/O
33
31
I/O
34
32
I/O
35
33
I/O
P1.4/
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: OUT0 output or BSL transmit
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
SMCLK/
SMCLK signal output
TCK
JTAG test clock, input terminal for device programming and test
P1.5/
General-purpose digital I/O pin
TA0.0/
36
34
I/O
Timer_A, compare: OUT0 output
TMS
JTAG test mode select, input terminal for device programming and test
P1.6/
General-purpose digital I/O pin /
TA0.1/
37
TDI/
35
I/O
Timer_A, compare: OUT1 output
JTAG test data input terminal during programming and test
TCLK
JTAG test clock input terminal during programming and test
P1.7/
General-purpose digital I/O pin
TA0.2/
38
TDO/
36
I/O
Timer_A, compare: OUT2 output
JTAG test data output terminal during programming and test
TDI (1)
JTAG test data input terminal during programming and test
P2.0/
General-purpose digital I/O pin
TA1CLK/
ACLK/
8
6
I/O
Timer1_A3.TACLK
ACLK output
A0
ADC10, analog input A0
P2.1/
General-purpose digital I/O pin
TAINCLK/
SMCLK/
9
7
I/O
A1
Timer_A, clock signal at INCLK
SMCLK signal output
ADC10, analog input A1
P2.2/
General-purpose digital I/O pin
TA0.0/
10
8
I/O
Timer_A, capture: CCI0B input or BSL receive, compare: OUT0 output
A2
ADC10, analog input A2
P2.3/
General-purpose digital I/O pin
TA0.1/
Timer_A, capture CCI1B input, compare: OUT1 output
A3/
29
27
I/O
ADC10, analog input A3
VREF-/
Negative reference voltage output
VEREF-
Negative reference voltage input
P2.4/
General-purpose digital I/O pin
TA0.2/
Timer_A, compare: OUT2 output
A4/
30
28
I/O
ADC10, analog input A4
VREF+/
Positive reference voltage output
VEREF+
Positive reference voltage input
(1)
4
TDO or TDI is selected via JTAG instruction.
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Table 2. Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
DA
RHA
3
40
P2.5/
TA1.0/
General-purpose digital I/O pin
I/O
ROSC
XIN/
P2.6
XOUT/
P2.7
UCA0CLK/
Timer_A, capture: CCI0B input or BSL receive, compare: OUT0 output
Input for external DCO resistor to define DCO frequency
6
3
I/O
5
2
I/O
P3.0/
UCB0STE/
DESCRIPTION
Input terminal of crystal oscillator
General-purpose digital I/O pin
Output terminal of crystal oscillator
General-purpose digital I/O pin (2)
General-purpose digital I/O pin
11
9
I/O
USCI_B0 slave transmit enable
USCI_A0 clock input/output
A5
ADC10, analog input A5
P3.1/
General-purpose digital I/O pin
UCB0SIMO/
12
10
I/O
USCI_B0 slave in, master out in SPI mode
UCB0SDA
USCI_B0 SDA I2C data in I2C mode
P3.2/
General-purpose digital I/O pin
UCB0SOMI/
13
11
I/O
UCB0SCL
USCI_B0 SCL I2C clock in I2C mode
P3.3/
UCB0CLK/
General-purpose digital I/O pin
14
12
I/O
UCA0STE
General-purpose digital I/O pin
25
23
I/O
UCA0SIMO
General-purpose digital I/O pin
26
24
I/O
UCA0SOMI
USCI_A0 receive data input in UART mode
USCI_A0 slave out, master in SPI mode
P3.6/
TA1.1/
USCI_A0 transmit data output in UART mode
USCI_A0 slave in, master out in SPI mode
P3.5/
UCA0RXD/
USCI_B0 clock input/output
USCI_A0 slave transmit enable
P3.4/
UCA0TXD/
USCI_B0 slave out, master in SPI mode
General-purpose digital I/O pin
27
25
I/O
A6
Timer_A, capture: CCI1B input or BSL receive, compare: OUT2 output
ADC10 analog input A6
P3.7/
TA1.2/
General-purpose digital I/O pin
28
26
I/O
A7
Timer_A, capture: CCI2B input or BSL receive, compare: OUT2 output
ADC10 analog input A7
P4.0/
TB0.0/
General-purpose digital I/O pin
17
15
I/O
CA0
Comparator_A+, CA0 input
P4.1/
TB0.1/
Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
18
16
I/O
Timer_B, capture: CCI1A input, compare: OUT1 output
CA1
Comparator_A+, CA1 input
P4.2/
General-purpose digital I/O pin
TB0.2/
19
CA2
(2)
17
I/O
Timer_B, capture: CCI2A input, compare: OUT2 output
Comparator_A+, CA2 input
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
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Table 2. Terminal Functions (continued)
TERMINAL
NAME
NO.
DA
I/O
DESCRIPTION
RHA
P4.3/
General-purpose digital I/O pin
TB0.0/
20
A12/
18
I/O
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12
CA3
Comparator_A+, CA3 input
P4.4/
General-purpose digital I/O pin
TB0.1/
21
A13/
19
I/O
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13
CA4
Comparator_A+, CA4 input
P4.5/
General-purpose digital I/O pin
TB0.2/
22
A14/
20
I/O
Timer_B, compare: OUT2 output
ADC10 analog input A14
CA5
Comparator_A+, CA5 input
P4.6/
General-purpose digital I/O pin
TBOUTH/
CAOUT/
Timer_B, switch all TB0 to TB3 outputs to high impedance
23
21
I/O
Comparator_A+ Output
A15/
ADC10 analog input A15
CA6
Comparator_A+, CA6 input
P4.7/
General-purpose digital I/O pinCB0
TBCLK/
CAOUT/
24
22
I/O
CA7
Timer_B, clock signal TBCLK input
Comparator_A+ Output
Comparator_A+, CA7 input
RST/
Reset or nonmaskable interrupt input
7
5
I
1
37
I
DVCC
2
38, 39
Digital supply voltage
AVCC
16
14
Analog supply voltage
DVSS
4
1, 4
Digital ground reference
NMI/SBWTDIO
TEST/
SBWTCK
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
AVSS
15
13
QFN Pad
NA
Pad
6
Spy-Bi-Wire test data input/output during programming and test
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Analog ground reference
NA
QFN package pad; connection to DVSS recommended.
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SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-toregister operation execution time is one cycle of the
CPU clock.
Constant Generator
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 3. Instruction Word Formats
EXAMPLE
OPERATION
Dual operands, source-destination
INSTRUCTION FORMAT
ADD R4,R5
R4 + R5 ---> R5
Single operands, destination only
CALL R8
PC -->(TOS), R8--> PC
JNE
Jump-on-equal bit = 0
Relative jump, un/conditional
Table 4. Address Mode Descriptions (1)
(1)
ADDRESS MODE
S
D
SYNTAX
EXAMPLE
OPERATION
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 -- --> R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) -- --> M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) -- --> M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) -- --> M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) -- --> M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) -- --> R11
R10 + 2-- --> R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 -- --> M(TONI)
S = source, D = destination
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Operating Modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active.
• Low-power mode 0 (LPM0)
– CPU is disabled.
– ACLK and SMCLK remain active.
– MCLK is disabled.
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active.
– MCLK is disabled.
– DCO's dc generator is disabled if DCO not used in active mode.
• Low-power mode 2 (LPM2)
– CPU is disabled.
– ACLK remains active.
– MCLK and SMCLK are disabled.
– DCO's dc generator remains enabled.
• Low-power mode 3 (LPM3)
– CPU is disabled.
– ACLK remains active.
– MCLK and SMCLK are disabled.
– DCO's dc generator is disabled.
• Low-power mode 4 (LPM4)
– CPU is disabled.
– ACLK, MCLK, and SMCLK are disabled.
– DCO's dc generator is disabled.
– Crystal oscillator is stopped.
8
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the
CPU goes into LPM4 immediately after power-up.
Table 5. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
31, highest
NMIIFG
OFIFG
ACCVIFG (2) (3)
(non)-maskable
(non)-maskable
(non)-maskable
0FFFCh
30
Timer0_B3
TB0CCR0 CCIFG (4)
maskable
0FFFAh
29
Timer0_B3
TB0CCR2 TB0CCR1 CCIFG,
TBIFG (2) (4)
INTERRUPT SOURCE
INTERRUPT FLAG
Power-Up
External Reset
Watchdog Timer+
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV (2)
NMI
Oscillator fault
Flash memory access violation
Comparator_A+
maskable
0FFF8h
28
(4)
maskable
0FFF6h
27
WDTIFG
maskable
0FFF4h
26
maskable
0FFF2h
25
maskable
0FFF0h
24
maskable
0FFEEh
23
maskable
0FFECh
22
maskable
0FFEAh
21
0FFE8h
20
CAIFG
Watchdog Timer+
Timer0_A3
TA0CCR0 CCIFG
(4)
Timer0_A3
TA0CCR2 TA0CCR1 CCIFG,
TAIFG (5) (4)
USCI_A0 or USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG (2) (5)
USCI_A0 or USCI_B0 transmit
USCI_B0 I2C receive or transmit
UCA0TXIFG, UCB0TXIFG
(2) (6)
ADC10IFG (4)
ADC10
Reserved
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
I/O Port P2 (up to eight flags)
P2IFG.0 to P2IFG.7 (2) (4)
maskable
0FFE6h
19
I/O Port P1 (up to eight flags)
(2) (4)
maskable
0FFE4h
18
Timer1_A3
P1IFG.0 to P1IFG.7
TA1CCR0 CCIFG (4)
maskable
0FFE2h
17
Timer1_A3
TA1CCR2 TA1CCR1 CCIFG,
TAIFG (2) (4)
maskable
0FFE0h
16
See
(7)
0FFDEh
15
See
(8)
0FFDEh to
0FFC0h
14 to 0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
In UART or SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h)
disables the erasure of the flash if an invalid password is supplied.
The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
Address
5
4
1
0
ACCVIE
NMIIE
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
2
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog timer is configured in
interval timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
01h
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
3
3
2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw-0
rw-0
rw-0
rw-0
USCI_A0 receive interrupt enable
USCI_A0 transmit interrupt enable
USCI_B0 receive interrupt enable
USCI_B0 transmit interrupt enable
Table 7. Interrupt Flag Register 1 and 2
Address
7
6
5
02h
WDTIFG
OFIFG
PORIFG
RSTIFG
NMIIFG
Address
10
3
2
1
0
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault.
Power-on reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
7
6
03h
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
4
NMIIFG
5
4
3
2
1
0
UCB0TXIFG
UCB0RXIFG
UCA0TXIFG
UCA0RXIFG
rw-1
rw-0
rw-1
rw-0
USCI_A0 receive interrupt flag
USCI_A0 transmit interrupt flag
USCI_B0 receive interrupt flag
USCI_B0 transmit interrupt flag
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Memory Organization
Table 8. Memory Organization
MSP430G2755
MSP430G2855
Size
32kB
48kB
56kB
Main: interrupt vector
Flash
0xFFFF to 0xFFC0
0xFFFF to 0xFFC0
0xFFFF to 0xFFC0
Main: code memory
Flash
0xFFFF to 0x8000
0xFFFF to 0x4000
0xFFFF to 0x2100
Information memory
Size
256 Byte
256 Byte
256 Byte
Flash
0x10FF to 0x1000
0x10FF to 0x1000
0x10FF to 0x1000
RAM (total)
Size
4kB
4kB
4kB
0x20FF to 0x1100
0x20FF to 0x1100
0x20FF to 0x1100
Extended
Size
2KB
2KB
2KB
0x20FF to 0x1900
0x20FF to 0x1900
0x20FF to 0x1900
Memory
Mirrored
Size
RAM (mirrored at 0x18FF to
0x1100)
Peripherals
Size
MSP430G2955
2KB
2KB
2KB
0x18FF to 0x1100
0x18FF to 0x1100
0x18FF to 0x1100
2KB
2KB
2KB
0x09FF to 0x0200
0x09FF to 0x0200
0x09FF to 0x0200
16-bit
0x01FF to 0x0100
0x01FF to 0x0100
0x01FF to 0x0100
8-bit
0x00FF to 0x0010
0x00FF to 0x0010
0x00FF to 0x0010
8-bit SFR
0x000F to 0x0000
0x000F to 0x0000
0x000F to 0x0000
Bootstrap Loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to
the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's
Guide (SLAU319).
Table 9. BSL Function Pins
BSL FUNCTION
DA PACKAGE PINS
RHA PACKAGE PINS
Data transmit
32 - P1.1
30 - P1.1
Data receive
10 - P2.2
8 - P2.2
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire or JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
Main DCO Characteristics
• All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
• DCO control bits DCOx have a step size as defined by parameter SDCO.
• Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage =
12
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
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Calibration Data Stored in Information Memory Segment A
Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value (TLV) structure.
Table 10. Tags Used by the Devices
NAME
ADDRESS
VALUE
TAG_DCO_30
0x10F6
0x01
DCO frequency calibration at VCC = 3 V and TA = 30°C at calibration
DESCRIPTION
TAG_ADC10_1
0x10DA
0x10
ADC10_1 calibration tag
TAG_EMPTY
-
0xFE
Identifier for empty memory areas
Table 11. Labels Used by the Devices
LABEL
ADDRESS
OFFSET
SIZE
CAL_ADC_25T85
0x0010
word
INCHx = 0x1010, REF2_5 = 1, TA = 85°C
CONDITION AT CALIBRATION AND DESCRIPTION
CAL_ADC_25T30
0x000E
word
INCHx = 0x1010, REF2_5 = 1, TA = 30°C
CAL_ADC_25VREF_FACTOR
0x000C
word
REF2_5 = 1, TA = 30°C, IVREF+ = 1 mA
CAL_ADC_15T85
0x000A
word
INCHx = 0x1010, REF2_5 = 0, TA = 85°C
CAL_ADC_15T30
0x0008
word
INCHx = 0x1010, REF2_5 = 0, TA = 30°C
CAL_ADC_15VREF_FACTOR
0x0006
word
REF2_5 = 0, TA = 30°C, IVREF+ = 0.5 mA
CAL_ADC_OFFSET
0x0004
word
External VREF = 1.5 V, fADC10CLK = 5 MHz
CAL_ADC_GAIN_FACTOR
0x0002
word
External VREF = 1.5 V, fADC10CLK = 5 MHz
CAL_BC1_1MHZ
0x0009
byte
-
CAL_DCO_1MHZ
0x0008
byte
-
CAL_BC1_8MHZ
0x0007
byte
-
CAL_DCO_8MHZ
0x0006
byte
-
CAL_BC1_12MHZ
0x0005
byte
-
CAL_DCO_12MHZ
0x0004
byte
-
CAL_BC1_16MHZ
0x0003
byte
-
CAL_DCO_16MHZ
0x0002
byte
-
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
Four 8-bit I/O ports are implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible.
• Edge-selectable interrupt input capability for all bits of port P1 and port P2.
• Read and write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup or pulldown resistor.
• Each I/O has an individually programmable pin oscillator enable bit to enable low-cost touch sensing.
Watchdog Timer (WDT+)
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
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Timer_A3 (TA0, TA1)
Timer0_A3 and Timer1_A3 are 16-bit timers/counters with three capture/compare registers. Timer_A3 can
support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 12. Timer0_A3 Signal Connections
INPUT PIN NUMBER
DA38
RHA40
DEVICE INPUT
SIGNAL
P1.0 - 31
P1.0-29
TACLK
MODULE
INPUT NAME
TACLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
DA38
RHA40
P2.1 - 9
P2.1 - 7
TACLK
INCLK
P1.1 - 32
P1.1 - 30
TA0.0
CCI0A
P1.1- 32
P1.1 - 30
P2.2 - 10
P2.2 - 8
ACLK
CCI0B
P2.2 - 10
P2.2 - 8
P1.5 - 36
P1.5 - 34
VSS
GND
VCC
VCC
CCR0
TA0
P1.2 - 33
P1.2 - 31
TA0.1
CCI1A
P1.2 - 33
P1.2 - 31
P2.3 - 29
P2.3 - 27
TA0.1
CCI1B
P2.3 - 29
P2.3 - 27
P1.6 - 37
P1.6 - 35
P1.3 - 34
P1.3 - 32
P2.4 - 30
P2.4 - 28
P1.7 - 38
P1.7 - 36
P1.3 - 34
P1.3 - 32
VSS
GND
VCC
VCC
TA0.2
CCI2A
ACLK (internal)
CCI2B
VSS
GND
VCC
VCC
CCR1
CCR2
TA1
TA2
Table 13. Timer1_A3 Signal Connections
INPUT PIN NUMBER
DA38
RHA40
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
P2.0 - 8
P2.0 - 6
TACLK
TACLK
ACLK
SMCLK
PinOsc
PinOsc
TACLK
INCLK
P2.5 - 3
P2.5 - 40
TA1.0
CCI0A
TA1.0
CCI0B
VSS
GND
VCC
VCC
P3.6 - 27
14
ACLK
SMCLK
P3.6 - 25
TA1.1
CCI1A
CAOUT
CCI1B
VSS
GND
VCC
VCC
P3.7 - 28
P3.7 - 26
TA1.2
CCI2A
PinOsc
PinOsc
TA1.2
CCI2B
VSS
GND
VCC
VCC
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MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
CCR1
CCR2
OUTPUT PIN NUMBER
DA38
RHA40
P2.5 - 3
P2.5 - 40
P3.6 - 27
P3.6 - 25
P3.7 - 28
P3.7 - 26
TA0
TA1
TA2
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Timer_B3 (TB0)
Timer0_B3 is a 16-bit timer/counter with three capture/compare registers. Timer0_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer0_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 14. Timer0_B3 Signal Connections
INPUT PIN NUMBER
DA38
RHA40
DEVICE INPUT
SIGNAL
P4.7 - 24
P4.7 - 22
TBCLK
MODULE
INPUT NAME
TBCLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
DA38
RHA40
P4.7 - 27
P4.7 - 22
TBCLK
INCLK
P4.0 - 17
P4.0 - 15
TB0.0
CCI0A
P4.0 - 17
P4.0 - 15
P4.3 -20
P4.3 - 18
TB0.0
CCI0B
P4.3 - 20
P4.3 - 18
VSS
GND
VCC
VCC
CCR0
TB0
P4.1 - 18
P4.1 - 16
TB0.1
CCI1A
P4.1 - 18
P4.1 - 16
P4.4 - 21
P4.4 - 19
TB0.1
CCI1B
P4.4 - 21
P4.4 - 19
VSS
GND
P4.2 - 19
P4.2 - 17
P4.5 - 22
P4.5 - 20
P4.2 - 19
P4.2 - 17
VCC
VCC
TB0.2
CCI2A
ACLK (internal)
CCI2B
VSS
GND
VCC
VCC
CCR1
CCR2
TB1
TB2
Universal Serial Communications Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
Comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC10
The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
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Peripheral File Map
Table 15. Peripherals With Word Access
MODULE
REGISTER DESCRIPTION
ADC10
ADC data transfer start address
Timer0_B3
ADC10SA
1BCh
ADC10MEM
1B4h
ADC control register 1
ADC10CTL1
1B2h
ADC control register 0
ADC10CTL0
1B0h
Capture/compare register
TB0CCR2
0196h
Capture/compare register
TB0CCR1
0194h
Capture/compare register
TB0CCR0
0192h
TB0R
0190h
Capture/compare control
TB0CCTL2
0186h
Capture/compare control
TB0CCTL1
0184h
Capture/compare control
TB0CCTL0
0182h
TB0CTL
0180h
Timer_B interrupt vector
TB0IV
011Eh
Capture/compare register
TA0CCR2
0176h
Capture/compare register
TA0CCR1
0174h
Capture/compare register
TA0CCR0
0172h
Timer_B control
Timer_A register
TA0R
0170h
Capture/compare control
TA0CCTL2
0166h
Capture/compare control
TA0CCTL1
0164h
Capture/compare control
TA0CCTL0
0162h
Timer_A control
Timer1_A3
TA0CTL
0160h
Timer_A interrupt vector
TA0IV
012Eh
Capture/compare register
TA1CCR2
0156h
Capture/compare register
TA1CCR1
0154h
Capture/compare register
TA1CCR0
0152h
TA1R
0150h
Capture/compare control
TA1CCTL2
0146h
Capture/compare control
TA1CCTL1
0144h
Capture/compare control
TA1CCTL0
0142h
Timer_A register
Timer_A control
Flash Memory
Watchdog Timer+
16
TA1CTL
0140h
Timer_A interrupt vector
TA1IV
011Ch
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
WDTCTL
0120h
Watchdog/timer control
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OFFSET
ADC memory
Timer_B register
Timer0_A3
REGISTER
NAME
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Table 16. Peripherals With Byte Access
REGISTER
NAME
OFFSET
USCI_B0 transmit buffer
UCB0TXBUF
06Fh
USCI_B0 receive buffer
UCB0RXBUF
06Eh
UCB0STAT
06Dh
USCI B0 I2C Interrupt enable
UCB0CIE
06Ch
USCI_B0 bit rate control 1
UCB0BR1
06Bh
USCI_B0 bit rate control 0
UCB0BR0
06Ah
USCI_B0 control 1
UCB0CTL1
069h
USCI_B0 control 0
UCB0CTL0
068h
UCB0SA
011Ah
MODULE
USCI_B0
REGISTER DESCRIPTION
USCI_B0 status
USCI_B0 I2C slave address
USCI_B0 I2C own address
USCI_A0
UCB0OA
0118h
USCI_A0 transmit buffer
UCA0TXBUF
067h
USCI_A0 receive buffer
UCA0RXBUF
066h
USCI_A0 status
UCA0STAT
065h
USCI_A0 modulation control
UCA0MCTL
064h
USCI_A0 baud rate control 1
UCA0BR1
063h
USCI_A0 baud rate control 0
UCA0BR0
062h
USCI_A0 control 1
UCA0CTL1
061h
USCI_A0 control 0
ADC10
Comparator_A+
UCA0CTL0
060h
USCI_A0 IrDA receive control
UCA0IRRCTL
05Fh
USCI_A0 IrDA transmit control
UCA0IRTCTL
05Eh
USCI_A0 auto baud rate control
UCA0ABCTL
05Dh
ADC analog enable 0
ADC10AE0
04Ah
ADC analog enable 1
ADC10AE1
04Bh
ADC data transfer control register 1
ADC10DTC1
049h
ADC data transfer control register 0
ADC10DTC0
048h
CAPD
05Bh
CACTL2
05Ah
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
Basic Clock System+
Port P4
CACTL1
059h
Basic clock system control 3
BCSCTL3
053h
Basic clock system control 2
BCSCTL2
058h
Basic clock system control 1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
Port P4 selection 2
P4SEL2
044h
Port P4 resistor enable
P4REN
011h
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
Port P3
P4IN
01Ch
Port P3 selection 2
P3SEL2
043h
Port P3 resistor enable
P3REN
010h
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
P3IN
018h
Port P3 input
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Table 16. Peripherals With Byte Access (continued)
MODULE
REGISTER
NAME
REGISTER DESCRIPTION
Port P2
Port P2 selection 2
P2SEL2
042h
Port P2 resistor enable
P2REN
02Fh
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
P2IN
028h
Port P1 selection 2
P1SEL2
041h
Port P1 resistor enable
P1REN
027h
Port P1 selection
P1SEL
026h
P1IE
025h
Port P1 interrupt edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
Port P2 input
Port P1
Port P1 interrupt enable
Special Function
18
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OFFSET
P1OUT
021h
Port P1 input
P1IN
020h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
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Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
Voltage applied to any pin (2)
–0.3 V to VCC + 0.3 V
Diode current at any device pin
±2 mA
Storage temperature range, Tstg (3)
(1)
Unprogrammed device
–55°C to 150°C
Programmed device
–55°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
(2)
(3)
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
VCC
Supply voltage
VSS
Supply voltage
TA
Operating free-air temperature
fSYSTEM
(1)
(2)
NOM
MAX
During program execution
1.8
3.6
During flash programming or erase
2.2
3.6
0
Processor frequency (maximum MCLK frequency
using the USART module) (1) (2)
UNIT
V
V
-40
85
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
6
VCC = 2.7 V,
Duty cycle = 50% ± 10%
dc
12
VCC = 3.3 V,
Duty cycle = 50% ± 10%
dc
16
°C
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency - MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
1.8 V
Note:
2.7 V
2.2 V
Supply Voltage - V
3.3 V 3.6 V
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Safe Operating Area
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER
IAM,1MHz
(1)
(2)
TEST CONDITIONS
TA
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 0 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current at 1 MHz
VCC
MIN
TYP
2.2 V
250
3V
350
MAX
UNIT
µA
450
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Typical Characteristics, Active Mode Supply Current (Into VCC)
5.0
4.0
Active Mode Current − mA
Active Mode Current − mA
f DCO = 16 MHz
4.0
3.0
f DCO = 12 MHz
2.0
f DCO = 8 MHz
1.0
TA = 85 °C
3.0
TA = 25 °C
VCC = 3 V
2.0
TA = 85 °C
TA = 25 °C
1.0
f DCO = 1 MHz
0.0
1.5
2.0
2.5
3.0
3.5
VCC − Supply Voltage − V
Figure 2. Active Mode Current vs VCC, TA = 25°C
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VCC = 2.2 V
4.0
0.0
0.0
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 3. Active Mode Current vs DCO Frequency
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TA
VCC
Low-power mode 0
(LPM0) current (3)
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
25°C
2.2 V
56
µA
ILPM2
Low-power mode 2
(LPM2) current (4)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
22
µA
ILPM3,LFXT1
Low-power mode 3
(LPM3) current (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
1.0
1.5
µA
ILPM3,VLO
Low-power mode 3
current, (LPM3) (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.5
0.7
µA
2.2 V
0.1
0.5
ILPM4
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
25°C
Low-power mode 4
(LPM4) current (5)
85°C
2.2 V
1.6
2.5
ILPM0,1MHz
(1)
(2)
(3)
(4)
(5)
TEST CONDITIONS
MIN
(2)
TYP
MAX
UNIT
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
Typical Characteristics, Low-Power Mode Supply Currents
2.0
1.0
1.8
0.9
ILPM4 − Low−power mode current − µA
ILPM3 − Low−power mode current − µA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
1.6
1.4
1.2
VCC = 3.6 V
1.0
VCC = 3 V
0.8
VCC = 2.2 V
0.6
0.4
VCC = 1.8 V
0.2
0.0
−40.0 −20.0 0.0
20.0 40.0 60.0 80.0 100.0 120.0
TA − Temperature − °C
Figure 4. LPM3 Current vs Temperature
Copyright © 2013, Texas Instruments Incorporated
0.8
0.7
0.6
0.5
VCC = 3.6 V
0.4
VCC = 3 V
0.3
VCC = 2.2 V
0.2
0.1
0.0
−40.0 −20.0 0.0
VCC = 1.8 V
20.0 40.0 60.0 80.0 100.0 120.0
TA − Temperature − C
Figure 5. LPM4 Current vs Temperature
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Schmitt-Trigger Inputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
VCC
MIN
RPull
Pullup or pulldown resistor
CI
Input capacitance
VIN = VSS or VCC
MAX
0.45 VCC
0.75 VCC
1.35
2.25
3V
For pullup: VIN = VSS
For pulldown: VIN = VCC
TYP
UNIT
V
0.25 VCC
0.55 VCC
3V
0.75
1.65
3V
0.3
1
V
3V
20
50
kΩ
35
V
5
pF
Leakage Current, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
VCC
(1) (2)
High-impedance leakage current
MIN
3V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
I(OHmax) = –6 mA (1)
3V
VCC – 0.3
V
VOL
Low-level output voltage
I(OLmax) = 6 mA (1)
3V
VSS + 0.3
V
(1)
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fPx.y
Port output frequency
(with load)
Px.y, CL = 20 pF, RL = 1 kΩ
fPort_CLK
Clock output frequency
Px.y, CL = 20 pF (2)
(1)
(2)
22
(1) (2)
VCC
MIN
TYP
MAX
UNIT
3V
12
MHz
3V
16
MHz
A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics, Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
VCC = 2.2 V
P1.7
TA = 25°C
25
TA = 85°C
20
15
10
5
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
30
0
TA = 25°C
40
TA = 85°C
30
20
10
0
0
0.5
1
1.5
2
0
2.5
0.5
1
1.5
2
2.5
3
VOL − Low-Level Output Voltage − V
Figure 6.
VOL − Low-Level Output Voltage − V
Figure 7.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
3.5
0
0
VCC = 2.2 V
P1.7
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
VCC = 3 V
P1.7
−5
−10
−15
TA = 85°C
−20
TA = 25°C
−25
0
0.5
VCC = 3 V
P1.7
−10
−20
−30
TA = 85°C
−40
TA = 25°C
−50
1
1.5
2
VOH − High-Level Output Voltage − V
Figure 8.
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2.5
0
0.5
1
1.5
2
2.5
3
3.5
VOH − High-Level Output Voltage − V
Figure 9.
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Pin-Oscillator Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
foP1.x
Port output oscillation frequency
foP2.x
Port output oscillation frequency
foP2.6/7
Port output oscillation frequency
foP3.x
Port output oscillation frequency
foP4.x
Port output oscillation frequency
(1)
(2)
P1.y, CL = 10 pF, RL = 100 kΩ
VCC
MIN
(1) (2)
3V
P1.y, CL = 20 pF, RL = 100 kΩ (1) (2)
P2.0 to P2.5, CL = 10 pF, RL = 100 kΩ (1) (2)
P2.0 to P2.5, CL = 20 pF, RL = 100 kΩ (1) (2)
P2.6 and P2.7, CL = 20 pF, RL = 100 kΩ (1) (2)
P3.y, CL = 10 pF, RL = 100 kΩ (1) (2)
P3.y, CL = 20 pF, RL = 100 kΩ (1) (2)
P4.y, CL = 10 pF, RL = 100 kΩ (1) (2)
P4.y, CL = 20 pF, RL = 100 kΩ (1) (2)
3V
3V
3V
3V
TYP
MAX
UNIT
1400
kHz
900
1800
kHz
1000
700
kHz
1800
kHz
1000
1800
kHz
1000
A resistive divider with two 50-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Typical Characteristics, Pin-Oscillator Frequency
TYPICAL OSCILLATING FREQUENCY
vs
LOAD CAPACITANCE
TYPICAL OSCILLATING FREQUENCY
vs
LOAD CAPACITANCE
1.50
VCC = 3.0 V
1.35
1.20
1.05
P1.y
0.90
P2.0 to P2.5
0.75
P2.6 and P2.7
0.60
0.45
0.30
0.15
0.00
VCC = 2.2 V
1.35
1.20
1.05
P1.y
0.90
P2.0 to P2.5
0.75
P2.6 and P2.7
0.60
0.45
0.30
0.15
0.00
10
50
100
CLOAD − External Capacitance − pF
A. One output active at a time.
10
50
100
CLOAD − External Capacitance − pF
A. One output active at a time.
Figure 10.
24
fosc − Typical Oscillation Frequency − MHz
fosc − Typical Oscillation Frequency − MHz
1.50
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Figure 11.
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POR and BOR (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(start)
See Figure 12
dVCC/dt ≤ 3 V/s
0.7 × V(B_IT-)
V(B_IT-)
See Figure 12 through Figure 14
dVCC/dt ≤ 3 V/s
1.35
V
Vhys(B_IT-)
See Figure 12
dVCC/dt ≤ 3 V/s
140
mV
td(BOR)
See Figure 12
2000
µs
t(reset)
Pulse duration needed at RST/NMI pin
to accepted reset internally
(1)
(2)
2.2 V
2
V
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) +
Vhys(B_IT-)is ≤ 1.8 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 12. POR and BOR vs Supply Voltage
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Typical Characteristics, POR and BOR
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
t pw − Pulse Width − µs
t pw − Pulse Width − µs
Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR and BOR Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
1000
tf
tr
t pw − Pulse Width − µs
t pw − Pulse Width − µs
Figure 14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR and BOR Signal
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DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
Supply voltage
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
RSELx = 15
3
3.6
0.14
MHz
0.17
MHz
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
3V
0.06
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
3V
0.07
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
3V
0.15
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
3V
0.21
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
3V
0.30
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
3V
0.41
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
3V
0.58
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
3V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
3V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
3V
1.6
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
3V
2.3
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
3V
3.4
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
3V
4.25
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
3V
4.30
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
3V
6.00
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
3V
8.60
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3V
1.35
ratio
SDCO
Frequency step between
tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3V
1.08
ratio
Duty cycle
Measured at SMCLK output
3V
50
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MHz
7.30
MHz
9.60
MHz
13.9
MHz
12.0
18.5
MHz
16.0
26.0
MHz
7.8
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Calibrated DCO Frequencies, Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
3
%
1-MHz tolerance over VCC
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
30°C
1.8 V to 3.6 V
-3
±2
3
%
1-MHz tolerance overall
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
1.8 V to 3.6 V
-6
±3
6
%
8-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
3
%
8-MHz tolerance over VCC
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
30°C
2.2 V to 3.6 V
-3
±2
3
%
8-MHz tolerance overall
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
2.2 V to 3.6 V
-6
±3
6
%
12-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
3
%
12-MHz tolerance over VCC
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
30°C
2.7 V to 3.6 V
-3
±2
3
%
12-MHz tolerance overall
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
2.7 V to 3.6 V
-6
±3
6
%
16-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
3
%
16-MHz tolerance over VCC
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
30°C
3.3 V to 3.6 V
-3
±2
3
%
16-MHz tolerance overall
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
3.3 V to 3.6 V
-6
±3
6
%
(1)
28
This is the frequency change from the measured frequency at 30°C over temperature.
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Wake-Up From Lower-Power Modes (LPM3, LPM4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tDCO,LPM3/4
DCO clock wake-up time from LPM3
or LPM4 (1)
tCPU,LPM3/4
CPU wake-up time from LPM3 or
LPM4 (2)
(1)
(2)
VCC
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
MIN
3V
TYP
MAX
1.5
UNIT
µs
1/fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics, DCO Clock Wake-Up Time From LPM3 or LPM4
DCO Wake Time − µs
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 15. DCO Wake-Up Time From LPM3 vs DCO Frequency
Copyright © 2013, Texas Instruments Incorporated
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DCO With External Resistor ROSC (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fDCO,ROSC
DCO output frequency with ROSC
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0,
TA = 25°C
3V
1.95
MHz
DT
Temperature drift
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
3V
±0.1
%/°C
DV
Drift with VCC
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
3V
10
%/V
(1)
ROSC = 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK = ±50 ppm/°C.
Typical Characteristics - DCO With External Resistor ROSC
DCO FREQUENCY
vs
ROSC
VCC = 2.2 V, TA = 25°C
DCO FREQUENCY
vs
ROSC
VCC = 3 V, TA = 25°C
10.00
DCO Frequency − MHz
DCO Frequency − MHz
10.00
1.00
0.10
RSELx = 4
0.01
10.00
100.00
1000.00
100.00
1000.00
10000.00
ROSC − External Resistor − kW
Figure 17.
DCO FREQUENCY
vs
TEMPERATURE
VCC = 3 V
DCO FREQUENCY
vs
SUPPLY VOLTAGE
TA = 25°C
2.50
2.25
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
DCO Frequency − MHz
ROSC = 100k
2.00
DCO Frequency − MHz
RSELx = 4
ROSC − External Resistor − kW
Figure 16.
2.25
ROSC = 100k
2.00
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
0.50
ROSC = 1M
0.25
−25.0
0.0
25.0
50.0
TA − Temperature − C
Figure 18.
30
0.10
0.01
10.00
10000.00
2.50
0.00
−50.0
1.00
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75.0
ROSC = 1M
0.25
100.0
0.00
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 19.
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SLAS800 – MARCH 2013
Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0 or 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
OALF
Oscillation allowance for
LF crystals
CL,eff
fFault,LF
(1)
(2)
(3)
(4)
Integrated effective load
capacitance, LF mode (2)
XTS = 0, LFXT1Sx = 0 or 1
VCC
MIN
TYP
1.8 V to 3.6 V
1.8 V to 3.6 V
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
2.2 V
30
Oscillator fault frequency,
LF mode (3)
XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4)
2.2 V
10
50
pF
70
%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TA
VCC
MIN
TYP
MAX
fVLO
VLO frequency
PARAMETER
-40°C to 85°C
3V
4
12
20
dfVLO/dT
VLO frequency temperature drift
-40°C to 85°C
3V
25°C
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
Copyright © 2013, Texas Instruments Incorporated
kHz
0.5
%/°C
4
%/V
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Crystal Oscillator LFXT1, High-Frequency Mode (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
XTS = 1, LFXT1Sx = 0
1.8 V to 3.6 V
LFXT1 oscillator crystal
frequency, HF mode 1
XTS = 1, LFXT1Sx = 1
LFXT1 oscillator crystal
frequency, HF mode 2
XTS = 1, LFXT1Sx = 2
fLFXT1,HF0
LFXT1 oscillator crystal
frequency, HF mode 0
fLFXT1,HF1
fLFXT1,HF2
MAX
UNIT
0.4
1
MHz
1.8 V to 3.6 V
1
4
MHz
1.8 V to 3.6 V
2
10
2.2 V to 3.6 V
2
12
3 V to 3.6 V
fLFXT1,HF,logic
OAHF
CL,eff
LFXT1 oscillator logic-level
square-wave input frequency,
HF mode
Oscillation allowance for HF
crystals (see Figure 20 and
Figure 21)
Integrated effective load
capacitance, HF mode (2)
Duty cycle, HF mode
fFault,HF
(1)
(2)
(3)
(4)
(5)
32
Oscillator fault frequency (4)
XTS = 1, LFXT1Sx = 3
TYP
2
16
1.8 V to 3.6 V
0.4
10
2.2 V to 3.6 V
0.4
12
3 V to 3.6 V
0.4
16
XTS = 1, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz,
CL,eff = 15 pF
2700
XTS = 1, LFXT1Sx = 1,
fLFXT1,HF = 4 MHz,
CL,eff = 15 pF
800
XTS = 1, LFXT1Sx = 2,
fLFXT1,HF = 16 MHz,
CL,eff = 15 pF
300
XTS = 1 (3)
XTS = 1,
Measured at P2.0/ACLK,
fLFXT1,HF = 10 MHz
XTS = 1,
Measured at P2.0/ACLK,
fLFXT1,HF = 16 MHz
XTS = 1, LFXT1Sx = 3 (5)
50
pF
60
2.2 V, 3 V
%
40
2.2 V, 3 V
MHz
Ω
1
40
MHz
30
50
60
300
kHz
To improve EMI on the XT1 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
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Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
OSCILLATION ALLOWANCE
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
OSCILLATOR SUPPLY CURRENT
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
800.0
100000.00
LFXT1Sx = 3
10000.00
1000.00
LFXT1Sx = 3
100.00
LFXT1Sx = 1
LFXT1Sx = 2
XT Oscillator Supply Current − uA
Oscillation Allowance − Ohms
700.0
600.0
500.0
400.0
300.0
LFXT1Sx = 2
200.0
100.0
LFXT1Sx = 1
10.00
0.10
1.00
10.00
100.00
0.0
0.0
Crystal Frequency − MHz
4.0
8.0
12.0
16.0
20.0
Crystal Frequency − MHz
Figure 21.
Figure 20.
Timer_A, Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA/B
Timer_A or Timer_B input clock
frequency
SMCLK, duty cycle = 50% ± 10%
tTA/B,cap
Timer_A or Timer_B capture timing
TA0, TA1, TB0
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VCC
MIN
TYP
MAX
fSYSTEM
3V
20
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MHz
ns
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USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fUSCI
USCI input clock frequency
fmax,BITCLK
Maximum BITCLK clock frequency
(equals baudrate in MBaud) (1)
3V
2
tτ
UART receive deglitch time (2)
3V
50
(1)
(2)
SMCLK, duty cycle = 50% ± 10%
TYP
MAX
fSYSTEM
UNIT
MHz
MHz
100
600
ns
The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 22 and
Figure 23)
PARAMETER
TEST CONDITIONS
VCC
MIN
SMCLK, duty cycle = 50% ± 10%
TYP
MAX
UNIT
fSYSTEM
MHz
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
3V
75
ns
tHD,MI
SOMI input data hold time
3V
0
ns
tVALID,MO
SIMO output data valid time
UCLK edge to SIMO valid, CL = 20 pF
3V
20
ns
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 22. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 23. SPI Master Mode, CKPH = 1
34
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USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24 and
Figure 25)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
STE lead time, STE low to clock
3V
tSTE,LAG
STE lag time, Last clock to STE high
3V
tSTE,ACC
STE access time, STE low to SOMI data out
3V
50
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
3V
50
ns
tSU,SI
SIMO input data setup time
3V
15
ns
tHD,SI
SIMO input data hold time
3V
10
ns
tVALID,SO
UCLK edge to SOMI valid,
CL = 20 pF
SOMI output data valid time
tSTE,LEAD
3V
50
UNIT
tSTE,LEAD
ns
10
ns
50
75
ns
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 24. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tHD,MO
tVALID,SO
tSTE,DIS
SOMI
Figure 25. SPI Slave Mode, CKPH = 1
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 26)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
3V
0
TYP
SMCLK, duty cycle = 50% ± 10%
fSCL ≤ 100 kHz
MAX
UNIT
fSYSTEM
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
3V
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
3V
0
tSU,DAT
Data setup time
3V
250
ns
tSU,STO
Setup time for STOP
3V
4.0
µs
tSP
Pulse duration of spikes suppressed
by input filter
3V
50
fSCL > 100 kHz
fSCL ≤ 100 kHz
tSU,STA
tHD,STA
4.7
3V
fSCL > 100 kHz
µs
0.6
µs
0.6
tHD,STA
ns
100
600
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 26. I2C Mode Timing
Comparator_A+
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
I(DD)
See
TEST CONDITIONS
(1)
I(Refladder/
RefDiode)
VCC
MIN
TYP
MAX
UNIT
CAON = 1, CARSEL = 0, CAREF = 0
3V
45
µA
CAON = 1, CARSEL = 0,
CAREF = 1, 2, or 3,
No load at CA0 and CA1
3V
45
µA
V(IC)
Common-mode input voltage
CAON = 1
3V
V(Ref025)
(Voltage at 0.25 VCC node) / VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at CA0 and CA1
3V
0.24
V(Ref050)
(Voltage at 0.5 VCC node) / VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at CA0 and CA1
3V
0.48
V(RefVT)
See Figure 27 and Figure 28
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at CA0 and CA1, TA = 85°C
3V
490
mV
3V
±10
mV
3V
0.7
mV
120
ns
1.5
µs
(2)
V(offset)
Offset voltage
Vhys
Input hysteresis
t(response)
(1)
(2)
36
CAON = 1
Response time
(low-to-high and high-to-low)
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0
TA = 25°C, Overdrive 10 mV,
With filter: CAF = 1
0
VCC-1
V
3V
The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification.
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The
two successive measurements are then summed together.
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Typical Characteristics – Comparator_A+
650
650
VCC = 2.2 V
V(RefVT) – Reference Voltage – mV
V(RefVT) – Reference Voltage – mV
VCC = 3 V
600
Typical
550
500
450
400
-45
600
Typical
550
500
450
400
-45
-5
15
35
55
75
95
115
TA – Free-Air Temperature – °C
Figure 28. V(RefVT) vs Temperature, VCC = 2.2 V
-25
-5
15
35
55
75
95
115
TA – Free-Air Temperature – °C
Figure 27. V(RefVT) vs Temperature, VCC = 3 V
-25
Short Resistance – kW
100
VCC = 1.8 V
VCC = 2.2 V
VCC = 3 V
10
VCC = 3.6 V
1
0
0.2
0.4
0.6
0.8
1
VIN/VCC – Normalized Input Voltage – V/V
Figure 29. Short Resistance vs VIN/VCC
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10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
TEST CONDITIONS
Analog supply voltage
VAx
Analog input voltage
IADC10
IREF+
VCC
VSS = 0 V
All Ax terminals, Analog inputs
selected in ADC10AE register
(2)
ADC10 supply current
TA
(3)
Reference supply current,
reference buffer disabled (4)
fADC10CLK = 5.0 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
3V
25°C
3V
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
0.6
mA
0.25
25°C
3V
mA
0.25
IREFB,0
Reference buffer supply
current with ADC10SR = 0 (4)
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
25°C
3V
1.1
mA
IREFB,1
Reference buffer supply
current with ADC10SR = 1 (4)
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
25°C
3V
0.5
mA
CI
Input capacitance
Only one terminal Ax can be selected
at one time
25°C
3V
RI
Input MUX ON resistance
0 V ≤ VAx ≤ VCC
25°C
3V
(1)
(2)
(3)
(4)
38
27
1000
pF
Ω
The leakage current is defined in the leakage current table with Px.y/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
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10-Bit ADC, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VCC,REF+
Positive built-in reference
analog supply voltage range
IVREF+ ≤ 1 mA, REF2_5V = 0
2.2
IVREF+ ≤ 1 mA, REF2_5V = 1
2.9
VREF+
Positive built-in reference
voltage
IVREF+ ≤ IVREF+max, REF2_5V = 0
ILD,VREF+
Maximum VREF+ load
current
VREF+ load regulation
IVREF+ ≤ IVREF+max, REF2_5V = 1
3V
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
MAX
UNIT
V
1.41
1.5
1.59
2.35
2.5
2.65
3V
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 0.75 V,
REF2_5V = 0
TYP
±1
V
mA
±2
3V
LSB
±2
VREF+ load regulation
response time
IVREF+ = 100 µA→900 µA,
VAx ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB,
ADC10SR = 0
3V
400
ns
CVREF+
Maximum capacitance at
VREF+ pin
IVREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1
3V
100
pF
TCREF+
Temperature coefficient (1)
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA
3V
±100
ppm/
°C
tREFON
Settling time of internal
reference voltage to 99.9%
VREF
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
3.6 V
30
µs
tREFBURST
Settling time of reference
buffer to 99.9% VREF
IVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1,
REFBURST = 1, ADC10SR = 0
3V
2
µs
(1)
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
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10-Bit ADC, External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VEREF+
TEST CONDITIONS
Positive external reference input
voltage range (2)
1.4
3
0
1.2
V
1.4
VCC
V
Differential external reference
input voltage range,
ΔVEREF = VEREF+ – VEREF–
VEREF+ > VEREF–
(1)
(2)
(3)
(4)
(5)
UNIT
VEREF– ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1 (3)
ΔVEREF
Static input current into VEREF–
MAX
VCC
VEREF+ > VEREF–
IVEREF–
TYP
1.4
Negative external reference input
voltage range (4)
Static input current into VEREF+
MIN
VEREF+ > VEREF–,
SREF1 = 1, SREF0 = 0
VEREF–
IVEREF+
VCC
V
(5)
0 V ≤ VEREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
3V
±1
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1 (3)
3V
0
0 V ≤ VEREF– ≤ VCC
3V
±1
µA
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC10SR = 0
fADC10CLK
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10OSC
ADC10 built-in oscillator
frequency
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
tCONVERT
Conversion time
tADC10ON
Turn-on settling time of
the ADC
(1)
ADC10SR = 1
VCC
MIN
TYP
MAX
0.45
6.3
0.45
1.5
3V
3.7
6.3
3V
2.06
3.51
3V
UNIT
MHz
MHz
µs
13 ×
ADC10DIV ×
1/fADC10CLK
fADC10CLK from ACLK, MCLK, or SMCLK:
ADC10SSELx ≠ 0
(1)
100
ns
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
10-Bit ADC, Linearity Parameters (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
EI
Integral linearity error
PARAMETER
3V
±1
LSB
ED
Differential linearity error
3V
±1
LSB
EO
Offset error
3V
±1
LSB
EG
Gain error
3V
±1.1
±2
LSB
ET
Total unadjusted error
3V
±2
±5
LSB
(1)
40
TEST CONDITIONS
Source impedance RS < 100 Ω
VCC
MIN
TYP
The reference buffer's offset adds to the gain, and offset, and total unadjusted error.
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SLAS800 – MARCH 2013
10-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISENSOR
TEST CONDITIONS
Temperature sensor supply
current (1)
TCSENSOR
VCC
REFON = 0, INCHx = 0Ah,
TA = 25°C
ADC10ON = 1, INCHx = 0Ah
(2)
60
3V
3.55
tSensor(sample)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
3V
IVMID
Current into divider at channel 11
ADC10ON = 1, INCHx = 0Bh
3V
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID ≈ 0.5 × VCC
3V
tVMID(sample)
Sample time required if channel
11 is selected (5)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
3V
(2)
(3)
(4)
(5)
TYP
3V
Sample time required if channel
10 is selected (3)
(1)
MIN
MAX
UNIT
µA
mV/°C
30
µs
(4)
1.5
µA
V
1220
ns
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program or erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V, 3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V, 3.6 V
1
7
mA
tCPT
Cumulative program time (1)
2.2 V, 3.6 V
10
ms
tCMErase
Cumulative mass erase time
2.2 V, 3.6 V
20
104
Program and erase endurance
ms
105
100
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
See
(2)
30
years
tFTG
Block program time for first byte or word
See
(2)
25
tFTG
tBlock, 1-63
Block program time for each additional byte or word
See
(2)
18
tFTG
tBlock,
Block program end-sequence wait time
See
(2)
6
tFTG
10593
tFTG
4819
tFTG
tBlock,
0
End
tMass Erase
Mass erase time
See
(2)
tSeg Erase
Segment erase time
See
(2)
(1)
(2)
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word write, individual byte write, and block write modes.
These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
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RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
TEST CONDITIONS
(1)
MIN
CPU halted
MAX
UNIT
1.6
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.2 V
VCC
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V
0.025
15
µs
1
µs
(1)
TYP
tSBW,En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V
15
100
fTCK
TCK input frequency (2)
2.2 V
0
5
MHz
RInternal
Internal pulldown resistance on TEST
2.2 V
25
90
kΩ
(1)
(2)
)
MIN
2.2 V
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
42
TEST CONDITIONS
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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SLAS800 – MARCH 2013
PORT SCHEMATICS
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
PxSEL2.y
PxSEL.y
1
PxOUT.y
DVSS
0
DVCC
1
1
0
From Module
1
2
0
P1.0/TA0CLK/ADCCLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
3
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
EN
PxIRQ.y
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
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Table 17. Port P1 (P1.0 to P1.3) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
CONTROL BITS / SIGNALS (1)
P1DIR.x
P1SEL.x
P1SEL2.x
P1.0/
P1.x (I/O)
I: 0; O: 1
0
0
TA0CLK/
TA0.TACLK
0
1
0
ACLK
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P1.1/
P1.x (I/O)
I: 0; O: 1
0
0
TA0.0/
Timer0_A3.CCI0A
0
1
0
Timer0_A3.TA0
1
1
0
ADC10CLK
0
1
Pin Osc
Capacitive sensing
P1.2/
P1.x (I/O)
TA0.1/
Timer0_A3.CCI1A
2
X
0
1
I: 0; O: 1
0
0
0
1
0
Timer0_A3.TA1
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P1.3/
P1.x (I/O)
I: 0; O: 1
0
0
TA0.2/
Timer0_A3.CCI2A
0
1
0
Timer0_A3.TA2
1
1
0
Capacitive sensing
X
0
1
3
Pin Osc
(1)
44
X = don't care
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SLAS800 – MARCH 2013
Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Module
1
Direction
0: Input
1: Output
2
From Module
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
3
0
1
1
2
P1.4/SMCLK/TCK
P1.5/TA0.0/TMS
P1.6/TA0.1/TDI/TCLK
P1.7/TA0.2/TDO/TDI
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
EN
Set
Interrupt
Edge
Select
PxIES.y
From JTAG
To JTAG
* Note: MSP430G2x53 devices only. MSP430G2x13 devices have no ADC10.
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Table 18. Port P1 (P1.4 to P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
CONTROL BITS / SIGNALS (1)
P1DIR.x
P1SEL.x
P1SEL2.x
JTAG Mode
P1.4/
P1.x (I/O)
I: 0; O: 1
0
0
0
SMCLK/
SMCLK
1
1
0
0
TCK
X
X
X
1
Pin Osc
Capacitive sensing
X
0
1
0
P1.5/
P1.x (I/O)
I: 0; O: 1
0
0
0
TA0.0/
Timer0_A3.TA0
1
1
0
0
TMS
X
X
X
1
TCK/
4
5
TMS/
Pin Osc
Capacitive sensing
P1.6/
P1.x (I/O)
TA0.1/
TDI/
6
X
0
1
0
I: 0; O: 1
0
0
0
Timer0_A3.TA1
1
1
0
0
TDI
X
X
X
1
TCLK/
TCLK
X
X
X
1
Pin Osc
Capacitive sensing
X
0
1
0
P1.7/
P1.x (I/O)
I: 0; O: 1
0
0
0
TA0.2/
Timer0_A3.TA2
1
1
0
0
TDO
X
X
X
1
TDI/
TDI
X
X
X
1
Pin Osc
Capacitive sensing
X
0
1
0
TDO/
(1)
46
7
X = don't care
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SLAS800 – MARCH 2013
Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger
To ADC10
INCHx = y
ADC10AE0.y
PxSEL2.y PxSEL.y
PxDIR.y
0,2,3
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
3
0
1
1
2
Bus
Keeper
EN
P2.0/TA0CLK/ACLK/A0
P2.1/TA0INCLK/SMCLK/A1
P2.2/TA0.0/A2
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
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SREF2
To ADC10 VREF-
VSS
0
1
To ADC10
INCHx = y
ADC10AE0.y
PxSEL2.y PxSEL.y
PxDIR.y
0,2,3
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From ADC10
1
0
3
0
1
1
2
Bus
Keeper
EN
P2.3/TA0.1/A3/VREF-/VEREF-
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
48
Interrupt
Edge
Select
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SLAS800 – MARCH 2013
To ADC10 VREF+
To ADC10
INCHx = y
ADC10AE0.y
PxSEL2.y PxSEL.y
PxDIR.y
0,2,3
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From ADC10
1
0
1
1
2
0
Bus
Keeper
EN
3
P2.4/TA0.2/A4/VREF+/VEREF+
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
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to/from DCO
DCOR
PxSEL2.y PxSEL.y
PxDIR.y
0,2,3
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From ADC10
1
0
3
0
1
1
2
Bus
Keeper
EN
P2.5/TA1.0/ROSC
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
Interrupt
Edge
Select
PxIES.y
50
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SLAS800 – MARCH 2013
Table 19. Port P2 (P2.0 to P2.5) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2SEL2.x
ADC10AE.y
INCH.y=1
P2.0/
P2.x (I/O)
I: 0; O: 1
0
0
0
TA1CLK/
Timer1_A3.TACLK
0
1
0
0
ACLK output
1
1
0
0
A0/
A0
X
X
X
1 (y = 0)
Pin Osc
Capacitive sensing
X
0
1
0
P2.1/
P2.x (I/O)
I: 0; O: 1
0
0
0
Timer0_A3.TAINCLK
0
1
0
0
SMCLK output
1
1
0
0
A1/
A1
X
X
X
1 (y = 1)
Pin Osc
Capacitive sensing
X
0
1
0
P2.2/
P2.x (I/O)
I: 0; O: 1
0
0
0
TA0.0/
Timer0_A3.CCI0B
0
1
0
0
Timer0_A3.TA0
1
1
0
0
A2/
A2
X
X
X
1 (y = 2)
Pin Osc
Capacitive sensing
X
0
1
0
P2.3/
P2.x (I/O)
I: 0; O: 1
0
0
0
TA0.1/
Timer0_A3.CCI1B
0
1
0
0
Timer0_A3.TA1
1
1
0
0
A3
X
X
X
1 (y = 3)
VREF-/
VREF-
X
X
X
1
VEREF-/
VEREF-
X
X
X
1
Pin Osc
Capacitive sensing
X
0
1
0
P2.4/
P2.x (I/O)
I: 0; O: 1
0
0
0
TA0.2/
Timer0_A3.CCI2B
0
1
0
0
Timer0_A3.TA2
1
1
0
0
A4
X
X
X
1 (y = 4)
VREF+/
VREF+
X
X
X
1
VEREF+/
VEREF+
X
X
X
1
Pin Osc
Capacitive sensing
X
0
1
0
P2.5/
P2.x (I/O)
I: 0; O: 1
0
0
0
TA1.0/
Timer1_A3.CCI0A
0
1
0
0
Timer1_A3.TA0
1
1
0
0
ROSC/
ROSC (DCOR = 1 to enable its
function)
X
X
X
0
Pin Osc
Capacitive sensing
X
0
1
0
ACLK/
0
TA0INCLK/
SMCLK/
1
2
A3/
3
A4/
4
5
(1)
X = don't care
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Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
XOUT/P2.7
LF off
PxSEL.6 and PxSEL.7
BCSCTL3.LFXT1Sx = 11
0
1
LFXT1CLK
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
1
1
2
XIN/P2.6
3
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
52
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SLAS800 – MARCH 2013
Table 20. Port P2 (P2.6) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P2.x)
x
XIN/
P2.6/
Pin Osc
(1)
FUNCTION
XIN
6
P2.x (I/O)
Capacitive sensing
P2DIR.x
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
0
1
1
0
0
I: 0; O: 1
0
X
0
0
X
0
X
1
X
X = don't care
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Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
XIN
LF off
PxSEL.6 and PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
1
from P2.6
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
1
1
0
From Module
1
2
XOUT/P2.7
3
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
PxIFG.y
Set
Interrupt
Edge
Select
PxSEL.y
PxIES.y
54
EN
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SLAS800 – MARCH 2013
Table 21. Port P2 (P2.7) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P2.x)
x
XOUT/
P2.7/
Pin Osc
(1)
FUNCTION
XOUT
7
P2.x (I/O)
Capacitive sensing
P2DIR.x
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
1
1
1
0
0
I: 0; O: 1
0
X
0
0
X
0
X
1
X
X = don't care
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Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger
To ADC10
INCHx = y
ADC10AE0.y
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Module
1
Direction
0: Input
1: Output
2
From Module
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
3
2
0
1
Bus
Keeper
EN
1
P3.0/UCB0STE/UCA0CLK/A5
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
56
EN
Interrupt
Edge
Select
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PxSEL2.y
PxSEL.y
PxDIR.y
0
From Module
1
Direction
0: Input
1: Output
2
From Module
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
1
1
2
0
3
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
PxIFG.y
PxSEL.y
PxIES.y
EN
Q
Set
Interrupt
Edge
Select
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To ADC10
INCHx = y
ADC10AE0.y
PxSEL2.y PxSEL.y
PxDIR.y
0,2,3
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
1
1
2
0
Bus
Keeper
EN
3
P3.6/TA1.1/A6
P3.7/TA1.2/A7
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
Interrupt
Edge
Select
PxIES.y
58
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SLAS800 – MARCH 2013
Table 22. Port P3 (P3.0 to P3.7) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL.x
P3SEL2.x
ADC10AE.y
INCH.y=1
P3.0/
P3.x (I/O)
I: 0; O: 1
0
0
0
UCB0STE/
UCB0STE
from USCI
1
0
0
UCA0CLK
from USCI
1
0
0
1 (y = 5)
UCA0CLK/
0
A5/
A5
X
X
X
Pin Osc
Capacitive sensing
X
0
1
0
P3.1/
P3.x (I/O)
I: 0; O: 1
0
0
n/a
UCB0SIMO
from USCI
1
0
n/a
UCB0SDA
from USCI
1
0
n/a
X
0
1
n/a
I: 0; O: 1
0
0
n/a
UCB0SOMI
from USCI
1
0
n/a
UCB0SCL
from USCI
1
0
n/a
X
0
1
n/a
UCB0SIMO/
UCB0SDA/
1
Pin Osc
Capacitive sensing
P3.2/
P3.x (I/O)
UCB0SOMI/
UCB0SCL/
2
Pin Osc
Capacitive sensing
P3.3/
P3.x (I/O)
I: 0; O: 1
0
0
n/a
UCB0CLK/
UCB0CLK
from USCI
1
0
n/a
UCA0STE
from USCI
1
0
n/a
UCA0STE/
3
Pin Osc
Capacitive sensing
X
0
1
n/a
P3.4/
P3.x (I/O)
I: 0; O: 1
0
0
n/a
UCA0TXD/
UCA0TXD
from USCI
1
0
n/a
UCA0SIMO
from USCI
1
0
n/a
UCA0SIMO/
4
Pin Osc
Capacitive sensing
X
0
1
n/a
P3.5/
P3.x (I/O)
I: 0; O: 1
0
0
n/a
UCA0RXD/
UCA0RXD
from USCI
1
0
n/a
UCA0TXD
from USCI
1
0
n/a
X
0
1
n/a
I: 0; O: 1
0
0
0
Timer1_A3.CCI1A
0
1
0
0
Timer1_A3.TA1
1
1
0
0
A6/
A6
X
X
X
1 (y = 6)
Pin Osc
Capacitive sensing
X
0
1
0
P3.7/
P3.x (I/O)
I: 0; O: 1
0
0
0
TA1.2/
Timer1_A3.CCI2A
0
1
0
0
Timer1_A3.TA2
1
1
0
0
A7/
A7
X
X
X
1 (y = 7)
Pin Osc
Capacitive sensing
X
0
1
0
UCA0TXD/
5
Pin Osc
Capacitive sensing
P3.6/
P3.x (I/O)
TA1.1/
6
7
(1)
X = don't care
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Port P4 Pin Schematic: P4.0 to P4.7, Input/Output With Schmitt Trigger
To Comparator
From Comparator
CAPD.y
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Module
1
Direction
0: Input
1: Output
2
From Module
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
3
2
0
1
1
Bus
Keeper
EN
P4.0/TB0.0/CA0
P4.1/TB0.1/CA1
P4.2/TB0.2/CA2
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
Set
Interrupt
Edge
Select
PxIES.y
60
EN
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SLAS800 – MARCH 2013
To Comparator
From Comparator
To ADC10 *
INCHx = y *
CAPD.y
ADC10AE0.y *
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Module
1
Direction
0: Input
1: Output
2
From Module
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
3
2
0
1
1
Bus
Keeper
EN
P4.3/TB0.0/A12/CA3
P4.4/TB0.1/A13/CA4
P4.5/TB0.2/A14/CA5
P4.6/TBOUTH/CAOUT/A15/CA6
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
PxIFG.y
PxSEL.y
PxIES.y
EN
Q
Set
Interrupt
Edge
Select
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To Comparator
From Comparator
CAPD.y
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Module
1
Direction
0: Input
1: Output
2
From Module
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
3
2
0
1
1
Bus
Keeper
EN
P4.7/TB0CLK/CAOUT/CA7
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
Set
Interrupt
Edge
Select
PxIES.y
62
EN
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SLAS800 – MARCH 2013
Table 23. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME
(P4.x)
CONTROL BITS / SIGNALS (1)
x
FUNCTION
P4DIR.x
P4SEL.x
P4SEL2.x
ADC10AE.y
INCH.y=1
CAPD.y
P4.0/
P4.x (I/O)
I: 0; O: 1
0
0
n/a
0
TB0.0/
Timer0_B3.CCI0A
0
1
0
n/a
0
Timer0_B3.TA0
1
1
0
n/a
0
CA0/
CA0
X
X
X
n/a
1 (y = 0)
Pin Osc
Capacitive sensing
X
0
1
n/a
0
P4.1/
P4.x (I/O)
I: 0; O: 1
0
0
n/a
0
Timer0_B3.CCI1A
0
1
0
n/a
0
Timer0_B3.TA1
1
1
0
n/a
0
CA1/
CA1
X
X
X
n/a
1 (y = 1)
Pin Osc
Capacitive sensing
X
0
1
n/a
0
P4.2/
P4.x (I/O)
I: 0; O: 1
0
0
n/a
0
TB0.2/
Timer0_B3.CCI2A
0
1
0
n/a
0
Timer0_B3.TA2
1
1
0
n/a
0
CA2/
CA2
X
X
X
n/a
1 (y = 2)
Pin Osc
Capacitive sensing
X
0
1
n/a
0
P4.3/
P4.x (I/O)
I: 0; O: 1
0
0
0
0
TB0.0/
Timer0_B3.CCI0A
0
1
0
0
0
Timer0_B3.TA0
1
1
0
0
0
A12
X
X
X
1 (y =12)
0
CA3/
CA3
X
X
X
0
1 (y = 3)
Pin Osc
Capacitive sensing
P4.4/
P4.x (I/O)
TB0.1/
Timer0_B3.CCI1A
0
TB0.1/
1
2
A12/
3
X
0
1
0
0
I: 0; O: 1
0
0
0
0
0
1
0
0
0
0
Timer0_B3.TA1
1
1
0
0
A13
X
X
X
1 (y = 13)
0
CA4/
CA4
X
X
X
0
1 (y = 4)
Pin Osc
Capacitive sensing
P4.5/
P4.x (I/O)
TB0.2/
A13/
4
X
0
1
0
0
I: 0; O: 1
0
0
0
0
Timer0_B3.TB2
1
1
0
0
0
A14
X
X
X
1 (y = 14)
0
CA5/
CA5
X
X
X
0
1 (y = 5)
Pin Osc
Capacitive sensing
X
0
1
0
0
P4.6/
P4.x (I/O)
I: 0; O: 1
0
0
0
0
TB0OUTH/
TBOUTH
0
1
0
0
0
CAOUT/
CAOUT
1
1
0
0
0
A15
X
X
X
1 (y = 15)
0
CA6/
CA6
X
X
X
0
1 (y = 6)
Pin Osc
Capacitive sensing
X
0
1
0
0
P4.7/
P4.x (I/O)
I: 0; O: 1
0
0
n/a
0
TB0CLK/
Timer0_B3.TBCLK
0
1
0
n/a
0
A14/
A15/
CAOUT/
5
6
CAOUT
1
1
0
n/a
0
CA7/
CA7
X
X
X
n/a
1 (y = 7)
Pin Osc
Capacitive sensing
X
0
1
n/a
0
(1)
7
X = don't care
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Jun-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
MSP430G2755IDA38
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
G2755
MSP430G2755IDA38R
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
G2755
MSP430G2755IRHA40R
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
G2755
MSP430G2755IRHA40T
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
G2755
MSP430G2855IDA38
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
G2855
MSP430G2855IDA38R
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
G2855
MSP430G2855IRHA40R
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
G2855
MSP430G2855IRHA40T
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
G2855
MSP430G2955IDA38
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
G2955
MSP430G2955IDA38R
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
G2955
MSP430G2955IRHA40R
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
G2955
MSP430G2955IRHA40T
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
G2955
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jun-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
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of the previous line and the two combined represent the entire Device Marking for that device.
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Addendum-Page 2
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