LM5111 www.ti.com SNVS300F – JULY 2004 – REVISED MAY 2011 LM5111 Dual 5A Compound Gate Driver Check for Samples: LM5111 FEATURES DESCRIPTION • The LM5111 Dual Gate Driver replaces industry standard gate drivers with improved peak output current and efficiency. Each “compound” output driver stage includes MOS and bipolar transistors operating in parallel that together sink more than 5A peak from capacitive loads. Combining the unique characteristics of MOS and bipolar devices reduces drive current variation with voltage and temperature. Under-voltage lockout protection is also provided. The drivers can be operated in parallel with inputs and outputs connected to double the drive current capability. This device is available in the SOIC package or the thermally enhanced VSSOP package. 1 2 • • • • • • • • • • Independently Drives Two N-Channel MOSFETs Compound CMOS and Bipolar Outputs Reduce Output Current Variation 5A Sink/3A Source Current Capability Two Channels can be Connected in Parallel to Double the Drive Current Independent Inputs (TTL Compatible) Fast Propagation Times (25 ns Typical) Fast Rise and Fall Times (14 ns/12 ns Rise/Fall with 2 nF Load) Available in Dual Non-Inverting, Dual Inverting and Combination Configurations Supply Rail Under-Voltage Lockout Protection (UVLO) LM5111-4 UVLO Configured to Drive PFET through OUT_A and NFET through OUT_B Pin Compatible with Industry Standard Gate Drivers TYPICAL APPLICATIONS • • • Synchronous Rectifier Gate Drivers Switch-mode Power Supply Gate Driver Solenoid and Motor Drivers PACKAGES • • SOIC Thermally Enhanced VSSOP CONNECTION DIAGRAM NC IN_A VEE IN_B 1 8 2 7 3 6 4 5 NC OUT A VCC OUT_B Figure 1. 8-Lead SOIC or VSSOP See D or DGN0008A Package 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2011, Texas Instruments Incorporated LM5111 SNVS300F – JULY 2004 – REVISED MAY 2011 www.ti.com PIN DESCRIPTIONS Pin Name Description Application Information 1 NC No Connect 2 IN_A ‘A’ side control input TTL compatible thresholds. 3 VEE Ground reference for both inputs and outputs Connect to power ground. 4 IN_B ‘B’ side control input TTL compatible thresholds. 5 OUT_B Output for the ‘B’ side driver. Voltage swing of this output is from VCC to VEE. The output stage is capable of sourcing 3A and sinking 5A. 6 VCC Positive output supply Locally decouple to VEE. 7 OUT_A. Output for the ‘A’ side driver. Voltage swing of this output is from VCC to VEE. The output stage is capable of sourcing 3A and sinking 5A. 8 NC No Connect EP (VSSOP Package) It is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PC board to aid thermal dissipation. Configuration Table Part Number “A” Output Configuration “B” Output Configuration Package LM5111-1M/-1MX/-1MY/-1MYX Non-Inverting (Low in UVLO) Non-Inverting (Low in UVLO) SOIC, VSSOP LM5111-2M/-2MX/-2MY/-2MYX Inverting (Low in UVLO) Inverting (Low in UVLO) SOIC, VSSOP LM5111-3M/-3MX/-3MY/-3MYX Inverting (Low in UVLO) Non-Inverting (Low in UVLO) SOIC, VSSOP LM5111-4M/-4MX/-4MY/-4MYX Inverting (High in UVLO) Non-Inverting (Low in UVLO) SOIC, VSSOP These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to 15V VCC to VEE −0.3V to 15V IN to VEE −55°C to +150°C Storage Temperature Range, (TSTG) Maximum Junction Temperature, (TJ(max)) +150°C Operating Junction Temperature +125°C ESD Rating (1) (2) 2 2kV Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300F – JULY 2004 – REVISED MAY 2011 Electrical Characteristics TJ = −40°C to +125°C, VCC = 12V, VEE = 0V, No Load on OUT_A or OUT_B, unless otherwise specified. Symbol Parameter Conditions Min VCC−VEE 3.5 VCCR VCC Under Voltage Lockout (rising) VCC−VEE 2.3 VCCH VCC Under Voltage Lockout Hysteresis VCC Operating Range ICC VCC Supply Current (ICC) Typ Max Units 14 V 2.9 3.5 V 230 mV IN_A = IN_B = 0V (5111-1) 1 2 IN_A = IN_B = VCC (5111-2) 1 2 IN_A = VCC, IN_B = 0V (5111-3) 1 2 mA CONTROL INPUTS VIH Logic High VIL Logic Low VthH High Threshold 1.3 VthL Low Threshold 0.8 HYS Input Hysteresis IIL Input Current Low IIH Input Current High 2.2 V 0.8 V 1.75 2.2 V 1.35 2.0 V 400 IN_A=IN_B=VCC (5111-1-2-3) −1 mV 0.1 1 25 IN_B=VCC (5111-3) 10 18 IN_A=IN_B=VCC (5111-2) −1 0.1 1 IN_A=IN_B=VCC (5111-1) 10 18 25 IN_A=VCC (5111-3) -1 0.1 1 µA OUTPUT DRIVERS ROH Output Resistance High IOUT = −10 mA (1) 30 50 Ω ROL Output Resistance Low IOUT = + 10 mA (1) 1.4 2.5 Ω ISource Peak Source Current OUTA/OUTB = VCC/2, 200 ns Pulsed Current 3 A ISink Peak Sink Current OUTA/OUTB = VCC/2, 200 ns Pulsed Current 5 A SWITCHING CHARACTERISTICS td1 Propagation Delay Time Low to High, IN rising (IN to OUT) CLOAD = 2 nF See Figure 2 and Figure 3 25 40 ns td2 Propagation Delay Time High to Low, IN falling (IN to OUT) CLOAD = 2 nF See Figure 2 and Figure 3 25 40 ns tr Rise Time CLOAD = 2 nF See Figure 2 and Figure 3 14 25 ns tf Fall Time CLOAD = 2 nF See Figure 2 and Figure 3 12 25 ns TJ = 150°C 500 mA LATCHUP PROTECTION AEC - Q100, Method 004 THERMAL RESISTANCE θJA Junction to Ambient, 0 LFPM Air Flow SOIC Package VSSOP Package 170 60 °C/W θJC Junction to Case SOIC Package VSSOP Package 70 4.7 °C/W (1) The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and Bipolar devices. Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM5111 3 LM5111 SNVS300F – JULY 2004 – REVISED MAY 2011 www.ti.com Timing Waveforms INPUT INPUT OUTPUT 50% 50% 50% 50% tD1 tD2 tD1 tD2 90% 90% OUTPUT 10% 10% tf tr tr Figure 2. Inverting 4 tf Figure 3. Non-Inverting Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300F – JULY 2004 – REVISED MAY 2011 Typical Performance Characteristics Supply Current vs Frequency Supply Current vs Capacitive Load 1000 100 TA = 25°C 10 VCC = 12V SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) VCC = 15V VCC = 10V VCC = 5V 1 f = 500kHz 100 10 f = 100kHz 1 TA = 25°C f = 10kHz CL = 2200pF 0.1 100 0.1 1 10 100 1000 10k 1k CAPACITIVE LOAD (pF) FREQUENCY (kHz) Figure 4. Figure 5. Rise and Fall Time vs Supply Voltage Rise and Fall Time vs Temperature 20 20 TA = 25°C VCC = 12V CL = 2200pF CL = 2200pF 18 18 16 16 TIME (ns) TIME (ns) tr tr 14 14 tf tf 12 12 10 10 5 6 4 7 8 9 10 11 12 13 14 15 16 -75 -50 -25 0 25 50 75 100 125 150 175 SUPPLY VOLTAGE (V) TEMPERATURE (°C) Figure 6. Figure 7. Rise and Fall Time vs Capacitive Load Delay Time vs Supply Voltage 32.5 50 TA = 25°C TA = 25°C VCC = 12V CL = 2200pF 30 40 tr 20 tD2 TIME (ns) TIME (ns) 27.5 30 tf 25 22.5 tD1 10 20 17.5 0 100 1k CAPACITIVE LOAD (pF) 10k 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V) Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM5111 5 LM5111 SNVS300F – JULY 2004 – REVISED MAY 2011 www.ti.com Typical Performance Characteristics (continued) Delay Time vs Temperature RDSON vs Supply Voltage 32.5 3.25 VCC = 12V CL = 2200pF IOUT = 10mA 2.75 tD2 ROH ROL (:) TIME (ns) 27.5 55 25 tD1 45 2.25 1.75 35 22.5 ROH (:) 30 65 TA = 25°C ROL 1.25 20 17.5 25 15 0.75 -75 -50 -25 0 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3 6 9 12 15 18 SUPPLY VOLTAGE (V) Figure 10. Figure 11. UVLO Thresholds and Hysteresis vs Temperature 0.450 VCCR 2.800 2.500 VCCF 0.390 0.330 2.200 0.270 VCCH 1.900 1.600 -75 -50 -25 0 HYSTERESIS (V) UVLO THRESHOLDS (V) 3.100 0.210 0.150 25 50 75 100 125 150 175 TEMPERATURE (°C) Figure 12. 6 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300F – JULY 2004 – REVISED MAY 2011 Block Diagram VCC UVLO VEE OUT_A IN_A VEE VCC IN_B OUT_B VEE Figure 13. Block Diagram of LM5111 Detailed Operating Description LM5111 dual gate driver consists of two independent and identical driver channels with TTL compatible logic inputs and high current totem-pole outputs that source or sink current to drive MOSFET gates. The driver output consist of a compound structure with MOS and bipolar transistor operating in parallel to optimize current capability over a wide output voltage and operating temperature range. The bipolar device provides high peak current at the critical threshold region of the MOSFET VGS while the MOS devices provide rail-to-rail output swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power ground potential at the VEE pin. The control inputs of the drivers are high impedance CMOS buffers with TTL compatible threshold voltages. The LM5111 pinout was designed for compatibility with industry standard gate drivers in single supply gate driver applications. The input stage of each driver should be driven by a signal with a short rise and fall time. Slow rising and falling input signals, although not harmful to the driver, may result in the output switching repeatedly at a high frequency. The two driver channels of the LM5111 are designed as identical cells. Transistor matching inherent to integrated circuit manufacturing ensures that the AC and DC peformance of the channels are nearly identical. Closely matched propagation delays allow the dual driver to be operated as a single with inputs and output pins connected. The drive current capability in parallel operation is precisely 2X the drive of an individual channel. Small differences in switching speed between the driver channels will produce a transient current (shoot-through) in the output stage when two output pins are connected to drive a single load. Differences in input thresholds Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM5111 7 LM5111 SNVS300F – JULY 2004 – REVISED MAY 2011 www.ti.com between the driver channels will also produce a transient current (shoot-through) in the output stage. Fast transition input signals are especially important while operating in a parallel configuration. The efficiency loss for parallel operation has been characterized at various loads, supply voltages and operating frequencies. The power dissipation in the LM5111 increases be less than 1% relative to the dual driver configuration when operated as a single driver with inputs/ outputs connected. An Under Voltage Lock Out (UVLO) circuit is included in the LM5111, which senses the voltage difference between VCC and the chip ground pin, VEE. When the VCC to VEE voltage difference falls below 2.8V both driver channels are disabled. The UVLO hysteresis prevents chattering during brown-out conditions and the driver will resume normal operation when the VCC to VEE differential voltage exceeds approximately 3.0V. The LM5111-1, -2 and -3 devices hold both outputs in the low state in the under-voltage lockout (UVLO) condition. The LM5111-4 is distinguished from the LM5111-3 by the active high output state of OUT_A during UVLO. When VCC is less than the UVLO threshold voltage, OUT_A of the LM5111-4 will be locked in the high state while OUT_B will be disabled in the low state. This configuration allows the LM5111-4 to drive a PFET through OUT_A and an NFET through OUT_B with both FETs safely turned off during UVLO. The LM5111 is available in dual non-inverting (-1), dual Inverting (-2) and the combination inverting plus noninverting (-3, -4) configurations. All configurations are offered in the SOIC and VSSOP plastic packages. Layout Considerations Attention must be given to board layout when using LM5111. Some important considerations include: 1. A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support high peak currents being drawn from VCC during turn-on of the MOSFET. 2. Proper grounding is crucial. The drivers need a very low impedance path for current return to ground avoiding inductive loops. The two paths for returning current to ground are a) between LM5111 VEE pin and the ground of the circuit that controls the driver inputs, b) between LM5111 VEE pin and the source of the power MOSFET being driven. All these paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. All these ground paths should be kept distinctly separate to avoid coupling between the high current output paths and the logic signals that drive the LM5111. A good method is to dedicate one copper plane in a multi-layered PCB to provide a common ground surface. 3. With the rise and fall times in the range of 10 ns to 30 ns, care is required to minimize the lengths of current carrying conductors to reduce their inductance and EMI from the high di/dt transients generated by the LM5111. 4. The LM5111 footprint is compatible with other industry standard drivers including the TC4426/27/28 and UCC27323/4/5. 5. If either channel is not being used, the respective input pin (IN_A or IN_B) should be connected to either VEE or VCC to avoid spurious output signals. 8 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM5111 LM5111 www.ti.com SNVS300F – JULY 2004 – REVISED MAY 2011 Thermal Performance INTRODUCTION The primary goal of thermal management is to maintain the integrated circuit (IC) junction temperature (TJ) below a specified maximum operating temperature to ensure reliability. It is essential to estimate the maximum TJ of IC components in worst case operating conditions. The junction temperature is estimated based on the power dissipated in the IC and the junction to ambient thermal resistance θJA for the IC package in the application board and environment. The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment. DRIVE POWER REQUIREMENT CALCULATIONS IN LM5111 The LM5111 dual low side MOSFET driver is capable of sourcing/sinking 3A/5A peak currents for short intervals to drive a MOSFET without exceeding package power dissipation limits. High peak currents are required to switch the MOSFET gate very quickly for operation at high frequencies. VGATE VHIGH Q1 RG VTRIG CIN Q2 The schematic above shows a conceptual diagram of the LM5111 output and MOSFET load. Q1 and Q2 are the switches within the gate driver. RG is the gate resistance of the external MOSFET, and CIN is the equivalent gate capacitance of the MOSFET. The gate resistance Rg is usually very small and losses in it can be neglected. The equivalent gate capacitance is a difficult parameter to measure since it is the combination of CGS (gate to source capacitance) and CGD (gate to drain capacitance). Both of these MOSFET capacitances are not constants and vary with the gate and drain voltage. The better way of quantifying gate capacitance is the total gate charge QG in coloumbs. QG combines the charge required by CGS and CGD for a given gate drive voltage VGATE. Assuming negligible gate resistance, the total power dissipated in the MOSFET driver due to gate charge is approximated by PDRIVER = VGATE x QG x FSW where • FSW = switching frequency of the MOSFET (1) For example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for VGATE = 12V. The power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching frequency of 300 kHz and VGATE of 12V is equal to PDRIVER = 12V x 30 nC x 300 kHz = 0.108W. (2) If both channels of the LM5111 are operating at equal frequency with equivalent loads, the total losses will be twice as this value which is 0.216W. In addition to the above gate charge power dissipation, - transient power is dissipated in the driver during output transitions. When either output of the LM5111 changes state, current will flow from VCC to VEE for a very brief interval of time through the output totem-pole N and P channel MOSFETs. The final component of power dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input stage and Under-voltage lockout sections. Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM5111 9 LM5111 SNVS300F – JULY 2004 – REVISED MAY 2011 www.ti.com Characterization of the LM5111 provides accurate estimates of the transient and quiescent power dissipation components. At 300 kHz switching frequency and 30 nC load used in the example, the transient power will be 8 mW. The 1 mA nominal quiescent current and 12V VGATE supply produce a 12 mW typical quiescent power. Therefore the total power dissipation PD = 0.216 + 0.008 + 0.012 = 0.236W. (3) We know that the junction temperature is given by TJ = PD x θJA + TA (4) Or the rise in temperature is given by TRISE = TJ − TA = PD x θJA (5) For SOIC package, θJA is estimated as 170°C/W for the conditions of natural convection. For VSSOP, θJA is typically 60°C/W. Therefore for SOIC TRISE is equal to TRISE = 0.236 x 170 = 40.1°C (6) CONTINUOUS CURRENT RATING OF LM5111 The LM5111 can deliver pulsed source/sink currents of 3A and 5A to capacitive loads. In applications requiring continuous load current (resistive or inductive loads), package power dissipation, limits the LM5111 current capability far below the 5A sink/3A source capability. Rated continuous current can be estimated both when sourcing current to or sinking current from the load. For example when sinking, the maximum sink current can be calculated as: ISINK (MAX) := TJ(MAX) - TA TJA · RDS (ON) where • RDS(on) is the on resistance of lower MOSFET in the output stage of LM5111 (7) Consider TJ(max) of 125°C and θJA of 170°C/W for an SO-8 package under the condition of natural convection and no air flow. If the ambient temperature (TA) is 60°C, and the RDS(on) of the LM5111 output at TJ(max) is 2.5Ω, this equation yields ISINK(max) of 391mA which is much smaller than 5A peak pulsed currents. Similarly, the maximum continuous source current can be calculated as TJ(MAX) - TA ISOURCE (MAX) := TJA · VDIODE where • VDIODE is the voltage drop across hybrid output stage which varies over temperature and can be assumed to be about 1.1V at TJ(max) of 125°C (8) Assuming the same parameters as above, this equation yields ISOURCE(max) of 347mA. 10 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM5111 PACKAGE OPTION ADDENDUM www.ti.com 9-Mar-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM5111-1M ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 5111 -1M LM5111-1M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5111 -1M LM5111-1MX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 5111 -1M LM5111-1MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5111 -1M LM5111-1MY ACTIVE MSOPPowerPAD DGN 8 1000 TBD Call TI Call TI SJKB LM5111-1MY/NOPB ACTIVE MSOPPowerPAD DGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SJKB LM5111-1MYX ACTIVE MSOPPowerPAD DGN 8 3500 TBD Call TI Call TI SJKB LM5111-1MYX/NOPB ACTIVE MSOPPowerPAD DGN 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SJKB LM5111-2M ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 5111 -2M LM5111-2M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5111 -2M LM5111-2MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5111 -2M LM5111-2MY ACTIVE MSOPPowerPAD DGN 8 1000 TBD Call TI Call TI SJLB LM5111-2MY/NOPB ACTIVE MSOPPowerPAD DGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SJLB LM5111-2MYX ACTIVE MSOPPowerPAD DGN 8 3500 TBD Call TI Call TI SJLB LM5111-2MYX/NOPB ACTIVE MSOPPowerPAD DGN 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SJLB LM5111-3M ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 5111 -3M LM5111-3M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5111 -3M Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Mar-2013 Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM5111-3MX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 5111 -3M LM5111-3MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5111 -3M LM5111-3MY ACTIVE MSOPPowerPAD DGN 8 1000 TBD Call TI Call TI SJNB LM5111-3MY/NOPB ACTIVE MSOPPowerPAD DGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SJNB LM5111-3MYX ACTIVE MSOPPowerPAD DGN 8 3500 TBD Call TI Call TI SJNB LM5111-3MYX/NOPB ACTIVE MSOPPowerPAD DGN 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SJNB LM5111-4M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 5111 -4M LM5111-4MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 5111 -4M LM5111-4MY/NOPB ACTIVE MSOPPowerPAD DGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SSYB LM5111-4MYX/NOPB ACTIVE MSOPPowerPAD DGN 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SSYB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Mar-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. 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Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM5111-1MX Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5111-1MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5111-1MY MSOPPower PAD DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-1MY/NOPB MSOPPower PAD DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-1MYX MSOPPower PAD DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-1MYX/NOPB MSOPPower PAD DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-2MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5111-2MY MSOPPower PAD DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-2MY/NOPB MSOPPower PAD DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-2MYX MSOP- DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant Power PAD LM5111-2MYX/NOPB MSOPPower PAD DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-3MX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5111-3MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5111-3MY MSOPPower PAD DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-3MY/NOPB MSOPPower PAD DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-3MYX MSOPPower PAD DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-3MYX/NOPB MSOPPower PAD DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-4MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5111-4MY/NOPB MSOPPower PAD DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5111-4MYX/NOPB MSOPPower PAD DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5111-1MX SOIC D 8 2500 349.0 337.0 45.0 LM5111-1MX/NOPB SOIC D 8 2500 349.0 337.0 45.0 LM5111-1MY MSOP-PowerPAD DGN 8 1000 203.0 190.0 41.0 LM5111-1MY/NOPB MSOP-PowerPAD DGN 8 1000 203.0 190.0 41.0 LM5111-1MYX MSOP-PowerPAD DGN 8 3500 349.0 337.0 45.0 LM5111-1MYX/NOPB MSOP-PowerPAD DGN 8 3500 349.0 337.0 45.0 LM5111-2MX/NOPB SOIC D 8 2500 349.0 337.0 45.0 LM5111-2MY MSOP-PowerPAD DGN 8 1000 203.0 190.0 41.0 LM5111-2MY/NOPB MSOP-PowerPAD DGN 8 1000 203.0 190.0 41.0 LM5111-2MYX MSOP-PowerPAD DGN 8 3500 349.0 337.0 45.0 LM5111-2MYX/NOPB MSOP-PowerPAD DGN 8 3500 349.0 337.0 45.0 LM5111-3MX SOIC D 8 2500 349.0 337.0 45.0 LM5111-3MX/NOPB SOIC D 8 2500 349.0 337.0 45.0 LM5111-3MY MSOP-PowerPAD DGN 8 1000 203.0 190.0 41.0 LM5111-3MY/NOPB MSOP-PowerPAD DGN 8 1000 203.0 190.0 41.0 LM5111-3MYX MSOP-PowerPAD DGN 8 3500 349.0 337.0 45.0 LM5111-3MYX/NOPB MSOP-PowerPAD DGN 8 3500 349.0 337.0 45.0 LM5111-4MX/NOPB SOIC D 8 2500 349.0 337.0 45.0 LM5111-4MY/NOPB MSOP-PowerPAD DGN 8 1000 203.0 190.0 41.0 LM5111-4MYX/NOPB MSOP-PowerPAD DGN 8 3500 349.0 337.0 45.0 Pack Materials-Page 3 MECHANICAL DATA DGN0008A MUY08A (Rev A) BOTTOM VIEW www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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