HEF4053B Triple single-pole double-throw analog switch Rev. 10 — 17 November 2011 Product data sheet 1. General description The HEF4053B is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. Each switch has a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all switches into the high-impedance OFF-state, independent of Sn. VDD and VSS are the supply voltage connections for the digital control inputs (Sn and E). The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (nY0, nY1 and nZ) can swing between VDD as a positive limit and VEE as a negative limit. VDD VEE may not exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches. 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 4. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4053BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4053BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4053BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch 5. Functional diagram E 6 VDD 16 13 1Y1 S1 11 LOGIC LEVEL CONVERSION DECODER 12 1Y0 14 1Z 1 2Y1 S2 10 11 S1 1Y0 12 10 S2 1Y1 13 9 S3 1Z 14 LOGIC LEVEL CONVERSION 2 2Y0 15 2Z 3 3Y1 2Y0 2 2Y1 1 2Z S3 9 15 3Y0 5 3Y1 3 3Z 4 LOGIC LEVEL CONVERSION 5 3Y0 4 3Z 6 E 8 VSS 001aae125 Fig 1. Logic symbol Fig 2. 7 VEE 001aae124 Functional diagram nZ nY1 Sn LEVEL CONVERTER nY0 E LEVEL CONVERTER to other multiplexers/demultiplexers 001aae645 Fig 3. Logic diagram (one multiplexer/demultiplexer) HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch nYn VDD VEE from decoder and enable logic Fig 4. VDD nZ 001aae644 Schematic diagram (one switch) 6. Pinning information 6.1 Pinning HEF4053B 2Y1 1 16 VDD 2Y0 2 15 2Z 3Y1 3 14 1Z 3Z 4 13 1Y1 3Y0 E VEE VSS HEF4053B 12 1Y0 5 11 S1 6 2Y1 1 16 VDD 2Y0 2 15 2Z 3Y1 3 14 1Z 3Z 4 13 1Y1 3Y0 5 12 1Y0 E 6 11 S1 VEE 7 10 S2 VSS 8 10 S2 7 9 8 S3 001aae643 Fig 5. 9 S3 001aaj899 Pin configuration for SOT38-4 (DIP16) and SOT109-1 (SO16) Fig 6. Pin configuration for SOT403-1 (TSSOP16) 6.2 Pin description Table 2. Pin description Symbol Pin Description E 6 enable input (active LOW) VEE 7 supply voltage VSS 8 ground supply voltage S1, S2, S3 11, 10, 9 select input 1Y0, 2Y0, 3Y0 12, 2, 5 independent input or output 1Y1, 2Y1, 3Y1 13, 1, 3 independent input or output 1Z, 2Z, 3Z 14, 15, 4 independent output or input VDD 16 supply voltage HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch 7. Functional description Table 3. Function table [1] Inputs Channel on E Sn L L nY0 to nZ L H nY1 to nZ H X switches OFF [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage Conditions [1] Min Max Unit 0.5 +18 V 18 +0.5 V - 10 mA VEE supply voltage referenced to VDD IIK input clamping current pins Sn and E; VI < 0.5 V or VI > VDD + 0.5 V VI input voltage 0.5 VDD + 0.5 V II/O input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C DIP16 package - 750 mW SO16 package - 500 mW TSSOP16 package - 500 mW - 100 mW total power dissipation Ptot P [1] [2] power dissipation Tamb = 40 C to +125 C [2] per output To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE. For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage see Figure 7 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature 40 - +125 C HEF4053B Product data sheet in free air All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch Table 5. Recommended operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V 001aae646 15 VDD − VSS (V) 10 operating area 5 0 0 Fig 7. 5 10 VDD − VEE (V) 15 Operating area as a function of the supply voltages 10. Static characteristics Table 6. Static characteristics VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL HIGH-level input voltage LOW-level input voltage II input leakage current IS(OFF) OFF-state leakage current HEF4053B Product data sheet Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit Conditions VDD Min Max Min Max Min Max Min Max IO < 1 A 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V IO < 1 A 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 15 V - 0.1 - 0.1 - 1.0 - 1.0 A Z port; 15 V all channels OFF; see Figure 8 - - - 1000 - - - - nA Y port; per channel; see Figure 9 - - - 200 - - - - nA 15 V All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch Table 6. Static characteristics …continued VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter IDD CI Conditions Tamb = 85 C Tamb = 125 C Unit Min Max Min Max Min Max Min Max 5V - 5 - 5 - 150 - 150 A 10 V - 10 - 10 - 300 - 300 A 15 V - 20 - 20 - 600 - 600 A - - - - 7.5 - - - - pF supply current IO = 0 A input capacitance Tamb = 40 C Tamb = 25 C VDD Sn, E inputs 10.1 Test circuits VDD VDD or VSS IS S1 to S3 nY0 1 nZ nY1 2 switch E VSS = VEE VDD VI VO 001aaj900 Fig 8. Test circuit for measuring OFF-state leakage current Z port VDD VDD or VSS S1 to S3 nY0 1 nZ nY1 2 switch IS E VSS = VEE VSS VO VI 001aaj901 Fig 9. Test circuit for measuring OFF-state leakage current nYn port 10.2 ON resistance Table 7. ON resistance Tamb = 25 C; ISW = 200 A; VSS = VEE = 0 V. Symbol Parameter Conditions VDD VEE Typ Max Unit RON(peak) ON resistance (peak) VI = 0 V to VDD VEE; see Figure 10 and Figure 11 5V 350 2500 10 V 80 245 15 V 60 175 HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch Table 7. ON resistance …continued Tamb = 25 C; ISW = 200 A; VSS = VEE = 0 V. Symbol Parameter Conditions VDD VEE Typ Max Unit RON(rail) ON resistance (rail) VI = 0 V; see Figure 10 and Figure 11 5V 115 340 10 V 50 160 15 V 40 115 5V 120 365 10 V 65 200 15 V 50 155 VI = VDD VEE; see Figure 10 and Figure 11 RON VI = 0 V to VDD VEE; see Figure 10 ON resistance mismatch between channels 5V 25 - 10 V 10 - 15 V 5 - 10.2.1 ON resistance waveform and test circuit V VSW VDD VDD or VSS S1 to S3 nY0 1 nZ nY1 2 switch E VSS = VEE VSS ISW VI 001aaj902 RON = VSW / ISW. Fig 10. Test circuit for measuring RON 001aae648 400 RON (Ω) VDD = 5 V 300 200 10 V 100 15 V 0 0 5 10 15 VI (V) Fig 11. Typical RON as a function of input voltage HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch 11. Dynamic characteristics Table 8. Dynamic characteristics Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 15. Symbol Parameter Conditions tPHL HIGH to LOW propagation delay nYn, nZ to nZ, nYn; see Figure 12 Sn to nYn, nZ; see Figure 13 LOW to HIGH propagation delay nYn, nZ to nZ, nYn; see Figure 12 tPLH Sn to nYn, nZ; see Figure 13 HIGH to OFF-state propagation delay tPHZ tPZH tPLZ OFF-state to HIGH propagation delay E to nYn, nZ; see Figure 14 LOW to OFF-state propagation delay E to nYn, nZ; see Figure 14 OFF-state to LOW propagation delay tPZL E to nYn, nZ; see Figure 14 E to nYn, nZ; see Figure 14 VDD Typ Max Unit 5V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns 5V 200 400 ns 10 V 85 170 ns 15 V 65 130 ns 5V 15 30 ns 10 V 5 10 ns 15 V 5 10 ns 5V 275 555 ns 10 V 100 200 ns 15 V 65 130 ns 5V 200 400 ns 10 V 115 230 ns 15 V 110 220 ns 5V 260 525 ns 10 V 95 190 ns 15 V 65 130 ns 5V 200 400 ns 10 V 120 245 ns 15 V 110 215 ns 5V 280 565 ns 10 V 105 205 ns 15 V 70 140 ns 11.1 Waveforms and test circuit VDD nYn or nZ input VM VDD Sn input VEE tPLH tPHL tPLH VO nZ or nYn output VM VSS tPHL VO 90 % nYn or nZ output VM 10 % VEE VEE switch OFF switch ON Measurement points are given in Table 9. Measurement points are given in Table 9. Fig 12. nYn, nZ to nZ, nYn propagation delays HEF4053B Product data sheet switch OFF 001aac291 001aac290 Fig 13. Sn to nYn, nZ propagation delays All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch VDD E input VM VSS tPLZ nYn or nZ output LOW-to-OFF OFF-to-LOW tPZL VO 90 % 10 % VEE tPHZ VO tPZH 90 % nYn or nZ output HIGH-to-OFF OFF-to-HIGH 10 % VEE switch ON switch OFF switch ON 001aac292 Measurement points are given in Table 9. Fig 14. Enable and disable times Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch tW VI negative pulse 0V 90 % VM 10 % tf tr tr tf VI positive pulse 0V VM 10 % 90 % VM VM tW VDD VDD VI PULSE GENERATOR VI VO RL S1 open DUT RT CL VSS VEE 001aaj903 Test data is given in Table 10. Definitions: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including test jig and probe. RL = Load resistance. Fig 15. Test circuit for measuring switching times Table 10. Test data Input nYn, nZ Load Sn and E tr, tf VDD or VEE VDD or VSS 20 ns [1] S1 position VM CL RL tPHL[1] 0.5VDD 50 pF 10 k VDD or VEE VEE tPLH tPZH, tPHZ tPZL, tPLZ other VEE VDD VEE For nYn to nZ or nZ to nYn propagation delays use VEE. For Sn to nYn or nZ propagation delays use VDD. HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch 11.2 Additional dynamic parameters Table 11. Additional dynamic characteristics VSS = VEE = 0 V; Tamb = 25 C. Symbol Parameter THD Conditions total harmonic distortion 3 dB frequency response f(3dB) VDD Typ Max Unit see Figure 16; RL = 10 k; CL = 15 pF; 5 V channel ON; VI = 0.5VDD (p-p); 10 V fi = 1 kHz 15 V [1] 0.25 - % [1] 0.04 - % [1] 0.04 - % see Figure 17; RL = 1 k; CL = 5 pF; channel ON; VI = 0.5VDD (p-p) 5V [1] 13 - MHz 10 V [1] 40 - MHz 70 - 50 15 V [1] iso isolation (OFF-state) see Figure 18; fi = 1 MHz; RL = 1 k; CL = 5 pF; channel OFF; VI = 0.5VDD (p-p) 10 V [1] Vct crosstalk voltage digital inputs to switch; see Figure 19; RL = 10 k; CL = 15 pF; E or Sn = VDD (square-wave) 10 V Xtalk crosstalk between switches; see Figure 20; fi = 1 MHz; RL = 1 k; VI = 0.5VDD (p-p) 10 V [1] 50 [1] MHz - dB - mV 50 - dB fi is biased at 0.5 VDD; VI = 0.5VDD (p-p). Table 12. Dynamic power dissipation PD PD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD Typical formula for PD (W) where: 5V PD = 2500 fi + (fo CL) VDD 10 V PD = 11500 fi + (fo CL) 15 V PD = 29000 fi + (fo CL) VDD2 2 fi = input frequency in MHz; VDD2 fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; (CL fo) = sum of the outputs. 11.2.1 Test circuits VDD VDD or VSS VDD S1 to S3 nY0 1 nZ nY1 2 VDD or VSS switch S1 to S3 nY0 1 nZ nY1 2 E E VSS = VEE VSS RL CL D RL CL dB fi 001aaj904 Fig 16. Test circuit for measuring total harmonic distortion Product data sheet VSS = VEE VSS fi HEF4053B switch 001aaj905 Fig 17. Test circuit for measuring frequency response All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch VDD VDD or VSS S1 to S3 nY0 1 nZ nY1 2 switch E VSS = VEE VSS RL CL dB fi 001aaj906 Fig 18. Test circuit for measuring isolation (OFF-state) 0.5VDD VDD RL S1 to S3 nY0 1 nZ nY1 2 switch E G VSS = VEE VDD or VSS RL CL V VO 001aaj907 a. Test circuit logic input (Sn, E) off on off Vct VO 001aaj908 b. Input and output pulse definitions Fig 19. Test circuit for measuring crosstalk voltage between digital inputs and switch HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch VDD VDD VDD or VSS S1 to S3 nY0 nZ nY1 VDD or VSS S1 to S3 nY0 nZ nY1 E E VSS = VEE VSS RL VO RL VSS = VEE VSS VI RL VI VO 001aaj909 a. Switch closed condition RL 001aaj910 b. Switch open condition Fig 20. Test circuit for measuring crosstalk between switches HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 21. Package outline SOT38-4 (DIP16) HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 22. Package outline SOT109-1 (SO16) HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 15 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 23. Package outline SOT403-1 (TSSOP16) HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 16 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch 13. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4053B v.10 20111117 Product data sheet - HEF4053B v.9 Modifications: • • Legal pages updated. Changes in “General description”, “Features and benefits” and “Applications”. HEF4053B v.9 20100325 Product data sheet - HEF4053B v.8 HEF4053B v.8 20100224 Product data sheet - HEF4053B v.7 HEF4053B v.7 20091127 Product data sheet - HEF4053B v.6 HEF4053B v.6 20090924 Product data sheet - HEF4053B v.5 HEF4053B v.5 20090825 Product data sheet - HEF4053B v.4 HEF4053B v.4 20090713 Product data sheet - HEF4053B_CNV v.3 HEF4053B_CNV v.3 19950101 Product specification - HEF4053B_CNV v.2 HEF4053B_CNV v.2 19950101 Product specification - - HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 17 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). 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Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Export might require a prior authorization from competent authorities. HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 18 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4053B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 19 of 20 HEF4053B NXP Semiconductors Triple single-pole double-throw analog switch 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.2.1 11 11.1 11.2 11.2.1 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance waveform and test circuit . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms and test circuit . . . . . . . . . . . . . . . . 8 Additional dynamic parameters . . . . . . . . . . . 11 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 17 November 2011 Document identifier: HEF4053B