Dallas DS83C520-ECL Eprom/rom high-speed micro Datasheet

PRELIMINARY
DS87C520/DS83C520
EPROM/ROM High-Speed Micro
www.maxim-ic.com
FEATURES
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PACKAGE OUTLINE
80C52-compatible
- 8051 pin and instruction set compatible
- Four 8-bit I/O ports
- Three 16-bit timer/counters
- 256 bytes scratchpad RAM
Large on-chip memory
- 16kB program memory
- 1kB extra on-chip SRAM for MOVX
ROMSIZE feature
- Selects internal ROM size from 0 to 16kB
- Allows access to entire external memory
map
- Dynamically adjustable by software
- Useful as boot block for external FLASH
High-speed architecture
- 4 clocks/machine cycle (8051 = 12)
- Runs DC to 33MHz clock rates
- Single-cycle instruction in 121ns
- Dual data pointer
- Optional variable length MOVX to access
fast/slow RAM/peripherals
Power Management Mode
- Programmable clock source to save power
- CPU runs from (crystal/64) or
(crystal/1024)
- Provides automatic hardware and software
exit
EMI Reduction Mode disables ALE
Two full-duplex hardware serial ports
High integration controller includes:
- Power-Fail Reset
- Early-Warning Power-Fail Interrupt
- Programmable Watchdog Timer
13 total interrupt sources with 6 external
Available in 40-pin PDIP, 44-pin PLCC,
44-pin TQFP, and 40-pin windowed CERDIP
Factory Mask DS83C520 or EPROM (OTP)
DS87C520
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, click here: http://www.maxim-ic.com/errata.
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070300
DS87C520/DS83C520
DESCRIPTION
The DS87C520/DS83C520 EPROM/ROM High-Speed Micro is a fast 8051-compatible microcontroller.
It features a redesigned processor core without wasted clock and memory cycles. As a result, it executes
every 8051 instruction between 1.5 and 3 times faster than the original for the same crystal speed.
Typical applications will see a speed improvement of 2.5 times using the same code and the same crystal.
The DS87C520/DS83C520 offers a maximum crystal speed of 33 MHz, resulting in apparent execution
speeds of 82.5 MHz (approximately 2.5X).
The DS87C520/DS83C520 is pin-compatible with all three packages of the standard 8051 and includes
standard resources such as three timer/counters, serial port, and four 8-bit I/O ports. It features 16 kB of
EPROM or Mask ROM with an extra 1 kB of data RAM. Both OTP and windowed packages are
available.
Besides greater speed, the microcontroller includes a second full hardware serial port, seven additional
interrupts, programmable Watchdog Timer, Brown-out Monitor, and Power-Fail Reset. The device also
provides dual data pointers (DPTRs) to speed block data memory moves. It also can adjust the speed of
MOVX data memory access from two to nine machine cycles for flexibility in selecting external memory
and peripherals.
A new Power Management Mode (PMM) is useful for portable applications. This feature allows software
to select a lower speed clock as the main time base. While normal operation has a machine cycle rate of 4
clocks per cycle, the PMM runs the processor at 64 or 1024 clocks per cycle. For example, at 12 MHz,
standard operation has a machine cycle rate of 3 MHz. In Power Management Mode, software can select
either 187.5 kHz or 11.7 kHz machine cycle rate. There is a corresponding reduction in power
consumption when the processor runs slower.
The EMI reduction feature allows software to select a reduced emission mode. This disables the ALE
signal when it is unneeded.
The DS83C520 is a factory Mask ROM version of the DS87C520 designed for high-volume, costsensitive applications. It is identical in all respects to the DS87C520, except that the 16 kB of EPROM is
replaced by a user-supplied application program. All references to features of the DS87C520 will apply to
the DS83C520, with the exception of EPROM-specific features where noted. Please contact your local
Dallas Semiconductor sales representative for ordering information.
ORDERING INFORMATION: DESCRIPTION
PART NUMBER
DS87C520-MCL
DS87C520-QCL
DS87C520-ECL
DS87C520-MNL
DS87C520-QNL
DS87C520-ENL
DS87C520-WCL
PACKAGE
40-pin plastic DIP
44-pin PLCC
44-pin TQFP
40-pin plastic DIP
44-pin PLCC
44-pin TQFP
40-pin windowed CERDIP
DS83C520-MCL
DS83C520-QCL
DS83C520-ECL
DS83C520-MNL
DS83C520-QNL
DS83C520-ENL
40-pin plastic DIP
44-pin PLCC
44-pin TQFP
40-pin plastic DIP
44-pin PLCC
44-pin TQFP
MAX. CLOCK SPEED
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
TEMPERATURE RANGE
0°C to 70°C
0°C to 70°C
0°C to 70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to 70°C
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
0°C to 70°C
0°C to 70°C
0°C to 70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
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DS87C520/DS83C520
DS87C530/DS83C520 BLOCK DIAGRAM Figure 1
PIN DESCRIPTION Table 1
DIP
PLCC
TQFP
SIGNAL
NAME
VCC
GND
40
20
9
44
22,23,
1
10
38
16, 17,
39
4
18
19
20
21
14
15
XTAL2
XTAL1
29
32
26
PSEN
RST
DESCRIPTION
VCC - +5V
GND - Digital circuit ground.
RST - input. The RST input pin contains a Schmitt
voltage input to recognize external active high Reset
inputs. The pin also employs an internal pulldown resistor
to allow for a combination of wired OR external Reset
sources. An RC is not required for power-up, as the
device provides this function internally.
XTAL1, XTAL2 - The crystal oscillator pins XTAL1 and
XTAL2 provide support for parallel resonant, AT cut
crystals. XTAL1 acts also as an input if there is an external
clock source in place of a crystal. XTAL2 serves as the
output of the crystal amplifier.
PSEN - Output. The Program Store Enable output. This
signal is commonly connected to optional external ROM
memory as a chip enable. PSEN will provide an active
low pulse and is driven high when external ROM is not
being accessed.
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DS87C520/DS83C520
DIP
PLCC
TQFP
30
33
27
SIGNAL
NAME
ALE
39
38
37
36
35
34
33
32
43
42
41
40
39
38
37
36
37
36
35
34
33
32
31
30
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
1-8
2-9
40-44
1-3
P1.0-P1.7
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
40
41
42
43
44
1
2
3
DESCRIPTION
ALE - Output. The Address Latch Enable output
functions as a clock to latch the external address LSB from
the multiplexed address/data bus on Port 0. This signal is
commonly connected to the latch enable of an external 373
family transparent latch. ALE has a pulse width of 1.5
XTAL1 cycles and a period of four XTAL1 cycles. ALE is
forced high when the DS87C520/DS83C520 is in a Reset
condition. ALE can also be disabled and forced high by
writing
ALEOFF=1
(PMR.2).
ALE
operates
independently of ALEOFF during external memory
accesses.
Port 0 (AD0-7) - I/O. Port 0 is an open-drain 8-bit bidirectional I/O port. As an alternate function Port 0 can
function as the multiplexed address/data bus to access offchip memory. During the time when ALE is high, the LSB
of a memo ry address is presented. When ALE falls to a
logic 0, the port transitions to a bi-directional data bus.
This bus is used to read external ROM and read/write
external RAM memory or peripherals. When used as a
memory bus, the port provides active high drivers. The
reset condition of Port 0 is tri-state. Pullup resistors are
required when using Port 0 as an I/O port.
Port 1 - I/O. Port 1 functions as both an 8-bit bidirectional I/O port and an alternate functional interface
for Timer 2 I/O, new External Interrupts, and new Serial
Port 1. The reset condition of Port 1 is with all bits at a
logic 1. In this state, a weak pullup holds the port high.
This condition also serves as an input state, a weak pullup
holds the port high. This condition also serves as an input
mode, since any external circuit that writes to the port will
overcome the weak pullup. When software writes a 0 to
any port pin, the DS87C520/DS83C520 will activate a
strong pulldown that remains on until either a 1 is written
or a reset occurs. Writing a 1 after the port has been at 0
will cause a strong transition driver to turn on, followed by
a weaker sustaining pullup. Once the momentary strong
driver turns off, the port again becomes the output high
(and input) state. The alternate modes of Port 1 are outlines as follows.
Port
P1.0
P1.1
Alternate
T2
T2EX
P1.2
P1.3
P1.4
RXD1
TXD1
INT2
P1.5
INT3
P1.6
INT4
P1.7
INT5
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Function
External I/O for Timer/Counter 2
EX Timer/Counter 2
Capture/Reload Trigger
Serial Port 1 Input
Serial Port 1 Output
External Interrupt 2 (Positive Edge
Detect)
External Interrupt 3 (Negative
Edge Detect)
External Interrupt 4 (Positive Edge
Detect)
External Interrupt 5 (Negative
Edge Detect)
DS87C520/DS83C520
DIP
PLCC
TQFP
21
22
23
24
25
26
27
28
24
25
26
27
28
29
30
31
18
19
20
21
22
23
24
25
SIGNAL
NAME
P2.0 (A8)
P2.1 (A9)
P2.2(A10)
P2.3(A11)
P2.4(A12)
P2.5(A13)
P2.6(A14)
P2.7(A15)
10-17
11,
13-19
5, 7-13
P3.0-P3.7
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
31
35
29
EA
-
12
34
6
28
NC
DESCRIPTION
Port 2 (A8-15) - I/O. Port 2 is a bi-directional I/O port.
The reset condition of Port 2 is logic high. In this state, a
weak pullup holds the port high. This condition also serves
as an input mode, since any external circuit that writes to
the port will overcome the weak pullup. When software
writes a 0 to any port pin, the DS87C520/DS83C520 will
activate a strong pulldown that remains on until either a 1
is written or a reset occurs. Writing a 1 after the port has
been at 0 will cause a strong transition driver to turn on,
followed by a weaker sustaining pullup. Once the
momentary strong driver turns off, the port again becomes
both the output high and input state. As an alternate
function Port 2 can function as MSB of the external
address bus. This bus can be used to read external ROM
and read/write external RAM memory or peripherals.
Port 3 - I/O. Port 3 functions as both an 8-bit bidirectional I/O port and an alternate functional interface
for External Interrupts, Serial Port 0, Timer 0 and 1 Inputs,
and RD and WR strobes. The reset condition of Port 3 is
with all bits at a logic 1. In this state, a weak pullup holds
the port high. This condition also serves as an input mode,
since any external circuit that writes to the port will
overcome the weak pullup. When software writes a 0 to
any port pin, the DS87C520/DS83C520 will activate a
strong pulldown that remains on until either a 1 is written
or a reset occurs. Writing a 1 after the port has been at 0
will cause a strong transition driver to turn on, followed by
a weaker sustaining pullup. Once the momentary strong
driver turns off, the port again becomes both the output
high and input state. The alternate modes of Port 3 are
outlined below.
Port
P3.0
P3.1
Alternate
RXD0
TXD0
Mode
Serial Port 0 Input
Serial Port 0 Output
P3.2
External Interrupt 0
P3.6
INT0
INT1
T0
T1
WR
P3.7
RD
External Data Memory Read Strobe
P3.3
P3.4
P3.5
External Interrupt 1
Timer 0 External Input
Timer 1 External Input
External Data Memory Write Strobe
EA - Input. Connect to ground to force the
DS87C520/DS83C520 to use an external ROM. The
internal RAM is still accessible as determined by register
settings. Connect EA to VCC to use internal ROM.
NC - Reserved. These pins should not be connected. They
are reserved for use with future devices in this family.
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DS87C520/DS83C520
COMPATIBILITY
The DS87C520/DS83C520 is a fully static CMOS 8051 compatible microcontroller designed for high
performance. In most cases the DS87C520/DS83C520 can drop into an existing socket for the 8xc51
family to improve the operation significantly. While remaining familiar to 8051 family users, it has many
new features. In general, software written for existing 8051 based systems works without modification
on the DS87C520/DS83C520. The exception is critical timing since the High-Speed Micro performs its
instructions much faster than the original for any given crystal selection. The DS87C520/DS83C520 runs
the standard 8051 family instruction set and is pin compatible with DIP, PLCC or TQFP packages.
The DS87C520/DS83C520 provides three 16-bit timer/ counters, full-duplex serial port (2), 256 bytes of
direct RAM plus 1 kB of extra MOVX RAM. I/O ports have the same operation as a standard 8051
product. Timers will default to a 12-clock per cycle operation to keep their timing compatible with
original 8051 family systems. However, timers are individually programmable to run at the new 4 clocks
per cycle if desired. The PCA is not supported.
The DS87C520/DS83C520 provides several new hardware features implemented by new Special
Function Registers. A summary of these SFRs is provided below.
PERFORMANCE OVERVIEW
The DS87C520/DS83C520 features a high-speed 8051 compatible core. Higher speed comes not just
from increasing the clock frequency, but from a newer, more efficient design.
This updated core does not have the dummy memory cycles that are present in a standard 8051. A
conventional 8051 generates machine cycles using the clock frequency divided by 12. In the
DS87C520/DS83C520, the same machine cycle takes 4 clocks. Thus the fastest instruction, 1 machine
cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions.
The majority of instructions on the DS87C520/DS83C520 will see the full 3 to 1 speed improvement.
Some instructions will get between 1.5 and 2.4 to 1 improvement. All instructions are faster than the
original 8051.
The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual instructions used. Speed-sensitive applications would make
the most use of instructions that are three times faster. However, the sheer number of 3 to 1 improved
opcodes makes dramatic speed improvements likely for any code. These architecture improvements
produce a peak instruction cycle in 121 ns (8.25 MIPs). The Dual Data Pointer feature also allows the
user to eliminate wasted instructions when moving blocks of memory.
INSTRUCTION SET SUMMARY
All instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and
other status functions is identical. However, the timing of each instruction is different. This applies both
in absolute and relative number of clocks.
For absolute timing of real-time events, the timing of software loops can be calculated using a table in the
High-Speed Microcontroller User’s Guide. However, counter/timers default to run at the older 12 clocks
per increment. In this way, timer-based events occur at the standard intervals with software executing at
higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor
operation.
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DS87C520/DS83C520
The relative time of two instructions might be different in the new architecture than it was previously. For
example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct”
instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of
time. In the DS87C520/DS83C520, the MOVX instruction takes as little as two machine cycles or eight
oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While
both are faster than their original counterparts, they now have different execution times. This is because
the DS87C520/DS83C520 usually uses one instruction cycle for each instruction byte. The user
concerned with precise program timing should examine the timing of each instruction for familiarity with
the changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle.
Many instructions require only one cycle, but some require five. In the original architecture, all were one
or two cycles except for MUL and DIV. Refer to the High-Speed Microcontroller User’s Guide for details
and individual instruction timing.
SPECIAL FUNCTION REGISTERS
Special Function Registers (SFRs) control most special features of the DS87C520/DS83C520. This
allows the DS87C520/DS83C520 to have many new features but use the same instruction set as the 8051.
When writing software to use a new feature, an equate statement defines the SFR to an assembler or
comp iler. This is the only change needed to access the new function. The DS87C520/DS83C520
duplicates the SFRs contained in the standard 80C52. Table 2 shows the register addresses and bit
locations. The High-Speed Microcontroller User’s Guide describes all SFRs.
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DS87C520/DS83C520
SPECIAL FUNCTION REGISTER LOCATIONS Table 2
* New functions are in bold
REGISTER
P0
SP
DPL
DPH
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
PORT1
EXIF
SCON0
SBUF0
P2
IE
SADDR0
SADDR1
P3
IP
SADEN0
SADEN 1
SCON1
SBUF1
ROMSIZE
PMR
STATUS
TA
T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TH2
PSW
WDCON
ACC
EIE
B
EIP
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADDRESS
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
0
SMOD_0
TF1
GATE
0
SMOD0
TR1
0
TR0
M0
0
GF1
IE1
GATE
0
GF0
IT1
C/ T
0
TF0
M1
C/ T
0
STOP
IE0
M1
SEL
IDLE
IT0
M0
WD1
P1.7
WD0
P1.6
T2M
P1.5
T1M
P1.4
T0M
P1.3
MD2
P1.2
MD1
P1.1
MD0
P1.0
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
90h
IE5
SM0/FE_0
IE4
SM1_0
IE3
SM2_0
IE
REN_0
XT/ RG
TB8_0
RGMD
RB8_0
RGSL
TI_0
BGS
RI_0
P2.7
EA
P2.6
ES1
P2.5
ET2
P2.4
ES0
P2.3
ET1
P2.2
EX1
P2.1
ET0
P2.0
EX0
P3.7
-
P3.6
PS1
P3.5
PT2
P3.4
PS0
P3.3
PT1
P3.2
PX1
P3.1
PT0
P3.0
PX0
SM0/FE_1
SB7
CD1
PIP
SM1_1
SB6
CD0
HIP
SM2_1
SB5
SWB
LIP
REN_1
SB4
XTUP
TB8_1
SB3
XTOFF
SPTA1
RB8_1
SB2
RMS2
ALEOFF
SPTA1
TI_1
SB1
RMS1
DME1
SPTA0
R1_1
SB0
RMS0
DME0
SPRA0
TF2
-
EXF2
-
RCLK
-
TCLK
-
EXEN2
-
TR2
-
C/ T2
T2OE
C/ RL2
DCEN
CY
SMOD_1
AC
POR
F0
EPFI
RS1
PFI
RS0
WDIF
OV
WTRF
FL
EWT
P
RWT
-
-
-
EWDI
EX5
EX4
EX3
EX2
-
-
-
PWDI
PX5
PX4
PX3
PX2
-
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91h
98h
99h
A0h
A8h
A9h
AAh
B0h
B8h
B9h
BAh
C0h
C1h
C2h
C4h
C5h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
D0h
D8h
E0h
E8h
F0h
F8h
DS87C520/DS83C520
MEMORY RESOURCES
Like the 8051, the DS87C520/DS83C520 uses three memory areas. The total memory configuration of
the DS87C520/DS83C520 is 16 kB of ROM, 1 kB of data SRAM and 256 bytes of scratchpad or direct
RAM. The 1 kB of data space SRAM is read/write accessible and is memory mapped. This on-chip
SRAM is reached by the MOVX instruction. It is not used for executable memory. The scratchpad area is
256 bytes of register mapped RAM and is identical to the RAM found on the 80C52. There is no conflict
or overlap among the 256 bytes and the 1 kB as they use different addressing modes and separate
instructions.
OPERATIONAL CONSIDERATION
The erasure window of the windowed CERDIP should be covered without regard to the
programmed/unprogrammed state of the EPROM. Otherwise, the device may not meet the AC and DC
parameters listed in the datasheet.
PROGRAM MEMORY ACCESS
On-chip ROM begins at address 0000h and is contiguous through 3FFFh (16 kB). Exceeding the
maximum address of on-chip ROM will cause the device to access off-chip memory. However, the
maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can
cause the DS87C520/DS83C520 to behave like a device with less on-chip memory. This is beneficial
when overlapping external memory, such as Flash, is used. The maximum memory size is dynamically
variable. Thus a portion of memory can be removed from the memory map to access off-chip memory,
then restored to access on-chip memory. In fact, all of the on-chip memory can be removed from the
memory map allowing the full 64 kB memory space to be addressed from off-chip memory. ROM
addresses that are larger than the selected maximum are automatically fetched from outside the part via
Ports 0 and 2. A depiction of the ROM memory map is shown in Figure 2.
The ROMSIZE register is used to select the maximum on-chip decoded address for ROM. Bits RMS2,
RMS1, RMS0 have the following affect.
RMS2
RMS1
RMS0
Maximum on-chip ROM Address
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 kB
1 kB/03FFh
2 kB/07FFh
4 kB/0FFFh
8 kB/1FFFh
16 kB (default)/3FFFh
Invalid - reserved
Invalid - reserved
The reset default condition is a maximum on-chip ROM address of 16 kB. Thus no action is required if
this feature is not used. When accessing external program memory, the first 16 kB would be inaccessible.
To select a smaller effective ROM size, software must alter bits RMS2-RMS0. Altering these bits
requires a Timed Access procedure as explained later.
Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For
example, assume that a DS87C520/DS83C520 is executing instructions from internal program memory
near the 12 kB boundary (~3000h) and that the ROMSIZE register is currently configured for a 16 kB
internal program space. If software reconfigures the ROMSIZE register to 4 kB (0000h-0FFFh) in the
current state, the device will immediately jump to external program execution because program code
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DS87C520/DS83C520
from 4 kB to 16 kB (1000h-3FFFh) is no longer located on-chip. This could result in code misalignment
and execution of an invalid instruction. The recommended method is to modify the ROMSIZE register
from a location in memory that will be internal (or external) both before and after the operation. In the
above example, the instruction which modifies the ROMSIZE register should be located below the 4 kB
(1000h) boundary, so that it will be unaffected by the memory modification. The same precaution should
be applied if the internal program memory size is modified while executing from external program
memory.
Off-chip memory is accessed using the multiple xed address/data bus on P0 and the MSB address on P2.
While serving as a memory bus, these pins are not I/O ports. This convention follows the standard 8051
method of expanding on-chip memory. Off-chip ROM access also occurs if the EA pin is a logic 0. EA
overrides all bit settings. The PSEN signal will go active (low) to serve as a chip enable or output enable
when Ports 0 and 2 fetch from external ROM.
ROM MEMORY MAP Figure 2
ROM SIZE ADJUSTABLE
DEFAULT = 16K BYTES
ROM SIZE IGNORED
DATA MEMORY ACCESS
Unlike many 8051 derivatives, the DS87C520/DS83C520 contains on-chip data memory. It also contains
the standard 256 bytes of RAM accessed by direct instructions. These areas are separate. The MOVX
instruction accesses the on-chip data memory. Although physically on-chip, software treats this area as
though it was located off- chip. The 1 kB of SRAM is between address 0000h and 03FFh.
Access to the on-chip data RAM is optional under software control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX instruction that uses this area will go to the on-chip
RAM while enabled. MOVX addresses greater tha n 03FFh automatically go to external memory through
Ports 0 and 2.
When disabled, the 1 kB memory area is transparent to the system memory map. Any MOVX directed to
the space between 0000h and FFFFh goes to the expanded bus on Ports 0 and 2. This also is the default
condition. This default allows the DS87C520/DS83C520 to drop into an existing system that uses these
addresses for other hardware and still have full compatibility.
The on-chip data area is software selectable using 2 bits in the Power Mana gement Register at location
C4h. This selection is dynamically programmable. Thus access to the on-chip area becomes transparent
to reach off-chip devices at the same addresses. The control bits are DME1 (PMR.1) and DME0
(PMR.0). They have the following operation:
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DS87C520/DS83C520
DATA MEMORY ACCESS CONTROL Table 3
DME1
0
0
DME0
0
1
1
1
0
1
DATA MEMEORY ADDRESS
0000h-FFFFh
0000h-03FFh
0400h-FFFFh
Reserved
0000h-03FFh
0400h-FFFBh
FFFCh
FFFDh-FFFFh
MEMORY FUNCTION
External Data Memory *Default condition
Internal SRAM Data Memory
External Data Memory
Reserved
Internal SRAM Data Memory
Reserved - no external access
Read access to the status of lock bits
Reserved - no external access
Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2-0 reflect the programmed status of
the security lock bits LB2-LB0. They are individually set to a logic 1 to correspond to a security lock bit
that has been programmed. These status bits allow software to verify that the part has been locked before
running if desired. The bits are read only.
Note: After internal MOVX SRAM has been initialized, changing DME0/1 bits will have no effect on the
contents of the SRAM.
STRETCH MEMORY CYCLE
The DS87C520/DS83C520 allows software to adjust the speed of off-chip data memory access. The
microcontroller is capable of performing the MOVX in as few as two instruction cycles. The on-chip
SRAM uses this speed and any MOVX instruction directed internally uses two cycles. However, the time
can be stretched for interface to external devices. This allows access to both fast memory and slow
memory or peripherals with no glue logic. Even in high-speed systems, it may not be necessary or
desirable to perform off- chip data memory access at full speed. In addition, there are a variety of memory
mapped peripherals such as LCDs or UARTs that are slow.
The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below.
It allows the user to select a Stretch value between 0 and 7. A Stretch of 0 will result in a two- machine
cycle MOVX. A Stretch of 7 will result in a MOVX of nine machine cycles. Software can dynamically
change this value depending on the particular memory or peripheral.
On reset, the Stretch value will default to a 1, resulting in a three-cycle MOVX for any external access.
Therefore, off-chip RAM access is not at full speed. This is a convenience to existing designs that may
not have fast RAM in place. Internal SRAM access is always at full speed regardless of the Stretch
setting. When desiring maximum speed, software should select a Stretch value of 0. When using very
slow RAM or peripherals, select a larger Stretch value. Note that this affects data memory only and the
only way to slow program memory (ROM) access is to use a slower crystal.
Using a Stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all
related timing. Also, setup and hold times are increased by 1 clock when using any Stretch greater than 0.
This results in a wider read/write strobe and relaxed interface timing, allowing more time for
memory/peripherals to respond. The timing of the variable speed MOVX is in the Electrical
Specifications. Table 4 shows the resulting strobe widths for each Stretch value. The memory Stretch
uses the Clock Control Special Function Register at SFR location 8Eh. The Stretch value is selected using
bits CKCON.2-0. In the table, these bits are referred to as M2 through M0. The first Stretch (default)
allows the use of common 120 ns RAMs without dramatically lengthening the memory access.
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DS87C520/DS83C520
DATA MEMORY CYCLE STRETCH VALUES Table 4
M2
0
0
0
0
1
1
1
1
CKCON.2-0
M1
M0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
OR WR STROBE
WIDTH IN CLOCKS
2
4
8
12
16
20
24
28
RD
MEMORY CYCLES
2 (forced internal)
3 (default external)
4
5
6
7
8
9
STROBE WIDTH TIME
@ 33 MHz
60 ns
121 ns
242 ns
364 ns
485 ns
606 ns
727 ns
848 ns
DUAL DATA POINTER
The timing of block moves of data memory is faster using the Dual Data Pointer (DPTR). The standard
8051 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS87C520/DS83C520, this data pointer is called DPTR0, located at SFR addresses 82h and 83h. These
are the original locations. Using DPTR requires no modification of standard code. The new DPTR at
SFR 84h and 85h is called DPTR1. The DPTR Select bit (DPS ) chooses the active pointer. Its location is
the lsb of the SFR location 86h. No other bits in register 86h have any effect and are 0. The user switches
between data pointers by toggling the lsb of register 86h. The increment (INC) instruction is the fastest
way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any activity.
Therefore it takes only one instruction to switch from a source to a destination address. Using the Dual
Data Pointer saves code from needing to save source and destination addresses when doing a block move.
The software simply switches between DPTR0 and 1 once software loads them. The relevant register
locations are as follows:
DPL
DPH
DPL1
DPH1
DPS
82h
83h
84h
85h
86h
Low byte original DPTR
High byte original DPTR
Low byte new DPTR
High byte new DPTR
DPTR Select (lsb)
POWER MANAGEMENT
Along with the standard Idle and power down (Stop) modes of the standard 80C52, the
DS87C520/DS83C520 provides a new Power Management Mode. This mode allows the processor to
continue functioning, yet to save power compared with full operation. The DS87C520/DS83C520 also
features several enhancements to Stop mode that make it more useful.
POWER MANAGEMENT MODE (PMM)
Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU
to run software but to use substantially less power. During default operation, the DS87C520/DS83C520
uses four clocks per machine cycle. Thus the instruction cycle rate is Clock/4. At 33 MHz crystal speed,
the instruction cycle speed is 8.25 MHz (33/4). In PMM, the microcontroller continues to operate but uses
an internally divided version of the clock source. This creates a lower power state without external
components. It offers a choice of two reduced instruction cycle speeds (and two clock sources - discussed
below). The speeds are (Clock/64) and (Clock/1024).
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DS87C520/DS83C520
Software is the only mechanism to invoke the PMM. Table 5 illustrates the instruction cycle rate in
PMM for several common crystal frequencies. Since power consumption is a direct function of operating
speed, PMM 1 eliminates most of the power consumption while still allowing a reasonable speed of
processing. PMM 2 runs very slow and provides the lowest power consumption without stopping the
CPU. This is illustrated in Table 6.
Note that PMM provides a lower power condition than Idle mode. This is because in Idle mode, all
clocked functions such as timers run at a rate of crystal divided by 4. Since wake-up from PMM is as fast
as or faster than from Idle and PMM allows the CPU to operate (even if doing NOPs), there is little
reason to use Idle mode in new designs.
MACHINE CYCLE RATE Table 5
CRYSTAL SPEED
FULL OPERATION
PMM1
PMM2
(4 CLOCKS)
(64 CLOCKS)
(1024 CLOCKS)
11.0592 MHz
2.765 MHz
172.8 kHz
10.8 kHz
16 MHz
4.00 MHz
250.0 kHz
15.6 kHz
25 MHz
6.25 MHz
390.6 kHz
24.4 kHz
33 MHz
8.25 MHz
515.6 kHz
32.2 kHz
TYPICAL OPERATING CURRENT IN PMM Table 6
CRYSTAL SPEED
FULL OPERATION
(4 CLOCKS)
PMM1
(64 CLOCKS)
PMM2
(1024 CLOCKS)
11.0592 MHz
13.1 mA
5.3 mA
4.8 mA
16 MHz
17.2 mA
6.4 mA
5.6 mA
25 MHz
25.7 mA
8.1 mA
7.0 mA
33 MHz
32.8 mA
9.8 mA
8.2 mA
CRYSTALESS PMM
A major component of power consumption in PMM is the crystal amplifier circuit. The
DS87C520/DS83C520 allows the user to switch CPU operation to an internal ring oscillator and turn off
the crystal amplifier. The CPU would then have a clock source of approximately 2-4 MHz, divided by
either 4, 64, or 1024. The ring is not accurate, so software can not perform precision timing. However,
this mode allows an additional saving of between 0.5 and 6.0 mA, depending on the actual crystal
frequency. While this saving is of little use when running at 4 clocks per instruction cycle, it makes a
major contribution when running in PMM1 or PMM2.
PMM OPERATION
Software invokes the PMM by setting the appropriate bits in the SFR area. The basic choices are divider
speed and clo ck source. There are three speeds (4, 64, and 1024) and two clock sources (crystal and ring).
Both the decisions and the controls are separate. Software will typically select the clock speed first. Then,
it will perform the switch to ring operation if desired. Lastly, software can disable the crystal amplifier if
desired.
There are two ways of exiting PMM. Software can remove the condition by reversing the procedure that
invoked PMM or hardware can (optionally) remove it. To resume operation at a divide by 4 rate under
software control, simply select 4 clocks per cycle, then crystal based operation if relevant. When
disabling the crystal as the time base in favor of the ring oscillator, there are timing restrictions associated
with restarting the crystal operation. Details are described below.
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DS87C520/DS83C520
There are three registers containing bits that are concerned with PMM functions. They are Power
Management Register (PMR; C4h), Status (STATUS; C5h), and External Interrupt Flag (EXIF; 91h).
Clock Divider
Software can select the instruction cycle rate by selecting bits CD1 (PMR.7) and CD0 (PMR.6) as
follows:
CD1
0
0
1
1
CD0
0
1
0
1
Cycle rate
Reserved
4 clocks (default)
64 clocks
1024 clocks
The selection of instruction cycle rate will take effect after a delay of one instruction cycle. Note that the
clock divider choice applies to all functions including timers. Since baud rates are altered, it will be
difficult to conduct serial communication while in PMM. There are minor restrictions on accessing the
clock selection bits. The processor must be running in a 4-clock state to select either 64 (PMM1) or 1024
(PMM2) clocks. This means software cannot go directly from PMM1 to PMM2 or visa versa. It must
return to a 4-clock rate first.
Switchback
To return to a 4-clock rate from PMM, software can simply select the CD1 and CD0 clock control bits to
the 4 clocks per cycle state. However, the DS87C520/DS83C520 provides several hardware alternatives
for automatic Switchback. If Switchback is enabled, then the device will automatically return to a 4-clock
per cycle speed when an interrupt occurs from an enabled, valid external interrupt source. A Switchback
will also occur when a UART detects the beginning of a serial start bit if the serial receiver is enabled
(REN=1). Note the beginning of a start bit does not generate an interrupt; this occurs on reception of a
complete serial word. The automatic Switchback on detection of a start bit allows hardware to correct
baud rates in time for a proper serial reception. A switchback will also occur when a byte is written to
SBUF0 or SBUF1 for transmission.
Switchback is enabled by setting the SWB bit (PMR.5) to a 1 in software. For an external interrupt,
Switchback will occur only if the interrupt source could really generate the interrupt. For example, if
INT0 is enabled but has a low priority setting, then Switchback will not occur on INT0 if the CPU is
servicing a high priority interrupt.
Status
Information in the Status register assists decisions about switching into PMM. This register contains
information about the level of active interrupts and the activity on the serial ports.
The DS87C520/DS83C520 supports three levels of interrupt priority. These levels are Power- fail, High,
and Low. Bits STATUS.7-5 indicate the service status of each level. If PIP (Power- fail Interrupt Priority;
STATUS. 7) is a 1, then the processor is servicing this level. If either HIP (High Interrupt Priority;
STATUS.6) or LIP (Low Interrupt Priority; STATUS.5) is high, then the corresponding level is in
service.
Software should not rely on a lower priority level interrupt source to remove PMM (Switchback) when a
higher level is in service. Check the current priority service level before entering PMM. If the current
service level locks out a desired Switchback source, then it would be advisable to wait until this condition
clears before entering PMM.
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DS87C520/DS83C520
Alternately, software can prevent an undesired exit from PMM by entering a low priority interrupt service
level before entering PMM. This will prevent other low priority interrupts from causing a Switchback.
Status also contains information about the state of the serial ports. Serial Port 0 Receive Activity
(SPRA0;STATUS.0) indicates a serial word is being received on Serial Port 0 when this bit is set to a 1.
Serial Port 0 Transmit Activity (SPTA0; STATUS.1) indicates that the serial port is still shifting out a
serial transmission. STATUS.2 and STATUS.3 provide the same information for Serial Port 1,
respectively. These bits should be interrogated before entering PMM1 or PMM2 to ensure that no serial
port operations are in progress. Changing the clock divisor rate during a serial transmission or reception
will corrupt the operation.
Crystal/Ring Operation
The DS87C520/DS83C520 allows software to choose the clock source as an independent selection from
the instruction cycle rate. The user can select crystal-based or ring oscillator-based operation under software control. Power-on reset default is the crystal (or external clock) source. The ring may save power
depending on the actual crystal speed. To save still more power, software can then disable the crystal
amplifier. This process requires two steps. Reversing the process also requires two steps.
The XT/ RG bit (EXIF.3) selects the crystal or ring as the clock source. Setting XT/ RG =1 selects the
crystal. Setting XT/ RG =0 selects the ring. The RGMD (EXIF.2) bit serves as a status bit by indicating
the active clock source. RGMD=0 indicates the CPU is running from the crystal. RGMD=1 indicates it is
running from the ring. When operating from the ring, disable the crystal amplifier by setting the XTOFF
bit (PMR.3) to a 1. This can only be done when XT/ RG =0.
When changing the clock source, the selection will take effect after a one- instruction cycle delay. This
applies to changes from crystal to ring and vise versa. However, this assumes that the crystal amplifier is
running. In most cases, when the ring is active, software previously disabled the crystal to save power. If
ring operation is being used and the system must switch to crystal operation, the crystal must first be
enabled. Set the XTOFF bit to a 0. At this time, the crystal oscillation will begin. The
DS87C520/DS83C520 then provides a warm-up delay to make certain that the frequency is stable.
Hardware will set the XTUP bit (STATUS.4) to a 1 when the crystal is ready for use. Then software
should write XT/ RG to a 1 to begin operating from the crystal. Hardware prevents writing XT/ RG to a 1
before XTUP=1. The delay between XTOFF=0 and XTUP=1 will be 65,536 crystal clocks in addition to
the crystal cycle startup time.
Switchback has no effect on the clock source. If software selects a reduced clock divider and enables the
ring, a Switchback will only restore the divider speed. The ring will remain as the time base until altered
by software. If there is serial activity, Switchback usually occurs with enough time to create proper baud
rates. This is not true if the crystal is off and the CPU is running from the ring. If sending a serial
character that wakes the system from crystal- less PMM, then it should be a dummy character of no
importance with a subsequent delay for crystal startup.
Figure 3 illustrates a typical decision set associated with PMM. Table 7 is a summary of the bits relating
to PMM and its operation.
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DS87C520/DS83C520
PMM CONTROL AND STATUS BIT SUMMARY Table 7
BIT NAME
XT/ RG
LOCATION
EXIF.3
RGMD
EXIF.2
CD1, CD0
SWB
PMR.7,
PMR.6
PMR.5
XTOFF
PMR.3
PIP
STATUS.7
HIP
STATUS.6
LIP
STATUS.5
XTUP
STATUS.4
SPTA1
SPRA1
SPTA0
SPRA0
STATUS.3
STATUS.2
STATUS.1
STATUS.0
FUNCTION
Control. XT/ RG =1, runs from crystal or
external clock; XT/ RG =0, runs from internal
ring oscillator.
Status. RGMD=1, CPU clock = ring;
RGMD=0, CPU clock = crystal.
Control. CD1,0=01, 4 clocks; CS1,0=10,
PMM1; CD1,0=11, PMM2.
Control. SWB=1, hardware invokes switchback to 4 clocks, SWB=0, no hardware
switchback.
Control. Disables crystal operation after ring
is selected.
Status. 1 indicates a power-fail interrupt in
service.
Status. 1 indicates high priority interrupt in
service.
Status. 1 indicates low priority interrupt in
service.
Status. 1 indicates that the crystal has
stabilized.
Status. Serial transmission on serial port 1.
Status. Serial word reception on serial port 1.
Status. Serial transmission on serial port 0.
Status. Serial word reception on serial port 0.
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RESET
X
0
0,1
WRITE ACCESS
0 to 1 only when
XTUP=1 and XTOFF=0
None
Write CD1,0=10 or 11
only from CD1,0=01
0
Unrestricted
0
1 only when XT/ RG =0
0
None
0
None
0
None
1
None
0
0
0
0
None
None
None
None
DS87C520/DS83C520
INVOKING AND CLEARING PMM Figure 3
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DS87C520/DS83C520
IDLE MODE
Setting the lsb of the Power Control register (PCON;87h) invokes the Idle mode. Idle will leave internal
clocks, serial ports and timers running. Power consumption drops because the CPU is not active. Since
clocks are running, the Idle power consumption is a function of crystal frequency. It should be
approximately ½ of the operational power at a given frequency. The CPU can exit the Idle state with any
interrupt or a reset. Idle is available for backward software compatibility. The system can now reduce
power consumption to below Idle levels by using PMM1 or PMM2 and running NOPs.
STOP MODE ENHANCEMENTS
Setting Bit 1 of the Power Control register (PCON; 87h) invokes the Stop mode. Stop mode is the lowest
power state since it turns off all internal clocking. The ICC f a standard Stop mode is approximately 1 µA
(but is specified in the Electrical Specifications). The CPU will exit Stop mode from an eternal interrupt
or a reset condition. Internally generated interrupts (timer, serial port, Watchdog) are not useful since
they require clocking activity.
The DS87C520/DS83C520 provides two enhancements to the Stop mode. As documented below, the
device provides a band-gap reference to determine Power-Fail Interrupt and Reset thresholds. The default
state is that the band-gap reference is off while in Stop mode. This allows the extremely low-power state
mentioned above. A user can optionally choose to have the band-gap enabled during Stop mode. With the
band-gap reference enabled, PFI and Power- fail Reset are functional and are a valid means for leaving
Stop mode. This allows software to detect and compensate for a brown-out or power supply sag, even
when in Stop mode. In Stop mode with the band-gap enabled, ICC will be approximately 50 µA compared
with 1 µA with the band- gap off. If a user does not require a Power- fail Reset or Interrupt while in Stop
mode, the band-gap can remain disabled. Only the most power-sensitive applications should turn off the
band-gap, as this results in an uncontrolled power-down condition.
The control of the band- gap reference is located in the Extended Interrupt Flag register (EXIF; 91h).
Setting BGS (EXIF.0) to a 1 will keep the band-gap reference enabled during Stop mode. The default or
reset condition is with the bit at a logic 0. This results in the band-gap being off during Stop mode. Note
that this bit has no control of the reference during full power, PMM, or Idle modes.
The second feature allows an additional power saving option while also making Stop easier to use. This is
the ability to start instantly when exiting Stop mode. It is the internal ring oscillator that provides this
feature. This ring can be a clock source when exiting Stop mode in response to an interrupt. The benefit
of the ring oscillator is as follows.
Using Stop mode turns off the crystal oscillator and all internal clocks to save power. This requires that
the oscillator be restarted when exiting Stop mode. Actual startup time is crystal-dependent, but is
normally at least 4 ms. A common recommendation is 10 ms. In an application that will wake up, perform
a short operation, then return to sleep, the crystal startup can be longer than the real transaction. However,
the ring oscillator will start instantly. Running from the ring, the user can perform a simple operation and
return to sleep before the crystal has even started. If a user selects the ring to provide the startup clock and
the processor remains running, hardware will automatically switch to the crystal once a power-on reset
interval (65536 clocks) has expired. Hardware uses this value to assure proper crystal start even though
power is not being cycled.
The ring oscillator runs at approximately 2-4 MHz but will not be a precise value. Do not conduct realtime precision operations (including serial communication) during this ring period. Figure 3 shows how
the operation would compare when using the ring, and when starting up normally. The default state is to
exit Stop mode without using the ring oscillator.
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DS87C520/DS83C520
The RGSL - Ring Select bit at EXIF.1 (EXIF; 91h) controls this function. When RGSL=1, the CPU will
use the ring oscillator to exit Stop mode quickly. As mentioned above, the processor will automatically
switch from the ring to the crystal after a delay of 65,536 crystal clocks. For a 3.57 MHz crystal, this is
approximately 18 ms. The processor sets a flag called RGMD-Ring Mode, located at EXIF.2, that tells
software that the ring is being used. The bit will be a logic 1 when the ring is in use. Attempt no serial
communication or precision timing while this bit is set, since the operating frequency is not precise.
RING OSCILLATOR EXIT FROM STOP MODE Figure
STOP MODE WITHOUT RING STARTUP
STOP MODE WITH RING STARTUP
Note: Diagram assumes that the operation following Stop requires less than 18 ms to complete.
EMI REDUCTION
One of the major contributors to radiated noise in an 8051-based system is the toggling of ALE. The
microcontroller allows software to disable ALE when not used by setting the ALEOFF (PMR.2) bit to a
1. When ALE-OFF= 1, ALE will still toggle during an off-chip MOVX. However, ALE will remain in a
static mode when performing on-chip memory access. The default state of ALEOFF=0 so ALE toggles at
a frequency of XTAL/4.
PERIPHERAL OVERVIEW
The DS87C520/DS83C520 provides several of the most commonly needed peripheral functions in microcomputer-based systems. These new functions include a second serial port, Power- fail Reset, Power- fail
Interrupt, and a programmable Watchdog Timer. These are described below, and more details are
available in the High-Speed Microcontroller User’s Guide.
SERIAL PORTS
The DS87C520/DS83C520 provides a serial port (UART) that is identical to the 80C52. In addition it
includes a second hardware serial port that is a full duplicate of the standard one. This port optionally
uses pins P1.2 (RXD1) and P1.3 (TXD1). It has duplicate control functions included in new SFR
locations.
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DS87C520/DS83C520
Both ports can operate simultaneously but can be at different baud rates or even in different modes. The
second serial port has similar control registers (SCON1 at C0h, SBUF1 at C1h) to the original. The new
serial port can only use Timer 1 for timer generated baud rates.
TIMER RATE CONTROL
There is one important difference between the DS87C520/DS83C520 and 8051 regarding timers. The
original 8051 used 12 clocks per cycle for timers as well as for machine cycles. The
DS87C520/DS83C520 architecture normally uses four clocks per machine cycle. However, in the area of
timers and serial ports, the DS87C520/DS83C520 will default to 12 clocks per cycle on reset. This allows
existing code with real-time dependencies such as baud rates to operate properly.
If an application needs higher speed timers or serial baud rates, the user can select individual timers to run
at the 4-clock rate. The Clock Control register (CKCON;8Eh) determines these timer speeds. When the
relevant CKCON bit is a logic 1, the DS87C520/DS83C520 uses 4 clocks per cycle to generate timer
speeds. When the bit is a 0, the DS87C520/DS83C520 uses 12 clocks for timer speeds. The reset
condition is a 0. CKCON.5 selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3
selects Timer 0. Unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the
timer controls are independent.
POWER-FAIL RESET
The DS87C520/DS83C520 uses a precision band-gap voltage reference to decide if VCC is out of
tolerance. While powering up, the internal monitor circuit maintains a reset state until VCC rises above the
VRST level. Once above this level, the monitor enables the crystal oscillator and counts 65536 clocks. It
then exits the reset state. This power-on reset (POR) interval allows time for the oscillator to stabilize.
A system needs no external components to generate a power-related reset. Anytime VCC drops below
VRST , as in power failure or a power drop, the monitor will generate and hold a reset. It occurs
automatically, needing no action from the software. Refer to the Electrical Specifications for the exact
value of VRST .
POWER-FAIL INTERRUPT
The voltage reference that sets a precise reset threshold also generates an optional early warning PowerFail Interrupt (PFI). When enabled by software, the processor will vector to program memory address
0033h if VCC drops below VPFW . PFI has the highest priority. The PFI enable is in the Watchdog Control
SFR (WDCON-D8h). Setting WDCON.5 to a logic 1 will enable the PFI. Application software can also
read the PFI flag at WDCON.4. A PFI condition sets this bit to a 1. The flag is independent of the
interrupt enable and software must manually clear it.
WATCHDOG TIMER
To prevent software from losing control, the DS87C520/DS83C520 includes a programmable Watchdog
Timer. The Watchdog is a free running timer that sets a flag if allowed to reach a preselected time-out. It
can be (re)started by software.
A typical application is to select the flag as a reset source. When the Watchdog times out, it sets its flag
which generates reset. Software must restart the timer before it reaches its time-out or the processor is
reset.
Software can select one of four time-out values. Then, it restarts the timer and enables the reset function.
After enabling the reset function, software must then restart the timer before its expiration or hardware
will reset the CPU. Both the Watchdog Reset Enable and the Watchdog Restart control bits are protected
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DS87C520/DS83C520
by a “Timed Access” circuit. This prevents errant software from accidentally clearing the Watchdog.
Time-out values are precise since they are a function of the crystal frequency as shown in Table 8. For
reference, the time periods at 33 MHz also are shown.
The Watchdog also provides a useful option for systems that do not require a reset circuit. It will set an
interrupt flag 512 clocks before setting the reset flag. Software can optionally enable this interrupt source.
The interrupt is independent of the reset. A common use of the interrupt is during debug, to show
developers where the Watchdog times out. This indicates where the Watchdog must be restarted by
software. The interrupt also can serve as a convenient time-base generator or can wake-up the processor
from power saving modes.
The Watchdog function is controlled by the Clock Control (CKCON-8Eh), Watchdog Control (WDCOND8h), and Extended Interrupt Enable (EIE-E8h) SFRs. CKCON.7 and CKCON.6 are WD1 and WD0
respectively and they select the Watchdog time-out period as shown in Table 8.
WATCHDOG TIME-OUT VALUES Table 8
WD1
WD2
INTERRUPT
TIME (33 MHz)
RESET TIME-OUT
TIME (33 MHz)
3.9718 ms
217 + 512 clocks
3.9874 ms
TIME-OUT
0
0
217 clocks
20
20
0
1
2 clocks
31.77 ms
2 + 512 clocks
31.79 ms
1
0
223 clocks
254.20 ms
223 + 512 clocks
254.21 ms
1
1
226 clocks
2033.60 ms
226 + 512 clocks
2033.62 ms
As shown above, the Watchdog Timer uses the crystal frequency as a time base. A user selects one of
four counter values to determine the time-out. These clock counter lengths are 217 =131,072 clocks; 220
=1,048,576; 223 =8,388,608 clocks; and 226 =67,108,864 clocks. The times shown in Table 8 above are
with a 33 MHz crystal frequency. Once the counter chain has completed a full interrupt count, hardware
will set an interrupt flag. Regardless of whether the user enables this interrupt, there are then 512 clocks
left until the reset flag is set. Software can enable the interrup t and reset individually. Note that the
Watchdog is a free running timer and does not require an enable.
There are 5 control bits in special function registers that affect the Watchdog Timer and two status flags
that report to the user. WDIF (WDCON.3) is the interrupt flag that is set at timer termination when there
are 512 clocks remaining until the reset flag is set. WTRF (WDCON.2) is the flag that is set when the
timer has completely timed out. This flag is normally associated with a CPU reset and allows software to
determine the reset source.
EWT (WDCON.1) is the enable for the Watchdog timer reset function. RWT (WDCON.0) is the bit that
software uses to restart the Watchdog Timer. Setting this bit restarts the timer for another full interval.
Application software must set this bit before the time-out. Both of these bits are protected by Timed
Access discussed below. As mentioned previously, WD1 and 0 (CKCON .7 and 6) select the time-out.
The Reset Watchdog Timer bit (WDCON.0) should be asserted prior to modifying the Watchdog Timer
Mode Select bits (WD1, WD0) to avoid corruption of the watchdog count. Finally, the user can enable
the Watchdog Interrupt using EWDI (EIE.4). The Special Function Register map is shown above.
INTERRUPTS
The DS87C520/DS83C520 provides 13 interrupt sources with three priority levels. The Power- fail
Interrupt (PFI) has the highest priority. Software can assign high or low priority to other sources. All
interrupts that are new to the 8051 family, except for the PFI, have a lower natural priority than the
originals.
21 of 42
DS87C520/DS83C520
INTERRUPT SOURCES AND PRIORITIES Table 9
NAME
DESCRIPTION
VECTOR
NATURAL
PRIORITY
8051/DALLAS
PFI
Power-Fail Interrupt
33h
1
DALLAS
INT0
External Interrupt 0
03h
2
8051
TF0
Timer 0
0Bh
3
8051
INT1
External Interrupt 1
13h
4
8051
TF1
Timer 1
1Bh
5
8051
SCON0
TI0 or RI0 from serial port 0
23h
6
8051
TF2
Timer 2
2Bh
7
8051
SCON1
TI1 or RI1 from serial port 1
3Bh
8
DALLAS
INT2
External Interrupt 2
43h
9
DALLAS
INT3
External Interrupt 3
4Bh
10
DALLAS
INT4
External Interrupt 4
53h
11
DALLAS
INT5
External Interrupt 5
5Bh
12
DALLAS
WDTI
Watchdog Time -Out Interrupt
63h
13
DALLAS
TIMED ACCESS PROTECTION
It is useful to protect certain SFR bits from an accidental write operation. The Timed Access procedure
stops an errant CPU from accidentally changing these bits. It requires that the following instructions
precede a write of a protected bit.
MOV
MOV
0C7h,
0C7h,
#0Aah
#55h
Writing an AAh then a 55h to the Timed Access register (location C7h) opens a 3-cycle window for write
access. The window allows software to modify a protected bit(s). If these instructions do not
immediately precede the write operation, then the write will not take effect. The protected bits are:
EXIF.0
WDCON.6
WDCON.1
WDCON.0
WDCON.3
ROMSIZE.2
ROMSIZE.1
ROMSIZE.0
BGS
POR
EWT
RWT
WDIF
RMS2
RMS1
RMS0
Band-gap Select
Power-on Reset flag
Enable Watchdog Reset
Restart Watchdog
Watchdog Interrupt Flag
ROM size select 2
ROM size select 1
ROM size select 0
EPROM PROGRAMMING
The DS87C520 follows standards for a 16 kB EPROM version in the 8051 family. It is available in a UVerasable, ceramic windowed package and in plastic packages for one-time user-programmable versions.
The part has unique signature information so programmers can support its specific EPROM options.
ROM-specific features are described later in this data sheet.
Most commercially available device programmers will directly support Dallas Semiconductor
microcontrollers. If your programmer does not, please contact the manufacturer for updated software.
22 of 42
DS87C520/DS83C520
PROGRAMMING PROCEDURE
The DS87C520 should run from a clock speed between 4 and 6 MHz when being programmed. The
programming fixture should apply address information for each byte to the address lines and the data
value to the data lines. The control signals must be manipulated as shown in Table 10. The diagram in
Figure 5 shows the expected electrical connection for programming. Note that the programmer must
apply addresses in demultiplexed fashion to Ports 1 and 2 with data on Port 0. Waveforms and timing are
provided in the Electrical Specifications.
Program the DS87C520 as follows:
1. Apply the address value,
2. Apply the data value,
3. Select the programming option from Table 10 using the control signals,
4. Increase the voltage on VPP from 5V to 12.75V if writing to the EPROM,
5. Pulse the PROG signal five times for EPROM array and 25 times for encryption table, lock bits, and
other EPROM bits,
6. Repeat as many times as necessary.
EPROM PROGRAMMING MODES Table 10
MODE
RST
PSEN
ALE/ PROG
EA/VPP
P2.6
P2.7
P3.3
P3.6
P3.7
Program Code Data
H
L
PL
12.75V
L
H
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption Array
Address 0-3Fh
H
L
PL
12.75V
L
H
H
L
H
Program Lock Bits
LB1
H
L
PL
12.75V
H
H
H
H
H
LB2
H
L
PL
12.75V
H
H
H
L
L
LB3
H
L
PL
12.75V
H
L
H
H
L
Program Option Register
Address FCh
H
L
PL
12.75V
L
H
H
L
L
Read Signature or Option
Registers 30, 31, 60 FCh
H
L
H
H
L
L
L
L
L
DS87C520 EPROM LOCK BITS Table 11
LEVEL
LOCK BITS
PROTECTION
LB1
LB2
LB3
1
U
U
U
No program lock. Encrypted verify if encryption table was
programmed.
2
P
U
U
Prevent MOVC instructions in external memory from reading
program bytes in internal memory. EA is sampled and latched
on reset. Allow no further programming of EPROM.
3
P
P
U
Level 2 plus no verify operation. Also, prevent MOVX
instructions in external memory from reading SRAM (MOVX)
in internal memory.
4
P
P
P
Level 3 plus no external execution.
23 of 42
DS87C520/DS83C520
SECURITY OPTIONS
The DS87C520 employs a standard three- level lock that restricts viewing of the EPROM contents. A 64byte Encryption Array allows the authorized user to verify memory by presenting the data in encrypted
form.
Lock Bits
The security lock consists of three lock bits. These bits select a total of four levels of security. Higher
levels provide increasing security but also limit application flexibility. Table 11 shows the security
settings. Note that the programmer cannot directly read the state of the security lock. User software has
access to this information as described in the Memory section.
Encryption Array
The Encryption Array allows an authorized user to verify EPROM without allowing the true memory to
be dumped. During a verify, each byte is Exclusive NORed (XNOR) with a byte in the Encryption Array.
This results in a true representation of the EPROM while the Encryption is unprogrammed (FFh). Once
the Encryption Array is programmed in a non-FFh state, the verify value will be encrypted.
For encryption to be effective, the Encryption Array must be unknown to the party that is trying to verify
memory. The entire EPROM also should be a non-FFh state or the Encryptio n Array can be discovered.
The Encryption Array is programmed as shown in Table 10. Note that the programmer cannot read the
array. Also note that the verify operation always uses the Encryption Array. The array has no impact
while FFh. Simply programming the array to a non-FFh state will cause the encryption to function.
OTHER EPROM OPTIONS
The DS87C520 has user selectable options that must be set before beginning software execution. These
options use EPROM bits rather than SFRs.
Program the EPROM selectable options as shown in Table 10. The Option Register sets or reads these
selections. The bits in the Option Control Register have the following function:
Bit 7 -4
Reserved, program to a 1.
Bit 3
Watchdog POR default. Set=1; Watchdog reset function is disabled on power-up. Set=0;
Watchdog reset function is enabled automatically.
Bit 2-0
Reserved. Program to a 1.
SIGNATURE
The Signature bytes identify the product and programming revision to EPROM programmers. This
information is at programming addresses 30h, 31h, and 60h.
Address
30h
31h
60h
Value
DAh
20h
01h
Meaning
Manufacturer
Model
Extension
24 of 42
DS87C520/DS83C520
EPROM PROGRAMMING CONFIGURATION Figure 5
ROM-SPECIFIC FEATURES
The DS83C520 supports a subset of the EPROM features found on the DS87C520.
SECURITY OPTIONS
Lock Bits
The DS83C520 employs a lock that restricts viewing of the ROM contents. When set, the lock will
prevent MOVC instructions in external memory from reading program bytes in internal memory. When
locked, the EA pin is sampled and latched on reset. The lock setting is enabled or disabled when the
devices are manufactured according to customer specifications. The lock bit cannot be read in software,
and its status can only be determined by observing the operation of the device.
Encryption Array
The DS83C520 Encryption Array allows an authorized user to verify ROM without allowing the true
memory contents to be dumped. During a verify, each byte is Exclusive NORed (XNOR) with a byte in
the Encryption Array. This results in a true representation of the ROM while the Encryption is
unprogrammed (FFh) . Once the Encryption Array is programmed in a non-FFh state, the Encryption
Array is programmed (or optionally left unprogrammed) when the devices are manufactured according to
customer specifications.
DS83C520 ROM VERIFICATION
The DS83C520 memory contents can be verified using a standard EPROM programmer. The memory
address to be verified is placed on the pins shown in Figure 5, and the programming control pins are set to
the levels shown in Table 10. The data at that location is then asserted on port 0.
25 of 42
DS87C520/DS83C520
DS83C520 SIGNATURE
The Signature bytes identify the DS83C520 to EPROM programmers. This information is at
programming addresses 30h, 31h, and 60h. Because Mask ROM devices are not programmed in device
programmers, most designers will find little use for the feature, and it is included only for compatibility.
Address
30h
31h
60h
Value
DAh
21h
01h
Meaning
Manufacturer
Model
Extension
26 of 42
DS87C520/DS83C520
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-0.3V to +7.0V
0°C to 70°C
-55°C to +125°C
See J-STD-020A specification
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Supply Voltage
Power-fail Warning
Minimum Operating Voltage
Supply Current Active Mode
@ 33 MHz
Supply Current Idle Mode
@ 33 MHz
Supply Current Stop Mode
Band-gap Disabled
Supply Current Stop Mode,
Band-gap Enabled
Input Low Level
Input High Level
(except XTAL1 and RST)
Input High Level XTAL1 and RST
Output Low Voltage, Ports 1 and 3
@ IOL =1.6 mA
Output Low Voltage Ports 0 and 2,
VCC
VPFW
VRST
ICC
4.5
4.25
4.0
5.0
4.38
4.13
30
5.5
4.5
4.25
V
V
V
mA
1
1
1
2
ALE , PSEN @ IOL = 3.2 mA
Output High Voltage Ports 1, 2, 3,
ALE, PSEN @ IOH = -50 µA
Output High Voltage Ports 1, 2, 3
@ IOH = -1.5 mA
Output High Voltage Port 0, 2,
ALE, PSEN in Bus Mode
@ IOH = -8 mA
Input Low Current Ports 1, 2, 3 @
0.45V
Transition Current from 1 to 0 Ports
1, 2, 3 @ 2V
Input Leakage Port 0, and EA pins,
I/O Mode
Input Leakage Port 0, Bus Mode
RST Pulldown Resistance
IIDLE
15
mA
3
ISTOP
1
µA
4
ISPBG
50
µA
4
+0.8
VCC +0.3
V
V
1
1
0.15
VCC +0.3
0.45
V
V
1
1
0.15
0.45
V
1
VIL
VIH
-0.3
2.0
VIH2
VOL1
3.5
VOL2
VOH1
2.4
V
1,6
VOH2
2.4
V
1,7
VOH3
2.4
V
1,5
IIL
-55
µA
11
ITL
-650
µA
8
IL
-10
+10
µA
10
IL
RRST
-300
50
+300
200
µA
kO
9
27 of 42
DS87C520/DS83C520
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
1. All voltages are referenced to ground.
2. Active current measured with 33 MHz clock source on XTAL1, VCC =RST=5.5V, other pins
disconnected.
3. Idle mode current measured with 33 MHz clock source on XTAL1, VCC =5.5V, RST at ground, other
pins disconnected.
4. Stop mode current measured with XTAL1 and RST grounded, VCC =5.5V, all other pins disconnected.
This value is not guaranteed. Users that are sensitive to this specification should contact Dallas
Semiconductor for more information.
5. When addressing external memory.
6. RST=VCC. This condition mimics operation of pins in I/O mode. Port 0 is tristated in reset and when
at a logic high state during I/O mode.
7. During a 0 to 1 transition, a one-shot drives the ports hard for two clock cycles. This measurement
reflects port in transition mode.
8. Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum
at approximately 2V.
9. 0.45<VIN <VCC. Not a high- impedance input. This port is a weak address holding latch in Bus Mode.
Peak current occurs near the input transition point of the latch, approximately 2V.
10. 0.45<VIN <VCC. RST=VCC. This condition mimics operation of pins in I/O mode.
11. This is the current required from an external circuit to hold a logic low level on an I/O pin while the
corresponding port latch bit is set to 1. This is only the current required to hold the low level;
transitions from 1 to 0 on an I/O pin will also have to overcome the transition current.
TYPICAL ICC VERSUS FREQUENCY Figure 6
28 of 42
DS87C520/DS83C520
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Oscillator Freq. (Ext. Osc.)
(Ext. Crystal)
ALE Pulse Width
Port 0 Address Valid to ALE
Low
Address Hold after ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instr. In
Input Instruction Hold after
SYMBOL
tAVLL
10
VARIABLE CLOCK
MIN
MAX
0
33
1
33
1.53tCLCL 5
0.5tCLCL -5
tLLAX1
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
10
0.5tCLCL -5
1/tCLCL
tLHLL
33 MHz
MIN
MAX
0
33
1
33
40
56
10
55
2.5tCLCL -20
0.5tCLCL -5
2tCLCL -5
41
0
2tCLCL -20
0
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
PSEN
Input Instruction Float after
tPXIZ
26
tCLCL -5
ns
tAVIV
tAVIV2
tPLAZ
71
81
0
3tCLCL -20
3.5tCLCL -25
0
ns
ns
ns
PSEN
Port 0 Address to Valid Instr. In
Port 2 Address to Valid Instr. In
PSEN Low to Address Float
NOTES FOR AC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature range operation unless otherwise
noted. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN , RD and WR
with 100 pF. Interfacing to memory devices with float times (turn off times) over 25 ns may cause
contention. This will not damage the parts, but will cause an increase in operating current. Specifications
assume a 50% duty cycle for the oscillator. Port 2 and ALE timing will change in relation to duty cycle
variation.
29 of 42
DS87C520/DS83C520
MOVX CHARACTERISTICS
PARAMETER
SYMBOL
Data Access ALE Puls e Width
tLHLL2
Address Hold after ALE Low for
MOVX Write
tLLAX2
RD Pulse Width
tRLRH
WR Pulse Width
tWLWH
RD Low to Valid Data In
tRLDV
Data Hold After Read
Data Float after Read
tRHDX
tRHDZ
ALE Low to Valid Data In
tLLDV
Port 0 Address to Valid Data In
tAVDV1
Port 2 Address to Valid Data In
tAVDV2
ALE Low to RD or WR Low
tLLWL
Port 0 Address to RD or WR Low
tAVWL1
Port 2 Address to RD or WR Low
tAVWL2
Data Valid to WR Transition
Data Hold after Write
tQVWX
RD Low to Address Float
tRLAZ
RD or WR High to ALE High
tWHLH
tWHQX
VARIABLE CLOCK
MIN
MAX
1.5t CLCL -5
2t CLCL -5
0.5t CLCL -5
tCLCL -5
2t CLCL -5
tMCS-10
2t CLCL -5
tMCS-10
STRETCH
ns
tMCS=0
tMCS>0
tMCS=0
tMCS>0
tMCS=0
tMCS>0
tMCS=0
tMCS>0
tMCS=0
tMCS>0
ns
ns
ns
2t CLCL -20
tMCS-20
0
0.5t CLCL -5
tCLCL -5
tCLCL -5
2.5t CLCL -5
1.5t CLCL -10
2.5t CLCL -10
-5
UNITS
tCLCL -5
2t CLCL -5
2.5t CLCL -20
tMCS+ t CLCL -40
3t CLCL -20
tMCS+1.5t CLCL -20
3.5t CLCL -20
tMCS+2t CLCL -20
0.5t CLCL +5
tCLCL +5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tMCS=0
tMCS>0
tMCS=0
tMCS>0
tMCS=0
tMCS>0
tMCS=0
tMCS>0
tMCS=0
tMCS>0
tMCS=0
tMCS>0
tMCS=0
tMCS>0
ns
tCLCL -5
2t CLCL -5
ns
-0.5t CLCL -5
ns
0
10
ns
tCLCL -5
tCLCL +5
tMCS=0
tMCS>0
tMCS=0
tMCS>0
NOTE:
tMCS is a time period related to the Stretch memory cycle selection. The following table shows the value of
tMCS for each Stretch selection.
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
MOVX CYCLES
2 machine cycles
3 machine cycles (default)
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
30 of 42
tMCS
0
4 tCLCL
8 tCLCL
12 tCLCL
16 tCLCL
20 tCLCL
24 tCLCL
28 tCLCL
DS87C520/DS83C520
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER
SYMBOL
MIN
tCHCX
10
10
Clock High Time
Clock Low Time
tCLCX
Clock Rise Time
Clock Fall Time
tCLCL
tCHCL
TYP
MAX
UNITS
NOTES
ns
ns
5
5
ns
ns
MAX
UNITS
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER
SYMBOL
MIN
TYP
Serial Port Clock Cycle Time
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Output Data Setup to Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Output Data Hold from Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Input Data Hold after Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Clock Rising Edge to Input Data
Valid
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
tXLXL
12t CLCL
4t CLCL
ns
ns
tQVXH
10t CLCL
3t CLCL
ns
ns
tXHQX
2t CLCL
tCLCL
ns
ns
tXHDX
tCLCL
tCLCL
ns
ns
tXHDV
11t CLCL
3t CLCL
ns
ns
NOTES
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters
as such devices, using the same symbols. For completeness, the following is an explanation of the
symbols.
t
A
C
D
H
L
I
P
Q
R
V
W
X
Z
Time
Address
Clock
Input data
Logic level high
Logic level low
Instruction
PSEN
Output data
RD signal
Valid
WR signal
No longer a valid logic level
Tristate
31 of 42
DS87C520/DS83C520
POWER CYCLE TIMING CHARACTERISTICS
PARAMETER
Cycle Startup Time
Power-on Reset Delay
SYMBOL
MIN
tCSU
tPOR
TYP
MAX
1.8
65536
UNITS
NOTES
ms
1
2
tCLCL
NOTES FOR POWER CYCLE TIMING CHARACTERISTICS:
1. Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592
MHz crystal manufactured by Fox.
2. Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins
when the level on the XTAL1 pin meets the VIH2 criteria. Counting begins when the level on the
XTAL1 pin meets the VIH2 criteria.At 33 MHz, this time is 1.99 ms.
EPROM PROGRAMMING AND VERIFICATION
(21°C to 27°C; V CC =4.5V to 5.5V)
PARAMETER
SYMBOL
MIN
VP P
IPP
1/tCLCL
tAVGL
12.5
4
48t CLCL
Address Hold after PROG
tGHAX
48 t CLCL
Data Setup to PROG Low
tDVGL
48 t CLCL
Data Hold after PROG
Enable High to VPP
tGHDX
48 t CLCL
VP P Setup to PROG Low
tEHSH
tSHGL
48 t CLCL
10
µs
VP P Hold after PROG
tSHGL
10
µs
PROG Width
Address to Data Valid
Enable Low to Data Valid
Data Float after Enable
tGLGH
90
Programming Voltage
Programming Supply Current
Oscillator Frequency
Address Setup to PROG Low
PROG High to PROG Low
tAVQV
tELQV
tEHQZ
tGHGL
0
10
NOTE:
1. All voltages are referenced to ground.
32 of 42
TYP
MAX
UNITS
NOTES
13.0
50
6
V
mA
MHz
1
110
µs
48 t CLCL
48 t CLCL
48 t CLCL
µs
DS87C520/DS83C520
EXTERNAL PROGRAM MEMORY READ CYCLE
EXTERNAL DATA MEMORY READ CYCLE
33 of 42
DS87C520/DS83C520
EXTERNAL DATA MEMORY WRITE CYCLE
DATA MEMORY WRITE WITH STRETCH=1
34 of 42
DS87C520/DS83C520
DAT A MEMORY WRITE WITH STRETCH=2
FOUR CYCLE DATA MEMORY WRITE
STRETCH VALUE=2
EXTERNAL CLOCK DRIVE
35 of 42
DS87C520/DS83C520
SERIAL PORT MODE 0 TIMING
SERIAL PORT 0 (SYNCHRONOUS MODE)
HIGH SPEED OPERATION SM2=1=>TXD CLOCK=XTAL/4
36 of 42
DS87C520/DS83C520
POWER CYCLE TIMING
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
37 of 42
DS87C520/DS83C520
40-PIN PDIP (600-MIL)
DIMENSIONS ARE IN INCHES.
PKG
DIM
.
40-PIN
MIN
MAX
A
-
0.200
A1
0.015
-
A2
0.140
0.160
b
0.014
0.022
c
0.008
0.012
D
1.980
2.085
E
0.600
0.625
E1
0.530
0.555
e
0.090
0.110
L
0.115
0.145
eB
0.600
0.700
56-G5000-000
38 of 42
DS87C520/DS83C520
40-PIN CER DIP
DIMENSIONS ARE IN INCHES.
PKG
40-PIN
DIM
MIN
MAX
A
-
0.225
B
0.014
0.023
B1
0.038
0.065
C
0.006
0.015
D
-
2.096
E
0.510
0.620
E1
0.590
0.630
e
100 BSC
L
0.125
0.200
L1
0.150
-
Q
0.020
0.060
S
-
0.098
S1
0.005
-
a
0°
15°
56-G4008-001
39 of 42
DS87C520/DS83C520
44-PIN PLCC
NOTE:
1. PIN-1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED
2. CONTROLLING DIMENSIONS ARE IN INCHES
PKG
DIM
A
A1
A2
B
B1
c
CH1
D
D1
D2
E
E1
E2
e1
N
44-PIN
MIN MAX
0.165 0.180
0.090 0.120
0.020
0.026 0.033
0.013 0.021
0.009 0.012
0.042 0.048
0.685 0.695
0.650 0.656
0.590 0.630
0.685 0.695
0.650 0.656
0.590 0.630
0.050 BSC
44
-
56-G4003-001
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DS87C520/DS83C520
44-PIN TQFP
PKG
DIM
A
A1
A2
D
D1
E
E1
L
e
B
C
44-PIN
MIN
MAX
1.20
0.05
0.15
0.95
1.05
11.80
12.20
10.00 BSC
11.80
12.20
10.00 BSC
0.45
0.75
0.80 BSC
0.30
0.45
0.09
0.20
56-G4012-001
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DS87C520/DS83C520
DATA SHEET REVISION SUMMARY
The following represent the key differences between 07/06/98 and 07/03/00 version of the DS87C520
data sheet. Please review this summary carefully.
1. Corrected P0 pinout description for TQFP package
2. Clarified point at which reset delay begins
The following represent the key differences between 02/20/97 and 07/06/98 version of the DS87C520
data sheet. Please review this summary carefully.
1. Update PMM operating current estimates
2. Added note to clarify IIL specification.
3. Added note to prevent accidental corruption of Watchdog Timer count while changing counter length.
4. Changed minimum oscillator frequency to 1 MHz when using external crystal.
5. Changed RST pulldown resistance from 170 kΩ to 200 kΩ maximum.
6. Corrected “Data memory write with stretch” diagrams to show falling edge of ALE coincident with
rising edge of C3 clock.
The following represent the key differences between 110195 and 02/20/97 version of the DS87C520 data
sheet. Please review this summary carefully.
1. Update ALE pin description.
2. Add note pertaining to erasure window.
3. Add note pertaining to internal MOVX SRAM.
4. Change note 10 from RST=5.5V to RST=VCC.
5. Change serial port mode 0 timing diagram label from tQVXL to tQVXH.
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