A26E001A 2M and 256K MaskRAM Document Title 2M and 256K MaskRAM Revision History Rev. No. History Issue Date Remark 2.0 Final spec release October 12, 1998 Final 2.1 Change tOE speed from 150ns to 200ns November 20, 1998 (November, 1998, Version 2.1) AMIC Technology, Inc. A26E001A 2M and 256K MaskRAM Features n n n n n n Power supply range: 1.8V to 3.3V n Access time: 450 ns (max.) n Current: Low power version: Operating: 4mA (max.) Standby: 10µA (max.) n Extended operating temperature range: -25°C to 85°C Full static operation, no clock or refreshing required All inputs and outputs are CMOS compatible Common I/O using three-state output Data retention voltage: 1.6V (min.) Available in 32-pin TSOP and sTSOP packages General Description Minimum standby power is drawn by this device when ROMCE and RAMCE are at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 1.6V. Pin Configuration Pin Description 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ~ ~ A26E001AV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ~ ~ A11 A9 A8 A13 A14 A17 RAMCE VCC WE A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A26E001AX (November, 1998, Version 21) ~ ~ A11 A9 A8 A13 A14 A17 RAMCE VCC WE A16 A15 A12 A7 A6 A5 A4 ~ ~ The A26E001A is a low operating current 262,144 x 8 bit CMOS MASK ROM and 32,768 x 8 bit CMOS SRAM integrated into one chip. It operates on a low power supply voltage from 1.8V to 3.3V, with two chip selects to enable the MASK ROM or SRAM independently. Inputs and three-state outputs are CMOS compatible and allow for direct interfacing with common system bus structures. 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 ROMCE D7 D6 D5 D4 D3 GND D2 D1 D0 A0 A1 A2 A3 OE A10 ROMCE D7 D6 D5 D4 D3 GND D2 D1 D0 A0 A1 A2 A3 1 Pin No. Symbol Description 1 - 6, 10 - 20, 31 A0 - A17 Address Inputs 7 RAMCE SRAM Enable 9 WE Write Enable 21 - 23, 25 - 29 D0 - D7 Data Input/Outputs 30 ROMCE ROM Enable 32 OE Output Enable 8 VCC Power Supply 24 GND Ground AMIC Technology, Inc. A26E001A Block Diagram VCC GND RAM A0 - A14 WE A0-A14 A15 - A17 OE ADDRESS BUFFER RAMCE D0-D7 D0 - D7 DATA BUFFER CIRCUIT D0-D7 WE OE A0-A14 ROMCE A15-A17 WE OE CONTROL CIRCUIT RAMCE ROM ROMCE Truth Table Mode ROMCE RAMCE OE WE D0 - D7 Supply Current Standby H H X X High Z ISB, ISB1 Output Disable L H H X High Z ICCR ROM Read L H L X DOUT ICCR Output Disable H L H H High Z ICCS SRAM Read H L L H DOUT ICCS SRAM Write H L X L DIN ICCS Notes: 1. X = H or L 2. A15 - A17 are only valid for ROM. 3. In case that ROMCE and RAMCE are "L" at the same time, both ROM and SRAM will be disabled. (November, 1998, Version 2.1) 2 AMIC Technology, Inc. A26E001A Recommended DC Operating Conditions Symbol (TA = -25°C to + 85°C) Parameter Min. Typ. Max. Unit 1.8 3.0 3.3 V 0 0 0 V VCC Supply Voltage GND Ground VIH Input High Voltage VCC x 0.7 - VCC + 0.3 V VIL Input Low Voltage -0.3 - VCC x 0.3 V Absolute Maximum Ratings* *Comments VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . . . -25°C to +85°C Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . . . 260°C, 10 sec Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol Parameter (TA = -25°C to + 85°C, VCC = 1.8V to 3.3V) Min. Max. Unit Conditions ILI Input Leakage Current - 1 µA VIN = GND to VCC ILO Output Leakage Current - 1 µA VI/O = GND to VCC ICCR ROM Operating Current - 4 mA Min. Cycle, Duty = 100% ROMCE = VIL and RAMCE = VIH, II/O = 0mA, VIN = VCC or GND ICCS SRAM Operating Current - 4 mA Min. Cycle, Duty = 100% ROMCE = VIH and RAMCE = VIL, II/O = 0mA, VIN = VCC or GND - 50 µA ROMCE = VIH and RAMCE = VIH - 10 µA ROMCE ≥ VCC - 0.2V and ISB ISB1 Standby Supply Current RAMCE ≥ VCC - o.2V VOL Output Low Voltage - 0.4 V IOL = 200µA VOH Output High Voltage VCC - 0.4 - V IOH = -200µA (November, 1998, Version 2.1) 3 AMIC Technology, Inc. A26E001A Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit CI* Input Capacitance 6 pF CO* Input/Output Capacitance 8 pF Conditions TA = 25°C f = 1.0MHz * These parameters are sampled and not 100% tested. AC Characteristics (ROM/SRAM Selection) Symbol (TA = -25°C to +85°C, VCC = 1.8V to 3.3V) Parameter Min. Max. Unit tRTS ROMCE Disable to RAMCE Enable Time 10 - ns tSTR RAMCE Disable to ROMCE Enable Time 10 - ns AC Characteristics (ROM Selected) Symbol (TA = -25°C to +85°C, VCC = 1.8V to 3.3V) Parameter Min. Max. Unit 500 - ns tRC Read Cycle Time tAA Address Access Time - 450 ns tACE ROMCE Chip Enable Access Time - 450 ns tOE Output Enable to Output Valid - 200 ns tCLZ ROMCE Chip Enable to Output in Low Z 10 - ns tOLZ Output Enable to Output in Low Z 10 - ns tCHZ ROMCE Chip Disable to Output in High Z - 100 ns tOHZ Output Disable to Output in High Z - 100 ns tOH Output Hold from Address Change 10 - ns Notes: tCHZ, and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. (November, 1998, Version 2.1) 4 AMIC Technology, Inc. A26E001A AC Characteristics (SRAM Selected) Symbol (TA = -25°C to +85°C, VCC = 1.8V to 3.3V) Parameter Min. Max. Unit 500 - ns Read Cycle tRC Read Cycle Time tAA Address Access Time - 450 ns tACE RAMCE Chip Enable Access Time - 450 ns tOE Output Enable to Output Valid - 200 ns tCLZ RAMCE Chip Enable to Output in Low Z 10 - ns tOLZ Output Enable to Output in Low Z 10 - ns tCHZ RAMCE Chip Disable to Output in High Z - 100 ns tOHZ Output Disable to Output in High Z - 100 ns tOH Output Hold from Address Change 10 - ns tWC Write Cycle Time 500 - ns tCW RAMCE Chip Enable to End of Write 220 - ns tAS Address Setup Time 0 - ns tAW Address Valid to End of Write 220 - ns tWP Write Pulse Width 200 - ns tWR Write Recovery Time 0 - ns tWHZ Write to Output in High Z - 100 ns tDW Data to Write Time Overlap 100 - ns tDH Data Hold from Write Time 0 - ns tOW Output Active from End of Write 10 - ns Write Cycle Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. (November, 1998, Version 2.1) 5 AMIC Technology, Inc. A26E001A Timing Waveforms (ROM/SRAM Selection) ROMCE tRTS tSTR RAMCE Timing Waveforms (ROM Selected) Read from Address ( ROMCE = Active, OE = Active) tRC ADDRESS INPUTS tAA tOH DATA OUT Read from ROMCE Chip Enable or Output Enable (Address Valid) tACE ROMCE tCHZ tOE OE tOHZ tOLZ DATA OUT tCLZ (November, 1998, Version 2.1) 6 AMIC Technology, Inc. A26E001A Timing Waveforms (SRAM Selected) Read Cycle 1 (1) tRC Address tAA OE tOE tOH tOLZ 5 RAMCE tOHZ 5 tACE tCHZ 5 tCLZ 5 DOUT Read Cycle 2 (1, 2, 4) tRC Address tAA tOH tOH DOUT (November, 1998, Version 2.1) 7 AMIC Technology, Inc. A26E001A Timing Waveforms (SRAM Selected continued) Read Cycle 3 (1, 3, 4) RAMCE tACE tCLZ 5 tCHZ 5 D OUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled, RAMCE = VIL. 3. Address valid prior to or coincident with RAMCE transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. Write Cycle 1(6) (Write Enable Controlled) tWC Address tAW tWR 3 tCW 5 RAMCE (4) tAS1 tWP 2 WE tDW tDH D IN tWHZ 7 tOW 7 D OUT (November, 1998, Version 2.1) 8 AMIC Technology, Inc. A26E001A Timing Waveforms (SRAM Selected continued) Write Cycle 2 (6) (Chip Enable Controlled) tWC Address tWR 3 tAW tCW RAMCE tAS1 5 (4) tWP 2 WE tDW tDH D IN tWHZ 7 D OUT Notes: 1. 2. 3. 4. tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low RAMCE and a low WE . tWR is measured from the earliest of RAMCE or WE going high to the end of the Write cycle. If the RAMCE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of RAMCE going low to the end of Write. 6. OE level is high or low. 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. (November, 1998, Version 2.1) 9 AMIC Technology, Inc. A26E001A AC Test Conditions Input Pulse Levels 0V, VCC Input Rise And Fall Time 3 ns Input and Output Timing Reference Levels VCC/2 Output Load See Figure 1 CL 30pF * Including scope and jig. Figure 1. Output Load Data Retention Characteristics (TA = -25°C to 85°C) Symbol Parameter Min. Max. Unit Conditions VDR VCC for Data Retention 1.6 3.6 V RAMCE ≥ VCC - 0.2V ICCDR Data Retention Current - 3 µA VCC = 1.6V, RAMCE ≥ VCC - 0.2V VIN ≥ 0V tCDR Chip Disable to Data Retention Time 0 - ns tRC - ns tR Operation Recovery Time See Retention Waveform Low VCC Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR RAMCE 3.0V tR VDR ≥ 1.6V VIH VIH RAMCE ≥ VDR - 0.2V (November, 1998, Version 2.1) 10 AMIC Technology, Inc. A26E001A Ordering Information Part No. Access Time (ns) Operation Current Max. (mA) Standby Current Max. (µA) Package A26E001AV 450 4 10 32L TSOP A26E001AX 450 4 10 32L sTSOP (November, 1998, Version 2.1) 11 AMIC Technology, Inc. A26E001A Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm A A1 c E A2 e D θ L LE HD Detail "A" D Detail "A" y S Dimensions in inches Symbol Min Nom Max A - - A1 0.002 - A2 0.037 b 0.007 b Dimensions in mm Min Nom Max 0.047 - - 1.20 0.006 0.05 - 0.15 0.039 0.041 0.95 1.00 1.05 0.009 0.011 0.18 0.22 0.27 c 0.004 - 0.008 0.11 - 0.20 D 0.720 0.724 0.728 18.30 18.40 18.50 E - 0.315 0.319 - 8.00 8.10 e 0.020 BSC 0.50 BSC HD 0.779 0.787 0.795 19.80 20.00 20.20 L 0.016 0.020 0.024 0.40 0.50 0.60 LE - 0.032 - - 0.80 - S - - 0.020 - - 0.50 y - - 0.003 - - 0.08 θ 0° - 5° 0° - 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (November, 1998, Version 2.1) 12 AMIC Technology, Inc. A26E001A Package Information sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions A A1 c E A2 e unit: inches/mm θ L LE D1 D Detail "A" D Detail "A" 0.076MM S b SEATING PLANE Dimensions in inches Symbol Min Nom Max Dimensions in mm Min Nom Max A - - 0.049 - - 1.25 A1 0.002 - - 0.05 - - A2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.008 0.009 0.17 0.20 0.23 c 0.0056 0.0059 0.0062 0.142 0.150 0.158 E 0.311 0.315 0.319 7.90 8.00 8.10 e 0.020 TYP 0.50 TYP D 0.520 0.528 0.535 13.20 13.40 13.60 D1 0.461 0.465 0.469 11.70 11.80 11.90 L 0.012 0.020 0.028 0.30 0.50 0.70 LE 0.0275 0.0315 0.0355 0.700 0.800 0.900 S θ 0.0109 TYP 0° 3° 0.278 TYP 5° 0° 3° 5° Notes: 1. The maximum value of dimension D1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (November, 1998, Version 2.1) 13 AMIC Technology, Inc.