ON FAN6300A Highly integrated quasi-resonant current mode pwm controller Datasheet

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FAN6300A / FAN6300H
Highly Integrated Quasi-Resonant Current Mode
PWM Controller
Features
Description












High-Voltage Startup

Low Frequency Operation (below 100 kHz) for
FAN6300A

High Frequency Operation (up to 190 kHz) for
FAN6300H
Quasi-Resonant Operation
Cycle-by-Cycle Current Limiting
Peak-Current-Mode Control
Leading-Edge Blanking (LEB)
Internal Minimum tOFF
Internal 5 ms Soft-Start
Over Power Compensation
GATE Output Maximum Voltage
Auto-Recovery Over-Current Protection(FB Pin)
Auto-Recovery Open-Loop Protection(FB Pin)
VDD Pin and Output Voltage (DET Pin)
OVP Latched
Applications


The highly integrated FAN6300A/H of PWM controller
provides several features to enhance the performance
of flyback converters. FAN6300A is applied on quasiresonant flyback converters where maximum operating
frequency is below 100 kHz. FAN6300H is suitable for
high-frequency operation (up to 190 kHz). A built-in HV
startup circuit can provide more startup current to
reduce the startup time of the controller. Once the VDD
voltage exceeds the turn-on threshold voltage, the HV
startup function is disabled immediately to reduce power
consumption. An internal valley voltage detector
ensures power system operates at quasi-resonant
operation over a wide-range of line voltage and any load
conditions, as well as reducing switching loss to
minimize switching voltage on drain of power MOSFET.
To minimize standby power consumption and light-load
efficiency, a proprietary green-mode function provides
off-time modulation to decrease switching frequency
and perform extended valley voltage switching to keep
to a minimum switching voltage. The operating
frequency is limited by minimum toff time, which is 38 µs
to 8 µs in FAN6300A and 13 µs to 3 µs in FAN6300H,
so FAN6300H can operate at higher switching
frequency than FAN6300A.
FAN6300A/H controller also provides many protection
functions. Pulse-by-pulse current limiting ensures the
fixed-peak current limit level, even when a short circuit
occurs. Once an open-circuit failure occurs in the
feedback loop, the internal protection circuit disables
PWM output immediately. As long as VDD drops below the
turn-off threshold voltage, the controller also disables
PWM output. The gate output is clamped at 18 V to
protect the power MOS from high gate-source voltage
conditions. The minimum tOFF time limit prevents the
system frequency from being too high. If the DET pin
triggers OVP, internal OTP is triggered and the power
system enters latch-mode until AC power is removed.
The FAN6300A/H controller is available in the 8-pin
Small Outline Package (SOP).
AC/DC NB Adapters
Open-Frame SMPS
Ordering Information
Part Number
FAN6300AMY
FAN6300HMY
Operating Temperature Range
Package
Packing Method
-40°C to +125°C
8-Lead, Small Outline Package (SOP)
Tape & Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html
© 2009 Fairchild Semiconductor Corporation
FAN6300A/H • Rev. 1.0.2
www.fairchildsemi.com
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
January 2014
Figure 1. Typical Application
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.2
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Application Diagram
www.fairchildsemi.com
2
HV
VDD
8
6
4 .2V
2
FB
27 V
2R
Soft -Start
5ms
T im er
52 m s
R
Internal
Bias
OVP
IH V
Latched
T w o Steps
U VLO
16 V/10 V/ 8V
F B OLP
2 .1m s
30 µs
Starter
3
CS
D RV
Blanking
C ircuit
S
PW M
C ur rent Lim it
Over-Pow er
C om pensation
R
ID ET
SE T
C LR
5
Q
Q
18 V
Latched
0.3 V
tO F F - M IN
Valley
D etector
V D ET
tO F F
Blanking
S/ H
tT IM E -O U T
V D ET
Latched
2. 5V
D ET OVP
DET
1
5V
I D ET
Internal
OT P
0 .3 V
Latched
4
7
GN D
NC
Figure 2. Functional Block Diagram
Marking Information
ZXYTT
6300A
TPM
GA T E
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Internal Block Diagram
: Fairchild Logo
Z: Plant Code
X: Year Code
Y: Week Code
TT: Die Run Code
T: Package Type (M = SOP)
P: Y = Green Package
M: Manufacturing Flow Code
ZXYTT
6300H
TPM
Figure 3. Marking Diagram
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.2
www.fairchildsemi.com
3
Figure 4. Pin Configuration
Pin Definitions
Pin #
1
Name
DET
Description
This pin is connected to an auxiliary winding of the transformer via resistors of the divider for
the following purposes:
- Generates a ZCD signal once the secondary-side switching current falls to zero.
- Produces an offset voltage to compensate the threshold voltage of the peak current limit to
provide a constant power limit. The offset is generated in accordance with the input voltage
when PWM signal is enabled.
- Detects the valley voltage of the switching waveform to achieve the valley voltage switching
and minimize the switching losses.
A voltage comparator and a 2.5 V reference voltage develop a output OVP protection. The ratio
of the divider decides what output voltage to stop gate, as an optical coupler and secondary
shunt regulator are used.
2
FB
The feedback pin should to be connected to the output of the error amplifier for achieving the
voltage control loop. The FB should be connected to the output of the optical coupler if the
error-amplifier is equipped at the secondary-side of the power converter.
For the primary-side control application, FB is applied to connect a RC network to the ground
for feedback-loop compensation.
The input impedance of this pin is a 5 kΩ equivalent resistance. A 1/3 attenuator connected
between the FB and the PWM circuit is used for the loop-gain attenuation. FAN6300A/H
performs an open-loop protection once the FB voltage is higher than a threshold voltage
(around 4.2 V) more than 55 ms.
3
CS
Input to the comparator of the over-current protection. A resistor senses the switching current
and the resulting voltage is applied to this pin for the cycle-by-cycle current limit.
4
GND
The power ground and signal ground. A 0.1 µF decoupling capacitor placed between VDD and
GND is recommended.
5
GATE
Totem-pole output generates the PWM signal to drive the external power MOSFET. The
clamped gate output voltage is 18 V.
6
VDD
7
NC
No connect
8
HV
High-voltage startup.
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Pin Configuration
Power supply. The threshold voltages for startup and turn-off are 16 V and 10 V, respectively.
The startup current is less than 20 µA and the operating current is lower than 4.5 mA.
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.2
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
DC Supply Voltage
30
V
VHV
HV
500
V
VH
GATE
-0.3
25.0
V
-0.3
VL
VFB, VCS, VDET
7.0
V
PD
Power Dissipation
400
mW
TJ
Operating Junction Temperature
+150
°C
TSTG
TL
ESD
+150
°C
Lead Temperature (Soldering 10 Seconds)
Storage Temperature Range
-55
+270
°C
Human Body Model, JEDEC:JESD22-A114
3.0
Charged Device Model, JEDEC:JESD22-C101
1.5
KV
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Conditions
Operating Ambient Temperature
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.2
Min.
-40
Typ.
Max.
Unit
+125
°C
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Absolute Maximum Ratings
www.fairchildsemi.com
5
Unless otherwise specified, VDD=10~25 V, TA=-40°C~125°C (TA=TJ).
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
25
V
V
VDD Section
VOP
Continuously Operating Voltage
VDD-ON
Turn-On Threshold Voltage
15
16
17
VDD-PWM-OFF
PWM Off Threshold Voltage
9
10
11
V
VDD-OFF
Turn-Off Threshold Voltage
7
8
9
V
IDD-ST
Startup Current
VDD=VDD-ON -0.16 V
GATE Open
10
20
µA
IDD-OP
Operating Current
VDD=15 V, fS=60 KHz,
CL=2 nF
4.5
5.5
mA
Green-Mode Operating Supply Current
(Average)
VDD=15 V, fS=2 KHz,
CL=2 nF
3.5
mA
Operating Current at PWM-Off Phase
VDD=VDD-PWM-OFF-0.5 V
90
µA
IDD-GREEN
IDD-PWM-OFF
70
80
VDD-OVP
VDD Over-Voltage Protection (Latch-Off)
26
27
28
V
tVDD-OVP
VDD OVP Debounce Time
100
150
200
µs
IDD-LATCH
VDD OVP Latch-Up Holding Current
VDD=5 V
42
µA
HV Startup Current Source Section
VHV-MIN
Minimum Startup Voltage on Pin HV
IHV
Supply Current Drawn from Pin HV
VAC=90 V(VDC=120V)
VDD=0 V
Leakage Current After Startup
HV=500 V,
VDD=VDD-OFF +1 V
IHV-LC
50
V
4.0
mA
1
20
µA
1/2.75
1/3.00
1/3.25
V/V
3
5
7
KΩ
1.2
2
mA
1.5
Feedback Input Section
AV =∆VCS/∆VFB
AV
Input-Voltage to Current Sense
Attenuation
ZFB
Input Impedance
IOZ
Bias Current
VOZ
Zero Duty-Cycle Input Voltage
0.8
1.0
1.2
V
VFB-OLP
Open Loop Protection Threshold Voltage
3.9
4.2
4.5
V
tD-OLP
Debounce Time for Open-Loop/Overload
Protection
46
52
62
ms
tSS
0<VCS<0.9
FB=VOZ
Internal Soft-Start Time
5
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Electrical Characteristics
ms
Continued on the following page...
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.2
www.fairchildsemi.com
6
Unless otherwise specified, VDD=10~25 V, TA=-40°C ~125°C (TA=TJ).
Symbol
Parameter
Conditions
Min.
Typ.
Max.
2.45
2.50
2.55
Unit
DET Pin OVP and Valley Detection Section
VDET-OVP
Comparator Reference Voltage
(3)
Av
Open-Loop Gain
Bw
Gain Bandwidth
(3)
VV-HIGH
Output High Voltage
VV-LOW
Output Low Voltage
tDET-OVP
Output OVP (Latched) Debounce Time
IDET-SOURCE
Maximum Source Current
VDET=0 V
VDET-HIGH
Upper Clamp Voltage
IDET=-1 mA
VDET-LOW
Lower Clamp Voltage
IDET=1 mA
tVALLEY-DELAY
Delay Time from Valley-Signal Detected to
(3)
Output Turn-On
tOFF-BNK
Leading-Edge-Blanking Time for DET when
(3)
PWM MOS Turns Off
tTIME-OUT
Time-Out after tOFF-MIN
dB
1
MHz
4.5
100
0.1
V
60
V
150
0.5
V
200
µs
1
mA
5
V
0.3
V
200
ns
FAN6300A
4.0
FAN6300H
1.5
FAN6300A
9
FAN6300H
5
µs
µs
Oscillator Section
tON-MAX
tOFF-MIN
Maximum On-Time
38
Minimum Off-Time
45
54
µs
VFB≧VN,
FAN6300A
8
µs
VFB≧VN
FAN6300H
3
µs
VFB=VG
FAN6300A
38
µs
VFB=VG
FAN6300H
13
µs
VN
Beginning of Green-On Mode at FB Voltage
Level
1.95
2.10
2.25
V
VG
Beginning of Green-Off Mode at FB Voltage
Level
1.0
1.2
1.4
V
Green-Off Mode VFB Hysteresis Voltage
0.05
0.10
0.20
V
VFB<VG
1.8
2.1
2.4
ms
VFB>VFB-OLP
25
30
45
µs
1.5
V
∆VFBG
tSTARTER
Start Timer (Time-Out Timer)
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Electrical Characteristics (Continued)
Output Section
VOL
Output Voltage Low
VDD=15 V,
IO=150 mA
VOH
Output Voltage High
VDD=12 V,
IO=150 mA
7.5
V
tR
Rising Time
145
200
ns
tF
Falling Time
55
120
ns
18.0
19.3
V
VCLAMP
Gate Output Clamping Voltage
16.7
Continued on following page…
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.2
www.fairchildsemi.com
7
Unless otherwise specified, VDD=10~25 V, TA=-40°C ~125°C (TA=TJ).
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
20
150
200
ns
IDET < 74.41 µA
0.82
0.85
0.88
V
IDET=550 µA
0.380
0.415
0.450
Current Sense Section
tPD
VLIMIT
VSLOPE
tBNK
Delay to Output
Limit Voltage on CS Pin for Over-Power
Compensation
Slope Compensation
(3)
V
tON=45 µs
0.3
V
tON=0 µs
0.1
V
Leading-Edge-Blanking Time
(MOS Turns ON)
525
VCS-H
VCS Clamped High Voltage once CS Pin
Floating
CS Pin Floating
tCS-H
Delay Time once CS Pin Floating
CS Pin Floating
625
4.5
725
ns
5.0
V
150
µs
+140
°C
+15
°C
Internal Over-Temperature Protection Section
TOTP
TOTP-HYST
Internal Threshold Temperature for OTP
(3)
(3)
Hysteresis Temperature for Internal OTP
Note:
3. Guaranteed by design.
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.2
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Electrical Characteristics(Continued)
www.fairchildsemi.com
8
Graphs are normalized at TA=25°C.
10.00
17.0
9.80
VDD-PWM-OFF(V)
VDD-ON (V)
16.5
16.0
9.60
9.40
15.5
9.20
15.0
-40℃ -25℃ -10℃ 5℃
9.00
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃
o
Temperature( C)
-10℃
5℃
20℃
35℃ 50℃ 65℃
Temperature(°C)
80℃
95℃
110℃ 125℃
Figure 6. PWM-Off Threshold Voltage
8.1
18
8.0
16
7.9
14
IDD-ST(µA)
VDD-OFF (V)
Figure 5. Turn-On Threshold Voltage
-25℃
7.8
12
7.7
10
7.6
8
7.5
6
-40℃ -25℃ -10℃
5℃
-40℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-25℃
-10℃
5℃
20℃
Temperature(oC)
35℃
50℃
65℃
80℃
95℃
110℃ 125℃
Temperature(°C)
Figure 7. Turn-Off Threshold Voltage
Figure 8. Startup Current
4.0
4.50
3.5
4.20
I HV(mA)
IDD-OP(mA)
3.0
3.90
3.60
2.5
2.0
1.5
3.30
1.0
3.00
-40℃
-25℃
-10℃
5℃
20℃
35℃
50℃
65℃
80℃
95℃
110℃
-40℃
125℃
-25℃
-10℃
5℃
20℃
Figure 9. Operating Current
65℃
80℃
95℃
110℃
125℃
0.40
0.31
0.35
0.30
0.29
VDET-LOW (V)
IHV-LC(µA)
50℃
Figure 10. Supply Current Drawn From HV Pin
0.32
0.28
0.27
0.26
0.30
0.25
0.20
0.15
0.25
-40℃ -25℃ -10℃
35℃
Temperature(°C)
Temperature(°C)
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Typical Performance Characteristics
5℃
0.10
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃
Temperature(°C)
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature(oC)
Figure 11. Leakage Current After Startup
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.2
5℃
Figure 12. Lower Clamp Voltage
www.fairchildsemi.com
9
These characteristic graphs are normalized at TA = 25°C.
8.70
2.52
8.40
toff-min(µs)
VDET-OVP(V)
2.51
2.50
2.49
8.10
7.80
2.48
-40℃ -25℃ -10℃
5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
7.50
-40℃ -25℃ -10℃
Temperature(oC)
35℃
50℃
65℃
80℃
95℃ 110℃ 125℃
Figure 14. Minimum Off Time (VFB>VN)
42.0
2.50
40.0
2.40
tSTARTER(ms)
t OFF-MIN(μs)
20℃
Temperature(°C)
Figure 13. Comparator Reference Voltage
38.0
36.0
34.0
2.30
2.20
2.10
2.00
1.90
32.0
-40℃ -25℃ -10℃
5℃
5℃
20℃
35℃
50℃
65℃
-40℃ -25℃ -10℃ 5℃
80℃ 95℃ 110℃ 125℃
Figure 15. Minimum Off Time (VFB=VG)
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.2
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature(°C)
Temperature(oC)
Figure 16. Start Timer (VFB<VG)
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
10
The FAN6300A/H PWM controller integrates designs to
enhance the performance of flyback converters. An
internal valley voltage detector ensures power system
operates at Quasi-Resonant (QR) operation across a
wide range of line voltage. The following descriptions
highlight some of the features of the FAN6300A/H.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load conditions. VFB, which is derived from
the voltage feedback loop, is taken as the reference. In
Figure 19, once VFB is lower than VN, tOFF-MIN increases
linearly with lower VFB. The valley voltage detection
signal does not start until tOFF-MIN finishes. Therefore, the
valley detect circuit is activated until tOFF-MIN finishes,
which decreases the switching frequency and provides
extended valley voltage switching. However, in very light
load condition, it might fail to detect the valley voltage
after the tOFF-MIN expires. Under this condition, an internal
tTIME-OUT signal initiates a new cycle start after a 9 μs
delay (with 5 µs delay for H version). Figure 20 and
Figure 21 show the two different conditions.
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
RHV, which are recommended as 1N4007 and 100 kΩ.
Typical startup current drawn from the HV pin is 1.2 mA
and it charges the hold-up capacitor through the diode
and resistor. When the VDD voltage level reaches VDD-ON,
the startup current switches off. At this moment, the VDD
capacitor only supplies the FAN6300A/H to maintain VDD
until the auxiliary winding of the main transformer
provides the operating current.
tO F F -M I N
2 .1 m s
Valley Detection
The DET pin is connected to an auxiliary winding of the
transformer via resistors of the divider to generate a
valley signal once the secondary-side switching current
discharges to zero. It detects the valley voltage of the
switching waveform to achieve the valley voltage
switching. This ensures QR operation, minimizes
switching losses, and reduces EMI. Figure 17 shows
divider resistors RDET and RA. RDET is recommended as
150 kΩ to 220 kΩ to achieve valley voltage switching.
When VAUX (in Figure 17) is negative, the DET pin
voltage is clamped to 0.3 V.
38/13 μ s
8 /3μ s
1 .2 V
VFB
2 .1 V
Figure 19. VFB vs. tOFF-MIN Curve
Figure 17. Valley Detect Section
The internal timer (minimum tOFF time) prevents gate
retriggering within 8 µs (3 µs for H version) after the gate
signal going-low transition. The minimum tOFF limit
prevents system frequency being too high. Figure 18
shows a typical drain voltage waveform with first valley
switching.
Figure 20. QR Operation in Extended Valley Voltage
Detection Mode
Figure 21. Internal tTIME-OUT Initiates New Cycle After
Failure to Detect Valley Voltage
(with 5 µs Delay for FAN6300H version)
Figure 18. First Valley Switching
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.2
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Operation Description
www.fairchildsemi.com
11
VDD Over-Voltage Protection
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the CS
pin. The PWM duty cycle is determined by this currentsense signal and VFB. When the voltage on CS reaches
around VLIMIT = (VFB-1.2)/3, the switch cycle is terminated
immediately. VLIMIT is internally clamped to a variable
voltage around 0.85 V for output power limit.
VDD over-voltage protection prevents damage due to
abnormal conditions. Once the VDD voltage is over the
VDD over-voltage protection voltage (VDD-OVP) and lasts
for tVDDOVP, the PWM pulse is disabled until the VDD
voltage drops below the UVLO, then starts again.
Output Over-Voltage Protection
The output over-voltage protection works by the
sampling voltage, as shown in Figure 23, after switch-off
sequence. A 4 μs (1.5 μs for H version) blanking time
ignores the leakage inductance ringing. A voltage
comparator and a 2.5 V reference voltage develop an
output OVP protection. The ratio of the divider
determines the sampling voltage of the stop gate, as an
optical coupler and secondary shunt regulator are used.
If the DET pin OVP is triggered, the power system enters
latch-mode until AC power is removed.
Leading-Edge Blanking (LEB)
Each time the power MOFFET switches on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, lead-edge blanking time
is built in. During the blanking period, the current limit
comparator is disabled; it cannot switch off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on, PWM-off, and turn-off thresholds are fixed
internally at 16/10/8 V. During startup, the startup
capacitor must be charged to 16 V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply VDD until energy can be delivered
from the auxiliary winding of the main transformer. VDD
must not drop below 10 V during this startup process.
This UVLO hysteresis window ensures that hold-up
capacitor is adequate to supply VDD during startup.
Gate Output
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18 V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.
Figure 23. Voltage Sampled After 4μs
(1.5 μs for FAN6300H version) Blanking Time
After Switch-Off Sequence
Over-Power Compensation
Short-Circuit and Open-Loop Protection
To compensate this variation for wide AC input range,
the DET pin produces an offset voltage to compensate
the threshold voltage of the peak current limit to provide
a constant-power limit. The offset is generated in
accordance with the input voltage when PWM signal is
enabled. This results in a lower current limit at high-line
inputs than low-line inputs. At fixed-load condition, the
CS limit is higher when the value of RDET is higher. RDET
also affects the H/L line constant power limit.
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than tDOLP, PWM output is turned off. As PWM output is turnedoff, the supply voltage VDD begins decreasing.
FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Current Sensing and PWM Current Limiting
When VDD goes below the PWM-off threshold of 10 V,
VDD decreases to 8 V, then the controller is totally shut
down. VDD is charged up to the turn-on threshold voltage
of 16 V through the startup resistor until PWM output is
restarted. This protection feature continues as long as
the overloading condition persists. This prevents the
power supply from overheating due to overloading.
Figure 22. H/L Line Constant Power Limit
Compensated by DET Pin
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.2
www.fairchildsemi.com
12
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