Maxim MAX7036 300mhz to 450mhz ask receiver with internal if filter Datasheet

19-4386; Rev 1; 8/10
KIT
ATION
EVALU
E
L
B
A
IL
AVA
300MHz to 450MHz ASK Receiver
with Internal IF Filter
o < 250µs Enable Turn-On Time
o On-Chip PLL, VCO, Mixer, IF, Baseband
o Low IF (200kHz Nominal)
o 5.5mA DC Current
o 1µA Standby Current
o 3.3V/5V Operation
o Small 20-Pin Thin QFN Package with an Exposed
Pad
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX7036GTP/V+
-40°C to +105°C
20 Thin QFN-EP*
/Vdenotes an automative qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
IFC3
Low-Cost RKE
DVDD
TOP VIEW
Applications
DCOC
Pin Configuration
OPP
The MAX7036 is available in a 20-pin thin QFN package with an exposed pad and is specified over the
AEC-Q100 Level 2 (-40°C to +105°C) temperature
range.
o ASK/OOK Modulation
DFFB
The MAX7036 low-cost receiver is designed to receive
amplitude-shift-keyed (ASK) and on-off-keyed (OOK)
data in the 300MHz to 450MHz frequency range. The
receiver has an RF input signal range of -109dBm to
0dBm.
The MAX7036 requires few external components and
has a power-down pin to put it in a low-current sleep
mode, making it ideal for cost- and power-sensitive
applications. The low-noise amplifier (LNA), phaselocked loop (PLL), mixer, IF filter, received-signalstrength indicator (RSSI), and baseband sections are
all on-chip. The MAX7036 uses a very-low intermediate
frequency (VLIF) architecture. The MAX7036 integrates
the IF filter on-chip and therefore eliminates an external
ceramic filter, reducing the bill-of-materials cost. The
device also contains an on-chip automatic gain control
(AGC) that reduces the LNA gain by 30dB when the
input signal power is large. The MAX7036 operates
from either a 5V or a 3.3V power supply and draws
5.5mA (typ) of current.
Features
15
14
13
12
11
Garage Door Openers
10
IFC1
DSN 17
9
IFC2
8
MIXIN1
7
MIXIN2
6
LNAOUT
Security Systems
VDD 19
DATAOUT 20
MAX7036
EP
+
ENABLE
1
2
3
4
5
LNAIN
PDOUT 18
AVDD
Sensor Networks
XTAL1
Home Automation
DSP 16
XTAL2
Remote Controls
THIN QFN
5mm x 5mm
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX7036
General Description
MAX7036
300MHz to 450MHz ASK Receiver
with Internal IF Filter
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +6.0V
AVDD to GND........................................................-0.3V to +4.0V
DVDD to GND........................................................-0.3V to +4.0V
ENABLE to GND.........................................-0.3V to (VDD + 0.3V)
LNAIN to GND .......................................................-0.3V to +1.2V
All Other Pins to GND.............................-0.3V to (VDVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
20-Pin TQFN (derate 20.8mW/°C above +70°C) ....1666.7mW
Junction-to-Case Thermal Resistance (θJC) (Note 1)
20-Pin TQFN...................................................................2°C/W
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
20-Pin TQFN.................................................................48°C/W
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a singlelayer board. For detailed information on package thermal considerations, go to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
3.3V DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VDD = 3.0V to 3.6V, fRF = 300MHz to 450MHz, TA = -40°C to
+105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD = 3.3V, TA = +25°C, unless otherwise noted.) (100%
tested at TA = +105°C.)
PARAMETER
Supply Voltage
Supply Current
SYMBOL
VDD
IIN
CONDITIONS
VAVDD = VDVDD = VDD
TA < +105°C
MIN
TYP
MAX
UNITS
3.0
V
3.3
3.6
fRF = 315MHz
5.3
6.7
fRF = 433MHz
5.8
7.3
1
2.7
Deep-sleep mode,
VENABLE = 0V
mA
µA
DIGITAL INPUT (ENABLE)
VDD 0.4
V
Input High Voltage
VIH
VAVDD = VDVDD = VDD
Input Low Voltage
VIL
VAVDD = VDVDD = VDD
0.4
V
0 ≤ VENABLE ≤ VDD
20
µA
0.4
V
Input Current
IENABLE
DIGITAL OUTPUT (DATAOUT)
Output Low Voltage
VOL
ISINK = 100µA
Output High Voltage
VOH
ISOURCE = 100µA
2
VDD 0.4
_______________________________________________________________________________________
V
300MHz to 450MHz ASK Receiver
with Internal IF Filter
(Typical Application Circuit, 50Ω system impedance, VDD = 4.5V to 5.5V, fRF = 300MHz to 450MHz, TA = -40°C to +105°C, unless
otherwise noted. Typical values are at VDD = 5.0V, TA = +25°C, unless otherwise noted.) (100% tested at TA = +105°C.)
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4.5
5.0
5.5
V
fRF = 315MHz
5.4
6.8
fRF = 433MHz
5.9
7.4
1
3.4
VDD
Supply Current
IIN
TA < +105°C
Deep-sleep mode,
VENABLE = 0V
mA
µA
DIGITAL INPUT (ENABLE)
VDD 0.4
V
Input High Voltage
VIH
VAVDD = VDVDD
Input Low Voltage
VIL
VAVDD = VDVDD
0.4
V
0 ≤ VENABLE ≤ VDD
20
µA
0.4
V
Input Current
IENABLE
DIGITAL OUTPUT (DATAOUT)
Output Low Voltage
VOL
ISINK = 100µA
Output High Voltage
VOH
ISOURCE = 100µA
VDD 0.4
V
AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VDD = 3.0V to 3.6V, fRF = 300MHz to 450MHz, TA = -40°C to
+105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD = 3.3V, TA = +25°C, fRF = 315MHz, unless otherwise
noted.) (100% tested at TA = +105°C.)
PARAMETER
SYMBOL
Receiver Input Frequency Range
fRF
Maximum Receiver Input Level
CONDITIONS
TYP
300
PRFIN
Sensitivity (Note 2)
MIN
0
fRF = 315MHz
-109
fRF = 433MHz
-107
Time for valid RSSI
output, does not
include baseband
filter settling
Enable power on
(VDD > 3.0V)
MAX
UNITS
450
MHz
dBm
dBm
250
µs
1
ms
AGC Hysteresis
5
dB
AGC Low Gain-to-High Gain
Switching Time
13
ms
Power-On Time
tON
VDD power on
_______________________________________________________________________________________
3
MAX7036
5.0V DC ELECTRICAL CHARACTERISTICS
MAX7036
300MHz to 450MHz ASK Receiver
with Internal IF Filter
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VDD = 3.0V to 3.6V, fRF = 300MHz to 450MHz, TA = -40°C to
+105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD = 3.3V, TA = +25°C, fRF = 315MHz, unless otherwise
noted.) (100% tested at TA = +105°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LNA/MIXER
LNA Input Impedance
ZINLNA
fRF = 315MHz
0.4 j5.6
fRF = 433MHz
0.4 j4.0
LO Signal Feedthrough to
Antenna
Voltage Gain Reduction
LNA/Mixer Voltage Gain
3dB Cutoff Frequency
BWIF
-75
dBm
Low-gain mode, AGC enabled
29
dB
High-gain LNA mode
55
Low-gain LNA mode
26
Set by capacitors on IFC1 and IFC2 (see
the Typical Application Circuit)
400
kHz
±0.5
dB
80
dB
RSSI Linearity
RSSI Dynamic Range
Includes AGC
RSSI Level
Intermediate Frequency
Ω
Normalized to 50Ω
PRFIN < -120dBm
1.34
PRFIN > 0dBm, AGC enabled
2.35
dB
V
fIF
200
kHz
Maximum Data-Filter Bandwidth
BWDF
50
kHz
Maximum Data-Slicer Bandwidth
BWDS
100
kHz
50
kHz
Maximum Peak Detector
Bandwidth
Maximum Data Rate
Crystal Frequency
Crystal Load Capacitance
Manchester coded
33
Nonreturn to zero (NRZ)
66
fXTAL
CLOAD
9.36
14.06
10
Note 2: BER = 2 x 10-3, Manchester coded, data rate = 4kbps. IF bandwidth = 400kHz.
4
kbps
_______________________________________________________________________________________
MHz
pF
300MHz to 450MHz ASK Receiver
with Internal IF Filter
TA = +85°C
TA = +105°C
5.1
TA = +25°C
5.0
TA = +85°C
5.30
5.25
5.20
TA = +25°
5.15
5.10
4.9
TA = -40°C
TA = -40°C
3.4
3.5
TA = +85°C
TA = +105°C
5.5
5.0
TA = +25° T = -40°C
A
4.0
4.5
3.6
4.7
4.9
5.1
250
5.5
5.3
300
BIT ERROR RATE vs. PEAK RF
INPUT POWER
fRF = 433MHz
BER = 0.2%
-106.5 DATA RATE = 4kbps
MANCHESTER
-107.0
SENSITIVITY (dBm)
10
fRF = 315MHz
1
0.1
400
450
500
RSSI vs. INPUT POWER
SENSITIVITY vs. TEMPERATURE
-106.0
MAX7036 toc04
100
350
RF FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
2.4
2.2
fRF = 433MHz
fIF = 200kHz
2.0
-107.5
RSSI (V)
3.3
MAX7036 toc05
3.2
6.0
4.5
5.00
3.1
SUPPLY VOLTAGE (V)
BIT ERROR RATE (%)
6.5
5.05
4.8
3.0
MAX7036 toc03
TA = +105°C
5.35
PRF = -80dBm
MAX7036 toc06
5.2
5.0V APPLICATION CIRCUIT
5.40
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
5.3
SUPPLY CURRENT vs. RF FREQUENCY
7.0
SUPPLY CURRENT (mA)
VAVDD = VDVDD = VDD
5.4
5.45
MAX7036 toc01
5.5
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(5.0V OPERATION)
MAX7036 toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(3.3V OPERATION)
-108.0
fRF = 433MHz
-108.5
fRF = 315MHz
1.8
1.6
-109.0
-109.5
0.01
1.4
-110.0
-110.5
-120
-115
-110
-40
-15
10
35
60
85
105
1.2
-120
-100
-80
-60
-40
-20
TEMPERATURE (°C)
INPUT POWER (dBm)
LNA/MIXER VOLTAGE GAIN
vs. IF FREQUENCY
S11 SMITH CHART PLOT OF RFIN
(315MHz CIRCUIT)
S11 SMITH CHART PLOT OF RFIN
(433MHz CIRCUIT)
fRF = 433.92MHz
56
MAX7036 toc08
PRF = -71dBm
58
0
MAX7036 toc09
PEAK RF INPUT POWER (dBm)
60
LNA/MIXER VOLTAGE GAIN (dB)
-105
MAX7036 toc07
0.001
-125
54
52
50
48
S11 = 7.9729Ω - j0.6085Ω
at fRF = 315MHz
46
S11 = 6.5175Ω - j5.5849Ω
at fRF = 433MHz
44
42
40
0
200
400
600
800
1000
IF FREQUENCY (kHz)
_______________________________________________________________________________________
5
MAX7036
Typical Operating Characteristics
(Typical Application Circuit, VAVDD = VDD = VDVDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Typical Application Circuit, VAVDD = VDD = VDVDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.)
TA = +25°C
TA = -40°C
MAX7036 toc11
-60
-70
-80
-90
-100
0
5
10
15
20
REGULATOR CURRENT (mA)
25
-120
0.01
fRF = 433MHz
-60
-70
-80
-90
-100
-110
-110
3.00
-50
PHASE NOISE (dBc/Hz)
3.10
3.05
fRF = 315MHz
PHASE NOISE (dBc/Hz)
VDD = 5V, +5V CIRCUIT
TA = +105°C
TA = +85°C
-50
MAX7036 toc10
3.15
PHASE NOISE
vs. OFFSET FREQUENCY
PHASE NOISE
vs. OFFSET FREQUENCY
MAX7036 toc12
REGULATOR VOLTAGE
vs. REGULATOR CURRENT
REGULATOR VOLTAGE (V)
MAX7036
300MHz to 450MHz ASK Receiver
with Internal IF Filter
0.1
1
10
100
1000 10,000
OFFSET FREQUENCY (kHz)
-120
0.01
0.1
1
10
100
1000 10,000
OFFSET FREQUENCY (kHz)
Pin Description
6
PIN
NAME
1
ENABLE
FUNCTION
Enable Input. Internally pulled down to ground. Set VENABLE = VDD for normal operation.
2
XTAL2
Crystal Input 2. Connect an external crystal from XTAL2 to XTAL1. Bypass to GND if XTAL1 is driven
from an AC-coupled external reference (see the Crystal Oscillator section).
3
XTAL1
Crystal Input 1. Connect an external crystal from XTAL2 to XTAL1. Can also be driven with an ACcoupled external reference oscillator (see the Crystal Oscillator section).
4
AVDD
Positive Analog Supply Voltage. Connect to DVDD. Bypass to GND with a 0.1µF capacitor as close as
possible to the device (see the Typical Application Circuit). For 5.0V operation, AVDD is internally
connected to an on-chip 3.2V LDO regulator. For 3.3V operation, connect AVDD to VDD.
5
LNAIN
Low-Noise Amplifier Input. Must be AC-coupled (see the Low-Noise Amplifier section).
6
LNAOUT
7
MIXIN2
2nd Differential Mixer Input. Connect to the LNAOUT side of the LC tank filter through a 100pF
capacitor (see the Typical Application Circuit).
8
MIXIN1
1st Differential Mixer Input. Connect to the AVDD side of the LC tank filter through a 100pF capacitor
(see the Typical Application Circuit).
9
IFC2
IF Filter Capacitor Connection 2. This is for the Sallen-Key IF filter. Connect a capacitor from IFC2 to GND.
The value of the capacitor is determined by the IF filter bandwidth (see the Typical Application Circuit).
10
IFC1
IF Filter Capacitor Connection 1. This is for the Sallen-Key IF filter. Connect a capacitor from IFC1 to IFC3.
The value of the capacitor is determined by the IF filter bandwidth (see the Typical Application Circuit).
11
IFC3
IF Filter Capacitor Connection 3. This is for the Sallen-Key IF filter. Connect a capacitor from IFC3 to IFC1.
The value of the capacitor is determined by the IF filter bandwidth (see the Typical Application Circuit).
12
DVDD
Positive Digital Supply Voltage Input. Connect to AVDD. Bypass to GND with a 0.01µF capacitor as
close as possible to the device (see the Typical Application Circuit).
Low-Noise Amplifier Output. Must be connected to AVDD through a parallel LC tank circuit. ACcouple to MIXIN2 (see the Low-Noise Amplifier section).
_______________________________________________________________________________________
300MHz to 450MHz ASK Receiver
with Internal IF Filter
PIN
NAME
FUNCTION
13
DCOC
DC Offset Capacitor Connection. This is for the RSSI amplifier. Connect a 1µF capacitor from this pin
to ground (see the Typical Application Circuit).
14
OPP
Noninverting Op-Amp Input. This is for the Sallen-Key data filter. Connect a capacitor from this pin to
GND. The value of the capacitor is determined by the data-filter bandwidth.
15
DFFB
Data-Filter Feedback Input. Input for the feedback of the Sallen-Key data filter. Connect a capacitor
from this pin to DSP. The value of the capacitor is determined by the data-filter bandwidth.
16
DSP
Positive Data-Slicer Input. Connect a capacitor from this pin to DFFB. The value of the capacitor is
determined by the data-filter bandwidth.
17
DSN
Negative Data-Slicer Input
18
PDOUT
19
VDD
20
DATAOUT
—
EP
Peak-Detector Output
Power-Supply Voltage Input. For 5.0V operation, VDD is the input to an on-chip voltage regulator
whose 3.2V output drives AVDD. Bypass to ground with a 0.1µF capacitor as close as possible to the
device (see the Typical Application Circuit).
Digital Baseband Data Output
Exposed Pad. Internally connected to ground. Connect to a large ground plane using multiple vias to
maximize thermal and electrical performance.
Functional Diagram
DATAOUT
20
DSN
17
PDOUT
18
DSP
16
OPP
14
DFFB
15
XTAL1 3
PEAK
DETECTOR
MAX7036
PLL
XTAL2 2
ENABLE 1
VDD 19
3.2V
REGULATOR
AVDD 4
DVDD 12
∑
EP*
AGC
REF
∑
LNAIN 5
REF
6
8 7
LNAOUT
MIXIN2
MIXIN1
10
IFC1
9
IFC2
11
IFC3
13
DCOC
*EXPOSED PAD.
CONNECT TO GND.
_______________________________________________________________________________________
7
MAX7036
Pin Description (continued)
MAX7036
300MHz to 450MHz ASK Receiver
with Internal IF Filter
Detailed Description
The MAX7036 CMOS RF receiver, and a few external
components, provide the complete receiver chain from
the antenna to the digital output data. Depending on
signal power and component selection, data rates as
high as 33kbps Manchester (66kbps NRZ) can be
achieved.
The MAX7036 is designed to receive binary ASK/OOK
data modulated in the 300MHz to 450MHz frequency
range. ASK modulation uses a difference in amplitude
of the carrier to represent digital data.
Automatic Gain Control (AGC)
The AGC circuit monitors the RSSI output. The AGC
switches to its low-gain state when the RSSI output
reaches 2.2V. The AGC gain reduction is typically
29dB, corresponding to an RSSI voltage drop of
435mV. The LNA resumes high-gain mode when the
RSSI level drops back below 1.67V for 13ms for
315MHz and 10ms for 433MHz operation. The AGC has
a hysteresis of 5dB. With this AGC function, the
MAX7036 can reliably produce an ASK output for RF
input levels up to 0dBm, with modulation depth of
30dB.
Voltage Regulator
Mixer
For operation with a single 3.0V to 3.6V supply voltage,
connect AVDD, DVDD, and VDD to the supply voltage.
For operation with a single 4.5V to 5.5V supply voltage,
connect VDD to the supply voltage. An on-chip voltage
regulator drives the AVDD pin to approximately 3.2V.
For proper operation, connect DVDD and AVDD together. Bypass VDD and AVDD to GND with 0.1µF capacitors placed as close as possible to the device. Bypass
DVDD to GND with a 0.01µF capacitor (see the Typical
Application Circuit).
The mixer cell is a double-balanced mixer that performs
a downconversion of the RF input to a typical IF of
200kHz from either a high-side or a low-side injected LO.
The mixer output drives the input of the on-chip IF filter.
Low-Noise Amplifier
The LNA is an nMOS cascode amplifier. The LNA and
mixer have a combined 55dB voltage gain. The gain
and noise figures are dependent on both the antennamatching network at the LNA input and the LC tank network between the LNA output and the mixer inputs.
L2 and C1 comprise the LC tank filter connected to
LNAOUT (see the Typical Application Circuit). L2 also
serves as a bias inductor to LNAOUT. Bypass the
power-supply side of L2 to GND with a capacitor that
provides a low-impedance path at the RF carrier frequency (e.g., 220pF). Select L2 and C1 to resonate at
the desired RF input frequency. The resonant frequency is given by:
fRF =
1
2π L TOTAL × CTOTAL
where LTOTAL = L2 + LPARASITICS and CTOTAL = C1 +
CPARASITICS.
LPARASITICS and CPARASITICS include inductance and
capacitance of the PCB traces, package pins, mixer
input impedance, LNA output impedance, etc. At high
frequencies, these parasitics can have a dramatic
effect on the tank filter center frequency and must not
be ignored. The total parasitic capacitance is generally
4pF to 6pF. Adjust L2 and C1 accordingly to achieve
the desired tank center frequency.
8
Phase-Locked Loop (PLL)
The PLL block contains a phase detector, charge pump,
integrated loop filter, VCO, asynchronous clock dividers,
and crystal-oscillator driver. Besides the crystal, this PLL
does not require any external components. The VCO
generates the LO. The relationship between the RF, IF,
and crystal reference frequencies is given by:
f XTAL =
fLO
32
where fLO = fRF ± fIF
Received-Signal-Strength Indicator (RSSI)
The RSSI circuit provides a DC output proportional to
the logarithm of the input power level. RSSI output voltage has a slope of about 14.5mV/dB (of input
power).The RSSI monotonic dynamic range exceeds
80dB. This includes the 30dB of AGC.
Applications Information
Crystal Oscillator
The crystal (XTAL) oscillator in the MAX7036 is
designed to present a capacitance of approximately
4pF between XTAL1 and XTAL2. In most cases, this
corresponds to a 6pF load capacitance applied to the
external crystal when typical PCB parasitics are added.
The MAX7036 is designed to operate with a typical
10pF load capacitance crystal. It is very important to
use a crystal with a load capacitance equal to the
capacitance of the MAX7036 crystal oscillator plus
PCB parasitics. If a crystal designed to oscillate with a
different load capacitance is used, the crystal is pulled
away from its stated operating frequency, introducing
_______________________________________________________________________________________
300MHz to 450MHz ASK Receiver
with Internal IF Filter
f P=
CM
2
⎛
⎞
1
1
⎜⎜
⎟⎟ × 106
−
C
+
C
C
+
C
⎝ CASE
LOAD
CASE
SPEC ⎠
where:
fp is the amount the crystal frequency is pulled in
ppm.
CM is the motional capacitance of the crystal.
CCASE is the case capacitance.
CSPEC is the specified load capacitance.
CLOAD is the actual load capacitance.
When the crystal is loaded, as specified (i.e., CLOAD =
CSPEC), the frequency pulling equals zero.
It is possible to use an external reference oscillator in
place of a crystal to drive the VCO. AC-couple the external oscillator to XTAL1 with a 1000pF capacitor. Drive
XTAL1 with a signal level of approximately -10dBm. ACcouple XTAL2 to ground with a 1000pF capacitor.
IF Filter
The IF filter is a 2nd-order Butterworth lowpass filter
preceded by a low-frequency DC block. The lowpass
filter is implemented as a Sallen-Key filter using an
internal op amp and two on-chip 22kΩ resistors. The
pole locations are set by the combination of the on-chip
resistors and two external capacitors (C9 and C10,
Figure 1). The values of these two capacitors for a 3dB
cutoff frequency of 400kHz are given below:
C9 =
1
=
1
(1.414)(R)( π ) ( fc ) (1.414)(22kΩ)(3.14) (400kHz )
C10 =
= 26pF
1
1
=
= 13pF
.
22
k
Ω
3.14 )( 400kHz )
2
828
2
828
.
π
R
f
(
)
(
)(
(
)( )( ) ( c )
Because the stray shunt capacitance at each of the
pins (IFC1 and IFC2) on a typical PCB is approximately
2pF, choose the value of the external capacitors to be
approximately 2pF lower than the desired total capacitance. Therefore, the practical values for C9 and C10
are 22pF and 10pF, respectively.
MAX7036
22kΩ
22kΩ
10
IFC1
9
IFC2
11
IFC3
C10
C9
Figure 1. Sallen-Key Lowpass IF Filter
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors
changes the corner frequency to optimize for different
data rates. Set the corner frequency to approximately
1.5 times the fastest Manchester expected data rate
from the transmitter. Keeping the corner frequency near
the data rate rejects any noise at higher frequencies,
resulting in an increase in receiver sensitivity.
The configuration shown in Figure 2 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works with the coefficients in Table 1.
C5 =
b
a (100k )( π ) ( fc )
C6 =
a
4 (100k )( π ) ( fc )
where fC is the desired corner frequency.
_______________________________________________________________________________________
9
MAX7036
an error in the reference frequency. A crystal designed
to operate at a higher load capacitance than the value
specified for the oscillator is always pulled higher in frequency. Adding capacitance to increase the load
capacitance on the crystal increases the start-up time
and may prevent oscillation altogether.
In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
MAX7036
300MHz to 450MHz ASK Receiver
with Internal IF Filter
For example, to choose a Butterworth filter response
with a corner frequency of 6kHz:
C5 =
1.000
(1.414)(100kΩ)(3.14)(6kHz )
C6 =
1.414
(4)(100kΩ)(3.14)(6kHz )
= 375pF
= 186pF
Choosing standard capacitor values changes C5 to
390pF and C6 to 180pF, as shown in the Typical
Application Circuit.
Table 1. Coefficients to Calculate C5
and C6
The suggested data-slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capacitor (C4) from DSN to GND (Figure 3). This configuration
averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts
as the analog signal varies, minimizing the possibility
for errors in the digital data. The values of R1 and C4
affect how fast the threshold tracks to the analog amplitude. Be sure to keep the corner frequency of the RC
circuit much lower than the lowest expected data rate.
MAX7036
FILTER TYPE
a
b
Butterworth (Q = 0.707)
1.414
1.000
Bessel (Q = 0.577)
1.3617
0.618
DATA
FILTER
DATA
SLICER
20
17
DSN
16
DSP
R1
DATAOUT
MAX7036
RDF2
100kΩ
16
DSP
14
OPP
C6
C4
RSSI
RDF1
100kΩ
Figure 3. Generating Data-Slicer Threshold
Note that a long string of zeros or ones can cause the
threshold to drift. This configuration works best if a
coding scheme (e.g., Manchester coding, which has an
equal number of zeros and ones) is used.
15
DFFB
C5
Peak Detector
Figure 2. Sallen-Key Lowpass Data Filter
Data Slicer
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. One input is supplied by the datafilter output. Both comparator inputs are accessible off
chip to allow for different methods of generating the
slicing threshold, which is applied to the second comparator input.
10
The peak-detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the
peak detector to dynamically follow peak changes of
the data-filter output voltage. The peak detector can be
used for at least two functions. First, it can serve as an
RSSI for ASK modulation. Second, it can be used for
faster data-slicer response by adding it to the threshold
pin (DSN) on the data-slicer comparator (Figure 4). The
two capacitors in this circuit should be equal, and the
peak detector resistor should be approximately 10
______________________________________________________________________________________
300MHz to 450MHz ASK Receiver
with Internal IF Filter
DATA
FILTER
MAX7036
DATA
SLICER
20
17
DSN
16
DSP
18
PDOUT
R1
DATAOUT
C4
Figure 4. Using PDOUT for Faster Startup
Layout Considerations
A properly designed PCB is an essential part of any
RF/microwave circuit. On high-frequency inputs and
outputs, use controlled-impedance lines and keep them
as short as possible to minimize losses and radiation.
At high frequencies, trace lengths that are λ/10 or
longer act as antennas.
Keeping the traces short also reduces parasitic inductance. Generally, 1in of a PCB trace adds about 20nH
of parasitic inductance. The parasitic inductance can
have a dramatic effect on the effective inductance of a
passive component. For example, a 0.5in trace connecting a 100nH inductor adds an extra 10nH of inductance or 10%.
To reduce the parasitic inductance, use wider traces
and a solid ground or power plane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
close to all power-supply connections.
Table 2. Component Values
COMPONENT
fRF = 315MHz
C1
4.7pF
fRF = 433.92MHz
2.7pF
C2
100pF
100pF
C3
100pF
100pF
C4
0.1µF
0.1µF
C5
390pF
390pF
C6
180pF
180pF
C7
1µF
1µF
C8
0.01µF
0.01µF
C9
22pF
22pF
C10
10pF
10pF
C11
0.1µF
0.1µF
C12
220pF
220pF
C13
10pF
10pF
C14
10pF
10pF
C15
100pF
100pF
C16
0.1µF
0.1µF
L1
100nH
47nH
L2
27nH
15nH
R1
22kΩ
22kΩ
Y1
9.8375MHz
13.55375MHz
______________________________________________________________________________________
11
MAX7036
times larger than the resistor in the RC smoothing circuit between DSP and DSN. This circuit will provide an
instantaneous jump of one-half of the DSP increase
from “no signal” voltage to peak voltage, which then
decays with the same time constant as that of the
threshold build-up from the RC smoothing circuit. The
DC slicing voltage at DSN is slightly higher (by the ratio
of the two resistors in the circuit) than it would be without the speed-up circuit. Always provide a capacitive
path from the PDOUT pin to ground when using the
peak-detector output.
300MHz to 450MHz ASK Receiver
with Internal IF Filter
MAX7036
Typical Application Circuit
V3V
IF VSUP IS
THEN V3V IS
3.0V TO 3.6V
TIED TO VSUP
4.5V TO 5.5V
CREATED BY LDO,
AVAILABLE AT
AVDD (PIN 4)
R2
C17
VSUP
R1
(SEE TABLE ABOVE)
C11
C4
DATAOUT
VDD
C5
PDOUT
DSN
DSP
ENABLE
DFFB
XTAL2
C13
C14
OPP
C6
Y1
MAX7036
XTAL1
DCOC
C7
AVDD
DVDD
C16
L1
C8
C15
LNAIN
IFC3
LNAOUT
MIXIN2
MIXIN1
IFC2
IFC1
C9
C3
C1
C2
C10
L2
C12
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
LAND
PACKAGE
PACKAGE
OUTLINE NO.
PATTERN NO.
TYPE
CODE
20 Thin QFN-EP
12
T2055+3
21-0140
______________________________________________________________________________________
90-0008
300MHz to 450MHz ASK Receiver
with Internal IF Filter
REVISION
NUMBER
REVISION
DATE
0
3/09
Initial release
1
8/10
Updated Absolute Maximum Ratings, TOCs 5, 11, and 12, Pin Description,
Phase-Locked Loop (PLL) and Crystal Oscillator sections, and Typical
Application Circuit
DESCRIPTION
PAGES
CHANGED
—
2, 5, 6, 8, 9, 12
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX7036
Revision History