Final Electrical Specifications LTC1096L/LTC1098L Low Voltage, Micropower Sampling 8-Bit Serial I/O A/D Converters December 1995 U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1096L/LTC1098L are 3V micropower, 8-bit successive approximation sampling A/D converters. They typically draw only 40µA of supply current when converting and automatically power down to a typical supply current of 1nA between conversions. They are packaged in 8-pin SO packages and operate on a 3V supply. These 8bit, switched capacitor, successive approximation ADCs include a sample-and-hold. The LTC1096L has a single differential analog input. The LTC1098L offers a software selectable 2-channel multiplexed input. Specified at 2.65V Minimum Supply Maximum Supply Current: 80µA Auto Shutdown to 1nA 8-Pin SO Package On-Chip Sample-and-Hold Conversion Time: 32µs Sample Rates: 16.5ksps I/O Compatible with SPI, MICROWIRETM, etc. UO APPLICATI ■ ■ ■ ■ ■ S On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three wires. This, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers. Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Battery Monitoring Temperature Measurement The circuits can be used in ratiometric applications or with an external reference. The high impedance analog inputs and the ability to operate with reduced spans (to 1V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a registered trademark of National Semiconductor Corporation. UO TYPICAL APPLICATI 10µW, SO-8 Package, 8-Bit A/D Converter Samples at 200Hz and Runs Off a 3V Battery ANALOG INPUT 0V TO 3V RANGE 1 CS/ VCC SHDN 2 +IN CLK LTC1096L 3 –IN DOUT 4 GND VREF 3V MPU 8 SERIAL DATA LINK (MICROWIRE AND SPI COMPATIBLE) 7 6 5 1000 SUPPLY CURRENT, ICC (µA) 1µF Supply Current vs Sample Rate 100 10 SERIAL DATA LINK 1096/8 TA01 1 0.1 1 10 SAMPLE FREQUENCY (kHz) 100 1096/8 TA02 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 LTC1096L/LTC1098L W W W AXI U U ABSOLUTE RATI GS (Notes 1 and 2) Operating Temperature LTC1096LAC/LTC1098LAC .................... 0°C to 70°C LTC1096LAI/LTC1098LAI .................. – 40°C to 85°C LTC1096LC/LTC1098LC......................... 0°C to 70°C LTC1096LI/LTC1098LI ....................... – 40°C to 85°C Storage Temperature Range ................. – 65°c to 150°C Lead Temperature (Soldering, 10 sec.)................ 300°C Supply Voltage (VCC) to GND ................................... 12V Voltage Analog and Reference ................ –0.3V to VCC + 0.3V Digital Inputs......................................... –0.3V to 12V Digital Outputs ........................... –0.3V to VCC + 0.3V Power Dissipation.............................................. 500mW U W U PACKAGE/ORDER I FOR ATIO (Note 3) ORDER PART NUMBER ORDER PART NUMBER TOP VIEW CS/ 1 SHDN +IN 2 8 VCC 7 CLK –IN 3 6 DOUT GND 4 5 VREF S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W TOP VIEW LTC1096LACS8 LTC1096LAIS8 LTC1096LCS8 LTC1096LIS8 CS/ 1 SHDN CH0 2 S8 PART MARKING 096LIA 1096LA 1096LI 1096L 8 VCC(VREF) 7 CLK CH1 3 6 DOUT GND 4 5 DIN LTC1098LACS8 LTC1098LAIS8 LTC1098LCS8 LTC1098LIS8 S8 PART MARKING 098LIA 1098LA 1098LI 1098L S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W Consult factory for Military grade parts. U U U U WW RECO E DED OPERATI G CO DITIO S SYMBOL PARAMETER VCC Supply Voltage 2.65 4.0 V fCLK Clock Frequency VCC = 2.65V 25 250 kHz tCYC Total Cycle Time LTC1096L, fCLK = 250kHz LTC1098L, fCLK = 250kHz 58 58 µs µs thDI Hold Time, DIN After CLK↑ VCC = 2.65V 450 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Operating Sequence) VCC = 2.65V, LTC1096L VCC = 2.65V, LTC1098L 1 1 µs µs tWAKEUP Wakeup Time CS↓ Before First CLK↓ After First CLK↑ (See Figure 1, LTC1096L Operating Sequence) VCC = 2.65V, LTC1096L 10 µs Wakeup Time CS↓ Before MSBF Bit CLK↓ (See Figure 2, LTC1098L Operating Sequence) VCC = 2.65V, LTC1098L 10 µs tsuDI Setup Time, DIN Stable Before CLK↑ VCC = 2.65V 1 µs tWHCLK CLK High Time VCC = 2.65V 1.6 µs tWLCLK CLK Low Time VCC = 2.65V 1.6 µs tWHCS CS High Time Between Data Transfer Cycles VCC = 2.65V 2 µs tWLCS CS Low Time During Data Transfer LTC1096L, fCLK = 250kHz LTC1098L, fCLK = 250kHz 56 56 µs µs 2 CONDITIONS MIN TYP MAX UNITS LTC1096L/LTC1098L U U W CO VERTER A D ULTIPLEXER CHARACTERISTICS VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted. PARAMETER LTC1096LA/LTC1098LA MIN TYP MAX CONDITIONS Resolution (No Missing Code) ● 8 LTC1096L/LTC1098L MIN TYP MAX 8 UNITS Bits ● ±0.5 ±1 Linearity Error ● ±0.5 ±1 LSB Full Scale Error ● ±0.5 ±1 LSB ±1 ±1.5 LSB Offset Error (Note 4) LSB Total Unadjusted Error (Note 5) VREF = 2.5V Analog Input Range (Note 6) – 0.05V to VCC + 0.05V V REF Input Range (Note 6) 2.65 ≤ VCC ≤ 4.0V – 0.05V to VCC + 0.05V V Analog Input Leakage Current (Note 7) ● ● ±1 ±1 µA MAX UNITS U DIGITAL A D DC ELECTRICAL CHARACTERISTICS VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP VIH High Level Input Voltage VCC = 3.6V ● VIL Low Level Input Voltage VCC = 2.65V ● 0.45 V IIH High Level Input Current VIN = VCC ● 2.5 µA IIL Low Level Input Current VIN = 0V ● – 2.5 µA VOH High Level Output Voltage VCC = 2.65V, IO = 10µA IO = 360µA ● ● VOL Low Level Output Voltage VCC = 2.65V, IO = 400µA ● 0.3 V IOZ Hi-Z Output Leakage CS =High ● ±3 µA ISOURCE Output Source Current VOUT = 0V ISINK Output Sink Current VOUT = VCC IREF Reference Current CS = VCC tCYC ≥ 200µs, fCLK ≤ 50kHz tCYC = 58µs, fCLK = 250kHz ● ● ● 0.001 2.5 3.500 7.5 35.00 50.0 µA µA µA ICC Supply Current CS = VCC ● 0.001 ± 3 µA 1.9 2.4 2.1 V 2.64 2.50 V V – 10 mA 15 mA LTC1096L, tCYC ≥ 200µs, fCLK ≤ 50kHz tCYC = 58µs, fCLK = 250kHz ● ● 40 120 80 180 µA µA LTC1098L, tCYC ≥ 200µs, fCLK ≤ 50kHz tCYC = 58µs, fCLK = 250kHz ● ● 44 155 88 230 µA µA 3 LTC1096L/LTC1098L AC CHARACTERISTICS VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted. SYMBOL PARAMETER CONDITIONS tSMPL Analog Input Sample Time See Operating Sequences MIN fSMPL(MAX) Maximum Sampling Frequency MAX tCONV Conversion Time See Operating Sequences tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits ● 500 1000 ns tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits ● 220 800 ns ten Delay Time, CLK↓ to DOUT Enable See Test Circuits ● 160 480 ns thDO Time Output Data Remains Valid After CLK↓ CLOAD = 100pF tf DOUT Fall Time See Test Circuits tr DOUT Rise Time See Test Circuits CIN Input Capacitance Analog Inputs 1.5 ● On Channel Off Channel UNITS CLK Cycles 16.5 kHz 8 CLK Cycles 400 Digital Input The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: This device is specified at 2.65V. Consult factory for 5V specified devices. Note 4: Linearity error is specified between the actual end points of the A/D transfer curve. Note 5: Total unadjusted error includes offset, full scale, linearity, multiplexer and hold step errors. TYP ns ● 70 250 ns ● 50 200 ns 25 5 pF pF 5 pF Note 6: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below GND or one diode drop above VCC. This spec allows 50mV forward bias of either diode for 2.65V ≤ VCC ≤ 3.6V. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 3V input voltage range will therefore require a minimum supply voltage of 2.950V over initial tolerance, temperature variations and loading. Note 7: Channel leakage current is measured after the channel selection. U U U PI FU CTIO S LTC1096L CS/SHDN (Pin 1): Chip Select Input. A logic low on this input enables the LTC1096L. A logic high on this input disables the LTC1096L and disconnects the power to the LTC1096L. IN+ (Pin 2): Analog Input. This input must be free of noise with respect to GND. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. VCC (Pin 8): Power Supply Voltage. This pin provides power to the A/D converter. It must be free of noise and ripple by bypassing directly to the analog ground plane. IN– (Pin 3): Analog Input. This input must be free of noise with respect to GND. LTC1098L GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CS/SHDN (Pin 1): Chip Select Input. A logic low on this input enables the LTC1098L. A logic high on this input disables the LTC1098L and disconnects the power to the LTC1098L. VREF (Pin 5): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. 4 CHO (Pin 2): Analog Input. This input must be free of noise with respect to GND. LTC1096L/LTC1098L U U U PI FU CTIO S CH1 (Pin 3): Analog Input. This input must be free of noise with respect to GND. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. DIN (Pin 5): Digital Data Input. The multiplexer address is shifted into this pin. VCC (VREF) (Pin 8): Power Supply Voltage. This pin provides power and defines the span of the A/D converter. It must be free of noise and ripple by bypassing directly to the analog ground plane TEST CIRCUITS Load Circuit for tdDO, tr and tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf 1.4V 3k VOH DOUT DOUT VOL TEST POINT 100pF tr tf LTC1096/98 • TC02 LTC1096/98 • TC01 Load Circuit for tdis and ten Voltage Waveforms for tdis VIH CS TEST POINT VCC tdis WAVEFORM 2, t en 3k DOUT 90% tdis tdis WAVEFORM 1 100pF DOUT WAVEFORM 1 (SEE NOTE 1) LTC1096/98 • TC03 DOUT WAVEFORM 2 (SEE NOTE 2) 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. LTC1096/98 • TC04 Voltage Waveforms for DOUT Delay Time, tdDO CLK VIL tdDO VOH DOUT VOL LTC1096/98 • TC05 5 LTC1096L/LTC1098L TEST CIRCUITS Voltage Waveforms for ten LTC1096L CS t WAKEUP 1 CLK B7 DOUT VOL t en LTC1096/98 • TC06 LTC1098L CS START DIN 1 CLK 2 3 4 5 B7 DOUT VOL t en U W U UO APPLICATI LTC1096/98 • TC07 S I FOR ATIO INPUT DATA WORD Start Bit The LTC1096L requires no DIN word. It is permanently configured to have a single differential input. The conversion result, in which the output on the DOUT line is presented in MSB-first sequence followed by LSB sequence, provides easy interface to MSB- or LSB-first serial ports. The first “logical one” clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer. The LTC1098L will ignore all leading zeroes which precede this logical one. After the start bit is received, the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle. The LTC1098L latches data into the DIN input on the rising edge of the clock. The input data words are defined as follows: SGL/ START DIFF ODD/ MSBF SIGN MUX MSB-FIRST/ ADDRESS LSB-FIRST LTC1096/9 • AI01 6 Multiplexer (MUX) Address The bits of the input word following the START bit assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of the following tables. In LTC1096L/LTC1098L W U U UO APPLICATI S I FOR ATIO single-ended mode, all input channels are measured with respect to GND. not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance use a printed circuit board. The GND pin (Pin 4) should be tied directly to the ground plane with minimum lead length. LTC1098L Channel Selection MUX ADDRESS CHANNEL # ODD/SIGN CH0 SGL/DIFF CH1 GND 0 1 – + 1 1 – + 0 0 – + 1 0 + – Bypassing For good performance, the LTC1096L/LTC1098L VCC and VREF pins must be free of noise and ripple. Any changes in the VCC and VREF voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a minimum 0.1µF capacitor and with leads as short as possible. The LTC1098L combines VCC and VREF into one pin, VCC(VREF), which can be bypassed by a 0.1µF capacitor. LTC1096/8 • AI02 MSB-First/LSB-First (MSBF) The output data of the LTC1098L is programmed for MSB-first or LSB-first sequence using the MSBF bit. When the MSBF bit is a logical one, data will appear on the DOUT line in MSB-first format. Logical zeroes will be filled in indefinitely following the last data bit. When the MSBF bit is a logical zero, LSB-first data will follow the normal MSB-first data on the DOUT line (see Figures 1 and 2). Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1096L/ LTC1098L have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. But if large source resistances are used or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins. ANALOG CONSIDERATIONS Grounding The LTC1096L/LTC1098L should be used with an analog ground plane and single point grounding techniques. Do t CYC CS POWER DOWN CLK tsuCS tWAKEUP DOUT Hi-Z NULL BIT B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 tCONV B3 B4 B5 B6 B7 Hi-Z FILLED WITH ZEROES LTC1096/98 F01 Figure 1. LTC1096L Operating Sequence 7 LTC1096L/LTC1098L W U U UO APPLICATI S I FOR ATIO MSB-FIRST DATA (MSBF = 0) tCYC CS POWER DOWN tWAKEUP CLK tsuCS ODD/ SIGN START DIN DON'T CARE SGL/ DIFF DOUT MSBF NULL BIT B7 Hi-Z B6 B5 tSMPL B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 Hi-Z B7 FILLED WITH ZEROES tCONV LTC1096/98 F02 Figure 2. LTC1098L Operating Sequence Example: Differential Inputs (CH+, CH–) U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 7 8 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH 0.004 – 0.010 (0.101 – 0.254) 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 0.050 (1.270) BSC 1 2 3 4 SO8 0695 SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS PART NUMBER DESCRIPTION LTC1096/LTC1098 8-Pin SO, Micropower 8-Bit ADC COMMENTS Low Power, Small Size, Low Cost LTC1196/LTC1198 8-Pin SO, 1Msps 8-Bit ADC Low Power, Small Size, Low Cost LTC1285/LTC1288 8-Pin SO, 3V Micropower 12-Bit ADC 12-Bit ADC in SO-8 LTC1289 Multiplexed 3V 12-Bit ADC 8-Channel 12-Bit Serial I/O LTC1584L Multiplexed 3V 12-Bit ADC 4-Channel 12-Bit Serial I/O, Micropower 8 Linear Technology Corporation LT/GP 1295 5K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1995