DS92LV090A www.ti.com SNLS025D – APRIL 2000 – REVISED APRIL 2013 DS92LV090A 9 Channel Bus LVDS Transceiver Check for Samples: DS92LV090A FEATURES DESCRIPTION • • • • • The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. 1 2 • • • • • • • • • • • • Bus LVDS Signaling 3.2 Nanosecond Propagation Delay Max Chip to Chip Skew ±800ps Low Power CMOS Design High Signaling Rate Capability (Above 100 Mbps) 0.1V to 2.3V Common Mode Range for VID = 200mV ±100 mV Receiver Sensitivity Supports Open and Terminated Failsafe on Port Pins 3.3V Operation Glitch Free Power Up/Down (Driver & Receiver Disabled) Light Bus Loading (5 pF Typical) per Bus LVDS Load Designed for Double Termination Applications Balanced Output Impedance Product Offered in 64 Pin LQFP Package High Impedance Bus Pins on Power off (VCC = 0V) Driver Channel to Channel Skew (Same Device) 230ps Typical Receiver Channel to Channel Skew (Same Device) 370ps Typical The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V. The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. (See Applications Information Section for more details.) Simplified Functional Diagram Figure 1. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated DS92LV090A SNLS025D – APRIL 2000 – REVISED APRIL 2013 www.ti.com Connection Diagram Figure 2. Top View Package Number PM0064 PIN DESCRIPTIONS Pin Name Pin # Input/Output Descriptions DO+/RI+ 27, 31, 35, 37, 41, 45, 47, 51, 55 I/O True Bus LVDS Driver Outputs and Receiver Inputs. DO−/RI− 26, 30, 34, 36, 40, 44, 46, 50, 54 I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs. DIN 2, 6, 12, 18, 20, 22, 58, 60, 62 I TTL Driver Input. RO 3, 7, 13, 19, 21, 23, 59, 61, 63 O TTL Receiver Output. RE 17 I Receiver Enable TTL Input (Active Low). DE 16 I Driver Enable TTL Input (Active High). GND 4, 5, 9, 14, 25, 56 Power Ground for digital circuitry (must connect to GND on PC board). These pins connected internally. VCC 10, 15, 24, 57, 64 Power VCC for digital circuitry (must connect to VCC on PC board). These pins connected internally. AGND 28, 33, 43, 49, 53 Power Ground for analog circuitry (must connect to GND on PC board). These pins connected internally. AVCC 29, 32, 42, 48, 52 Power Analog VCC (must connect to VCC on PC board). These pins connected internally. NC 1, 8, 11, 38, 39 N/A Leave open circuit, do not connect. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS92LV090A DS92LV090A www.ti.com Absolute Maximum Ratings SNLS025D – APRIL 2000 – REVISED APRIL 2013 (1) (2) (3) Supply Voltage (VCC) 4.0V Enable Input Voltage (DE, RE) −0.3V to (VCC +0.3V) Driver Input Voltage (DIN) −0.3V to (VCC +0.3V) Receiver Output Voltage (ROUT) −0.3V to (VCC +0.3V) −0.3V to +3.9V Bus Pin Voltage (DO/RI±) ESD (HBM 1.5 kΩ, 100 pF) >4.5 kV Driver Short Circuit Duration momentary Receiver Short Circuit Duration momentary Maximum Package Power Dissipation at 25°C LQFP 1.74 W Derate LQFP Package 13.9 mW/°C θja 71.7°C/W θjc 10.9°C/W Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Lead Temperature (Soldering, 4 sec.) (1) (2) (3) 260°C All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except VOD, ΔVOD and VID. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Recommended Operating Conditions Min Max Units Supply Voltage (VCC) 3.0 3.6 V Receiver Input Voltage 0.0 2.4 V Operating Free Air Temperature −40 +85 °C Maximum Input Edge Rate (20% to 80%) (1) (1) Δt/ΔV Data 1.0 ns/V Control 3.0 ns/V Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf = <1.0 ns (0%–100%). To ensure fastest propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate, the better the AC performance. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS92LV090A 3 DS92LV090A SNLS025D – APRIL 2000 – REVISED APRIL 2013 www.ti.com DC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified Symbol Parameter Conditions VOD Output Differential Voltage ΔVOD VOD Magnitude Change VOS Offset Voltage ΔVOS Offset Magnitude Change VOH Driver Output High Voltage (3) RL = 27Ω VOL Driver Output Low Voltage (3) RL = 27Ω IOSD Voltage Output High DO+/RI+, DO−/RI− Min Typ Max Unit s 240 300 460 mV 27 mV 1.5 V 5 10 mV 1.4 1.65 V 1.1 Output Short Circuit Current VOH RL = 27Ω, Figure 3 Pin (1) (2) (4) (5) 0.95 VOD = 0V, DE = VCC, Driver outputs shorted together 1.1 |36| |65| mA VCC−0.2 V VCC−0.2 V Inputs Terminated, RL = 27Ω VCC−0.2 V ROUT VOL Voltage Output Low IOL = 2.0 mA, VID = −300 mV IOD Receiver Output Dynamic Current (4) VID = 300mV, VOUT = VCC−1.0V VTH Input Threshold High DE = 0V, VCM = 1.5V VTL Input Threshold Low VCMR Receiver Common Mode Range IIN Input Current VIH Minimum Input High Voltage VIL Maximum Input Low Voltage IIH Input High Current VIN = VCC or 2.4V −20 IIL Input Low Current VIN = GND or 0.4V −20 VCL Input Diode Clamp Voltage ICLAMP = −18 mA −1.5 −0.8 ICCD Power Supply Current Drivers Enabled, Receivers Disabled No Load, DE = RE = VCC, DIN = VCC or GND ICCR Power Supply Current Drivers Disabled, Receivers Enabled ICCZ ICC 0.05 −110 VID = −300mV, VOUT = 1.0V DO+/RI+, DO−/RI− DIN, DE, RE V mA 110 mA +100 mV −100 mV |VID|/2 DE = 0V, RE = 2.4V, VIN = +2.4V or 0V 0.075 |75| |75| VCC = 0V, VIN = +2.4V or 0V IOFF V Inputs Open VID = +300 mV IOH = −400 µA 1.3 −20 ±1 −20 ±1 2.4 − |VID|/2 V +20 µA +20 µA 2.0 VCC V GND 0.8 V ±10 +20 µA ±10 +20 µA VCC V 55 80 mA DE = RE = 0V, VID = ±300mV 73 80 mA Power Supply Current, Drivers and Receivers TRI-STATE DE = 0V; RE = VCC, DIN = VCC or GND 35 80 mA Power Supply Current, Drivers and Receivers Enabled DE = VCC; RE = 0V, DIN = VCC or GND, RL = 27Ω 170 210 mA Power Off Leakage Current VCC = 0V or OPEN, DIN, DE, RE = 0V or OPEN, VAPPLIED = 3.6V (Port Pins) +20 µA DO+/RI+, DO−/RI− −20 COUTPUT Capacitance @ Bus Pins DO+/RI+, DO−/RI− 5 pF cOUTPUT Capacitance @ ROUT ROUT 7 pF (1) (2) (3) (4) (5) 4 All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except VOD, ΔVOD and VID. All typicals are given for VCC = +3.3V and TA = +25°C, unless otherwise stated. The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs. Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity. VOH failsafe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS92LV090A DS92LV090A www.ti.com SNLS025D – APRIL 2000 – REVISED APRIL 2013 AC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified Symbol Parameter (1) Conditions Min Typ Max Units RL = 27Ω, Figure 4, Figure 5, CL = 10 pF 0.6 1.4 2.2 ns 0.6 1.4 2.2 ns DIFFERENTIAL DRIVER TIMING REQUIREMENTS Differential Prop. Delay High to Low (2) tPLHD Differential Prop. Delay Low to High (2) tSKD1 Differential Skew |tPHLD–tPLHD| tPHLD (3) 80 (4) tSKD2 Chip to Chip Skew tSKD3 Channel to Channel Skew tTLH Transition Time Low to High tTHL Transition Time High to Low tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low ps 1.6 ns 0.25 0.45 ns 0.6 1.2 ns 0.5 1.2 ns 3 8 ns 3 8 ns 3 8 ns 3 8 ns 1.6 2.4 3.2 ns 1.6 2.4 3.2 ns (5) RL = 27Ω, Figure 6, Figure 7, CL = 10 pF DIFFERENTIAL RECEIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low tPLHD Differential Prop Delay Low to High tSDK1 Differential Skew |tPHLD–tPLHD| tSDK2 Chip to Chip Skew (2) (2) Figure 8, Figure 9, CL = 35 pF (3) 80 (4) (5) ps 1.6 ns tSDK3 Channel to Channel Skew 0.35 0.60 ns tTLH Transition Time Low to High 1.5 2.5 ns tTHL Transition Time High to Low 1.5 2.5 ns tPHZ Disable Time High to Z 4.5 10 ns tPLZ Disable Time Low to Z 3.5 8 ns tPZH Enable Time Z to High 3.5 8 ns tPZL Enable Time Z to Low 3.5 8 ns (1) (2) (3) (4) (5) RL = 500Ω, Figure 10, Figure 11, CL = 35 pF Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf = <1.0 ns (0%–100%). To ensure fastest propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate, the better the AC performance. Propagation delays are specified by design and characterization. tSKD1 |tPHLD–tPLHD| is the worse case skew between any channel and any device over recommended operation conditions. Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge. Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, either edge. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS92LV090A 5 DS92LV090A SNLS025D – APRIL 2000 – REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION General application guidelines and hints may be found in the following application notes: AN-808 (SNLA028), AN-903 (SNLA034), AN-971 (SNLA165), AN-977 (SNLA166), and AN-1108 (SNLA008). There are a few common practices which should be implied when designing PCB for Bus LVDS signaling. Recommended practices are: • Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals). • Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible. • Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface mount capacitors placed close to power and ground pins work best. Two or three high frequency, multi-layer ceramic (MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel should be used between each VCC and ground. The capacitors should be as close as possible to the VCC pin. – Multiple vias should be used to connect VCC and Ground planes to the pads of the by-pass capacitors. – In addition, randomly distributed by-pass capacitors should be used. • Use the termination resistor which best matches the differential impedance of your transmission line. • Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to <0.5 inches. • Isolate TTL signals from Bus LVDS signals MEDIA (CONNECTOR or BACKPLANE) SELECTION: • Use controlled impedance media. The backplane and connectors should have a matched differential impedance. Table 1. Functional Table MODE SELECTED DE RE DRIVER MODE H H RECEIVER MODE L L TRI-STATE MODE L H LOOP BACK MODE H L Table 2. Transmitter Mode INPUTS DE OUTPUTS DIN DO+ DO− H H L L H H H L H 0.8V< DIN <2.0V X X L X Z Z Table 3. Receiver Mode (1) INPUTS (1) 6 OUTPUT RE (RI+) – (RI−) L L (< −100 mV) L L H (> +100 mV) H L −100 mV < VID < +100 mV X H X Z X = High or Low logic state L = Low state Z = High impedance state H = High state Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS92LV090A DS92LV090A www.ti.com SNLS025D – APRIL 2000 – REVISED APRIL 2013 Test Circuits and Timing Waveforms Figure 3. Differential Driver DC Test Circuit Figure 4. Differential Driver Propagation Delay and Transition Time Test Circuit Figure 5. Differential Driver Propagation Delay and Transition Time Waveforms Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS92LV090A 7 DS92LV090A SNLS025D – APRIL 2000 – REVISED APRIL 2013 www.ti.com Figure 6. Driver TRI-STATE Delay Test Circuit Figure 7. Driver TRI-STATE Delay Waveforms Figure 8. Receiver Propagation Delay and Transition Time Test Circuit Figure 9. Receiver Propagation Delay and Transition Time Waveforms 8 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS92LV090A DS92LV090A www.ti.com SNLS025D – APRIL 2000 – REVISED APRIL 2013 Figure 10. Receiver TRI-STATE Delay Test Circuit Figure 11. Receiver TRI-STATE Delay Waveforms Typical Bus Application Configurations Figure 12. Bi-Directional Half-Duplex Point-to-Point Applications Figure 13. Multi-Point Bus Applications Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS92LV090A 9 DS92LV090A SNLS025D – APRIL 2000 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS92LV090A PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS92LV090ATVEH/NOPB ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS92LV090A TVEH DS92LV090ATVEHX/NOPB ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS92LV090A TVEH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS92LV090ATVEHX/NOP B Package Package Pins Type Drawing LQFP PM 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 12.35 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.35 2.2 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device DS92LV090ATVEHX/NOP B Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LQFP PM 64 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. 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