NSC ADC08161CIWM 500 ns a/d converter with s/h function and 2.5v bandgap reference Datasheet

ADC08161
500 ns A/D Converter with S/H Function and
2.5V Bandgap Reference
General Description
Key Specifications
Using a patented multi-step A/D conversion technique, the
8-bit ADC08161 CMOS A/D converter offers 500 ns conversion time, internal sample-and-hold (S/H), a 2.5V bandgap
reference, and dissipates only 100 mW of power. The
ADC08161 performs an 8-bit conversion with a 2-bit voltage
estimator that generates the 2 MSBs and two low-resolution
(3-bit) flashes that generate the 6 LBSs.
Input signals are tracked and held by the input sampling circuitry, eliminating the need for an external sample-and-hold.
The ADC08161 can perform accurate conversions of
full-scale input signals at frequencies from DC to typically
more than 300 kHz (full power bandwidth) without the need
of an external sample-and-hold (S/H).
For ease of interface to microprocessors, this part has been
designed to appear as a memory location or I/O port without
the need for external interfacing logic.
n
n
n
n
n
n
Resolution
Conversion time (tCONV)
Full power bandwidth
Throughput rate
Power dissipation
Total unadjusted error
8 Bits
560 ns max (WR-RD Mode)
300 kHz (typ)
1.5 MHz min
100 mW max
± 1⁄2 LSB and ± 1 LSB max
Features
n No external clock required
n Analog input voltage range from GND to V+
n 2.5V bandgap reference
Applications
n
n
n
n
Mobile telecommunications
Hard-disk drives
Instrumentation
High-speed data acquisition systems
Block Diagram
DS011149-1
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS011149
www.national.com
ADC08161 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference
June 1999
Connection Diagram
RD Mode (logic low on the MODE pin)
Wide-Body Small-Outline Package
INT
GND
VREF−, VREF+
These are the reference voltage inputs.
They may be placed at any voltage between GND − 50 mV and V+ + 50 mV, but
VREF+ must be greater than VREF−. Ideally,
an input voltage equal to VREF− produces
an output code of 0, and an input voltage
greater than VREF+ − 1.5 LSB produces an
output code of 255.
For the ADC08161 an input voltage that
exceeds V+ by more than 100 mV or is below GND by more than 100 mV will create
conversion errors.
CS
This is the active low Chip Select input. A
logic low signal applied to this input pin enables the RD and WR inputs. Internally,
the CS signal is ORed with RD and WR
signals.
Overflow Output. If the analog input is
higher than VREF+, OFL will be low at the
end of conversion. It can be used when
cascading two ADC08161s to achieve
higher resolution (9 bits). This output is always active and does not go into
TRI-STATE as DB0–DB7 do. When OFL
is set, all data outputs remain high when
the ADC08061’s output data is read.
DS011149-14
See NS Package Number M20B
Ordering Information
Industrial (−40˚C ≤ TA ≤ 85˚C)
ADC08161CIWM
Package
M20B
Pin Description
VIN
This is the analog input. The input range is
GND–50 mV ≤ VINPUT ≤ V+ + 50 mV.
DB0–DB7
TRI-STATE data outputs — bit 0 (LSB)
through bit 7 (MSB).
WR /RDY
WR-RD Mode (Logic high applied to
MODE pin)
WR: With CS low, the conversion is
started on the rising edge of WR. The digital result will be strobed into the output
latch at the end of conversion (Figures 2,
3, 4).
RD Mode (Logic low applied to MODE
pin)
RDY: This is an open drain output (no internal pull-up device). RDY will go low after the falling edge of CS and returns high
at the end of conversion.
Mode: Mode (RD or WR-RD ) selection
input– This pin is pulled to a logic low
through an internal 50 µA current sink
when left unconnected.
RD Mode is selected if the MODE pin is
left unconnected or externally forced low.
A complete conversion is accomplished by
pulling RD low until output data appears.
MODE
RD
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OFL
WR-RD Mode is selected when a high is
applied to the MODE pin. A conversion
starts with the WR signal’s rising edge and
then using RD to access the data.
WR-RD Mode (logic high on the MODE
pin)
This is the active low Read input. With a
logic low applied to the CS pin, the
TRI-STATE data outputs (DB0–DB7) will
be activated when RD goes low (Figures
2, 3, 4).
2
With CS low, a conversion starts on the
falling edge of RD. Output data appears
on DB0–DB7 at the end of conversion
(Figures 1, 5).
This is an active low output that indicates
that a conversion is complete and the data
is in the output latch. INT is reset by the
rising edge of RD.
This is the power supply ground pin. The
ground pin should be connected to a
“clean” ground reference point.
V+
Positive power supply voltage input. Nominal operating supply voltage is +5V. The
supply pin should be bypassed with a
10 µF bead tantalum in parallel with a 0.1
ceramic capacitor. Lead length should be
as short as possible.
VREFOUT
The internal bandgap reference’s 2.5V
output is available on this pin. Use a
220 µF bypass capacitor between this pin
and analog ground.
Absolute Maximum Ratings (Notes 1, 2)
Power Dissipation (Note 4)
Lead Temperature (Note 5)
(Vapor Phase, 60 sec.)
(Infrared, 15 sec.)
Storage Temperature
ESD Susceptibility (Note 6)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V+)
Logic Control Inputs
Voltage at Other Inputs and Outputs
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
6V
−0.3V to V+ + 0.3V
−0.3V to V+ + 0.3V
5 mA
20 mA
875 mW
+215˚C
+220˚C
−65˚C to +150˚C
750V
Operating Ratings(Notes 1, 2)
TMIN ≤ TA ≤ TMAX
−40˚C ≤ TA ≤ 85˚C
4.5V to 5.5V
Temperature Range
ADC08161CIWM
Supply Voltage, (V+)
Converter Characteristics
The following specifications apply for RD Mode, V+ = 5V, VREF+ = 5V, and VREF− = GND unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
INL
Integral Non Linearity
TUE
Total Unadjusted Error (Note 9)
INL
Integral Non Linearity
TUE
Total Unadjusted Error
Missing Codes
Conditions
Typical
Limits
Units
(Note 7)
(Note 8)
(Limit)
VREF = 5V
VREF = 5V
VREF = 2.5V
VREF = 2.5V
±1
±1
±1
±1
LSB (max)
VREF = 5V
VREF = 2.5V
0
Bits (max)
0
Bits (max)
Reference Input Resistance
VREF+
VREF−
VIN
LSB (max)
LSB (max)
LSB (max)
700
500
Ω (min)
700
1250
Ω (max)
Positive Reference Input Voltage
VREF−
V (min)
V+
V (max)
Negative Reference
GND
V (min)
Input Voltage
VREF+
V (max)
Analog
(Note 10)
GND − 0.1
V (min)
V+ + 0.1
V (max)
−0.4
−20
µA (max)
−0.4
−20
µA (max)
± 1/16
± 1⁄2
LSB (max)
Input Voltage
On-Channel Input Current
On Channel Input = 5V,
Off Channel Input = 0V
(Note 11)
On Channel Input = 0V,
Off Channel Input = 5V
PSS
Power Supply Sensitivity
(Note 11)
V+ = 5V ± 5%,
Effective Bits
All Codes Tested
VIN = 4.85 Vp-p
7.8
Bits
Full-Power Bandwidth
fIN = 20 Hz to 20 kHz
VIN = 4.85 Vp-p
300
kHz
0.5
%
50
dB
50
dB
25
pF
VREF = 4.75V
THD
Total Harmonic Distortion
S/N
Signal-to-Noise Ratio
VIN = 4.85 Vp-p
fIN = 20 Hz to 20 kHz
VIN = 4.85 Vp-p
Intermodulation Distortion
fIN = 20 Hz to 20 kHz
VIN = 4.85 Vp-p
IMD
fIN = 20 Hz to 20 kHz
CVIN
Analog Input Capacitance
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AC Electrical Characteristics
The following specifications apply for V+ = 5V, tr = tf = 10 ns, VREF+ = 5V, VREF− = 0V unless otherwise specified. Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
tWR
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
100
100
ns (min)
Mode Pin to V+, (Figure 2)
350
350
ns (min)
Mode Pin to GND (Figure 5 )
200
250
ns (min)
400
400
ns (max)
Mode Pin to V+, (Figure 2 )
500
560
ns (max)
Parameter
Conditions
Mode Pin to V+
Write Time
(Figures 2, 3, 4)
tRD
Read Time (Time from Rising Edge
of WR to Falling Edge of RD )
tRDW
tCONV
RD Width
WR -RD Mode Conversion Time
(tWR + tRD + tACC1)
tCRD
RD Mode Conversion Time
Mode Pin to GND, (Figure 1 )
655
900
ns (max)
tACCO
Access Time (Delay from Falling
CL ≤ 100 pF, Mode Pin to GND
640
900
ns (max)
Edge of RD to Output Valid)
(Figure 1 )
Access Time (Delay from
Falling Edge of RD
CL ≤ 10 pF
CL = 100 pF
110
ns (max)
to Output Valid)
Mode Pin to V+, tRD ≤ tINTL
30
55
ns (max)
tACC1
45
50
ns
(Figure 2 )
tACC2
t1H, t0H
Falling Edge of RD
CL ≤ 10 pF
CL = 100 pF
to Output Valid)
tRD > tINTL,
TRI-STATE ® Control
(Figures 3, 5)
RL = 3 kΩ, CL = 10 pF
(Delay from Rising Edge
(Figures 1, 2, 3, 4, 5)
30
60
ns (max)
Delay from Rising Edge of
Mode Pin = V+, CL = 50 pF
520
690
ns (max)
WR to Falling Edge of INT
(Figures 3, 4)
CL = 50 pF,
50
95
ns (max)
(Figures 1, 2, 3, 5)
CL = 50 pF, (Figure 4)
45
95
ns (max)
25
45
ns (max)
0
15
ns (max)
60
115
ns (max)
(Figures 1, 2, 3, 4, 5)
50
50
ns (min)
Access Time (Delay from
25
ns
of RD to HI-Z State)
tINTL
tINTH
Delay from Rising Edge of
RD to Rising Edge of INT
tINTH
Delay from Rising Edge of
WR to Rising Edge of INT
tRDY
tID
tRI
Delay from INT
Mode Pin = 0V, CL = 50 pF,
RL = 3 kΩ, (Figure 1)
RL = 3 kΩ, CL = 100 pF
to Output Valid
(Figure 4)
Delay from CS to RDY
Mode Pin = V+, tRD ≤ tINTL
Delay from RD to INT
(Figure 2)
tN
Time between End of RD
and Start of New Conversion
tCSS
CS Setup Time
(Figures 1, 2, 3, 4, 5)
0
0
ns (max)
tCSH
CS Hold Time
(Figures 1, 2, 3, 4, 5)
0
0
ns (max)
DC Electrical Characteristics
The following specifications apply for V+ = 5V unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = 25˚C.
Symbol
VIH
Limit
(Note 8)
Units
(Limit)
CS, WR, RD, A0, A1, A2 Pins
2.0
V (min)
Mode Pin
3.5
Parameter
Logic “1” Input Voltage
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Typical
(Note 7)
Conditions
V+ = 5.5 V
4
DC Electrical Characteristics
(Continued)
The following specifications apply for V+ = 5V unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = 25˚C.
Symbol
VIL
IIH
Limit
(Note 8)
Units
(Limit)
CS, WR, RD, A0, A1, A2 Pins
0.8
V (max)
Mode Pin
VH = 5V
1.5
Parameter
Logic “0” Input Voltage
Logic “1” Input Current
Typical
(Note 7)
Conditions
V+ = 4.5V
CS, RD, A0, A, A2 Pins
IIL
0.005
1
WR Pin
0.1
3
50
200
Logic “0” Input Current
Mode Pin
VL = 0V
−0.005
−2
µA (max)
Logic “1” Output Voltage
Mode Pins
V+ = 4.75V
IOUT = −360 µA
2.4
V (min)
DB0–DB7, OFL, INT
IOUT = −10 µA
4.5
V (min)
0.4
V (max)
µA (max)
CS, RD, WR, A0, A1, A2
VOH
Logic “0” Output Voltage
DB0–DB7, OFL, INT
V+ = 4.75V
TRI-STATE Output Current
DB0–DB7, OFL, INT, RDY
VOUT = 5.0V
0.1
3
µA (max)
DB0–DB7, RDY
VOUT = 0V
−0.1
−3
µA (max)
ISOURCE Output Source Current
DB0–DB7, RDY
VOUT = 0V
−26
−6
mA (min)
ISINK
Output Sink Current
DB0–DB7, OFL, INT
VOUT = 5V
24
7
mA (min)
DB0–DB7, OFL, INT, RDY
CS = WR = RD = 0
11.5
20
mA (max)
VOL
IOUT = 1.6 mA
IO
IC
Supply Current
COUT
Logic Output Capacitance
5
pF
CIN
Logic Input Capacitance
5
pF
Bandgap Reference Electrical Characteristics
The following specifications apply for V+ = 5V unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other
limits TA = TJ = 25˚C.
Symbol
Parameter
VREFOUT
Internal Reference Output Voltage
∆VREF/∆T
Internal Reference Temperature
Conditions
Typical
Limits
Units
(Note 7)
(Note 8)
(Limit)
2.5 ± 2.0%
V (max)
40
ppm/˚C
Coefficient
∆VREF/∆IL
Internal Reference Load
Sourcing (0 ≤ IL ≤ +10 mA)
0.01
0.1
%/mA (max)
4.75V ≤ V+ ≤ 5.25V
VREV = 0V
0.5
6.0
mV (max)
Regulation
Line Regulation
ISC
Short Circuit Current
∆VREF/∆t
Long Term Stability
Start-Up Time
V+: 0V→5V, CL = 220 µF
35
mA (max)
200
ppm/kHr
40
ms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits.
For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
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Bandgap Reference Electrical Characteristics
(Continued)
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply voltage (VIN < GND or VIN > V+), the absolute value of the current at that pin should be
limited to 5 mA or less. The 20 mA package input current specification limits the number of pins that can exceed the power supply boundaries with a 5 mA current
limit to four.
Note 4: The power dissipation of this device under normal operation should never exceed 875 mW (Quiescent Power Dissipation + TTL Loads on the digital outputs).
Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (e.g., when any input or output exceeds the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX (maximum junction temperature), θJA
(package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJMAX
− TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 105˚C and θJA = 85˚C/W.
Note 5: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices.
Note 6: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 7: Typicals are at 25˚C and represent most likely parametric norm.
Note 8: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 9: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 10: Two on-chip diodes are tied to each analog input and are reversed biased during normal operation. One is connected to V+ and the other is connected to
GND. They will become forward biased and conduct when an analog input voltage is equal to or greater than one diode drop above V+ or below GND. Therefore,
caution should be exercised when testing with V+ = 4.5V. Analog inputs with magnitudes equal to 5V can cause an input diode to conduct, especially at elevated temperatures. This can create conversion errors for analog signals near full-scale. The specification allows 50 mV forward bias on either diode; e.g., the output code will
be correct as long as the analog input signal does not exceed the supply voltage by more than 50 mV. Exceeding this range on an unselected channel will corrupt
the reading of a selected channel. An absolute analog input signal voltage range of 0V ≤ VIN ≤ 5V can be achieved by ensuring that the minimum supply voltage applied to V+ is 4.950V over temperature variations, initial tolerance, and loading.
Note 11: Off-channel leakage current is measured on the on-channel selection.
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TRI-STATE Test Circuit and Waveforms
t1H, CL = 10 pF
t1H
DS011149-2
DS011149-4
tr = 10 ns
t0H, CL = 10 pF
t0H
DS011149-5
DS011149-3
tr = 10 ns
DS011149-6
FIGURE 1. RD Mode (Mode Pin is Low)
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TRI-STATE Test Circuit and Waveforms
(Continued)
DS011149-7
FIGURE 2. WR-RD Mode with tRD ≤ tINTL (Mode Pin is High)
DS011149-8
FIGURE 3. WR-RD Mode with tRD > tINTL (Mode Pin is High)
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8
TRI-STATE Test Circuit and Waveforms
(Continued)
DS011149-9
FIGURE 4. WR-RD Mode Reduced Interface System Connection with CS = RD = 0 (Mode Pin is High)
DS011149-10
FIGURE 5. RD Mode (Pipeline Operation); tRDW must be between 200 ns and 400 ns.
(Mode Pin is Low)
Typical Performance Characteristics
tCRD vs Temperature
Linearity Error vs
Reference Voltage
Offset Error vs
Reference Voltage
DS011149-23
DS011149-24
9
DS011149-25
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Typical Performance Characteristics
Supply Current vs Temperature
(Continued)
Reference Output Voltage vs
Temperature
Logic Threshold vs
Temperature
DS011149-26
DS011149-27
Output Current vs Temperature
DS011149-29
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10
DS011149-28
Application Information
DS011149-17
FIGURE 6. Block Diagram of the ADC08161 Multi-Step Flash Architecture
points can be connected, in groups of eight, to the eight comparators shown at the right of Figure 6. This function provides the necessary reference voltages to the comparators
during each flash conversion.
The six comparators, seven-resistor string (estimator DAC),
and Estimator Decoder at the left of Figure 6 form the Voltage Estimator. The estimator DAC connected between
VREF+ and VREF− generates the reference voltages for the
six Voltage Estimator comparators. These comparators perform a very low resolution A/D conversion to obtain an “estimate” of the input voltage. This estimate is then used to control the Comparator Multiplexer, connecting the appropriate
MSB Ladder section to the eight flash comparators. Only 14
comparators, six in the Voltage Estimator and eight in the
flash converter, are needed to achieve the full eight-bit resolution, instead of 32 comparators that would be needed by
traditional half-flash methods.
A conversion begins with the Voltage Estimator comparing
the analog input signal against the six tap voltages on the estimator DAC. The estimator decoder then selects one of the
groups of tap points along the MSB Ladder. These eight tap
points are then connected to the eight flash comparators.
For example, if the analog input signal applied to VIN is be-
1.0 FUNCTIONAL DESCRIPTION
The ADC08161 performs an 8-bit analog-to-digital conversion using a multi-step flash technique. The first flash generates the five most significant bits (MSBs) and the second
flash generates the three least significant bits (LSBs). Figure
6 shows the major functional blocks of the ADC08161
multi-step flash converter. It consists of an over-encoded
21⁄2-bit Voltage Estimator, an internal DAC with two different
voltage spans, a 3-bit half-flash converter and a comparator
multiplexer.
The resistor string near the center of the block diagram in
Figure 6 forms the internal main DAC. Each of the eight resistors at the bottom of the string is equal to 1/256 of the total
string resistance. These resistors form the LSB Ladder and
have a voltage drop of 1/256 of the total reference voltage
(VREF+ − VREF−) across them. The remaining resistors make
up the MSB Ladder . They are made up of eight groups of
four resistors connected in series. Each MSB Ladder section
has 1⁄8 of the total reference voltage across it. Within a given
MSB Ladder section, each of the MSB resistors has 8/256,
or 1⁄32 of the total reference voltage across it. Tap points are
found between all of the resistors in both the MSB and LSB
Ladders. Through the Comparator Multiplexer these tap
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Application Information
high at the end-of-conversion. It can be used to signal a processor that the converter is busy or serve as a system Transfer Acknowledge signal.
(Continued)
tween 0 and 3/16 of VREF (VREF = VREF+ − VREF−), the estimator decoder instructs the comparator multiplexer to select
the eight tap points between 8/256 and 2/8 of VREF and connects them to the eight flash comparators. The first flash
conversion is now performed, producing the five MSBs of
data.
The remaining three LSBs are generated next using the
same eight comparators that were used for the first flash
conversion. As determined by the results of the MSB flash, a
voltage from the MSB Ladder equivalent to the magnitude of
the five MSBs is subtracted from the analog input voltage as
the upper switch is moved from position one to position two.
The resulting remainder voltage is applied to the eight flash
comparators and, with the lower switch in position two, compared with the eight tap points from the LSB Ladder.
By using the same eight comparators for both flash conversions, the number of comparators needed by the multi-step
converter is significantly reduced when compared to standard half-flash techniques.
Voltage Estimator errors as large as 1/16 of VREF(16 LSBs)
will be corrected since the flash comparators are connected
to ladder voltages that extend beyond the range specified by
the Voltage Estimator. For example, if 7/16 VREF < VIN <
9/16 VREF the Voltage Estimator’s comparators tied to the
tap points below 9/16 VREF will output “1”s (000111). This is
decoded by the estimator decoder to “10”. The eight flash
comparators will be placed at the MSB Ladder tap points between 3⁄8 VREF and 5⁄8 VREF. The overlap of 1/16 VREF on
each side of the Voltage Estimator’s span will automatically
correct an error of up to 16 LSBs (16 LSBs = 312.5 mV for
VREF = 5V). If the first flash conversion determines that the
input voltage is between 3⁄8 VREF and 4/8 VREF − LSB/2, the
Voltage Estimator’s output code will be corrected by subtracting “1”. This results in a corrected value of “01”. If the
first flash conversion determines that the input voltage is between 8/16 VREF − LSB/2 and 5⁄8 VREF, the Voltage Estimator’s output code remains unchanged.
After correction, the 2-bit data from both the Voltage Estimator and the first flash conversion are decoded to produce the
five MSBs. Decoding is similar to that of a 5-bit flash converter since there are 32 tap points on the MSB Ladder.
However, 31 comparators are not needed since the Voltage
Estimator places the eight comparators along the MSB Ladder where reference tap voltages are present that fall above
and below the magnitude of VIN. Comparators are not
needed outside this selected range. If a comparator’s output
is a “0”, all comparators above it will also have outputs of “0”
and if a comparator’s output is a “1”, all comparators below it
will also have outputs of “1”.
2.2 RD Mode Pipelined Operation
Applications that require shorter RD pulse widths than those
used in the Read mode as described above can be achieved
by setting RD’s width between 200 ns–400 ns (Figure 5). RD
pulse widths outside this range will create conversion linearity errors. These errors are caused by exercising internal interface logic circuitry using CS and/or RD during a conversion.
When RD goes low, a conversion is initiated and the data
from the previous conversion is available on the DB0–DB7
outputs. Reading DB0–DB7 for the first two times after
power-up produces random data. The data will be valid during the third RD pulse that occurs after the first conversion.
2.3 WR-RD (WR then RD ) Mode
The ADC08161 is in the WR-RD mode with the MODE pin
tied high. A conversion starts on the rising edge of the WR
signal. There are two options for reading the output data
which relate to interface timing. If an interrupt-driven scheme
is desired, the user can wait for the INT output to go low before reading the conversion result (Figure 3). Typically, INT
will go low 690 ns, maximum, after WR’s rising edge. However, if a shorter conversion time is desired, the processor
need not wait for INT and can exercise a read after only 350
ns (Figure 2). If RD is pulled low before INT goes low, INT
will immediately go low and data will appear at the outputs.
This is the fastest operating mode (tRD ≤ tINTL) with a conversion time, including data access time, of 560 ns. Allowing
100 ns for reading the conversion data and the delay between conversions gives a total throughput time of 660 ns
(throughput rate of 1.5 MHz).
2.4 WR-RD Mode with Reduced Interface System
Connection
CS and RD can be tied low, using only WR to control the
start of conversion for applications that require reduced digital interface while operating in the WR-RD mode (Figure 4).
Data will be valid approximately 705 ns following WR’s rising
edge.
3.0 REFERENCE INPUTS
The ADC08161’s two VREF inputs are fully differential and
define the zero to full-scale input range of the A to D converter. This allows the designer to vary the span of the analog input since this range will be equivalent to the voltage difference between VREF+and VREF−. Transducers that have
outputs that minimum output voltages above GND can also
be compensated by connecting VREF− to a voltage that is
equal to this minimum voltage. By reducing VREF (VREF =
VREF+–VREF−) to less than 5V, the sensitivity of the converter
can be increased (i.e., if VREF = 2.5V, then 1 LSB = 9.8 mV).
The reference arrangement also facilitates ratiometric operation and in may cases the power supply can be used for
transducer power as well as the VREF source. Ratiometric
operation is achieved by connecting VREF− to GND and connecting VREF+ and a transducer’s power supply input to V+.
The ADC08161s accuracy degrades when VREF+–|VREF−| is
less than 2.0V.
The voltage at VREF− sets the input level that produces a
digital output of all zeroes. Through VIN is not itself differen-
2.0 DIGITAL INTERFACE
The ADC08161 has two basic interface modes which are selected by connecting the MODE pin to a logic high or low.
2.1 RD Mode
With a logic low applied to the MODE pin, the converter is set
to Read mode. In this configuration (Figure 1), a complete
conversion is done by pulling RD low, and holding low, until
the conversion is complete and output data appears. This
typically takes 655 ns. The INT (interrupt) line goes low at
the end of conversion. A typical delay of 50 ns is needed between the rising edge of CS (after the end of a conversion)
and the start of the next conversion (by pulling RD low). The
RDY output goes low after the falling edge of CS and goes
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Application Information
ternal S/H. In a non-sampling converter, regardless of its
speed, the input must remain stable to at least 1⁄2 LSB
throughout the conversion process if full accuracy is to be
maintained. Consequently, for many high speed signals, this
signal must be externally sampled and held stationary during
the conversion.
The ADC08161 is suitable for DSP-based systems because
of the direct control of the S/H through the WR signal. The
WR input signal allows the A/D to be synchronized to a DSP
system’s sampling rate or to other ADC08161s.
The ADC08161 can perform accurate conversions of
full-scale input signals at frequencies from DC to more than
300 kHz (full power bandwidth) without the need of an external sample-and-hold (S/H).
(Continued)
tial, the reference design affords nearly differential-input capability for some measurement applications. Figure 7 shows
one possible differential configuration.
It should be noted that, while the two VREF inputs are fully
differential, the digital output will be zero for any analog input
voltage if VREF− ≥ VREF+.
4.0 ANALOG INPUT AND SOURCE IMPEDANCE
The ADC08161’s analog input circuitry includes an analog
switch with an “on” resistance of 70Ω and a 1.4 pF capacitor
(Figure 7). The switch is closed during the A/D’s input signal
acquisition time (while WR is low when using the WR-RD
Mode). A small transient current flows into the input pin each
time the switch closes. A transient voltage, whose magnitude
can increase as the source impedance increases, may be
present at the input. So long as the source impedance is less
than 500Ω, the input voltage transient will not cause errors
and need not be filtered.
Large source impedances can slow the charging of the sampling capacitors and degrade conversion accuracy. Therefore, only signal sources with output impedances less than
500Ω should be used if rated accuracy is to be achieved at
the minimum sample time (100 ns maximum). A signal
source with a high output impedance should have its output
buffered with an operational amplifier. Any ringing or voltage
shifts at the op amp’s output during the sampling period can
result in conversion errors.
Some suggested input configurations using the internal 2.5V
reference, an external reference, and adjusting the input
span are shown in Figure 8.
Correct conversion results will be obtained for input voltages
greater than GND − 100 mV and less than V+ + 100 mV. Do
not allow the signal source to drive the analog input pin more
than 300 mV higher than V+, or more than 300 mV lower
than GND. The current flowing through any analog input pin
should be limited to 5 mA or less to avoid permanent damage to the IC if an analog input pin is forced beyond these
voltages. The sum of all the overdrive currents into all pins
must be less than 20 mA. Some sort of protection scheme
should be used when the input signal is expected to extend
more than 300 mV beyond the power supply limits. A simple
protection network using resistors and diodes is shown in
Figure 9.
6.0 INTERNAL BANDGAP REFERENCE
The ADC08161 has an internal bandgap 2.5V reference that
can be used as the VREF+ input. A parallel combination of a
0.1 µF ceramic capacitor and a 220 µF tantalum capacitor
should be used to bypass the VREFOUT pin. This reduces
possible noise pickup that could cause conversion errors.
7.0 LAYOUT, GROUNDS, AND BYPASSING
In order to ensure fast, accurate conversions from the
ADC08161, it is necessary to use appropriate circuit board
layout techniques. Ideally, the analog-to-digital converter’s
ground reference should be low impedance and free of noise
from other parts of the system. Digital circuits can produce a
great deal of noise on their ground returns and, therefore,
should have their own separate ground lines. Best performance is obtained using separate ground planes should be
provided for the digital and analog parts of the system.
The analog inputs should be isolated from noisy signal
traces to avoid having spurious signals couple to the input.
Any external component (e.g., an input filter capacitor) connected across the inputs should be returned to a very clean
ground point. Incorrectly grounding the ADC08161 may result in reduced conversion accuracy.
The V+ supply pin, VREF+, and VREF− (if not grounded)
should be bypassed with a parallel combination of a 0.1 µF
ceramic capacitor and a 10 µF tantalum capacitor placed as
close as possible to the pins using short circuit board traces.
See Figures 8, 9.
5.0 INHERENT SAMPLE-AND-HOLD
An important benefit of the ADC08161’s input architecture is
the inherent sample-and-hold (S/H) and its ability to measure relatively high speed signals without the help of an ex-
DS011149-18
FIGURE 7. ADC08161 Equivalent Input Circuit Model
13
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Application Information
Internal Reference 2.5V Full-Scale
(Standard Application)
(Continued)
Power Supply as Reference
Input Not Referred to GND
DS011149-20
DS011149-21
DS011149-19
*Signal source driving VIN(−) must be capable
of sinking 5 mA.
Note: Bypass capacitors consist of a 0.1 µF ceramic in parallel with a 10 µF bead tantalum, unless otherwise specified.
FIGURE 8. Analog Input Options
DS011149-22
FIGURE 9. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. VREF−
should be bypassed to analog ground using multiple capacitors if it is not grounded (See Section 7.0 “LAYOUT,
GROUNDS, and BYPASSING”). VIN1 is shown with an optional input protection network.
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14
inches (millimeters) unless otherwise noted
Wide-Body Small-Outline
Order Number ADC08161CIWM
NS Package Number M20B
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ADC08161 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference
Physical Dimensions