Anpec APT7843NI Touch screen controller Datasheet

APT7843
Touch Screen Controller
Description
Features
The APT7843 Touch Screen Controller IC provides all
the screen drive , A/D converter and control circuits
to easily interface to 4 wire resistive touch screen.
The IC continually monitors the screen waiting for a
touch. When the screen touched , the IC performs
A/D converter to determine the location of touch.
Also , this device has 2 auxiliary input to A/D converter , allowing for the measurement of other inputs
such as battery voltage.
•
•
•
•
Operates with four wire touch screen
8-bit or 12 bit A/D converter
Ratiometric Conversion eliminates screen
calibration
•
•
•
Applications
•
•
•
16 pin SSOP or TSSOP
2 auxiliary analog inputs
4 wire serial interface
Full power down control
Pin Assignment
PDAs
Handheld computer
Touch-screen kiosks
+Vcc
1
16
DCLK
X+
2
15
CS
Y+
3
14
DIN
X-
4
13
BUSY
Y-
5
12
DOUT
GND
6
11 PENIRQ
IN3
7
10
+Vcc
IN4
8
9
VREF
Order Information
APT7843
Package Code
N : SSOP
Temp. Range
I : - 40 to 85 ° C
Temp. Range
O : TSSOP
Package Code
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
1
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APT7843
Block Diagram
PENIRQ
X+
DCLK
XCS
Screen Driver
Y+
Y-
12 Bit or 8 Bit
A/D Converter
MUX
Serial
Interface
IN3
DIN
DOUT
IN4
BUSY
VREF
Pin Descriptions
PIN
NAME
1
2
3
4
5
+Vcc
X+
Y+
XY-
6
7
8
9
GND
IN3
IN4
VREF
10
11
12
13
14
15
16
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
DESCRIPTION
Power Supply,2.2V to 5V.
Connect to X+ on touch screen.
Connect to Y+ on touch screen.
Connect to X- on touch screen.
Connect to Y- on touch screen.
Ground
Auxiliary Input of A/D converter.
Auxiliary input of A/D converter.
Voltage Reference Input.
+Vcc
Power Supply,2.2V to 5V.
PENIRQ Pen interrupt. Open anode output (requires
10kΩ to 100kΩ pull-up resistor externally)
DOUT Serial Data Output. This output is high
impedance when CS is HIGH.
BUSY Busy Output. This output is high impedance
when CS is HIGH.
DIN
Serial Data input.
CS
DCLK
Chip Select. (Active Low)
Serial Clock.
2
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APT7843
Electrical Characteristics
At TA = -40°C to 85°C , VCC = +2.7V , VREF = +2.5V , fSAMPLE = 125kHz , fCLK = 16 • f SAMPLE = 2MHz , 12-bit mode
, and digital inputs = GND or Vcc , unless otherwise noted.
PA R A M E T E R
C O N D IT IO N S
A P T 78 43
M IN
TYP
MAX
U N IT S
DC ACCURACY
R esolu tio n
12
N o m issing co de
B its
11
B its
Integra l N onlin earity
± 2
LS B
O ffset E rror
± 6
LS B
O ffset E rror M atch
0.1
G ain E rror
G ain E rror M atch
0.1
1
LS B
± 4
LS B
1
LS B
N oise
30
uV rm s
P ow er S u pply R ejectio n
70
dB
R E F E R A N C E IN P U T
V R E F In put Voltage R an ge
1.0
V cc
D C Le akage C urrent
V R E F In put Im p eda nce
C S = G N D or V cc
V R E F In put C urrent
± 1
µA
5
GΩ
13
F S A M P LE = 12 .5 kH z
40
µA
3
µA
µA
2.5
C S = V cc
D Y N A M IC P E R F O R E N C E
A perture D e lay
30
ns
A perture Jitter
100
ps
100
dB
C han nel to C han ne l Isolation
V IN = 2.5 V p-p ; F IN = 5 0kH z
C O N V E R S IO N R AT E
C onversion Tim e
12
Track/H old A cquis ition Tim e
3
DCLK cycles
DCLK cycles
T hrough put R ate
125
KSPS
S W IT C H D R IV E R S
O n-R esistance
Y+ , X+
4
15
Ω
Y- , X-
4
15
Ω
L O G IC O U T P U T S
O utput H ig h Vo lta ge , V O H
|I O H | ≤ -250µ A
O utput Low Voltage , V O L
|I O L | ≤ 250µ A
V cc–0.2
V
0.4
V
PEN IR Q output low voltage , V O L
0.2
V
Floating-S tate Leakage C urrent
± 10
µA
10
pF
Floating-State Output Capacitance
O utput C oding
S traight ( N atura l ) B in ary
Note : (1) LSB means least Significant Bit. With VREF equal to +2.5V , one LSB is 610µV
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
3
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APT7843
Electrical Characteristics (Cont.)
PA R A M E T E R
C O N D IT IO N S
L O G IC IN P U T S
In p u t H ig h Vo lta g e ,
V INH
In p u t L o w Vo lta g e ,
V INL
Inp ut C urre nt , IIN
In p u t C a p a c ita n c e ,
C IN
A N ALO G IN P U T
| I I N H | ≤ + 5 µA
APT7843
M IN
TYP
2.4
0
D C Le aka ge C u rre nt
In p u t C a p a c ita n c e
U N IT S
V
| I I N L | ≤ + 5 µA
In p u t Vo lta g e R a n g e s
MAX
0.8
V
± 1
µA
10
pF
V REF
Vo lts
± 0.1
µA
30
pF
P O W E R R EQ U IR E M EN T S
Vcc
Ic c
2.7
3.6
V
V cc = 3.6V
650
µA
V cc = 3.6V
540
µA
3
µA
3.6
µW
D ig ita l I/P s = 0 V o r V cc
N orm a l M o d e (S ta tic )
N orm al M od e (F S A M P L E =
1 2 .5k S P S )
S hutdow n
M o d e (S ta tic)
Showdown
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
V cc = 3.6V
4
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APT7843
Electrical Characteristics
At TA = -40°C to 85°C, VCC = +2.4V , VREF don’t care, fSAMPLE = 1.25KHz, fCLK = 16 • f SAMPLE = 20KHz, 8-bit
differential mode, no support single end mode, and digital inputs = GND or Vcc , unless otherwise noted.
PARAMETER
CONDITIONS
APT7843
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
8
No missing code
Bits
7
Bits
Integral Nonlinearity
Offset Error
Offset Error Match
0.1
Gain Error
±2
LSB
±6
LSB
1
LSB
±4
LSB
1
LSB
Gain Error Match
0.1
Noise
30
uV rms
Power Supply Rejection
70
dB
30
ns
DYNAMIC PERFORENCE
Aperture Delay
Aperture Jitter
Channel to Channel Isolation
VIN = 2.5Vp-p ; FIN = 50kHz
100
ps
100
dB
CONVERSION RATE
Conversion Time
12
Track/Hold Acquisition Time
3
DCLK cycles
DCLK cycles
Throughput Rate
1.25
KSPS
Y+ , X+
4
Ω
Y- , X-
4
Ω
SWITCH DRIVERS
On-Resistance
LOGIC OUTPUTS
Output High Voltage , VOH
|IOH| ≤ -250µA
Output Low Voltage , VOL
|IOL| ≤ 250µA
Vcc–0.2
V
0.4
V
PENIRQ output low voltage , VOL
0.2
V
Floating-State Leakage Current
± 10
µA
Floating-State Output Capacitance
10
pF
Output Coding
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
Straight ( Natural ) Binary
5
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APT7843
Electrical Characteristics (Cont.)
PA R A M E T E R
C O N D IT IO N S
APT7843
M IN
TYP
MAX
U N IT S
L O G IC IN P U T S
In p u t H ig h Vo lta g e , V IN H
| I I N H | ≤ + 5 µA
In p u t L o w Vo lta g e , V INL
| I I N L | ≤ + 5 µA
2.2
VDD+0.2
V
0.6
V
In p u t C urr e n t , IIN
± 1
µA
In p u t C a p a c it a n c e , C IN
10
pF
V REF
Vo lts
A NALOG IN PUT
In p u t Vo lt a g e R a n g e s
0
D C Leakage C urrent
In p u t C a p ac ita n c e
± 0 .1
µA
30
pF
P O W E R R E Q U IR E M E N T S
Vcc
Ic c
2.2
2.4
3.6
V
280
650
µA
µA
D ig ita l I/P s =0 V o r V cc
N orm a l M o d e (S ta tic )
N orm a l M o de (F S A M P L E =
1 2.5k S P S )
S h u td o w n M o d e (S ta tic)
V cc = 2.4V
V cc = 2.4V
540
3
µA
Showdown
V cc = 2.4V
3.6
µW
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
6
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APT7843
Chip Overview
Analog Input
The APT7843 is a successive approximation analogto-digital (A/D) converter based around a capacitive
redistribution DAC. Figure 1 show basic operation of
the APT7843.
The APT7843 communicates via a 4-wire serial
interface. The device also requires an external reference voltage Vref. The value of the reference voltage
directly sets the input range of the converter.
The analog input to the converter is provided via a
four-channel multiplexer. Figure 2 shows a simplified
diagram of the APT7843 with the difference input of
the A/D converter , and the converter’s reference.
Table I and Table II also show the relationship between
the A2 , A1 , A0 , SER/ DFR and the configuration of
the APT7843. See the section of single-ended reference mode and differential reference mode for more
details.
The APT7843 primary function is to control resistive
touchscreens. When a touch is detected , pen interrupt pin will go low to wake up extenal microprocess.
The microprocessor writes register to initiate
conversion.
This A/D converter may also be used to measure
voltage presented on the IN3 , IN4 pins.
+2 .2 V to +5 V
1u F
to
10 uF
(O ptio nal)
A P T 784 3
0.1u F
To
T o uch
S c ree n
DCLK
16
X+
CS
15
3
Y+
D IN
14
4
X-
BUSY
13
5
Y-
DOUT
12
6
GND
P E N IR Q
11
7
IN 3
+V c c
10
8
IN 4
V RE F
9
1
+V c c
2
A u xiliary Inpu t
C on nec t to
M icropros sor
10 0k oh m (op tion al)
0.1u F
FIGURE 1. Basic Operation of the APT7843
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
7
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APT7843
+Vcc
PENIRQ
VREF
A2-A0
(Shown 001 B)
SER/DFR
(Shown HIGH)
X+
X-
Y+
+IN
Y-
-IN
+REF
CONVERTER
-REF
IN3
IN4
GND
FIGURE 2. Simplified Diagram of Analog Input
A2
0
1
0
1
A1
0
0
1
1
A0
1
1
0
0
X+
+IN
Y+
IN3
IN4
+IN
+IN
+IN
-IN
GND
GND
GND
GND
X SWITCHES Y SWITCHES
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
+REF
+VREF
+VREF
+VREF
+VREF
-REF
GND
GND
GND
GND
+REF
+Y
+X
+VREF
+VREF
-REF
-Y
-X
GND
GND
TABLE I. Input C onfiguration, Single-Ended Reference Mode (SER/ DFR HIGH).
A2
0
1
0
1
A1
0
0
1
1
A0
1
1
0
0
X+
+IN
Y+
IN3
IN4
+IN
+IN
+IN
-IN
-Y
-X
GND
GND
X SWITCHES Y SWITCHES
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
TABLE II. Input Configuration, Differential Reference Mode (SER/ DFR LOW).
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
8
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APT7843
Single-Ended reference mode
+Vcc
Figure 3 shows the diagram of single-ended reference mode.
This application shows the measurement of current
Y poisition is made by connecting the X+ input to the
A/D converter, turning on the Y+ and Y- drivers, and
digitizing the voltage on X+ . For this measurement,
the resistance in the X+ lead does not affect the conversion. However, since the resistance between Y+
and Y- is fairly low, the on-resistance of the Y drivers
does make a small difference. Under the situation outlined so far, it would not be possible to achieve a zero
volt input or a full-scale input regardless of where the
pointing device is on the touch screen because some
voltage is lost across the internal switches. This situation can be remedied if use differential reference mode
Y+
Y+
X+
-IN
Y-
GND
Figure 4. Differential Reference Mode
(SER/DFR LOW, A2=Low,A1=Low,A0=High)
Serial Interface
Data is written to,and read from , the APT7843 via
the serial port. The serial port has 4 pins - serial
clock (DCLK),chip select ( CS ) ,data in (DIN) and
data out (DOUT). The DCLK acts on the rising edge.
The CS acts as a reset for the serial port with CS goes
low initating a conversion cycle. The cycle consists
of 2 parts - a write followed by a read. Figure 5
shows the typical timing of the APT7843’s serial
interface. A total of 24 clock cycles will complete
one conversion.
Also shown in Figure 5 is the placement and order of
the control bits within the control byte. Tables III and
IV give detailed information about these bits.
The first bit, the ′S′ bit, must always be HIGH and
indicates the start of the control byte. The APT7843
will ignore inputs on the DIN pin until the start bit S
detected.
The next three bits (A2 - A0) select the active input
channel or channels of the input multiplexer (see Tables
I and II and Figure 2).
The MODE bit determines the number of bits for each
conversion, either 12 bits (LOW) or 8 bits (HIGH).
The SER/DFR bit controls the reference mode: either
single-ended (HIGH) or differential (LOW). (The differential mode is also referred to as the ratiometric
conversion mode.)
The last two bits (PD1 - PD0) select the power- down
mode as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are
LOW, the device enters a power-down mode between conversions.
VREF
+IN
+REF
Converter
-IN
-REF
GND
Y Switch ON
GND
FIGURE 3.Single-Ended Reference Mode
(SER/DFR High, A2=Low,A1=Low,A0=High)
Differential reference mode
As shown in Figure 4,by setting the SER/ DFR bit
LOW, the +REF and -REF inputs are connected directly to Y+ and Y-. This makes the analog-to- digital
conversion ratiometric.
The result of the conversion is always a percentage
of the external resistance, reardless of how it changes
in relation to the on-resistance of the internal switches.
Note that there is an important consideration regarding power dissipation when using the ratiometric mode
of operation,the external device should powered
throughout the acquisition and conversion periods.
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
-REF
YY Switch ON
Y+
Y-
+REF
Converter
+Vcc
X+
+IN
9
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APT7843
Bit 7
(MSB)
Bit 6
S
A2
Bit 5
A1
Bit 4
Bit 3
A0
Bit 2
Bit 1
MODE SER/DFR
Bit 0
(LSB)
PD1
PD1 PD0
PD0
TABLE III. Order of the Control Bits in the Control
Byte.
BIT
NAME
7
S
6-4
2
1-0
DESCRIPTION
Start Bit. Control byte starts with first HIGH bit on
DIN. A new control byte can start every 15th clock
cycle in 12-bit conversion mode or every 11th clock
cycle in 8-bit conversion mode.
A2-A0 Channel Select Bits. Along with the SER/DFR bit,
these bits control the setting of the multiplexer
input, switches, and reference inputs, as detailed in
Tables I and II.
MODE 12-Bit/8-Bit Conversion Select Bit. This bit controls
the number of bits for the following conversion: 12bits(LOW) or 8-bits(HIGH).
SER/DFR Single-Ended/Differential Reference Select Bit.
Along with bits A2-A0, this bit controls the setting of
the multiplexer input, switches, and reference
inputs, as detailed in Tables I and II.
PD1-PD0 Power-Down Mode Select Bits. See Table V for
details.
PENIRQ DESCRIPTION
0
0
Enabled Power-down between conversions. When
each conversion is finished, the converter
enters a low power mode.
0
1
Enabled Reserved for future use
1
0
Enabled Reserved for future use.
1
1
Disabled No power-down between conversions,
device is always powered.
TABLE V. Power-Down Selection.
TABLE IV. Descriptions of the Control Bits within the
Control Byte.
CS
DCLK
1
8
1
8
1
8
tACQ
DIN
S
A2 A1
A0
MODE
SER/
DFR
PD1 PD0
(START)
ldle
Acquire
Conversion
ldle
BUSY
DOUT
11 10 9
(MSB)
8 7
6
5
4
3
2
1
0
(LSB)
FIGURE 5. Conversion Timing, 24-Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required
with Dedicated Serial Port.
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
10
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APT7843
CS
DCLK
1
DIN
8
1
8
S
1
8
1
S
CONTROL BITS
CONTROL BITS
BUSY
DOUT
11 10 9 8 7 6 5
4 3 2 1 0
11 10 9
FIGURE 6. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required
with Dedicated Serial Port.
16-Clocks or 15-Clocks per Conversion
AC Timing
Figure 8 and Table VI provide detailed timing of the
APT7843. Table VII provide detailed timing of low power
VCC=2.4V.
The APT7843 will alow a conversion every 16 clock
cycles, as shown in Figure 6. This figure shows
possible serial communication occurring with other
serial peripherals between each byte transfer between
the processor and the converter.
Figure 7 provides the fastest way to clock the
APT7843. This method will not work with the serial
interface of most microcontrollers and digital signal
processors as they are generally not capable of providing 15 clock cycles per serial transfer. However,
this method could be used with field programmable
gate arrays (FPGAs) or application specific integrated
circuits (ASICs). (Note that this effectively increases
the maximum conversion rate of the converter).
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
11
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APT7843
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tACQ
Acquisition Time
1.5
µs
tACQ
Acquisition Time
20
µs
tDS
DIN Valid Prior to DCLK Rising
100
ns
tDS
DIN Valid Prior to DCLK Rising
400
ns
tDH
DIN Hold After DCLK HIGH
10
20
tDO
DCLK Falling to DOUT Vaild
200
ns
tDH
DIN Hold After DCLK HIGH
ns
tDO
DCLK Falling to DOUT Vaild
ns
400
ns
tDV
CS Falling to DOUT Enabled
200
ns
tDV
CS Falling to DOUT Enabled
400
ns
tTR
CS Rising to DOUT Disabled
200
ns
tTR
CS Rising to DOUT Disabled
400
ns
tCSS
CS Falling to DCLK Rising
100
ns
tCSS
CS Falling to DCLK Rising
200
ns
CS Rising to DCLK lgnored
0
ns
tCSH
CS Rising to DCLK lgnored
0
ns
tCSH
tCH
DCLK HIGH
200
ns
tCH
DCLK HIGH
2.5
µs
tCL
DCLK LOW
200
ns
tCL
DCLK LOW
2.5
µs
tBD
DCLK Falling to BUSY Rising
200
ns
tBD
DCLK Falling to BUSY Rising
400
tBDV
CS Falling to BUSY Enabled
200
ns
tBDV
CS Falling to BUSY Enabled
400
ns
tBTR
CS Rising to BUSY Disable
200
ns
tBTR
CS Rising to BUSY Disable
400
ns
TABLE VI. Timing Specifications (+Vcc=+2.7V and
Above, TA=-40°C to +85°C, CLOAD=50pF).
ns
TABLE VI. Timing Specifications (+Vcc=+2.4V and
Above, TA=-40°C to +85°C, CLOAD=50pF).
CS
DCLK
1
DIN
S
15 1
A2 A1 A0
MODE
SGL/
DIF
S
PD1 PD0
15 1
A2 A1 A0
MODE
SGL/
DIF
PD1 PD0
S
A2 A1 A0
BUSY
DOUT
11 10 9 8 7 6 5 4 3 2 1 0
11 10 9 8 7 6 5 4 3 2
FIGURE 7. Maximum Conversion Rate, 15-Clocks per Conversion.
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
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APT7843
CS
tCSS
tCL
tCH
tBD
tBD
tBD
tCSH
DCLK
tDS
DIN
tDH
PD0
tBDV
tBTR
BUSY
DOUT
tTR
tDV
11
10
FIGURE 8. Detailed Timing Diagram.
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
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APT7843
Packaging Information
SSOP
D
N
H
GAUGE
PLANE
E
1 2 3
A
Millimeters
1
A1
B
e
L
Variations- D
Inches
Variations- D
Dim
Min.
Max.
Variations
Min.
Max.
Dim
Min.
Max. Variations
Min.
Max.
A
1.350
1.75
SSOP-16
4.75
5.05
A
0.053
0.069
0.187
0.199
A1
0.10
0.25
A1
0.004
0.010
B
0.20
0.30
B
0.008
0.012
D
See variations
D
See variations
E
3.75
E
0.147
e
4.05
0.625 TYP.
e
0.160
0.025 TYP.
H
5.75
6.25
H
0.226
0.246
L
0.4
1.27
L
0.016
0.050
See variations
N
See variations
N
φ1
0°
φ1
8°
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
14
SSOP-16
0°
8°
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APT7843
Packaging Information
TSSOP
e
N
2x E/2
E1
1 2 3
E
0.25
A2
A
A1
b
A
A1
A2
b
D
e
E
E1
L
φ1
φ2
φ3
GAUGE
PLANE
e/2
D
Dim
( 2)
L
( 3)
Millimeters
Inches
Min.
Max.
1.2
0.00
0.15
0.80
1.05
0.19
0.30
5.1 (N=16PIN)
4.9 (N=16PIN)
6.6 (N=20PIN)
6.4 (N=20PIN)
7.9 (N=24PIN)
7.7 (N=24PIN)
9.8 (N=28PIN)
9.6 (N=28PIN)
0.65 BSC
6.40 BSC
4.30
4.50
0.45
0.75
0°
8°
12° REF
12° REF
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
1
15
Min.
Max.
0.047
0.000
0.006
0.031
0.041
0.007
0.011
0.201 (N=16PIN)
0.193 (N=16PIN)
0.260 (N=20PIN)
0.252 (N=20PIN)
0.311 (N=24PIN)
0.303 (N=24PIN)
0.386 (N=28PIN)
0.378 (N=28PIN)
0.026 BSC
0.252 BSC
0.169
0.177
0.018
0.030
0°
8°
12° REF
12° REF
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APT7843
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
(IR/Convection or VPR Reflow)
temperature
Reflow Condition
Peak temperature
183°C
Pre-heat temperature
Time
Classification Reflow Profiles
Convection or IR/
Convection
Average ramp-up rate(183°C to Peak)
3°C/second max.
120 seconds max
Preheat temperature 125 ± 25°C)
60 – 150 seconds
Temperature maintained above 183°C
Time within 5°C of actual peak temperature 10 –20 seconds
Peak temperature range
220 +5/-0°C or 235 +5/-0°C
Ramp-down rate
6 °C /second max.
6 minutes max.
Time 25°C to peak temperature
VPR
10 °C /second max.
60 seconds
215-219°C or 235 +5/-0°C
10 °C /second max.
Package Reflow Conditions
pkg. thickness ≥ 2.5mm
and all bgas
Convection 220 +5/-0 °C
VPR 215-219 °C
IR/Convection 220 +5/-0 °C
pkg. thickness < 2.5mm and
pkg. volume ≥ 350 mm³
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
16
pkg. thickness < 2.5mm and pkg.
volume < 350mm³
Convection 235 +5/-0 °C
VPR 235 +5/-0 °C
IR/Convection 235 +5/-0 °C
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APT7843
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
Method
MIL-STD-883D-2003
MIL-STD 883D-1005.7
JESD-22-B, A102
MIL-STD 883D-1011.9
Description
245°C,5 SEC
1000 Hrs Bias @ 125°C
168 Hrs, 100% RH, 121°C
-65°C ~ 150°C, 200 Cycles
Carrier Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
F
W
Ao
D1
Ko
T2
J
C
A
B
T1
Application
SSOP-14/16
A
B
D0
6.95
5.4
T
T2
W
0.3±0.05
2.2
12.0±0.3
D1
E
F
P0
P1
P2
1.75±0.1
5.5±0.05
4.0±0.1
8.0±0.1
2.0±0.05
W1
C1
C2
T1
T2
C
9.5
13±0.3
21±0.8
13.5±0.5
2.0±0.2
80±1
1.55±0.05 1.55±0.1
(mm)
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
17
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APT7843
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.8 - Apr., 2002
18
www.anpec.com.tw