ICST ICS85310AYI21 Low skew, dual, 1-to-5 differential-to-2.5v/3.3v ecl/lvpecl fanout buffer Datasheet

Integrated
Circuit
Systems, Inc.
ICS85310I-21
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85310I-21 is a low skew, high performance dual 1-to- 5 Differential-to-2.5V/3.3V
HiPerClockS™
ECL/LVPECL Fanout Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The CLKx, nCLKx
pairs can accept most standard differential input levels.
The ICS85310I-21 is characterized to operate from either a
2.5V or a 3.3V power supply. Guaranteed output and partto-part skew characteristics make the ICS85310I-21 ideal
for those clock distribution applications demanding well
defined performance and repeatability.
• 2 differential 2.5V/3.3V LVPECL / ECL bank outputs
ICS
• 2 differential clock input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLKx input
• Output skew: 25ps (typical)
• Part-to-part skew: 270ps (typical)
• Propagation delay: 1.7ns (typical)
• Additive phase jitter, RMS: <0.13ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS complaint
BLOCK DIAGRAM
CLKA
nCLKA
PIN ASSIGNMENT
QA0
nQA0
VCCO
nQA2
QA2
nQA1
QA4
nQA4
QB0
nQB0
VCC
1
24
QA3
nc
2
23
nQA3
CLKA
3
22
QA4
nCLKA
4
21
nQA4
nc
5
20
QB0
CLKB
6
19
nQB0
nCLKB
7
18
QB1
VEE
8
17
nQB1
QB1
nQB1
ICS85310I-21
9 10 11 12 13 14 15 16
VCCO
QB2
nQB2
QB3
nQB3
QB4
nQB4
VCCO
QB2
nQB2
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
QB3
nQB3
QB4
nQB4
85310AYI-21
QA1
32 31 30 29 28 27 26 25
QA3
nQA3
CLKB
nCLKB
QA0
QA2
nQA2
nQA0
VCCO
QA1
nQA1
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ICS85310I-21
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VCC
Power
Type
2, 5
nc
Unused
3
CLKA
Input
4
nCLKA
Input
6
CLKB
Input
7
nCLKB
Input
8
VEE
Power
Description
Core supply pin.
No connect.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Negative supply pin.
9, 16, 25, 32
VCCO
Power
Output supply pins.
10, 11
nQB4, QB4
Output
Differential output pair. LVPECL interface levels.
12, 13
nQB3, QB3
Output
Differential output pair. LVPECL interface levels.
14, 15
nQB2, QB2
Output
Differential output pair. LVPECL interface levels.
17, 18
nQB1, QB1
Output
Differential output pair. LVPECL interface levels.
19, 20
nQB0, QB0
Output
Differential output pair. LVPECL interface levels.
21, 22
nQA4, QA4
Output
Differential output pair. LVPECL interface levels.
23, 24
nQA3, QA3
Output
Differential output pair. LVPECL interface levels.
26, 27
nQA2, QA2
Output
Differential output pair. LVPECL interface levels.
28, 29
nQA1, QA1
Output
Differential output pair. LVPECL interface levels.
30, 31
nQA0, QA0
Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
CLKA or CLKB
nCLKA or nCLKB
0
1
1
0
Outputs
QA0:QA4,
nQA0:nQA4,
QB0:QB4
nQB0:nQB4
LOW
HIGH
HIGH
LOW
Input to Output Mode
Polarity
Differential to Differential
Non Inver ting
Differential to Differential
Non Inver ting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inver ting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Negative Supply Voltage, VEE
4.6V
-4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
50mA
100mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
2.375
3.3
3.8
V
VCCO
Output Supply Voltage
2.375
3.3
3.8
V
IEE
Power Supply Current
120
mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VVCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
Minimum
Typical
Maximum
Units
CLKA, CLKB
VCC = VIN = 3.8V
15 0
µA
nCLKA, nCLKB
VCC = VIN = 3.8V
5
µA
CLKA, CLKB
VCC = 3.8V, VIN = 0V
-5
µA
nCLKA, nCLKB
VCC = 3.8V, VIN = 0V
-150
µA
0.15
1.3
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLKA, nCLKA and CLKB, nCLKB is VCC + 0.3V.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 1.0
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
0.85
V
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
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ICS85310I-21
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
Test Conditions
Minimum
IJ 500MHz
Typical
1.7
Maximum
Units
700
MHz
2.2
ns
tsk(o)
Output Skew; NOTE 2, 4
25
50
ps
tsk(pp)
270
550
ps
tR
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise Time
20% to 80%
200
700
ps
tF
Output Fall Time
20% to 80%
200
700
ps
53
%
tjit
<0.13
odc
Output Duty Cycle
47
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS85310I-21
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
Additive Phase Jitter, RMS
-20
@ 155.52MHz = <0.13ps typical
-30
-40
-50
SSB PHASE NOISE dBc/HZ
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC,
Qx
VCC
SCOPE
VCCO
nCLKA, nCLKB
LVPECL
V
Cross Points
PP
VEE
V
CMR
CLKA, CLKB
nQx
V EE
-0.375V to -1.8V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
nQy
nQy
Qx
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLKA,
nCLKB
80%
80%
CLKA,
CLKB
VSW I N G
Clock
Outputs
20%
20%
nQAx,
nQBx
tF
tR
QAx,
QBx
OUTPUT RISE/FALL TIME
tPD
PROPAGATION DELAY
nQA0:nQA4,
nQB0:nQB4
QA0:QA4,
QB0:QB4
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
VCC - 2V
Zo = 50Ω
RTT
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
85310AYI-21
FIN
50Ω
84Ω
FIGURE 2B. LVPECL OUTPUT TERMINATION
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TERMINATION
FOR
ICS85310I-21
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
2.5V LVPECL OUTPUTS
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in Figure 3C.
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
-
2,5V LVPECL
Driv er
2,5V LVPECL
Driv er
R2
62.5
R1
50
R4
62.5
R2
50
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
BY
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
BY
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVDS DRIVER
BY
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER WITH AC COUPLE
85310AYI-21
BY
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85310I-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85310I-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 120mA = 456mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.2mW = 302mW
Total Power_MAX (3.8V, with all outputs switching) = 4564mW + 302mW = 758mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.758W * 42.1°C/W = 117°C. This is below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
32-PIN LQFP, FORCED CONVECTION
θ by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
200
500
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
Figure 5. LVPECL DRIVER CIRCUIT
TERMINATION
AND
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
OL_MAX
-V
Pd_H = [(V
– (V
CCO_MAX
OH_MAX
OL_MAX
CCO_MAX
– 1.0V
) = 1.0V
For logic low, VOUT = V
(V
=V
=V
CCO_MAX
– 1.7V
) = 1.7V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
OH_MAX
) = [(2V - (V
CCO_MAX
))/R ] * (V
-V
OH_MAX
CCO _MAX
L
-V
)=
OH_MAX
[(2V - 1V)/50Ω] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
) = [(2V - (V
OL_MAX
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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RELIABILITY INFORMATION
TABLE 7.
θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85310I-21 is: 1216
Pin compatible with MC100LVEP210
85310AYI-21
www.icst.com/products/hiperclocks.html
12
REV. D JUNE 30, 2005
ICS85310I-21
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
FOR
32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
0.80 BASIC
e
0.60
0.75
L
0.45
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
85310AYI-21
www.icst.com/products/hiperclocks.html
13
REV. D JUNE 30, 2005
Integrated
Circuit
Systems, Inc.
ICS85310I-21
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS85310AYI-21
ICS85310AYI21
32 lead LQFP
tray
-40°C to 85°C
ICS85310AYI-21T
ICS85310AYI21
32 lead LQFP
1000 tape & reel
-40°C to 85°C
ICS85310AYI-21LN
ICS85310AI21N
32 lead LQFP, "Lead-Free Annealed"
250 per tray
-40°C to 85°C
ICS85310AYI-21LNT
ICS85310AI21N
32 lead LQFP "Lead-Free Annealed"
1000
-40°C to 85°C
NOTE: Par ts that are ordered with an "LN" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
85310AYI-21
www.icst.com/products/hiperclocks.html
14
REV. D JUNE 30, 2005
Integrated
Circuit
Systems, Inc.
ICS85310I-21
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table
A
Page
8
B
13
T4A
3
9
2
3
7
8
13
1
13
1
4
5
14
Power Considerations have re-adjusted to the increased IEE value.
Pin Characteristics table - changed CIN from 4pF max. to 4pF typical.
Updated Absolute Maximum Rating.
Added Termination for 2.5V LVPECL Outputs.
Added Differential Clock Input Interface.
Ordering Information table - added "Lead Free Annealed" marking.
Added Lead-Free bullet in Features section.
Ordering Information table - corrected "Lead Free" par t/order number.
Features Section - added Additive Phase Jitter bullet.
AC Characteristics Table - added Additive Phase Jitter row.
Added Additive Phase Jitter Section.
Ordering Information Table - added Lead-Free Note.
T2
C
C
D
T9
T5
T9
85310AYI-21
Date
T9
A
A
Description of Change
Added Termination for LVPECL Outputs.
Updated par t number from ICS85310-21 to ICS85310I-21 throughout the data
sheet to reflect operating temperature.
Ordering Information Table - corrected Marking from ICS85310AYI-21 to
ICS85310AYI21.
Power Supply table - increased max. value for IEE to 120mA from 30mA max.
www.icst.com/products/hiperclocks.html
15
5/30/02
7/24/02
7/25/02
10/23/02
4/14/04
10/8/04
6/30/05
REV. D JUNE 30, 2005
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