IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240 CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • • • • • The IDT72420/72200/72210/72220/72230/72240 SyncFIFO are very high-speed, low-power First-In, FirstOut (FIFO) memories with clocked read and write controls. The IDT72420/72200/72210/72220/72230/72240 have a 64, 256, 512, 1024, 2048, and 4096 x 8-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs, such as graphics, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 8-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and a write enable pin (WEN). Data is written into the Synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and a read enable pin (REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. An output enable pin (OE) is provided on the read port for three-state control of the output. These Synchronous FIFOs have two end-point flags, Empty (EF) and Full (FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are provided for improved system control. The partial ( AE) flags are set to Empty+7 and Full-7 for AE and AF respectively. The IDT72420/72200/72210/72220/72230/72240 are fabricated using IDT’s high-speed submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B. • • • • • • • • • 64 x 8-bit organization (IDT72420) 256 x 8-bit organization (IDT72200) 512 x 8-bit organization (IDT72210) 1024 x 8-bit organization (IDT72220) 2048 x 8-bit organization (IDT72230) 4096 x 8-bit organization (IDT72240) 12 ns read/write cycle time (IDT72420/72200/72210) 15 ns read/write cycle time (IDT72220/72230/72240) Read and write clocks can be asynchronous or coincidental Dual-Ported zero fall-through time architecture Empty and Full flags signal FIFO status Almost-empty and almost-full flags set to Empty+7 and Full-7, respectively Output enable puts output data bus in high-impedance state Produced with advanced submicron CMOS technology Available in 28-pin 300 mil plastic DIP and 300 mil ceramic DIP For surface mount product please see the IDT72421/ 72201/72211/72221/72231/72241 data sheet Military product compliant to MIL-STD-883, Class B Industrial temperature range (-40OC to +85OC) is available, tested to military electrical specifications FUNCTIONAL BLOCK DIAGRAM D0 - D7 WCLK WEN • INPUT REGISTER • FLAG LOGIC WRITE CONTROL LOGIC •• RAM ARRAY 64 x 8 256 x 8 512 x 8 •• WRITE POINTER EF AE AF FF READ POINTER READ CONTROL LOGIC OUTPUT REGISTER • RESET LOGIC RS RCLK OE Q0 - Q7 REN 2680 drw 01 The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. NOVEMBER 1996 DSC-2680/6 For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.12 1 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATION D4 1 28 D5 D3 2 27 D6 D2 3 26 D7 D1 4 25 D0 5 24 RS WEN 6 23 WCLK 22 VCC 21 Q7 AF AE 7 P28-2 C28-1 GND 8 RCLK 9 20 Q6 10 19 Q5 11 18 Q4 12 17 Q3 13 16 Q2 14 15 Q1 REN OE EF FF Q0 DIP TOP VIEW 2680 drw 02 PIN DESCRIPTIONS Symbol D0 - D7 Name Data Inputs RS Reset I WCLK Write Clock I WEN Write Enable I Q0 - Q7 Data Outputs O Data outputs for a 8-bit bus. RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted. REN Read Enable I OE Output Enable I EF Empty Flag O Almost-Empty Flag O When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized to RCLK. AF Almost-Full Flag O When AF is LOW, the FIFO is almost full based on the offset Full-7. WCLK. FF Full Flag O VCC Power One +5 volt power supply pin. GND Ground One 0 volt ground pin. AE I/O I Description Data inputs for a 8-bit bus. When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and AF go HIGH, and AE and EF go LOW. A reset is required before an initial WRITE after power-up. Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted. When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. Data will not be written into the FIFO if the FF is LOW. When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. AF is synchronized to When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. 2680 tbl 01 5.12 2 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TA TBIAS TSTG IOUT Rating Commercial Terminal Voltage –0.5 to + 7.0 with Respect to GND Operating 0 to + 70 Temperature Temperature –55 to + 125 Under Bias Storage –55 to + 125 Temperature DC Output 50 Current RECOMMENDED OPERATING CONDITIONS Military Unit –0.5 to + 7.0 V –55 to + 125 °C –65 to + 135 °C –65 to + 135 °C 50 mA Symbol VCCM VCCC GND VIH VIH VIL Parameter Min. Typ. Max. Unit Military Supply Voltage Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input High Voltage Military Input Low Voltage Commercial & Military 4.5 4.5 5.0 5.0 5.5 5.5 V V 0 2.0 0 — 0 — V V 2.2 — — V — — 0.8 V 2680 tbl 03 2680 tbl 02 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C, f = 1.0 MHz) Symbol CIN (2) Parameter Input Capacitance COUT(1, 2) Output Capacitance Conditions Max. Unit VIN = 0V 10 pF VOUT = 0V 10 NOTES: 1. With output deselected. (OE = HIGH) 2. Characterized values, not currently tested. pF 2680 tbl 04 DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) Symbol Parameter IDT72420 IDT72200 IDT72210 Commercial tCLK = 12, 15, 20, 25, 35, 50 ns Min. Typ. Max. IDT72420 IDT72200 IDT72210 Military tCLK = 20, 25,35, 50 ns Min. Typ. Max. Units ILI(1) Input Leakage Current (any input) –1 — 1 –10 — 10 µA ILO(2) Output Leakage Current –10 — 10 –10 — 10 µA VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V VOL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V ICC1(3) Active Power Supply Current — — 80 — — 100 mA 2680 tbl 05 Symbol Parameter IDT72220 IDT72230 IDT72240 Commercial tCLK = 15, 20, 25, 35, 50 ns Min. Typ. Max. IDT72220 IDT72230 IDT72240 Military tCLK = 25, 35, 50 ns Min. Typ. Max. Units ILI(1) Input Leakage Current (any input) –1 — 1 –10 — 10 µA ILO(2) Output Leakage Current –10 — 10 –10 — 10 µA VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V VOL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V ICC1(4) Active Power Supply Current — — 80 — — 100 mA NOTES: 1. Measurements with 0.4 ≤ VIN ≤ VCC. 2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 3 & 4. Measurements are made with outputs unloaded. Tested at fCLK = 20 MHZ. (3) Typical ICC1 = 30 + (fCLK*0.5/MHz) + (fCLK*CL*0.02/MHz-pF) mA (4) Typical ICC1 = 32 + (fCLK*0.6/MHz) + (fCLK*CL*0.02/MHz-pF) mA fCLK = 1 / tCLK CL = external capacitive load (30 pF typical) 5.12 2680 tbl 06 3 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) Commercial Comm. & Mil. 72200L12 72200L15 72200L20 72200L25 72210L12 72210L15 72210L20 72210L25 72420L12 72420L15 72420L20 72420L25 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. fS Clock Cycle Frequency tA Data Access Time 2 8 2 tCLK Clock Cycle Time 12 — 15 tCLKH Clock High Time 5 — tCLKL Clock Low Time 5 — tDS Data Set-up Time tDH Data Hold Time tENS Enable Set-up Time tENH Enable Hold Time Width(1) Comm. 72200L35 72210L35 72420L35 — 83.3 — 66.7 — 50 10 2 — 20 6 — 6 — — 28.6 Comm/Mil 72200L50 72210L50 72420L50 Min.Max. Unit — 40 — 20 MHz 12 3 15 3 20 3 25 ns — 25 — 35 — 50 — ns 8 — 10 — 14 — 20 — ns 8 — 10 — 14 — 20 — ns 3 — 4 — 5 — 6 — 8 — 10 — ns 0.5 — 1 — 1 — 1 — 2 — 2 — ns 3 — 4 — 5 — 6 — 8 — 10 — ns 0.5 — 1 — 1 — 1 — 2 — 2 — ns tRS Reset Pulse 12 — 15 — 20 — 25 — 35 — 50 — ns tRSS Reset Set-up Time 12 — 15 — 20 — 25 — 35 — 50 — ns tRSR Reset Recovery Time 12 — 15 — 20 — 25 — 35 — 50 — ns tRSF Reset to Flag and Output Time — 12 — 15 — 20 — 25 — 35 — 50 ns tOLZ Output Enable to Output in Low-Z(2) 0 — 0 — 0 — 0 — 0 — 0 — ns tOE Output Enable to Output Valid 3 7 3 8 3 10 3 13 3 15 3 28 ns tOHZ Output Enable to Output in High-Z(2) 3 7 3 8 3 10 3 13 3 15 3 28 ns tWFF Write Clock to Full Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tREF Read Clock to Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tAF Write Clock to Almost-Full Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tAE Read Clock to Almost-Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tSKEW1 Skew time between Read Clock & Write Clock for Empty Flag & Full Flag 5 — 6 — 8 — 10 — 12 — 15 — ns tSKEW2 Skew time between Read Clock & Write Clock for Almost-Empty Flag & Almost-Full Flag 22 — 28 — 35 — 40 — 42 — 45 — ns NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested. 2680 tbl 07 5.12 4 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) Symbol Parameter Commercial 72220L12 72220L15 72230L12 72230L15 72240L12 72240L15 Min. Max. Min. Max. Commercial & Military 72220L20 72220L25 72230L20 72230L25 72240L20 72240L25 Min. Max. Min. Max. Comm. 72220L35 72230L35 72240L35 Min. Max. Comm./Mil. 72220L50 72230L50 72240L50 Min. Max. Unit fS Clock Cycle Frequency — 83.3 — 66.7 — 50 — 40 — 28.6 — 20 MHz tA Data Access Time 2 8 2 10 2 12 3 15 3 20 3 25 ns tCLK Clock Cycle Time 12 — 15 — 20 — 25 — 35 — 50 — ns tCLKH Clock High Time 5 — 6 — 8 — 10 — 14 — 20 — ns tCLKL Clock Low Time 5 — 6 — 8 — 10 — 14 — 20 — ns tDS Data Set-up Time 3 — 4 — 5 — 6 — 8 — 10 — ns tDH Data Hold Time .5 — 1 — 1 — 1 — 2 — 2 — ns tENS Enable Set-up Time 3 — 4 — 5 — 6 — 8 — 10 — ns ns tENH Enable Hold Time .5 — 1 — 1 — 1 — 2 — 2 — tRS Reset Pulse Width(1) 12 — 15 — 20 — 25 — 35 — 50 — ns tRSS Reset Set-up Time 12 — 15 — 20 — 25 — 35 — 50 — ns tRSR Reset Recovery Time 12 — 15 — 20 — 25 — 35 — 50 — ns tRSF Reset to Flag and Output Time — 12 — 15 — 20 — 25 — 35 — 50 ns tOLZ Output Enable to Output in Low-Z(2) 0 — 0 — 0 — 0 — 0 — 0 — ns tOE Output Enable to Output Valid 3 7 3 8 3 10 3 13 3 15 3 23 ns tOHZ Output Enable to Output in High-Z(2) 3 7 3 8 3 10 3 13 3 15 3 23 ns tWFF Write Clock to Full Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tREF Read Clock to Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tAF Write Clock to Almost-Full Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tAE Read Clock to Almost-Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tSKEW1 Skew time between Read Clock & Write Clock for Empty Flag & Full Flag tSKEW2 Skew time between Read Clock & Write Clock for Almost-Empty Flag & Almost-Full Flag 5 — 6 — 8 — 10 — 12 — 15 — ns 22 — 28 — 35 — 40 — 42 — 45 — ns NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested. 2680 tbl 08 5V 1.1KΩ AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load D.U.T. GND to 3.0V 680Ω 30pF* See Figure 1 2680 tbl 09 2680 drw 03 or equivalent circuit Figure 1. Output Load *Includes jig and scope capacitances. 5.12 5 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES SIGNAL DESCRIPTIONS INPUTS: Data In (D0–D7) — Data inputs for 8-bit wide data. CONTROLS: Reset (RS) — Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. The Full Flag (FF) and Almost Full Flag (AF) will be reset to HIGH after tRSF. The Empty Flag (EF) and Almost Empty Flag (AE) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros. Write Clock (WCLK) — A write cycle is initiated on the LOWto-HIGH transition of the write clock (WCLK). Data set-up and hold times must be met in respect to the LOW-to-HIGH transition of the write clock (WCLK). The Full Flag (FF) and Almost Full Flag (AF) are synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK). The write and read clocks can be asynchronous or coincident. Write Enable (WEN) — When Write Enable (WEN) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. When Write Enable (WEN) is HIGH, the input register holds the previous data and no new data is allowed to be loaded into the register. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the Full Flag (FF) will go HIGH after tWFF, allowing a valid write to begin. Write Enable (WEN) is ignored when the FIFO is full. Read Clock (RCLK) — Data can be read on the outputs on the LOW-to-HIGH transition of the read clock (RCLK). The Empty Flag (EF) and Almost-Empty Flag (AE) are synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). The write and read clocks can be asynchronous or coincident. Read Enable (REN) — When Read Enable (REN) is LOW, data is read from the RAM array to the output register on the LOW-to-HIGH transition of the read clock (RCLK). When Read Enable (REN) is HIGH, the output register holds the previous data and no new data is allowed to be loaded into the register. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid read can begin. Read Enable (REN) is ignored when the FIFO is empty. Output Enable (OE) — When Output Enable (OE) is enabled (LOW), the parallel output buffers receive data from the output register. When Output Enable (OE) is disabled (HIGH), the Q output data bus is in a high-impedance state. OUTPUTS: Full Flag (FF) — The Full Flag (FF) will go LOW, inhibiting further write operation, when the device is full. If no reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72420, 256 writes for the IDT72200, 512 writes for the IDT72210, 1024 writes for the IDT72220, 2048 writes for the IDT72230, and 4096 writes for the IDT72240. The Full Flag (FF) is synchronized with respect to the LOWto-HIGH transition of the write clock (WCLK). Empty Flag (EF) — The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). Almost Full Flag (AF) — The Almost Full Flag (AF) will go LOW when the FIFO reaches the Almost-Full condition. If no reads are performed after Reset (RS), the Almost Full Flag (AF) will go LOW after 57 writes for the IDT72420, 249 writes for the IDT72200, 505 writes for the IDT72210, 1017 writes for the IDT72220, 2041 writes for the IDT72230 and 4089 writes for the IDT72240. The Almost Full Flag (AF) is synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK). Almost Empty Flag (AE) — The Almost Empty Flag (AE) will go LOW when the FIFO reaches the Almost-Empty condition. If no reads are performed after Reset (RS), the Almost Empty Flag (AE) will go HIGH after 8 writes for the IDT72420, IDT72200, IDT72210, IDT72220, IDT72230 and IDT72240. The Almost Empty Flag (AE) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). Data Outputs (Q0–Q7) — Data outputs for a 8-bit wide data. 5.12 6 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES TABLE 1: STATUS FLAGS Number of Words in FIFO IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240 FF AF AE EF 0 0 0 0 0 0 H H L L 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 H H L H 8 to 56 8 to 248 8 to 504 8 to 1016 8 to 2040 8 to 4088 H H H H 57 to 63 249 to 255 505 to 511 64 256 512 1017 to 1023 2041 to 2047 4089 to 4095 1024 2048 4096 H L H H L L H H 2680 tbl 10 tRS RS tRSS tRSR tRSS tRSR REN WEN tRSF EF, AE tRSF FF, AF tRSF OE = 1 Q0 - Q7 (1) OE = 0 2680 drw 04 NOTE: 1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1. 2. The clocks (RCLK, WCLK) can be free-running during reset. Figure 2. Reset Timing 5.12 7 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES tCLK tCLKH tCLKL WCLK tDS tDH D0 - D7 DATAIN VALID tENS tENH WEN NO OPERATION tWFF tWFF FF tSKEW1 (1) RCLK REN 2680 drw 05 NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the curent clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Figure 3. Write Cycle Timing 5.12 8 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES tCLK tCLKH tCLKL RCLK tENS tENH REN NO OPERATION tREF tREF EF tA Q0 - Q7 VALID DATA tOLZ tOHZ tOE OE tSKEW1(1) WCLK WEN 2680 drw 06 NOTE: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the curent clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 4. Read Cycle Timing 5.12 9 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES WCLK tDS D0 - D7 D0 (first valid write) D1 D2 D3 tENS WEN tFRL tSKEW1 (1) RCLK EF tREF REN tA tA Q0 - Q7 D0 D1 tOLZ tOE OE NOTE: 1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timing apply only at the Empty Boundry (EF = LOW). 2680 drw 07 Figure 5. First Data Word Latency Timing 5.12 10 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES NO WRITE NO WRITE WCLK tDS tDS tSKEW1 tSKEW1 D0 - D7 DATA WRITE DATA WRITE tWFF tWFF tWFF FF WEN RCLK tENH tENH tENS tENS REN OE Q0 - Q7 LOW tA tA DATA IN OUTPUT REGISTER DATA READ NEXT DATA READ 2680 drw 08 Figure 6. Full Flag Timing 5.12 11 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES WCLK tDS D0 - D7 tDS DATA WRITE 1 DATA WRITE 2 tENH tENS tENS tENH WEN tFRL (1) tFRL (1) tSKEW1 tSKEW1 RCLK tREF tREF tREF EF REN OE LOW tA Q0 - Q7 DATA READ DATA IN OUTPUT REGISTER NOTE: 1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timing apply only at the Empty Boundry (EF = LOW). 2680 drw 09 Figure 7. Empty Flag Timing 5.12 12 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES tCLKL tCLKH (2) WCLK tENS tENH WEN tAF AF Full - 7 words in FIFO Full - 8 words in FIFO tSKEW2 (1) tAF RCLK tENS tENH REN 2680 drw 10 NOTES: 1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for AF to change during the curent clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then AF may not change state until the next WCLK edge. 2. If a write is performed on this rising edge of the write clock, there will be Full - 6 words in the FIFO when AF goes LOW. Figure 8. Almost Full Flag Timing 5.12 13 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES tCLKL tCLKH WCLK tENS tENH WEN Empty+8 AE Empty+7 (1) tSKEW2 tAE tAE (2) RCLK tENS tENH REN 2680 drw 11 NOTES: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for AE to change during the curent clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then AE may not change state until the next RCLK edge. 2. If a read is performed on this rising edge of the read clock, there will be Empty - 6 words in the FIFO when AE goes LOW. Figure 9. Almost Empty Flag Timing 5.12 14 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION - A single IDT72420/ 72200/72210/72220/72230/72240 may be used when the application requirements are for 64/256/512/1024/2048/4096 words or less. See Figure 10. RESET (RS) WRITE CLOCK (WCLK) READ CLOCK (RCLK) WRITE ENABLE (WEN) READ ENABLE (REN) OUTPUT ENABLE (OE) IDT 72420/72200/ 72210/ 72220/ 72230/ 72240 DATA IN (D0-D7) FULL FLAG (FF) DATA OUT (Q0- Q7) EMPTY FLAG (EF) ALMOST FULL (AF) ALMOST EMPTY(AE) 2680 drw 12 Figure 10. Block Diagram of Single 64 x 8/256 x 8/512 x 8/1024 x 8/2048 x 8/4096 x 8 Synchronous FIFO WIDTH EXPANSION CONFIGURATION - Word width may be increased simply by connecting the corresponding input control signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF) The partial status flags (AE and AF) can be detected from any one device. Figure 11 demonstrates a 16-bit word width by using two IDT72420/72200/72210/72220/72230/72240s. Any word width can be attained by adding additional IDT72420/72200/ 72210/72220/72230/72240s. RESET (RS) DATA IN (D) 16 RESET (RS) 8 8 READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN) WRITE ENABLE (WEN) ALMOST FULL (AF) FULL FLAG (FF) #1 FULL FLAG (FF) #2 OUTPUT ENABLE (OE) IDT 72420/ 72200/ 72210/ 72220/ 72230/ 72240 IDT 72420/ 72200/ 72210/ 72220/ 72230/ 72240 8 ALMOST EMPTY (AE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF) #2 8 DATA OUT (Q) 16 2680 drw 13 Figure 11. Block Diagram of 64 x 16/256 x 16/512 x 16/1024 x 16/2048 x 16/4096 x 16 Synchronous FIFO Used in a Width Expansion Configuration 5.12 15 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES DEPTH EXPANSION - The IDT72420/72200/72210/72220/ 72230/72240 can be adapted to applications when the requirements are for greater than 64/256/512/1024/2048/4096 words. Depth expansion is possible by using expansion logic to direct the flow of data. A typical application would have the expansion logic alternate data accesses from one device to the next in a sequential manner. Please see the Application Note “DEPTH EXPANSION IDT'S SYNCHRONOUS FIFOs USING RING COUNTER APPROACH” for details of this configuration. ORDERING INFORMATION IDT XXXXX Device Type XX XX X Power Speed Package X Process / Temperature Range BLANK Commercial (0°C to +70°C) B Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B TP TC Plastic THINDIP Sidebraze THINDIP 12 15 20 25 35 50 Commercial Only Commercial Only Commercial and Military Commercial and Military Commercial Only Commercial and Military L Low Power 72420 72200 72210 72220 72230 72240 64 x 8 Synchronous FIFO 256 x 8 Synchronous FIFO 512 x 8 Synchronous FIFO 1024 x 8 Synchronous FIFO 2048 x 8 Synchronous FIFO 4098 x 8 Synchronous FIFO 5.12 Clock Cycle Time (tCLK) Speed in Nanoseconds 2680 drw 14 16