MOTOROLA MTD9N10E Tmos power fet 9.0 amperes 100 volts rds(on) = 0.25 ohm Datasheet

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by MTD9N10E/D
SEMICONDUCTOR TECHNICAL DATA
 
! Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
9.0 AMPERES
100 VOLTS
RDS(on) = 0.25 OHM
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
• Replaces MTD6N10

D
G
CASE 369A–13, Style 2
DPAK
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–Source Voltage
VDSS
100
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
100
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 30
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
9.0
5.0
27
Adc
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size
PD
40
0.32
1.75
Watts
W/°C
Watts
Rating
Apk
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 9.0 Apk, L = 1.0 mH, RG = 25 Ω)
EAS
40
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size
RθJC
RθJA
RθJA
3.13
100
71.4
°C/W
TL
260
°C
Operating and Storage Temperature Range
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
TMOS
 Motorola
Motorola, Inc.
1995
Power MOSFET Transistor Device Data
1
MTD9N10E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
100
—
—
103
—
—
Vdc
mV/°C
—
—
—
—
10
100
—
—
100
nAdc
2.0
—
—
6.0
4.0
—
Vdc
mV/°C
—
0.17
0.25
Ohm
—
—
—
—
2.43
2.40
gFS
4.0
—
—
mhos
Ciss
—
610
1200
pF
Coss
—
176
400
Crss
—
14
30
td(on)
—
8.8
20
tr
—
28
60
td(off)
—
16
30
tf
—
4.8
10
QT
—
14
21
Q1
—
5.2
—
Q2
—
3.2
—
Q3
—
6.6
—
—
—
0.98
0.9
1.8
—
trr
—
91
—
ta
—
71
—
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
µAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 4.5 Adc)
RDS(on)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 9.0 Adc)
(ID = 4.5 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 8.0 Vdc, ID = 4.5 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
(VDD = 50 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDS = 80 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 9.0 Adc, VGS = 0 Vdc)
(IS = 9.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(See Figure 14)
(IS = 9.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
VSD
Vdc
ns
tb
—
20
—
QRR
—
0.4
—
µC
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
—
4.5
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
—
7.5
—
nH
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTD9N10E
TYPICAL ELECTRICAL CHARACTERISTICS
18
18
14
8V
7V
12
10
8
6V
6
4
5V
2
0
1
2
3
4
5
6
7
8
9
25°C
12
100°C
10
8
6
4
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
VGS = 10 V
0.35
TJ = 100°C
0.30
0.25
25°C
0.20
0.15
– 55°C
0.10
0
14
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0
10
0.45
0.40
2
4
6
8
12
10
ID, DRAIN CURRENT (AMPS)
14
16
18
0.25
TJ = 25°C
0.23
0.21
0.19
VGS = 10 V
0.17
15 V
0.15
0
2
4
8
10
6
12
ID, DRAIN CURRENT (AMPS)
14
18
16
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1.9
100
VGS = 0 V
VGS = 10 V
ID = 4.5 A
1.5
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
Figure 3. On–Resistance versus Drain Current
and Temperature
1.7
TJ = – 55°C
2
4V
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0
VDS ≥ 10 V
16
I D , DRAIN CURRENT (AMPS)
16
I D , DRAIN CURRENT (AMPS)
TJ = 25°C
VGS = 10 V
1.3
1.1
0.9
TJ = 125°C
10
100°C
1.0
25°C
0.7
0.5
– 50
– 25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. On–Resistance Variation with
Temperature
Motorola TMOS Power MOSFET Transistor Device Data
0.1
30
40
60
50
70
80
90
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
100
Figure 6. Drain–To–Source Leakage
Current versus Voltage
3
MTD9N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data
is used. In most cases, a satisfactory estimate of average
input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times
may be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1200
C, CAPACITANCE (pF)
1000
VDS = 0
VGS = 0
TJ = 25°C
Ciss
800
Ciss
600
Crss
400
Coss
200
Crss
0
10
5
0
VGS
5
10
15
20
25
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
120
QT
100
10
VGS
Q2
8
80
Q1
6
60
4
ID = 9 A
TJ = 25°C
40
2
20
Q3
VDS
0
14
0
0
2
12
4
6
8
10
QG, TOTAL GATE CHARGE (nC)
100
VDD = 50 V
ID = 9 A
VGS = 10 V
TJ = 25°C
t, TIME (ns)
12
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTD9N10E
tr
td(off)
10
td(on)
tf
1
1
10
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
9
VGS = 0 V
TJ = 25°C
I S , SOURCE CURRENT (AMPS)
8
7
6
5
4
3
2
1
0
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1.0
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
Motorola TMOS Power MOSFET Transistor Device Data
able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
5
MTD9N10E
SAFE OPERATING AREA
10
40
VGS = 20 V
SINGLE
PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
10 µs
100 µs
1 ms
1.0
10 ms
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
10
1.0
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
ID = 9 A
32
24
16
8
0
25
100
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
150
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
D = 0.5
0.2
0.1
P(pk)
0.1
0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
t, TIME (s)
1.0E–01
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
MTD9N10E
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
0.165
4.191
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.118
3.0
0.100
2.54
0.063
1.6
0.190
4.826
0.243
6.172
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
PD =
TJ(max) – TA
RθJA
PD = 150°C – 25°C = 1.75 Watts
71.4°C/W
The 71.4°C/W for the DPAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.75 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
Motorola TMOS Power MOSFET Transistor Device Data
100
Board Material = 0.0625″
G–10/FR–4, 2 oz Copper
1.75 Watts
80
TA = 25°C
°
60
3.0 Watts
40
5.0 Watts
θ
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a DPAK
device, PD is calculated as follows.
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
RθJA versus drain pad area is shown in Figure 15.
R JA , Thermal Resistance, Junction
to Ambient ( C/W)
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RθJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:
20
0
2
4
6
A, Area (square inches)
8
10
Figure 15. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
7
MTD9N10E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC–59,
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
registration. This is not the case with the DPAK and D2PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 16 shows a typical stencil for the DPAK and D2PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
SOLDER PASTE
OPENINGS
STENCIL
Figure 16. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
8
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
* Due to shadowing and the inability to set the wave height to
incorporate other surface mount components, the D2PAK is
not recommended for wave soldering.
Motorola TMOS Power MOSFET Transistor Device Data
MTD9N10E
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. Taken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
17 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177 –189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
STEP 5
STEP 4
HEATING
HEATING
ZONES 3 & 6 ZONES 4 & 7
“SPIKE”
“SOAK”
170°C
STEP 6
VENT
STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER JOINT
160°C
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 17. Typical Solder Heating Profile
Motorola TMOS Power MOSFET Transistor Device Data
9
MTD9N10E
PACKAGE DIMENSIONS
–T–
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
Z
A
S
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
STYLE 2:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.180 BSC
0.034
0.040
0.018
0.023
0.102
0.114
0.090 BSC
0.175
0.215
0.020
0.050
0.020
–––
0.030
0.050
0.138
–––
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.45
5.46
0.51
1.27
0.51
–––
0.77
1.27
3.51
–––
CASE 369A–13
ISSUE W
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10
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*MTD9N10E/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MTD9N10E/D