TI DAC2902 Dual, 12-bit, 125msps digital-to-analog converter Datasheet

DAC
DAC2902
290
2
www.ti.com
SBAS167C– JUNE 2001 – REVISED SEPTEMBER 2008
Dual, 12-Bit, 125MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
●
●
●
●
●
●
●
● COMMUNICATIONS:
Base Stations, WLL, WLAN
Baseband I/Q Modulation
125MSPS UPDATE RATE
SINGLE SUPPLY: +3.3V or +5V
HIGH SFDR: 70dB at fOUT = 20MHz
LOW GLITCH: 2pV-s
LOW POWER: 310mW
INTERNAL REFERENCE
POWER-DOWN MODE: 23mW
● MEDICAL/TEST INSTRUMENTATION
● ARBITRARY WAVEFORM GENERATORS (ARB)
● DIRECT DIGITAL SYNTHESIS (DDS)
DESCRIPTION
The DAC2902 is a monolithic, 12-bit, dual-channel,
high-speed Digital-to-Analog Converter (DAC), and is optimized to provide high dynamic performance while dissipating only 310mW.
The DAC2902 combines high dynamic performance with
a high throughput rate to create a cost-effective solution
for a wide variety of waveform-synthesis applications:
• Pin compatibility between family members provides 10bit (DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904)
resolution.
Operating with high update rates of up to 125MSPS, the
DAC2902 offers exceptional dynamic performance, and
enables the generation of very high output frequencies
suitable for Direct IF applications. The DAC2902 has
been optimized for communications applications in which
separate I and Q data are processed while maintaining
tight gain and offset matching.
• Pin compatible to the AD9765 dual DAC.
Each DAC has a high-impedance differential-current output, suitable for single-ended or differential analog output
configurations.
• All digital inputs are +3.3V and +5V logic compatible.
The DAC2902 has an internal reference circuit, and
allows use of an external reference.
• Gain matching is typically 0.5% of full-scale, and offset
matching is specified at 0.02% max.
• The DAC2902 utilizes an advanced CMOS process; the
segmented architecture minimizes output glitch energy,
and maximizes the dynamic performance.
• The DAC2902 is available in a TQFP-48 package, and
is specified over the extended industrial temperature
range of –40°C to +85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2001-2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
+VA to AGND ........................................................................ –0.3V to +6V
+VD to DGND ........................................................................ –0.3V to +6V
AGND to DGND ................................................................. –0.3V to +0.3V
+VA to +VD ............................................................................... –6V to +6V
CLK, PD, WRT to DGND ........................................... –0.3V to VD + 0.3V
D0-D11 to DGND ....................................................... –0.3V to VD + 0.3V
IOUT, IOUT to AGND ........................................................ –1V to VA + 0.3V
GSET to AGND .......................................................... –0.3V to VA + 0.3V
REFIN, FSA to AGND ................................................. –0.3V to VA + 0.3V
Junction Temperature .................................................................... +150°C
Case Temperature ......................................................................... +100°C
Storage Temperature .................................................................... +125°C
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
DAC2902Y/250
DAC2902Y/1K
Tape and Reel, 250
Tape and Reel, 1000
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
DAC2902Y
TQFP-48
PFB
–40°C to +85°C
DAC2902Y
"
"
"
"
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
PRODUCT
DAC2902
EVM ORDERING NUMBER
DAC2902-EVM
COMMENT
Fully populated evaluation board. See user manual for details.
ELECTRICAL CHARACTERISTICS
At TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise noted. Independent Gain mode.
DAC2902Y
PARAMETER
CONDITIONS
MIN
RESOLUTION
Output Update Rate (fCLOCK)
STATIC ACCURACY(1)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
DYNAMIC PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
fOUT = 1MHz, fCLOCK = 50MSPS
fOUT = 1MHz, fCLOCK = 26MSPS
fOUT = 2.18MHz, fCLOCK = 52MSPS
fOUT = 5.24MHz, fCLOCK = 52MSPS
fOUT = 10.4MHz, fCLOCK = 78MSPS
fOUT = 15.7MHz, fCLOCK = 78MSPS
fOUT = 5.04MHz, fCLOCK = 100MSPS
fOUT = 20.2MHz, fCLOCK = 100MSPS
fOUT = 20.1MHz, fCLOCK = 125MSPS
fOUT = 40.2MHz, fCLOCK = 125MSPS
Spurious-Free Dynamic Range within a Window
fOUT = 1.0MHz, fCLOCK = 50MSPS
fOUT = 5.02MHz, fCLOCK = 50MSPS
fOUT = 5.03MHz, fCLOCK = 78MSPS
fOUT = 5.04MHz, fCLOCK = 125MSPS
Total Harmonic Distortion (THD)
fOUT = 1MHz, fCLOCK = 50MSPS
fOUT = 5.02MHz, fCLOCK = 50MSPS
fOUT = 5.03MHz, fCLOCK = 78MSPS
fOUT = 5.04MHz, fCLOCK = 125MSPS
Multitone Power Ratio
fOUT = 2.0MHz to 2.99MHz, fCLOCK = 65MSPS
TYP
MAX
12
125
TA = +25°C
TMIN to TMAX
TA = +25°C
TMIN to TMAX
To Nyquist
0dBFS Output
–6dBFS Output
–12dBFS Output
2MHz Span
10MHz Span
10MHz Span
10MHz Span
Bits
MSPS
–2.0
–2.5
–2.0
–3.0
±1
72
82
77
72
81
81
81
77
71
80
70
72
64
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
80
90
88
88
88
dBc
dBc
dBc
dBc
±1
–79
–77
–76
–75
8 Tone with 110kHz Spacing
0dBFS Output
UNIT
80
+2.0
+2.5
+2.0
+3.0
–70
LSB
LSB
LSB
LSB
dBc
dBc
dBc
dBc
dBc
DAC2902
2
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SBAS167C
ELECTRICAL CHARACTERISTICS (continued)
At TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise noted. Independent Gain mode.
DAC2902Y
PARAMETER
DYNAMIC PERFORMANCE (Cont.)
Signal-to-Noise Ratio (SNR)
fOUT = 5.02MHz, fCLOCK = 50MHz
Signal-to-Noise and Distortion (SINAD)
fOUT = 5.02MHz, fCLOCK = 50MHz
Channel Isolation
fOUT = 1MHz, fCLOCK = 52MSPS
fOUT = 20MHz, fCLOCK = 125MSPS
Output Settling Time(2)
Output Rise Time(2)
Output Fall Time(2)
Glitch Impulse
DC ACCURACY
Full-Scale Output Range(3)(FSR)
Output Compliance Range
Gain Error—Full-Scale
Gain Error
Gain Matching
Gain Drift
Offset Error
Offset Drift
Power-Supply Rejection, +VA
Power-Supply Rejection, +VD
Output Noise
Output Resistance
Output Capacitance
CONDITIONS
POWER SUPPLY
Supply Voltages
+VA
+VD
Supply Current
IVA(5)
IVA(5)
IVD(5)
IVD(6)
Power Dissipation(5)
Power Dissipation(6)
Power Dissipation(5)
Power Dissipation
Thermal Resistance, TQFP-48
θJA
θJC
TEMPERATURE RANGE
Specified
Operating
TYP
MAX
UNIT
0dBFS Output
68
dBc
0dBFS Output
67
dBc
85
77
30
2
2
2
dBc
dBc
ns
ns
ns
pV-s
to 0.1%
10% to 90%
10% to 90%
All Bits HIGH, IOUT
With Internal Reference
With External Reference
With Internal Reference
With Internal Reference
With Internal Reference
With Internal Reference
+5V, ±10%
+3.3V, ±10%
IOUT = 20mA, RLOAD = 50Ω
IOUT = 2mA
2
–1.0
–5
–2.5
–2.0
±1
±1
0.5
±50
–0.02
+0.02
–0.2
–0.025
+0.2
+0.025
50
30
200
6
+1.18
+1.25
±50
100
0.3
+0.5
+VD = +5V
+VD = +5V
+VD = 3.3V
+VD = 3.3V
+VD = 3.3V
+VD = 3.3V
20
+1.25
+5
+2.5
+2.0
±0.2
IOUT, IOUT to Ground
REFERENCE/CONTROL AMP
Reference Voltage
Reference Voltage Drift
Reference Output Current
Reference Multiplying Bandwidth
Input Compliance Range
DIGITAL INPUTS
Logic Coding
Logic High Voltage, VIH
Logic Low Voltage, VIL
Logic High Voltage, VIH
Logic Low Voltage, VIL
Logic High Current, IIH(4)
Logic Low Current
Input Capacitance
MIN
3.5
2
+3.0
+3.0
VA = +5V, lOUT = 20mA
Power-Down Mode
VA = +5V, VD = 3.3V, lOUT = 20mA
VA = +5V, VD = 3.3V, lOUT = 20mA
VA = +5V, VD = 3.3V, lOUT = 2mA
Power-Down Mode
+1.31
+1.25
Straight Binary
5
0
3
0
±10
±10
5
–40
–40
V
ppmFSR/°C
nA
MHz
V
0.8
V
V
V
V
µA
µA
pF
+5
+3.3
+5.5
+5.5
V
V
58
1.7
4.2
17
310
348
130
23
65
3
7
19.5
350
390
mA
mA
mA
mA
mW
mW
mW
mW
1.2
38
°C/W
°C/W
60
13
Ambient
Ambient
mA
V
%FSR
%FSR
%FSR
ppmFSR/°C
%FSR
ppmFSR/°C
%FSR/V
%FSR/V
pA/√Hz
pA/√Hz
kΩ
pF
+85
+85
°C
°C
NOTES: (1) At output lOUT, while driving a virtual ground. (2) Measured single-ended into 50Ω load. (3) Nominal full-scale output current is 32 × IREF; see Application
section for details. (4) Typically 45µA for the PD pin, which has an internal pull-down resistor. (5) Measured at fCLOCK = 25MSPS and fOUT = 1MHz. (6) Measured
at fCLOCK = 100MSPS and fOUT = 40MHz.
DAC2902
SBAS167C
3
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PIN CONFIGURATION
+VA
IOUT1
IOUT1
FSA
REFIN
GSET
FSA2
IOUT2
IOUT2
AGND
PD
TQFP-48
NC
Top View
48
47
46
45
44
43
42
41
40
39
38
37
D11_1 (MSB)
1
36 NC
D10_1
2
35 NC
D9_1
3
34 D0_2
D8_1
4
33 D1_2
D7_1
5
32 D2_2
D6_1
6
D5_1
7
30 D4_2
D4_1
8
29 D5_2
D3_1
9
28 D6_2
D2_1 10
27 D7_2
D1_1 11
26 D8_2
D0_1 12
25 D9_2
31 D3_2
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
DGND
+VD
WRT1
CLK1
CLK2
WRT2
DGND
+VD
D11_2 (MSB)
D10_2
DAC2902
PIN DESCRIPTIONS
PIN
DESIGNATOR
1-12
13, 14
15
16
17
18
19
20
21
22
23-34
35, 36
37
38
39
40
41
42
43
D[11:0]_1
NC
DGND
+VD
WRT1
CLK1
CLK2
WRT2
DGND
+VD
D[11:0]_2
NC
PD
AGND
IOUT2
IOUT2
FSA2
GSET
REFIN
44
45
46
47
48
FSA1
IOUT1
IOUT1
+VA
NC
DESCRIPTION
Data Port DAC1, Data Bit 11 (MSB) to Bit 0 (LSB).
No Connection
Digital Ground
Digital Supply, +3.0V to +5.5V
DAC1 Input Latches Write Signal
Clock Input DAC1
Clock Input DAC2
DAC2 Input Latches Write Signal
Digital Ground
Digital Supply, +3.0V to +5.5V
Data Port DAC2, Data Bit 11 (MSB) to Bit 0 (LSB).
No Connection
Power-Down Function Control Input; H = DAC in power-down mode; L = DAC in normal operation (Internal pull-down for default “L”).
Analog Ground
Current Output DAC2. Full-scale with all bits of data port 2 HIGH.
Complementary Current Output DAC2. Full-scale with all bits of data port 2 LOW.
Full-Scale Adjust, DAC2. Connect External RSET Resistor.
Gain-Setting Mode (H = 1 Resistor, L = 2 Resistor)
Internal Reference Voltage output; External Reference Voltage input. Bypass with 0.1µF to AGND for internal reference
operation.
Full-Scale Adjust, DAC1. Connect External RSET Resistor
Complementary Current Output DAC1. Full-scale with all bits of data port 1 LOW.
Current Output DAC1. Full-scale with all bits of data port 1 HIGH.
Analog Supply, +3.0V to +5.5V
No Connection
DAC2902
4
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SBAS167C
TIMING DIAGRAM
tS
DATA IN
tH
D[11:0](n)
D[11:0](n + 1)
tLPW
WRT1
WRT2
tCPW
CLK1
CLK2
tCW
tSET
IOUT1
IOUT(n)
50%
IOUT(n +1)
IOUT2
tPD
SYMBOL
DESCRIPTION
MIN
tS
tH
tLPW, tCPW
tCW
Input Setup Time
Input Hold Time
Latch/Clock Pulsewidth
Delay Rising CLK Edge to
Rising WRT Edge
Propagation Delay
Settling Time (0.1%)
2
1.5
3.5
0
tPD
tSET
DIGITAL INPUTS AND TIMING
The data input ports of the DAC2902 accept a standard
positive coding with data bit D11 being the most significant
bit (MSB). The converter outputs support a clock rate of up
to 125MSPS. The best performance will typically be achieved
with a symmetrical duty cycle for write and clock; however,
the duty cycle may vary as long as the timing specifications
are met. Also, the setup and hold times may be chosen
within their specified limits.
All digital inputs of the DAC2902 are CMOS-compatible.
The logic thresholds depend on the applied digital supply
voltages, such that they are set to approximately half the
supply voltage: Vth = +VD/2 (±20% tolerance). The DAC2902
is designed to operate with a digital supply (+VD) of +3.0V
to +5.5V.
MAX
UNITS
tPW – 2
ns
ns
ns
ns
4
1
30
ns
ns
The two converter channels within the DAC2902 consist of
two independent, 12-bit, parallel data ports. Each DAC
channel is controlled by its own set of write (WRT1, WRT2)
and clock (CLK1, CLK2) inputs. Here, the WRT lines
control the channel input latches and the CLK lines control
the DAC latches. The data is first loaded into the input latch
by a rising edge of the WRT line. This data is presented to
the DAC latch on the following falling edge of the WRT
signal. On the next rising edge of the CLK line, the DAC is
updated with the new data and the analog output signal will
change accordingly. The double latch architecture of the
DAC2902 results in a defined sequence for the WRT and
CLK signals, expressed by parameter tCW. A correct timing
is observed when the rising edge of CLK occurs at the same
time, or before, the rising edge of the WRT signal. This
condition can simply be met by connecting the WRT and
CLK lines together. Note that all specifications were measured with the WRT and CLK lines connected together.
DAC2902
SBAS167C
TYP
5
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TYPICAL CHARACTERISTICS
TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double-terminated load, and SFDR up to Nyquist, unless otherwise noted.
TYPICAL DNL
TYPICAL INL
1.4
1.5
1.2
1
1
0.6
0.4
INL (LSBs)
DNL (LSBs)
0.8
0.2
0
0.5
0
–0.2
–0.5
–0.4
–0.6
–1
–0.8
–1
–1.5
0
500
1k
1k5
2k
Code
2k5
3k
3k5
4k
0
500
1k
SFDR vs fOUT AT 26MSPS
2k5
3k
3k5
4k
90
85
85
0dBFS
80
SFDR (dBc)
SFDR (dBc)
2k
Code
SFDR vs fOUT AT 52MSPS
90
75
–6dBFS
70
0dBFS
80
75
–6dBFS
70
65
65
60
60
0
2
4
6
fOUT (MHz)
8
10
12
0
5
SFDR vs fOUT AT 78MSPS
10
15
fOUT (MHz)
85
80
80
25
0dBFS
75
75
20
SFDR vs fOUT AT 100MSPS
85
0dBFS
SFDR (dBc)
SFDR (dBc)
1k5
70
–6dBFS
65
70
65
60
60
–6dBFS
55
55
50
0
5
10
15
20
fOUT (MHz)
25
30
0
35
5
10
15
20
25
fOUT (MHz)
30
35
40
45
DAC2902
6
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SBAS167C
TYPICAL CHARACTERISTICS (continued)
TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double-terminated load, and SFDR up to Nyquist, unless otherwise noted.
SFDR vs fOUT AT 125MHz
SFDR vs IOUTFS AND fOUT AT 78MSPS, 0dBFS
85
80
76
–6dBFS
75
74
SFDR (dBc)
SFDR (dBc)
IOUTFS = 20mA
78
80
70
0dBFS
65
IOUTFS = 5mA
IOUTFS = 10mA
72
70
IOUTFS = 2mA
68
66
60
64
55
62
50
60
0
10
20
30
fOUT (MHz)
40
50
0
60
5
SFDR AT 125MSPS vs TEMPERATURE
20
25
SINAD vs fCLK AND IOUT AT 5MHz
70
90
85
2MHz
80
20mA
67.5
10MHz
SINAD (dBc)
SFDR (dBc)
10
15
fOUT (MHz)
75
70
20MHz
65
40MHz
60
10mA
65
5mA
62.5
55
50
–40
60
–20
0
25
50
Temperature (°C)
70
85
20
40
GAIN AND OFFSET DRIFT
60
80
100
fCLK (MSPS)
120
140
IVD vs RATIO AT +VD = +3.3V
0.8
0.004
0.6
0.003
25
0.002
0.2
0.001
0
0
–0.2
–0.001
Gain Error
–0.4
–0.002
100MSPS
20
IVD (mA)
Offset Error
0.4
Offset Error (% FS)
Gain Error (% FS)
125MSPS
78MSPS
15
52MSPS
10
26MSPS
5
–0.6
–0.8
–40
–0.003
–0.004
–20
0
20
40
Temperature (°C)
60
80 85
DAC2902
SBAS167C
0
0.00
0.05
0.10
0.15 0.20 0.25 0.30 0.35 0.40
Ratio (FOUT/FCLK)
0.45
7
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TYPICAL CHARACTERISTICS (continued)
TA = +25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50Ω double-terminated load, and SFDR up to Nyquist, unless otherwise noted.
IVA vs IOUTFS
SINGLE-TONE SFDR
10
55
0
50
–10
Magnitude (dBm)
60
IVA (mA)
45
40
35
30
25
fOUT = 5.23MHz
Amplitude = 0dBFS
–20
–30
–40
–50
–60
20
–70
15
–80
10
fCLOCK = 52MSPS
–90
0
5
10
15
IOUTFS (mA)
20
25
0
4
8
12
Frequency (MHz)
SINGLE-TONE SFDR
20
DUAL-TONE SFDR
10
10
fCLOCK = 100MSPS
0
fCLOCK = 78MSPS
0
fOUT = 20.2MHz
–10
–20
–30
–40
–50
–60
fOUT1 = 9.44MHz
–10
Amplitude = 0dBFS
Magnitude (dBm)
Magnitude (dBm)
16
–20
Amplitude = 0dBFS
–30
–40
–50
–60
–70
–70
–80
–80
–90
fOUT2 = 10.44MHz
–90
0
10
20
30
Frequency (MHz)
40
50
0
7.8
15.6
23.4
Frequency (MHz)
31.2
39.0
FOUR-TONE SFDR
10
fCLOCK = 50MSPS
0
fOUT1 = 6.25MHz
Magnitude (dBm)
–10
fOUT2 = 6.75MHz
–20
fOUT3 = 7.25MHz
–30
fOUT4 = 7.75MHz
–40
Amplitude = 0dBFS
–50
–60
–70
–80
–90
0
5
15
10
Frequency (MHz)
20
25
DAC2902
8
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SBAS167C
APPLICATION INFORMATION
DAC TRANSFER FUNCTION
Each of the DACs in the DAC2902 has a complementary
current output, IOUT1 and IOUT2. The full-scale output current, IOUTFS, is the summation of the two complementary
output currents:
THEORY OF OPERATION
The architecture of the DAC2902 uses the current steering
technique to enable fast switching and a high update rate.
The core element within the monolithic DAC is an array of
segmented current sources that are designed to deliver a fullscale output current of up to 20mA, as shown in Figure 1. An
internal decoder addresses the differential current switches
each time the DAC is updated and a corresponding output
current is formed by steering all currents to either output
summing node, IOUT or IOUT. The complementary outputs
deliver a differential output signal, which improves the
dynamic performance through reduction of even-order harmonics, common-mode signals (noise), and double the peakto-peak output signal swing by a factor of two, compared to
single-ended operation.
IOUTFS = IOUT + IOUT
The individual output currents depend on the DAC code and
can be expressed as:
IOUT = IOUTFS × (Code/4096)
(2)
IOUT = IOUTFS × (4095 - Code)
(3)
where Code is the decimal representation of the DAC data
input word. Additionally, IOUTFS is a function of the reference current IREF, which is determined by the reference
voltage and the external setting resistor, RSET.
The segmented architecture results in a significant reduction
of the glitch energy, improves the dynamic performance
(SFDR), and DNL. The current outputs maintain a very high
output impedance of greater than 200kΩ.
IOUTFS = 32 × IREF = 32 × VREF /RSET
The full-scale output current is determined by the ratio of the
internal reference voltage (approx. +1.25V) and an external
resistor, RSET. The resulting IREF is internally multiplied by a
factor of 32 to produce an effective DAC output current that
can range from 2mA to 20mA, depending on the value of RSET.
+VD
+VD
Input
Latch 1
DAC
Latch 1
VOUT = IOUT × RLOAD
(5)
VOUT = IOUT × RLOAD
(6)
+VA
DAC1
Segmented Switches
Current Sources
lOUT1
lOUT1
REFIN
WRT1
FSA1
CLK1
DAC2902
CLK2
Reference
Control Amplifier
FSA2
GSET
PD
WRT2
Data Input
Port 2
D[11:0]_2
(4)
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
The DAC2902 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and the
decoder logic, while the analog section consists of the
current source array with its associated switches, and the
reference circuitry.
Data Input
Port 1
D[11:0]_1
(1)
Input
Latch 2
DGND
DAC
Latch 2
DGND
DAC2
Segmented Switches
Current Sources
lOUT2
lOUT2
AGND
FIGURE 1. Block Diagram of the DAC2902.
DAC2902
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The value of the load resistance is limited by the output
compliance specification of the DAC2902. To maintain
specified linearity performance, the voltage for IOUT and
IOUT should not exceed the maximum allowable compliance
range.
The two single-ended output voltages can be combined to
find the total differential output swing:
VOUTDIFF = VOUT – VOUT
(2 × Code – 4095)
=
× IOUTFS × RLOAD (7)
4096
ANALOG OUTPUTS
The DAC2902 provides two complementary current outputs, IOUT and IOUT. The simplified circuit of the analog
output stage representing the differential topology is shown
in Figure 2. The output impedance of IOUT and IOUT results
from the parallel combination of the differential switches,
along with the current sources and associated parasitic
capacitances.
+VA
DAC2902
be adapted to the output of the DAC2902 by selecting a
suitable transformer while maintaining optimum voltage
levels at IOUT and IOUT. Furthermore, using the differential
output configuration in combination with a transformer will
be instrumental for achieving excellent distortion performance. Common-mode errors, such as even-order harmonics or noise, can be substantially reduced. This is particularly
the case with high output frequencies.
For those applications requiring the optimum distortion and
noise performance, it is recommended to select a full-scale
output of 20mA. A lower full-scale range down to 2mA may
be considered for applications that require a low power
consumption, but can tolerate a slightly reduced performance level.
OUTPUT CONFIGURATIONS
The current outputs of the DAC2902 allow for a variety of
configurations, some of which are illustrated in Table I. As
mentioned previously, utilizing the converter’s differential
outputs will yield the best dynamic performance. Such a
differential output circuit may consist of an RF transformer
or a differential amplifier configuration. The transformer
configuration is ideal for most applications with ac coupling,
while op amps will be suitable for a DC-coupled configuration.
INPUT CODE (D11 - D0)
IOUT
IOUT
1111 1111 1111
20mA
0mA
1000 0000 0000
10mA
10mA
0000 0000 0000
0mA
20mA
TABLE I. Input Coding Versus Analog Output Current.
IOUT
IOUT
RL
RL
The single-ended configuration may be considered for applications requiring a unipolar output voltage. Connecting a
resistor from either one of the outputs to ground will convert
the output current into a ground-referenced voltage signal.
To improve on the DC linearity by maintaining a virtual
ground, an I-to-V or op-amp configuration may be considered.
FIGURE 2. Equivalent Analog Output.
The signal voltage swing that may develop at the two
outputs, IOUT and IOUT, is limited by a negative and positive
compliance. The negative limit of –1V is given by the
breakdown voltage of the CMOS process, and exceeding it
will compromise the reliability of the DAC2902, or even
cause permanent damage. With the full-scale output set to
20mA, the positive compliance equals 1.25V, operating with
an analog supply of +VA = 5V. Note that the compliance
range decreases to about 1V for a selected output current of
IOUTFS = 2mA. Care should be taken that the configuration
of the DAC2902 does not exceed the compliance range to
avoid degradation of the distortion performance and integral
linearity.
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5VPP. This is the case for a 50Ω doubly-terminated load
and a 20mA full-scale output current. A variety of loads can
DIFFERENTIAL WITH TRANSFORMER
Using an RF transformer provides a convenient way of converting the differential output signal into a single-ended signal
while achieving excellent dynamic performance (see Figure 3).
The appropriate transformer should be carefully selected based
on the output frequency spectrum and impedance requirements.
The differential transformer configuration has the benefit of
significantly reducing common-mode signals, thus improving
the dynamic performance over a wide range of frequencies.
Furthermore, by selecting a suitable impedance ratio (winding
ratio), the transformer can be used to provide optimum impedance matching while controlling the compliance voltage for the
converter outputs. The model shown, ADTT1-1 (by MiniCircuits), has a 1:1 ratio and may be used to interface the
DAC2902 to a 50Ω load. This results in a 25Ω load for each of
the outputs, IOUT and IOUT. The output signals are ac coupled
and inherently isolated because of its magnetic coupling.
DAC2902
10
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SBAS167C
As shown in Figure 3, the transformer center tap is connected to ground. This forces the voltage swing on IOUT and
IOUT to be centered at 0V. In this case the two resistors, RL,
may be replaced with one, RDIFF, or omitted altogether. This
approach should only be used if all components are close to
each other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can be
realized, but the output compliance range should be observed. Alternatively, if the center tap is not connected, the
signal swing will be centered at RL × IOUTFS/2. However, in
this case, the two resistors (RL) must be used to enable the
necessary DC-current flow for both outputs.
ADTT1-1
(Mini-Circuits)
1:1
IOUT
DAC2902
RL
50Ω
RDIFF
100Ω
RS
50Ω
IOUT
RL
50Ω
FIGURE 3. Differential Output Configuration Using an RF
Transformer.
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a DC-coupled output, a difference
amplifier may be considered, as shown in Figure 4. Four
external resistors are needed to configure the voltage-feedback op amp OPA680 as a difference amplifier performing
the differential to single-ended conversion. Under the shown
configuration, the DAC2902 generates a differential output
signal of 0.5VPP at the load resistors, RL. The resistor values
shown were selected to result in a symmetric 25Ω loading
for each of the current outputs since the input impedance of
the difference amplifier is in parallel to resistors RL, and
should be considered.
The OPA680 is configured for a gain of two. Therefore,
operating the DAC2902 with a 20mA full-scale output will
produce a voltage output of ±1V. This requires the amplifier
to operate from a dual power supply (±5V). The tolerance of
the resistors typically sets the limit for the achievable common-mode rejection. An improvement can be obtained by
fine tuning resistor R4.
This configuration typically delivers a lower level of ac
performance than the previously discussed transformer solution because the amplifier introduces another source of
distortion. Suitable amplifiers should be selected based on
their slew-rate, harmonic distortion, and output swing capabilities. High-speed amplifiers like the OPA680 or OPA687
may be considered. The ac performance of this circuit may
be improved by adding a small capacitor (CDIFF) between the
outputs IOUT and IOUT, as shown in Figure 4). This will
introduce a real pole to create a low-pass filter in order to
slew-limit the DAC fast output signal steps, that otherwise
could drive the amplifier into slew-limitations or into an
overload condition; both would cause excessive distortion.
The difference amplifier can easily be modified to add a
level shift for applications requiring the single-ended output
voltage to be unipolar (that is, swing between 0V and +2V.)
DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION
The circuit example of Figure 5 shows the signal output
currents connected into the summing junctions of the dual
voltage-feedback op amp OPA2680 that is set up as a
transimpedance stage, or I-to-V converter. With this circuit,
the DAC output will be kept at a virtual ground, minimizing
the effects of output impedance variations, which results in
the best DC linearity (INL). As mentioned previously, care
should be taken not to drive the amplifier into slew-rate
limitations, and produce unwanted distortion.
+5V
50Ω
1/2
OPA2680
RF1
DAC2902
R2
402Ω
IOUT
R1
200Ω
–VOUT = IOUT • RF1
CD1
CF1
RF2
IOUT
DAC2902
IOUT
OPA680
COPT
RL
26.1Ω
R3
200Ω
RL
28.7Ω
VOUT
IOUT
CD2
CF2
–5V +5V
1/2
OPA2680
R4
402Ω
–VOUT = IOUT • RF2
50Ω
–5V
FIGURE 4. Difference Amplifier Provides Differential to
Single-Ended Conversion and DC-Coupling.
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680
Forms Differential Transimpedance Amplifier.
DAC2902
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The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2)
will produce a 0 in the noise gain for the OPA2680 that may
cause peaking in the closed-loop frequency response. CF is
added across RF to compensate for this noise gain peaking.
To achieve a flat transimpedance frequency response, the
pole in each feedback network should be set to:
IOUTFS = 20mA
VOUT = 0V to +0.5V
IOUT
DAC2902
50Ω
IOUT
50Ω
25Ω
1
GBP
=
2 πR F C F 4 πR F C D
(8)
with GBP = Gain Bandwidth Product of OPA,
FIGURE 6. Driving a Doubly Terminated 50Ω Cable Directly.
which will give a corner frequency f-3dB of approximately:
f−3dB
GBP
=
2πR F C D
(9)
The full-scale output voltage is simply defined by the product of IOUTFS × RF, and has a negative unipolar excursion. To
improve on the ac performance of this circuit, adjustment of
RF and/or IOUTFS should be considered. Further extensions of
this application example may include adding a differential
filter at the OPA2680 output followed by a transformer, in
order to convert to a single-ended signal.
SINGLE-ENDED CONFIGURATION
Using a single-load resistor connected to the one of the DAC
outputs, a simple current-to-voltage conversion can be accomplished. The circuit in Figure 6 shows a 50Ω resistor
connected to IOUT, providing the termination of the further
connected 50Ω cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0V to 0.5V into the 25Ω load.
VOUT ~ 0Vp to 1.20Vp
DAC2902
One of the main applications for the dual-channel DAC is
baseband I- and Q-channel transmission for digital communications. In this application, the DAC is followed by an
analog quadrature modulator, modulating an IF carrier with
the baseband data, as shown in Figure 7. Often, the input
stages of these quadrate modulators consist of npn-type
transistors that require a DC bias (base) voltage of > 0.8V.
The wide output compliance range (–10V to +1.25V) allows
for a direct DC–coupling between the DAC2902 and the
quadrature modulator.
IIN
IREF
IIN
IREF
IOUT1
Signal
Conditioning
IOUT2
INTERFACING ANALOG
QUADRATURE MODULATORS
VIN ~ 0.6Vp to 1.8Vp
IOUT1
IOUT2
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, IOUTFS, and the load resistor, may be mutually adjusted to provide the desired output signal swing and
performance.
∑
RF
QIN
QREF
Quadrature Modulator
FIGURE 7. Generic Interface to a Quadrature Modulator. Signal Conditioning (Level-Shifting) May Be Required to Ensure
Correct DC Common-Mode Levels At the Input of the Quadrature Modulator.
DAC2902
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SBAS167C
Figure 8 shows an example of a DC-coupled interface with
DC level-shifting, using a precision resistor network. An accoupled interface, as shown in Figure 9, has the advantage
that the common-mode levels at the input of the modulator
can be set independently of those at the output of the DAC.
Furthermore, no voltage loss is obtained in this setup.
VDC
R3
VOUT1
INTERNAL REFERENCE OPERATION
VOUT1
The DAC2902 has an on-chip reference circuit that consists
of a 1.25V bandgap reference and two control amplifiers,
one for each DAC. The full-scale output current, IOUTFS, of
the DAC2902 is determined by the reference voltage, VREF,
and the value of resistor RSET. IOUTFS can be calculated by:
IOUTFS = 32 × IREF = 32 × VREF / RSET
R4
IOUT1
IOUT1
(10)
The external resistor RSET connects to the FSA pin (FullScale Adjust), see Figure 10. The reference control amplifier
operates as a V-to-I converter producing a reference current,
IREF, which is determined by the ratio of VREF and RSET (as
shown in Equation 10). The full-scale output current, IOUTFS,
results from multiplying IREF by a fixed factor of 32.
IOUT1
DAC2902
IOUT1
R5
FIGURE 8. DC-Coupled Interface to Quadrature Modulator
Applying Level Shifting.
VDC
R1
IOUT1
DAC2902
0.01µF
VOUT1
IOUT1
VOUT1
IOUT1
0.01µF
IOUT1
50Ω
RLOAD
50Ω
R2
FIGURE 9. AC-Coupled Interface to Quadrature Modulator Applying Level Shifting.
DAC2902
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13
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one RSET connected to the FSA1 pin (pin 44) and the other to the
FSA2 pin (pin 41). In this configuration, the user has the
flexibility to set and adjust the full-scale output current for each
DAC independently, allowing for the compensation of possible
gain mismatches elsewhere within the transmit signal path.
+5V
+VA
DAC2902
IREF =
Alternatively, bringing the GSET pin HIGH (that is, connected to +VA), the DAC2902 will switch into the simultaneous gain set mode. Now the full-scale output current of both
DAC channels is determined by only one external RSET
resistor connected to the FSA1 pin. The resistor at the FSA2
pin may be removed, however this is not required since this
pin is not functional in this mode and the resistor has no effect
to the gain equation. The formula for deriving the correct RSET
remains unchanged (for example, RSET = 2kΩ will result in a
20mA output for both DACs).
VREF
RSET
FSA
REFIN
RSET
2kΩ
Ref
Control
Amp
Current
Sources
0.1µF
+1.25V Ref.
EXTERNAL REFERENCE OPERATION
FIGURE 10. Internal Reference Configuration.
The internal reference can be disabled by simply applying an
external reference voltage into the REFIN pin, which in this
case functions as an input, as shown in Figure 11. The use
of an external reference may be considered for applications
that require higher accuracy and drift performance, or to add
the ability of dynamic gain control.
Using the internal reference, a 2kΩ resistor value results in
a full-scale output of approximately 20mA. Resistors with a
tolerance of 1% or better should be considered. Selecting
higher values, the output current can be adjusted from 20mA
down to 2mA. Operating the DAC2902 at lower than 20mA
output currents may be desirable for reasons of reducing the
total power consumption, optimizing the distortion performance, or observing the output compliance voltage limitations for a given load condition.
While a 0.1µF capacitor is recommended to be used with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance (1MΩ) and can easily be driven by various
sources. Note that the voltage range of the external reference
should stay within the compliance range of the reference
input (0.5V to 1.25V).
It is recommended to bypass the REFIN pin with a ceramic
chip capacitor of 0.1µF or more. The control amplifier is
internally compensated, and its small signal bandwidth is
approximately 0.3MHz.
POWER-DOWN MODE
The DAC2902 features a power-down function that can be
used to reduce the total supply current to less than 6mA.
Applying a logic HIGH to the PD pin will initiate the powerdown mode, while a logic LOW enables normal operation.
When left unconnected, an internal active pull-down circuit
will enable the normal operation of the converter.
GAIN SETTING OPTIONS
The full-scale output current on the DAC2902 can be set two
ways: either for each of the two DAC channels independently or
for both channels simultaneously. For the independent gain set
mode, the GSET pin (pin 42) must be LOW (that is, connected
to AGND). In this mode, two external resistors are required—
+5V
+VA
DAC2902
IREF =
VREF
RSET
FSA
REFIN
External
Reference
Ref
Control
Amp
Current
Sources
RSET
+1.25V Ref.
FIGURE 11. External Reference Configuration.
DAC2902
14
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SBAS167C
GROUNDING, DECOUPLING, AND
LAYOUT INFORMATION
Proper grounding and bypassing, short lead length, and the use
of ground planes are particularly important for high-frequency
designs. Multilayer PCBs are recommended for best performance since they offer distinct advantages such as minimization of ground impedance, separation of signal layers by
ground layers, etc.
The DAC2902 uses separate pins for its analog and digital
supply and ground connections. The placement of the decoupling capacitor should be such that the analog supply (+VA)
is bypassed to the analog ground (AGND), and the digital
supply bypassed to the digital ground (DGND). In most
cases 0.1µF ceramic chip capacitors at each supply pin are
adequate to provide a low impedance decoupling path. Keep
in mind that their effectiveness largely depends on the
proximity to the individual supply and ground pins. Therefore, they should be located as close as physically possible
to those device leads. Whenever possible, the capacitors
should be located immediately under each pair of supply/
ground pins on the reverse side of the pc board. This layout
approach will minimize the parasitic inductance of component leads and PCB runs.
Further supply decoupling with surface-mount tantalum capacitors (1µF to 4.7µF) may be added as needed in proximity of the converter.
Low noise is required for all supply and ground connections
to the DAC2902. It is recommended to use a multilayer PCB
utilizing separate power and ground planes. Mixed signal
designs require particular attention to the routing of the
different supply currents and signal traces. Generally, analog
supply and ground planes should only extend into analog
signal areas, such as the DAC output signal and the reference signal. Digital supply and ground planes must be
confined to areas covering digital circuitry, including the
digital input lines connecting to the converter, as well as the
clock signal. The analog and digital ground planes should be
joined together at one point underneath the DAC. This can
be realized with a short track of approximately 1/8" (3mm).
The power to the DAC2902 should be provided through the
use of wide PCB runs or planes. Wide runs will present a
lower trace impedance, further optimizing the supply decoupling. The analog and digital supplies for the converter
should only be connected together at the supply connector of
the pc board. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with bypass
capacitors may be used to create an LC filter. This will
generate a low-noise analog supply voltage that can then be
connected to the +VA supply pin of the DAC2902.
While designing the layout, it is important to keep the analog
signal traces separated from any digital line, in order to
prevent noise coupling onto the analog signal path.
DAC2902
SBAS167C
15
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Revision History
DATE
REVISION
9/08
C
PAGE
SECTION
DESCRIPTION
1
–
2
Pkg/Ordering Info Table
Updated front page to standard format.
Updated Package/Ordering Information table.
3
Electrical Characteristics
Changed values for Supply Current and Power Dissipation.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DAC2902
16
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SBAS167C
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DAC2902Y/1K
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC2902Y
DAC2902Y/1KG4
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC2902Y
DAC2902Y/250
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC2902Y
DAC2902Y/250G4
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC2902Y
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC2902Y/1K
TQFP
PFB
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
DAC2902Y/250
TQFP
PFB
48
250
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC2902Y/1K
TQFP
PFB
48
1000
367.0
367.0
38.0
DAC2902Y/250
TQFP
PFB
48
250
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
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www.ti.com/audio
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Computers and Peripherals
www.ti.com/computers
DLP® Products
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Logic
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Microcontrollers
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RFID
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www.ti.com/omap
TI E2E Community
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Wireless Connectivity
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