Holtek HT82A520R Full speed usb 8-bit otp mcu with spi Datasheet

HT82A520R/HT82A620R
Full Speed USB 8-Bit OTP MCU with SPI
Features
· Operating voltage:
· Max. 4 endpoints supported - endpoint 0 included
fSYS = 6MHz: 2.2V~5.5V
fSYS = 12MHz: 4.0V~5.5V
· All endpoints support Interrupt and bulk transfer
· Endpoint 0 supports control and interrupt
· 4K´15 Program Memory
· All endpoints except endpoint 0 can be configured
· 160´8 data memory RAM
as 8, 16, 32, 64 FIFO size
· USB 2.0 Full Speed Compatible
· Endpoint 0 has 8 byte FIFO
· Single external interrupt input shared with I/O line
· Total FIFO size: 64+8 bytes (RAM0: 48 bytes;
· Single 16-bit programmable Timer/Event Counters
RAM1:16 bytes, 8 bytes for endpoint0)
with overflow interrupt
· Single SPI interfaces (master and slave mode)
shared with PA0~PA3
· Total of 4 Interrupts - INT, Timer, SPI, USB
· 6-level subroutine nesting
· Watchdog Timer function
· All instructions executed in one or two instruction
· Bit manipulation instruction
· Table read instructions
· 63 powerful instructions
· Power down and wake-up functions to reduce power
cycles
consumption
· 16 channel 12-bit resolution A/D converter for
HT82A620R
· Low voltage reset function (2.0V±0.1%)
· 20/24/28-pin SSOP, 32-pin QFN package
· PB7 can configure as GPIO or VDDIO by option.
· 3-channel 12-bit PWM output shared with three I/O
The power supply of the pin PB0~PB6 can be
optioned as VDD or VDDIO
lines
· 24 Bidirectional I/O lines
· Up to 0.33ms instruction cycle with 12MHz system
clock at VDD=5V
General Description
The HT82A520R/HT82A620R are 8-bit high performance RISC-like microcontrollers designed for USB
keyboard mouse and joystick product applications.
Width Modulation function, Watchdog timer, SPI interfaces, Power Down and wake-up functions, enhance
the versatility of these devices to suit a wide range of application possibilities such as sensor signal processing,
motor driving, industrial control, consumer products,
subsystem controllers, etc.
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, Pulse
Selection Table
Data
Memory
Program
Memory
I/O
Timer
A/D
PWM
SPI
Package
HT82A520R
160´8
4K´15
24
16-bit´1
¾
12-bit´3
1
20/24/28SSOP,
32QFN
HT82A620R
160´8
4K´15
24
16-bit´1
12-bit´16
12-bit´3
1
20/24/28SSOP,
32QFN
Part No.
Rev.1.30
1
January 14, 2011
HT82A520R/HT82A620R
Block Diagram
HT82A520R
3 .3 V
R e g u la to r
U S B 2 .0
X C V R
W a tc h d o g
T im e r
U S B 2 .0
F u ll S p e e d
E n g lin e
8 - b it
R IS C
M C U
C o re
S P I
In te rfa c e
O T P P ro g ra m
M e m o ry
D a ta
M e m o ry
L o w
V o lta g e
R e s e t
I/O
P o rts
1 6 - b it
T im e r
S ta c k
P W M
G e n e ra to r
W a tc h d o g
T im e r O s c illa to r
R e s e t
C ir c u it
In te rru p t
C o n tr o lle r
C ry s ta l
O s c illa to r
HT82A620R
3 .3 V
R e g u la to r
U S B 2 .0
X C V R
S P I
In te rfa c e
O T P P ro g ra m
M e m o ry
I/O
P o rts
1 6 - b it
T im e r
Rev.1.30
W a tc h d o g
T im e r
U S B 2 .0
F u ll S p e e d
E n g lin e
8 - b it
R IS C
M C U
C o re
L o w
V o lta g e
R e s e t
D a ta
M e m o ry
W a tc h d o g
T im e r O s c illa to r
R e s e t
C ir c u it
In te rru p t
C o n tr o lle r
C ry s ta l
O s c illa to r
A /D
C o n v e rte r
S ta c k
P W M
G e n e ra to r
2
January 14, 2011
HT82A520R/HT82A620R
Pin Assignment
P B 6
1
2 0
P B 1
V D D
3
1 8
P A 7 /T M R
1 9
P B 7
2
4
5
6
P A 4 /P W M 0
1 4
O S C O
7
P A 3 /S D O
1 3
8
P A 2 /S D I
1 2
9
R E S
P A 5 /P W M 1
1 5
V 3 3 O
V S S
P A 6 /IN T
1 6
D + /C L K
O S C I
P B 0 /P W M 2
1 7
D -/D A T A
P A 1 /S C K
1 1
1 0
1
2 4
P B 2
P B 7
3
2 2
P B 0 /P W M 2
P A 0 /S C S
1
2
3
4
5
6
7
D I
O
0
1
T
R
2
1
P C 0
R E S
V S S
O S C I
O S C O
V 3 3 O
D + /C L K
D -/D A T A
2 4
2 3
2
3
2 2
H T 8 2 A 5 2 0 R
3 2 Q F N -A
4
5
6
2 1
2 0
1 9
1 8
7
8
9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
1 7
V D D
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
1
2 8
P B 3 /A N 3
P B 6 /A N 6
3
2 6
P B 1 /A N 1
O S C O
O S C I
V S S
R E S
P C 0
4
V D D
2 5
5
D -/D A T A
2 4
6
D + /C L K
2 3
V 3 3 O
O S C O
O S C I
V S S
R E S
8
2 1
9
1 0
1 1
1 2
1 3
1 4
2 0
1 9
1 8
1 7
1 6
1 5
1 5
1 1
1 2
1 3
P C 7
P C 1
1
2 0
P B 1 /A N 1
9
1 0
1 1
1 2
P C 0
1 3
1 4
V D D
3
1 8
P A 7 /T M R
D -/D A T A
D + /C L K
V 3 3 O
O S C O
O S C I
V S S
R E S
P A 5 /P W M 1
P A 4 /P W M 0
P A 3 /S D O
P A 2 /S D I
P A 1 /S C K
P A 0 /S C S
2 1
5
2 0
6
1 9
7
O S C O
O S C I
V S S
R E S
P C 0 /A N 8
1 8
8
1 7
9
1 0
1 1
1 2
1 6
1 5
1 4
1 3
P B 1 /A N 1
P A 7 /T M R
P A 6 /IN T
P A 5 /P W M 1
P A 4 /P W M 0
P A 3 /S D O
P A 2 /S D I
P A 1 /S C K
P A 0 /S C S
P C 7 /A N 1 5
H T 8 2 A 6 2 0 R
2 4 S S O P -A
P B 0 /A N 0 /P W M 2
P A 6 /IN T
4
V 3 3 O
H T 8 2 A 6 2 0 R
2 0 S S O P -A
P B 2 /A N 2
P A 7 /T M R
P C 6
P B 0 /A N 0 /P W M 2
2 3
D + /C L K
P A 0 /S C S
1 1
1 0
P C 7
2 2
2
D -/D A T A
P A 1 /S C K
1 2
9
1 5
P A 0 /S C S
3
P A 2 /S D I
1 3
8
1 6
P A 1 /S C K
P B 7 /A N 7
P A 3 /S D O
1 4
7
1 7
P A 2 /S D I
P B 2 /A N 2
P A 4 /P W M 0
1 5
6
1 8
P A 3 /S D O
2 4
P A 5 /P W M 1
1 6
5
1 9
P A 4 /P W M 0
1
V D D
P A 6 /IN T
1 7
4
2 0
P A 5 /P W M 1
P B 5 /A N 5
P B 6 /A N 6
P B 0 /A N 0 /P W M 2
1 9
2
2 1
P A 6 /IN T
H T 8 2 A 5 2 0 R
2 8 S S O P -A
P B 6 /A N 6
P A 1
P A
P A 3
P A 4 /P
P A 5 /P
P A
P A 7
P B 0 /A N 0 /P
P C 7 /A N 1 5
P C 6 /A N 1 4
/S C
2 /S
/S D
W M
W M
6 /IN
/T M
W M
K
D I
O
0
1
T
R
2
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
1
2 4
2 3
2
3
H T 8 2 A 6 2 0 R
3 2 Q F N -A
4
5
6
8
2 2
2 1
2 0
1 9
1 8
7
9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
1 7
P C 0 /A N 8
R E S
V S S
O S C I
O S C O
V 3 3 O
D + /C L K
D -/D A T A
7
6
5
4
3
3
2
1
H T 8 2 A 6 2 0 R
2 8 S S O P -A
Rev.1.30
R E S
P A 0 /S C S
1 4
8
V S S
P A 1 /S C K
2 2
P A 7 /T M R
/A N
/A N
/A N
/A N
/A N
/A N
/A N
P C 1 /A N 9
2 2
1 0
7
O S C I
P A 2 /S D I
1 6
2 3
P B 0 /P W M 2
V D D
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P C 0 /A N 8
7
9
6
O S C O
P A 3 /S D O
1 7
2 4
N 9
1 0
1 1
1 2
1 3
1 4
1 5
C S
P B 7 /A N 7
2 7
8
5
V 3 3 O
P A 4 /P W M 0
1 8
2 5
P B 2
1 /A
/A N
/A N
/A N
/A N
/A N
/A N
0 /S
2
7
V 3 3 O
P B 1
4
D + /C L K
P A 5 /P W M 1
1 9
2 6
P C
P C 2
P C 3
P C 4
P C 5
P C 6
P C 7
P A
P B 4 /A N 4
P B 5 /A N 5
6
D + /C L K
3
D -/D A T A
P A 6 /IN T
2 0
P B 7 /A N 7
S
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
K
5
D -/D A T A
P B 6
2 7
V D D
P A 7 /T M R
2 1
P B 3
H T 8 2 A 5 2 0 R
2 4 S S O P -A
P C
P C
P C
P C
P C
P C
P C
P A 0 /\S C
/S C
2 /S
/S D
W M
W M
6 /IN
/T M
W M
4
2 8
2
P B 7
P B 1
2 3
V D D
H T 8 2 A 5 2 0 R
2 0 S S O P -A
P A 1
P A
P A 3
P A 4 /P
P A 5 /P
P A
P A 7
P B 0 /P
2
1
P B 5
P B 5
P B 6
P B 4
January 14, 2011
HT82A520R/HT82A620R
Pin Description
HT82A520R
Pin Name
I/O
Options
Description
Pull-high
Wake-up
NMOS or CMOS
Bidirectional 8-bit input/output port. Each pin can be configured as a
wake-up input by a configuration option. Software instructions determine if
the pin is output or Schmitt Trigger input. When if output, Configuration option may choose CMOS or NMOS. Configuration options determine if the
pins have pull-high resistors. The INT and TMR pins are pin-shared with
PA6 and PA7, respectively. PA0~PA3 are shared with the SPI function.
PA4~PA5 are shared with PWM0~PWM1.
PA0/SCS
PA1/SCK
PA2/SDI
PA3/SDO
PA4/PWM0
PA5/PWM1
PA6/INT
PA7/TMR
I/O
PB0/PWM2
PB1~PB7
Bi-directional 8-bit input/output port. Software instructions determine if the
pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors.
PB7: I/O or VDDIO A configuration option determines whether PB7 is an I/O pin or a power
I/O
PB0~PB6 power: supply pin for PB0~PB6.
A configuration option determines whether the power supply for PB0~PB6
from VDD or
is sourced from VDD or VDDIO.
VDDIO
PB0 shared with PWM2.
PC0~PC7
I/O
Pull-high
Wake-up
Bi-directional 8-bit input/output port. Software instructions determine if the
pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors.
OSCI
OSCO
I
O
¾
OSCI, OSCO are connected to an 6MHz or 12MHz Crystal/resonator (determined by software instructions) for the internal system clock
RES
I
¾
Schmitt Trigger reset input, active low
VDD
¾
¾
Positive power supply
D-/Data
I/O
¾
USBD- line
The USB function is controlled by software control registers
D+/CLK
I/O
¾
USBD+ line
The USB function is controlled by software control registers
V33O
O
¾
3.3V regulator output
VSS
¾
¾
Negative power supply, ground
Pull-high
Wake-up
Rev.1.30
4
January 14, 2011
HT82A520R/HT82A620R
HT82A620R
Pin Name
PA0/SCS
PA1/SCK
PA2/SDI
PA3/SDO
PA4/PWM0
PA5/PWM1
PA6/INT
PA7/TMR
I/O
I/O
Options
Description
Pull-high
Wake-up
NMOS or CMOS
Bi-directional 8-bit input/output port. Each bit can be configured as
wake-up input by option (bit option). Software instructions determine
if the pin is output or Schmitt Trigger input. When if output, Configuration option may choose CMOS or NMOS. Configuration options determine if the pins have pull-high resistors.
The TMR and INT are pin-shared with PA6 and PA7, respectively.
PA0~PA3 are shared with SPI function.
PA4~PA5 shared with PWM0~PWM1.
I/O
Bi-directional 8-bit input/output port. Software instructions determine
if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. PB is pin shared
Pull-high
with the A/D inputs. Once a PB line is selected as an A/D input, using
Wake-up
software control, the I/O function and pull-high resistor are disabled
PB7: I/O or VDDIO
automatically.
PB0~PB6 power: A configuration option determines whether PB7 is an I/O pin or a
from VDD or
power supply pin for PB0~PB6.
VDDIO
A configuration option determines whether the power supply for
PB0~PB6 is sourced from VDD or VDDIO
PB0 shared with PWM2.
PC0/AN8
PC1/AN9
PC2/AN10
PC3/AN11
PC4/AN12
PC5/AN13
PC6/AN14
PC7/AN15
I/O
Pull-high
Wake-up
Bi-directional 8-bit input/output port. Software instructions determine
if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. PC is pin shared
with the A/D inputs. Once a PB line is selected as an A/D input, using
software control, the I/O function and pull-high resistor are disabled
automatically
OSCI
OSCO
I
O
¾
OSCI, OSCO are connected to an external 6MHz or 12MHz Crystal/resonator, determined by software instructions, for the internal
system clock
RESB
I
¾
Schmitt trigger reset input, active low
VDD
¾
¾
Positive power supply
D -/Data
I/O
¾
USBD- line
The USB function is controlled by a software control register
D +/CLK
I/O
¾
USBD+ line
The USB function is controlled by a software control register
V33O
O
¾
3.3V regulator output
VSS
¾
¾
Negative power supply, ground
PB0/AN0/PWM2
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature.............................-0°C to 70°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev.1.30
5
January 14, 2011
HT82A520R/HT82A620R
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSYS=6MHz
2.2
¾
5.5
V
fSYS=12MHz
4.0
¾
5.5
V
5V
No load, fSYS=6MHz,
ADC Off, DAC Off
¾
8
¾
mA
5V
No load, system HALT,
USB transceiver,
3.3V Register on and clr
suspend2 (UCC.4 [22H])
¾
330
¾
mA
¾
220
¾
mA
¾
¾
10
mA
Conditions
VDD
VDD
IDD
Isus1
Operating Voltage
Operating Current
Suspend Current
¾
Isus2
Suspend Current
5V
No load, system HALT,
USB transceiver,
3.3V Register on and set
suspend2 (UCC.4 [22H])
ISTB1
Standby Current
(WDT Disabled)
5V
No load, system HALT,
USB disable
VIL1
Input Low Voltage for I/O Ports
5V
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports
5V
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
5V
¾
0
¾
0.4VDD
V
¾
VDD
V
VIH2
Input High Voltage (RES)
5V
¾
0.9VDD
VLVR0
Low Voltage Reset
5V
¾
1.9
2.0
2.1
V
VV33O
3.3V Regulator Output
5V
3.0
3.3
3.6
V
VOS*
Offset Error
¾
IOL
I/O Port Sink Current
IV33O=-5mA
-2
¾
2
mV
5V
VOL=0.1VDD
¾
10
20
¾
mA
VOH=0.9VDD
-5
-10
¾
mA
IOH
I/O Port Source Current
5V
RPH
Pull-high Resistance
5V
¾
10
30
50
kW
RPH1
Pull-high Resistance for DATA
5V
¾
¾
4.5
¾
kW
RPH2
Pull-high Resistance for CLK
5V
¾
¾
4.5
¾
kW
IADC*
Additional Power Consumption
if A/D Converter is Used
5V
No load
¾
1.5
3.0
mA
DNL*
A/D Differential Non-Linearity
¾
¾
¾
¾
±2
LSB
INL*
A/D Integral Non-Linearity
¾
¾
±2.5
±4.0
LSB
¾
¾
12
Bits
RESOLU* Resolution
Note: ²*²for HT82A620R
Rev.1.30
6
January 14, 2011
HT82A520R/HT82A620R
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
fSYS
System Clock
Min.
Typ.
Max.
Unit
Conditions
VDD
¾
2.2V~5.5V
¾
6000
¾
kHz
¾
4.0V~5.5V
¾
12000
¾
kHz
fSYS=6MHz
0
¾
6000
kHz
fSYS=12MHz
0
¾
12000
kHz
Timer I/P Frequency
(TMR)
¾
tWDTOSC
Watchdog Oscillator Period
5V
¾
¾
31
¾
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
tSYS
tOPD
Option Load Timer Period
5V
¾
33
70
140
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD*
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC*
A/D Conversion Time
¾
¾
¾
16
¾
tAD
tADCS*
A/D Sample Time
¾
¾
¾
8
¾
tAD
tCS_SK
SPI SCS to SCK Time
¾
¾
50
¾
¾
ns
tSPICK
SPI Clock Time
¾
¾
400
¾
¾
ns
fTIMER
Note:
Wake-up from HALT
tSYS=1/fSYS
²*² for HT82A620R
Rev.1.30
7
January 14, 2011
HT82A520R/HT82A620R
System Architecture
instruction cycle. Although the fetching and execution of
instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one
instruction cycle. The exception to this are instructions
where the contents of the Program Counter are
changed, such as subroutine calls or jumps, in which
case the instruction will take one more instruction cycle
to execute.
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O and A/D control system with maximum reliability and flexibility.
For instructions involving branches, such as jump or call
instructions, two instruction cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. It must be
noted that only the lower 8 bits, known as the Program
Counter Low Register, are directly addressable by user.
Clocking and Pipelining
The main system clock, derived from a Crystal/Resonator is subdivided into four internally generated
non-overlapping clocks, T1~T4. The Program Counter
is incremented at the beginning of the T1 clock during
which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution
functions. In this way, one T1~T4 clock cycle forms one
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1
M O V A ,[1 2 H ]
3
C P L [1 2 H ]
2
C A L L D E L A Y
4
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
5
:
6
D E L A Y :
E x e c u te In s t. 2
F e tc h In s t. 3
:
N O P
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
Instruction Fetching
Rev.1.30
8
January 14, 2011
HT82A520R/HT82A620R
After a device reset, the Stack Pointer will point to the
top of the stack.
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writeable register.
By transferring data directly into this register, a short program jump can be executed directly, however, as only
this low byte is available for manipulation, the jumps are
limited to the present page of memory, that is 256 locations. When such program jumps are executed it should
also be noted that a dummy cycle will be inserted.
P ro g ra m
T o p o f S ta c k
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
B o tto m
Stack
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
P ro g ra m
M e m o ry
S ta c k L e v e l 3
o f S ta c k
C o u n te r
S ta c k L e v e l 6
Arithmetic and Logic Unit - ALU
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has 6 levels and is neither part of the data nor part
of the program space, and is neither readable nor
writeable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writeable. At a
subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program
Counter is restored to its previous value from the stack.
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions.
Program Counter Bits
Mode
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
USB Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter
Overflow
0
0
0
0
0
0
0
0
1
1
0
0
SPI Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
Skip
Program Counter + 2
Loading PCL
PC11 PC10
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
PC11~PC8: Current Program Counter bits
#11~#0: Instruction code address bits
Rev.1.30
@7~@0: PCL bits
S11~S0: Stack register bits
9
January 14, 2011
HT82A520R/HT82A620R
· Location 010H
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
This vector is used by serial interface. When 8-bits of
data have been received or transmitted successfully
from serial interface, the program will jump to this location and begin execution if the interrupt is enabled
and the stack is not full.
SUB, SUBM, SBC, SBCM, DAA
· Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
0 0 0 H
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
0 0 4 H
SIZA, SDZA, CALL, RET, RETI
0 0 8 H
Program Memory
0 0 C H
The Program Memory is the location where the user
code or program is stored. The HT82A520R/
HT82A620R is a One-Time Programmable, OTP, memory type device where users can program their application code into the device. By using the appropriate
programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent
upgrades or program changes. OTP devices are also
applicable for use in applications that require low or medium volume production runs.
0 1 0 H
U S B
In te rru p t V e c to r
E x te rn a l
In te rru p t V e c to r
T im e r /E v e n t C o u n te r
In te rru p t V e c to r
S P I
In te rru p t V e c to r
F F F H
1 5 b its
Program Memory Structure
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, one method is to first
setup a low byte table pointer by placing the lower order
address of the look up data to be retrieved in the low
byte table pointer register, TBLP. This register defines
the lower 8-bit address of the look-up table.
Structure
The Program Memory has a capacity of 4K by 15 bits.
The Program Memory is addressed by the Program
Counter and also contains data, table information and
interrupt entries. Table data, which can be setup in any
location within the Program Memory, is addressed by
separate table pointer registers.
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
· Location 000H
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
· Location 004H
This area is reserved for the USB interrupt service
program. If the USB interrupt is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
The following diagram illustrates the addressing/data
flow of the look-up table:
· Location 008H
Table Program Example
This vector is used by the external interrupt. If the INT
external input pin on the device receives a high to low
transition, the program will jump to this location and
begin execution, if the interrupt is enabled and the
stack is not full.
Another method is to setup the full table address using
both the TBLP and TBHP low and high byte table pointer
registers to directly address any area in he Program
Memory. In this way any page of data can be accessed
directly using the TABRDL instruction. If the TBHP high
byte table pointer register is to be used, then it must first
be enabled with a configuration option.
· Location 00CH
This vector is used by the timer counter. If a counter
overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled
and the stack is not full.
Rev.1.30
In itia lis a tio n
V e c to r
10
January 14, 2011
HT82A520R/HT82A620R
P ro g ra m C o u n te r
H ig h B y te
The following example shows how the table pointer and
table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is
²F00H² which refers to the start address of the last page
within the 4K Program Memory of device. The table
pointer is setup here to have an initial value of ²06H².
This will ensure that the first data read from the data table will be at the Program Memory address ²F06H² or 6
locations after the start of the last page. Note that the
value for the table pointer is referenced to the first address of the present page if the ²TABRDC [m]² instruction is being used. The high byte of the table data which
in this case is equal to zero will be transferred to the
TBLH register automatically when the ²TABRDL [m]² instruction is executed.
tempreg1 db
tempreg2 db
:
:
?
?
P ro g ra m
M e m o ry
T B L P
T B L H
T B H P
P ro g ra m
M e m o ry
T B L P
T B L H
H ig h B y te o f T a b le C o n te n ts
; to the last page or present page
tabrdl
;
;
;
;
B y te o f T a b le C o n te n ts
transfers value in table referenced by table pointer
to tempregl
data at prog. memory address ²F06H² transferred to
tempreg1 and TBLH
; reduce value of table pointer by one
tempreg2
:
:
org F00h
dc
S p e c ifie d b y [m ]
; temporary register #1
; temporary register #2
mov tblp,a
:
:
tabrdl
L o w
T a b le R e a d - T B L P / T B H P
; initialise table pointer - note that this address
; is referenced
dec tblp
B y te
T a b le R e a d - T B L P O n ly
mov a,06h
tempreg1
S p e c ifie d b y [m ]
T a b le C o n te n ts L o w
T a b le C o n te n ts H ig h B y te
;
;
;
;
;
;
;
;
transfers value in table referenced by table pointer
to tempreg2
data at prog.memory address ²F05H² transferred to
tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
the value ²00H² will be transferred to the high byte
register TBLH
; sets initial address of last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Instruction
Table Location Bits
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m]
PC11
PC10
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
PC11~PC8: Current Program Counter bits
@7~@0: Table Pointer TBLP bits
Rev.1.30
TBHP register bit3~bit0 when TBHP is enabled
11
January 14, 2011
HT82A520R/HT82A620R
microcontrollers, such as ACC, PCL, etc., have the
same Data Memory address.
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use the table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user program for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
2 9 H
2 A H
2 B H
2 C H
2 D H
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM
internal memory and is the location where temporary information is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some remain
protected from user manipulation. The second area of
Data Memory is reserved for general purpose use. All
locations within this area are read and write accessible
under program control.
Structure
The two sections of Data Memory, the Special Purpose
and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are
8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start
address of the Data Memory for all devices is the address ²00H². Registers which are common to all
0 0 H
S p e c
P u rp o
D a
M e m o
ia l
s e
ta
ry
G e n e ra l
P u rp o s e
D a ta
M e m o ry
5 F H
6 0 H
F F H
Data Memory Structure
Note:
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C 0
T M R H
T M R L
T M R C
P A
P A C
P B
P B C
P C
P C C
U S B _ S T A T
U IN T
IN T C 1
T B H P
U S C
U S R
U C C
A W R
S T A L L
S IE S
M IS C
U F IE N
F IF O 0
F IF O 1
F IF O 2
F IF O 3
2 E
2 F
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
3 A
3 B
3 C
3 D
3 E
3 F
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
4 9
4 A
4 B
4 C
4 D
4 E
4 F
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
5 A
H
H
H
U F O E N
U F C 0
H
H
H
H
H
H
H
H
H
S B C
S B D
A D R
A D R
A D C
A D S
A
H
H
H
H
H
R
R
L *
H *
R *
R *
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
P
P W
P W
P
P W
P W
P
P W
P W
W M B R
M 0 D R
M 0 D R
W M B R
M 1 D R
M 1 D R
W M B R
M 2 D R
M 2 D R
S P IR
0
L
H
1
L
2
H
H
L
: U n u s e d R e a d a s "0 0 "
"* " fo r H T 8 2 A 6 2 0 R
Most of the Data Memory bits can be directly
manipulated using the ²SET [m].i² and ²CLR
[m].i² with the exception of a few dedicated bits.
The Data Memory can also be accessed
through the memory pointer register MP.
Rev.1.30
IA R 0
M P 0
IA R 1
M P 1
12
January 14, 2011
HT82A520R/HT82A620R
Special Purpose Data Memory
physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these
Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual
memory address is specified. Actions on the IAR0 and
IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location
specified by their corresponding Memory Pointer, MP0
or MP1. Acting as a pair, IAR0 and MP0 can together
only access data from Bank 0, while the IAR1 and MP1
register pair can access data from both Bank 0 and
Bank 1. As the Indirect Addressing Registers are not
physically implemented, reading the Indirect Addressing Registers indirectly will return a result of ²00H²
and writing to the registers indirectly will result in no operation.
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both readable and
writable but some are protected and are readable only,
the details of which are located under the relevant Special Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value ²00H².
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control. The
location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the
point where the General Purpose Memory begins is reserved and attempting to read data from these locations
will return a value of 00H.
Memory Pointer - MP0, MP1
For all devices, two Memory Pointers, known as MP0
and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be
manipulated in the same way as normal registers providing a convenient way with which to address and track
data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that
the microcontroller is directed to, is the address specified by the related Memory Pointer.
Indirect Addressing Register - IAR0, IAR1
The IAR0 and IAR1 register, although having their locations in normal RAM register space, do not actually
data .section ¢data¢
adres1
db ?
adres2
db ?
adres3
db ?
adres4
db ?
block
db ?
code .section at 0 ¢code¢
org 00h
start:
mov
mov
mov
mov
a,04h
; setup size of block
block,a
a,offset adres1; Accumulator loaded with first RAM address
mp0,a
; setup memory pointer with first RAM address
loop:
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
continue:
The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses.
Rev.1.30
13
January 14, 2011
HT82A520R/HT82A620R
Accumulator - ACC
Status Register - STATUS
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Program Counter Low Register - PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
· C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
· AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Look-up Table Registers - TBLP, TBHP, TBLH
· Z is set if the result of an arithmetic or logical operation
These three special function registers are used to control operation of the look-up table which is stored in the
Program Memory. TBLP and TBHP are the table pointer
low and high byte registers and indicate the location
where the table data is located. There value must be
setup before any table read commands are executed.
Their value can be changed, for example using the
²INC² or ²DEC² instructions, allowing for easy table data
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user defined location.
b 7
T O
P D F
O V
Z
is zero; otherwise Z is cleared.
· OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
· TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
A C
b 0
C
S T A T U S R e g is te r
A r
C a
A u
Z e
ith m e
r r y fla
x ilia r y
r o fla g
O v e r flo w
g
tic /L o g ic O p e r a tio n F la g s
c a r r y fla g
fla g
S y s te m M
P o w e r d o w
W a tc h d o g
N o t im p le m
a n
n
tim
e
a g e m e n t F la g s
fla g
e - o u t fla g
n te d , re a d a s "0 "
Status Register
Rev.1.30
14
January 14, 2011
HT82A520R/HT82A620R
I/O registers are mapped to specific addresses within
the Data Memory as shown in the Data Memory table,
which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC, also
mapped to specific addresses with the Data Memory.
The control register specifies which pins of that port are
set as inputs and which are set as outputs. To setup a
pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low.
During program initialisation, it is important to first setup
the control registers to specify which pins are outputs
and which are inputs before reading data from or writing
data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the
²SET [m].i² and ²CLR [m].i² instructions. The ability to
change I/O pins from output to input and vice versa by
manipulating specific bits of the I/O control registers during normal program operation is a useful feature of
these devices.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the interrupt routine can change the status register, precautions must be
taken to correctly save it.
Interrupt Control Registers - INTC0, INTC1
The microcontrollers provide one external interrupts,
one internal timer/event counter overflow interrupt, one
SPI interrupt and one USB interrupt. By setting various
bits within these registers using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently controlled. A master
interrupt bit within this register, the EMI bit, acts like a
global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and
is set by executing the ²RETI² instruction.
Timer/Event Counter Registers TMRH, TMRL, TMRC
Input/Output Ports
All devices possess one internal 16-bit count-up timer. An
associated register pair known as TMRL/TMRH are the
locations where the timer 16-bit values are located.
These registers can also be preloaded with fixed data to
allow different time intervals to be setup. Associated control registers, known as TMRC, contains the setup information for the timers, which determines in what mode the
timer is to be used as well as containing the timer on/off
control function.
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins,
the user is provided with an I/O structure to meet the
needs of a wide range of application possibilities.
Input/Output Ports and Control Registers
This register is mapped to the Data Memory with an addresses as shown in the Special Purpose Data Memory
table. Seven of these I/O lines can be used for input and
output operations and one line as an input only. For input operation, these ports are non-latching, which
Depending upon which package is chosen, the
microcontroller provides up to 24 bidirectional input/output lines labeled with port names PA, PB, PC.
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB, PC. These labeled
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
Q
D
W r ite D a ta R e g is te r
S
R e a d D a ta R e g is te r
S y s te m
D D
W e a k
P u ll- u p
I/O
D a ta B it
Q
D
C K
V
Q
C K
C h ip R e s e t
R e a d C o n tr o l R e g is te r
P u ll- H ig h
S e le c t
S
p in
Q
M
U
X
W a k e -u p
W a k e - u p S e le c t
Generic Input/Output Ports
Rev.1.30
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January 14, 2011
HT82A520R/HT82A620R
Port B VDDIO Function
means the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
The output drivers of most I/O pins use the VDD power
supply line as their high voltage level. In this device pins
PB0~PB6 can use a different voltage, other than VDD as
their high level. This is supplied externally on pin PB7.
This function is selected using a configuration option.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, I/O pins, when configured as an input have the
capability of being connected to an internal pull-high resistor. The pull-high resistors are selectable via configuration options and are implemented using weak PMOS
transistors. Each pin on all of I/O can be selected individually to have this pull-high Resistors feature and
each nibble on each of the other ports.
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
Port Pin Wake-up
· External interrupt input
If the HALT instruction is executed, the device will enter
the Power Down Mode, where the system clock will stop
resulting in power being conserved, a feature that is important for battery and other low-power applications.
Various methods exist to wake-up the microcontroller,
one of which is to change the logic condition on one of
the port pins from high to low. After a HALT instruction
forces the microcontroller into entering the Power Down
Mode, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on the
port pin changes from high to low. This function is especially suitable for applications that can be woken up via
external switches. Each pin on PA has a bit wake-up
configuration option and PB, PC have nibble wake-up
configuration options.
The external interrupt pin INT is pin-shared with the
I/O pin PA6. For applications not requiring an external
interrupt input, the pin-shared external interrupt pin
can be used as a normal I/O pin, however to do this,
the external interrupt enable bits in the INTC0 register
must be disabled.
· External Timer Clock Inputs
The external timer pin TMR is pin-shared with an I/O
pin. To configure this pin to operate as a timer input,
the corresponding control bit in the timer control register must be correctly set. For applications that do not
require an external timer input, this pin can be used as
a normal I/O pin. Note that if used as a normal I/O pin
the timer mode control bits in the timer control register
must select the timer mode, which has an internal
clock source, to prevent the input pin from interfering
with the timer operation.
I/O Port Control Registers
· PWM outputs
Each I/O port has its own control register PAC, PBC,
PCC, to control the input/output configuration. With this
control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each of the I/O ports is
directly mapped to a bit in its associated port control register. Note that several pins can be setup to have NMOS
outputs using configuration options.
The device contains three PWM outputs which are
pin-shared with I/O pins. The PWM output functions
are chosen via registers. Note that the corresponding
bit of the port control register, PAC and PBC, must
setup the pin as an output to enable the PWM output.
If the PAC and PBC port control register has setup the
pin as an input, then the pin will function as a normal
logic input with the usual pull-high option, even if the
PWM configuration option has been selected.
For the I/O pin to function as an input, the corresponding
bit of the control register must be written as a ²1². This
will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit
of the control register is written as a ²0², the I/O pin will
be setup as an output. If the pin is currently setup as an
output, instructions can still be used to read the output
register. However, it should be noted that the program
will in fact only read the status of the output data latch
and not the actual logic status of the output pin.
Rev.1.30
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January 14, 2011
HT82A520R/HT82A620R
· A/D inputs - HT82A620R
Timer/Event Counters
This device has 16 A/D converter inputs depending
upon which package type is chosen. All of these analog inputs are pin-shared with I/O pins on Port B and
Port C. If these pins are to be used as A/D inputs and
not as normal I/O pins then the corresponding bits in
the A/D Converter Control Register, ACSR, must be
properly set. There are no configuration options associated with the A/D function. If used as I/O pins, then
full pull-high resistor configuration options remain,
however if used as A/D inputs then any pull-high resistor options associated with these pins will be automatically disconnected.
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. This device contains a single
count-up timer of 16-bit capacity. As each timer has
three different operating modes, they can be configured
to operate as a general timer, an external event counter
or as a pulse width measurement device.
There are two types of registers related to the
Timer/Event Counters. The first is the register that contain the actual value of the Timer/Event Counter and into
which an initial value can be preloaded, and is known as
TMRH, TMRL. Reading from this register retrieves the
contents of the Timer/Event Counter. The second type
of associated register is the Timer Control Register,
which defines the timer options and determines how the
Timer/Event Counter is to be used, and has the name
TMRC. This device can have the timer clocks configured to come from the internal clock sources. In addition, the timer clock sources can also be configured to
come from the external timer pins.
I/O Pin Structures
The vast range of I/O functions and pin-shared options
results in a huge variety of I/O pin structure types. For
this reason the generic Input/Output Port diagram provided here is for general reference only. As the exact
logical construction of the I/O pin will differ from the
drawing, they are supplied as a guide only to assist with
the functional understanding of the basic I/O pins.
Programming Considerations
The external clock source is used when the Timer/Event
Counter is in the event counting mode, the clock source
being provided on the external timer pin. The external
timer pin has the name TMR. Depending upon the condition of the TE bit in the Timer Control Register, each
high to low, or low to high transition on the external timer
input pin will increment the Timer/Event Counter by one.
Within the user program, one of the first things to consider is port initialisation. After a reset, all of the data and
port control register will be set high. This means that all
I/O pins will default to an input state, the level of which
depends on the other connected circuitry and whether
pull-high options have been selected. If the PAC, PBC,
PCC port control register, are then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated PA, PB, PC
port data registers are first programmed. Selecting
which pins are inputs and which are outputs can be
achieved byte-wide by loading the correct value into the
port control register or by programming individual bits in
the port control register using the ²SET [m].i² and ²CLR
[m].i² instructions. Note that when using these bit control
instructions, a read-modify-write operation takes place.
The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then
rewrite this data back to the output ports.
Configuring the Timer/Event Counter Input Clock
Source
The Timer/Event Counter¢s clock can originate from various sources. The instruction clock source (system clock
source divided by 4) is used when the Timer/Event Counter is in the timer mode or in the pulse width measurement mode. The external clock source is used when the
Timer/Event Counter is in the event counting mode, the
clock source being provided on the external timer pin,
TMR. Depending upon the condition of the TE bit, each
high to low, or low to high transition on the external timer
pin will increment the counter by one.
The ports have the additional capability of providing
wake-up functions. When the device is in the Power
Down Mode, various methods are available to wake the
device up. One of these is a high to low transition of any
of the port pins. Single or multiple pins on the ports can
be setup to have this function.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
Timer Registers - TMRL, TMRH
The timer registers are special function registers located
in the Special Purpose RAM Data Memory and are the
places where the actual timer values are stored. The
timer registers are known as TMRL and TMRH. The
value in the timer registers increases by one each time
an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count
from the initial value loaded by the preload register to
the full count of FFFFH for the 16-bit timer at which point
the timer overflows and an internal interrupt signal is
generated. The timer value will then be reset with the initial preload register value and continue counting.
T 4
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing
Rev.1.30
17
January 14, 2011
HT82A520R/HT82A620R
D a ta B u s
T M 1
fS
Y S /4
L o w B y te
B u ffe r
T M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T M R
R e lo a d
1 6 - B it
P r e lo a d R e g is te r
T O N
H ig h B y te
T E
L o w
O v e r flo w
to In te rru p t
B y te
1 6 - B it T im e r /E v e n t C o u n te r
16-bit Timer/Event Counter Structure
buffer will be transferred into its associated low byte
timer register. For this reason, the low byte timer register should be written first when preloading data into the
16-bit timer registers. It must also be noted that to read
the contents of the low byte timer register, a read to the
high byte timer register must be executed first to latch
the contents of the low byte timer register into its associated low byte buffer. After this has been done, the low
byte timer register can be read in the normal way. Note
that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer
and not the actual contents of the low byte timer register.
To achieve a maximum full range count of FFFFH, the
preload registers must first be cleared to all zeros. It
should be noted that after power-on, the preload register
will be in an unknown condition. Note that if the
Timer/Event Counter is switched off and data is written
to its preload registers, this data will be immediately written into the actual timer registers. However, if the
Timer/Event Counter is enabled and counting, any new
data written into the preload data registers during this
period will remain in the preload registers and will only
be written into the timer registers the next time an overflow occurs.
For the 16-bit Timer/Event Counter which has both low
byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be note
when using instructions to preload data into the low byte
timer register, namely TMRL, the data will only be
placed in a low byte buffer and not directly into the low
byte timer register. The actual transfer of the data into
the low byte timer register is only carried out when a
write to its associated high byte timer register, namely
TMRH, is executed. On the other hand, using instructions to preload data into the high byte timer register will
result in the data being directly written to the high byte
timer register. At the same time the data in the low byte
b 7
T M 1
T M 0
T O N
Timer Control Register - TMRC
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their control register, which has the
name TMRC. It is the Timer Control Register together
with its corresponding timer register that control the full
operation of the Timer/Event Counter. Before the
Timer/Event Counter can be used, it is essential that the
Timer Control Register is fully programmed with the
right data to ensure its correct operation, a process that
is normally carried out during program initialisation.
b 0
T E
T M R C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
E v e n t C
1 : c o u n
0 : c o u n
P u ls e W
1 : s ta rt
0 : s ta rt
o u n te r a c tiv e e d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
e s e le c t
t a c tiv e e d g e s e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g m o d e s
T M 1
T M 0
n o
0
0
e v
0
1
1
tim
0
1
1
p u
e le c t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter Control Register
Rev.1.30
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January 14, 2011
HT82A520R/HT82A620R
Configuring the Event Counter Mode
To choose which of the three modes the Timer/Event
Counter is to operate in, either in the timer mode, the
event counting mode or the pulse width measurement
mode, bits 7 and 6 of the Timer Control Register, which
are known as the bit pair TM1/TM0, must be set to the
required logic levels. The Timer/Event Counter on/off
bit, which is bit 4 of the Timer Control Register and
known as TON, provides the basic on/off control of the
Timer/Event Counter. Setting the bit high allows the
Timer/Event Counter to run, clearing the bit stops it running. If the Timer/Event Counter is in the event count or
pulse width measurement mode, the active transition
edge level type is selected by the logic level of bit 3 of
the Timer Control Register which is known as TE.
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be recorded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair, TM1/TM0, in
the Timer Control Register must be set to the correct
value as shown.
Control Register Operating Mode
Select Bits for the Event Counter Mode
In this mode, the Timer/Event Counter can be utilised to
measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode
Select bit pair, TM1 or TM0, in the Timer Control Register must be set to the correct value as shown.
Bit7 Bit6
1
0
1
In this mode, the external timer pin, TMR, is used as the
Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the
Timer Control Register have been setup, the enable bit
TON, which is bit 4 of the Timer Control Register, can be
set high to enable the Timer/Event Counter to run. If the
Active Edge Select bit TE, which is bit 3 of the Timer
Control Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a low
to high transition. If the Active Edge Select bit is high,
the counter will increment each time the external timer
pin receives a high to low transition. When it is full and
overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the Interrupt
Control Register, INTC0, is reset to zero.
Configuring the Timer Mode
Control Register Operating Mode
Select Bits for the Timer Mode
Bit7 Bit6
0
In this mode the internal clock, fSYS/4 is used as the internal clock for the Timer/Event Counter. After the other
bits in the Timer Control Register have been setup, the
enable bit TON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter
to run. Each time an internal clock cycle occurs, the
Timer/Event Counter increments by one. When it is full
and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the Interrupt
Control Register, INTC0, is reset to zero.
As the external timer pin is an independent pin and not
shared with an I/O pin, the only thing to ensure the timer
operate as an event counter is to ensure that the Operating Mode Select bits in the Timer Control Register
place the Timer/Event Counter in the Event Counting
Mode. It should be noted that in the event counting
mode, even if the microcontroller is in the Power Down
Mode, the Timer/Event Counter will continue to record
externally changing logic events on the timer input pin.
As a result when the timer overflows it will generate a
timer interrupt and corresponding wake-up source.
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+ 1
Timer Mode Timing Chart
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
Rev.1.30
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January 14, 2011
HT82A520R/HT82A620R
Configuring the Pulse Width Measurement Mode
until the enable bit is again set high by the program can
the timer begin further pulse width measurements. In
this way, single shot pulse measurements can be easily
made.
In this mode, the Timer/Event Counter can be utilised to
measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating
Mode Select bit pair, TM1 or TM0, in the Timer Control
Register must be set to the correct value as shown.
It should be noted that in this mode the Timer/Event
Counter is controlled by logical transitions on the external
timer pin and not by the logic level. When the Timer/Event
Counter is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue
counting. The interrupt can be disabled by ensuring that
the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register, INTC0, is reset to zero.
Control Register Operating Mode
Bit7 Bit6
Select Bits for the Pulse Width Measure1
1
ment Mode
In this mode the internal clock, fSYS/4 is used as the internal clock for the 16-bit Timer/Event Counters. After
the other bits in the Timer Control Register have been
setup, the enable bit TON, which is bit 4 of the Timer
Control Register, can be set high to enable the
Timer/Event Counter, however it will not actually start
counting until an active edge is received on the external
timer pin.
I/O Interfacing
The Timer/Event Counter, when configured to run in the
event counter or pulse width measurement mode, requires the use of an external pin for correct operation.
This is implemented by ensuring that the mode select bits
in the Timer/Event Counter control register, select either
the event counter or pulse width measurement mode.
If the Active Edge Select bit TE , which is bit 3 of the
Timer Control Register, is low, once a high to low transition has been received on the external timer pin, TMR,
the Timer/Event Counter will start counting until the external timer pin returns to its original high level. At this
point the enable bit will be automatically reset to zero
and the Timer/Event Counter will stop counting. If the
Active Edge Select bit is high, the Timer/Event Counter
will begin counting once a low to high transition has
been received on the external timer pin and stop counting when the external timer pin returns to its original low
level. As before, the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. It is important to note that in the Pulse Width
Measurement Mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the
other two modes the enable bit can only be reset to zero
under program control.
Programming Considerations
When configured to run in the timer mode, the instruction clock (system clock divided by 4) is used as the internal timer clock source for the two 16-bit timers and is
therefore synchronized with the overall operation of the
microcontroller. In this mode, when the appropriate
timer register is full, the microcontroller will generate an
internal interrupt signal directing the program flow to the
respective internal interrupt vector. For the pulse width
measurement mode, the instruction clock is also used
as the timer clock source but the timer will only run when
the correct logic condition appears on the external timer
input pin. As this is an external event and not synchronised with the internal timer clock, the microcontroller
will only see this external event when the next timer
clock pulse arrives. As a result there may be small differences in measured values requiring programmers to
take this into account during programming. The same
applies if the timer is configured to be in the event counting mode which again is an external event and not synchronised with the internal system or timer clock.
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the external timer
pin. As the enable bit has now been reset, any further
transitions on the external timer pin will be ignored. Not
E x te r n a l T im e r
P in In p u t
T O N
( w ith T E = 0 )
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
T im e r
+ 1
+ 2
+ 3
+ 4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart
Rev.1.30
20
January 14, 2011
HT82A520R/HT82A620R
register will be set. If the timer interrupt is enabled this
will in turn generate an interrupt signal. However irrespective of whether the timer interrupt is enabled or not,
a Timer/Event counter overflow will also generate a
wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter
is in the Event Counting Mode and if the external signal
continues to change state. In such a case, the
Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be
woken up from its Power-down condition. To prevent
such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the
HALT instruction to enter the Power Down Mode.
When the Timer/Event Counter is read or if data is written
to the preload registers, the clock is inhibited to avoid errors, however as this may result in a counting error, this
should be taken into account by the programmer. Care
must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer interrupt enable bits in the interrupt control
register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The
edge select, timer mode and clock source control bits in
timer control register must also be correctly set to ensure
the timer is properly configured for the required application. It is also important to ensure that an initial value is
first loaded into the timer register before the timer is
switched on; this is because after power-on the initial
value of the timer register is unknown. After the timer has
been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Note
that setting the timer enable bit high to turn the timer on,
should only be executed after the timer mode bits have
been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper
timer operation if executed as a single timer control register byte write instruction.
Timer Program Example
This program example shows how the Timer/Event
Counter registers are setup, along with how the interrupts are enabled and managed. Note how the
Timer/Event Counter is turned on, by setting bit 4 of the
Timer Control Register. The Timer/Event Counter can
be turned off in a similar way by clearing the same bit.
This example program sets the Timer/Event Counter
tobe in the timer mode, which uses the internal system
clock as the clock source.
When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control
org 04h
; USB interrupt vector
reti
org 08h
; external interrupt vector
reti
org 0ch
; Timer/Event Counter interrupt vector
jmp tmr0int
; jump here when Timer/Event Counter overflows
org 010h
; SPI interrupt vector
reti
:
org 20h
; main program
:
;internal Timer/Event Counter interrupt routine
tmrint:
:
; Timer/Event Counter main program placed here
:
reti
:
begin:
;setup Timer/Event
mov a,0e8h
mov tmrl,a
mov a,09bh
mov tmrh,a
mov a,080h
mov tmrc,a
mov a,009h
mov intc0,a
:
set tmrc.4
Rev.1.30
Counter registers
; setup low byte preload value for Timer/Event Counter
; low byte must be setup before high byte
; setup high byte preload value for Timer/Event Counter
;
; setup Timer control register TMRC
; Timer/Event Counter clock source is fSYS/4
; setup interrupt register
; enable master interrupt and timer interrupts
; start Timer/Event Counter _ note mode bits must be previously setup
21
January 14, 2011
HT82A520R/HT82A620R
Interrupts
to be executed, will be transferred onto the stack. The
Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next
instruction from this interrupt vector. The instruction at
this vector will usually be a JMP statement which will
jump to another section of program which is known as
the interrupt service routine. Here is located the code to
control the appropriate interrupt. The interrupt service
routine must be terminated with a RETI statement,
which retrieves the original Program Counter address
from the stack and allows the microcontroller to continue
with normal execution at the point where the interrupt
occurred.
Interrupts are an important part of any microcontroller
system. When an external interrupt pin transition or an
internal function such as a Timer/Event Counter overflow, an USB interrupt, or transmission or reception of
SPI data occurs, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their
respective needs. Each device contains a single external interrupt and several internal interrupts functions.
The external interrupt is controlled by the action of the
external interrupt pins, while the internal interrupts are
controlled by the Timer/Event Counter overflow, a USB
interrupt and SPI data transmission or reception.
Interrupt Registers
The various interrupt enable bits, together with their associated request flags, are shown in the accompanying
diagram with their order of priority.
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by the two interrupt control registers, which are located in the Data
Memory. By controlling the appropriate enable bits in
these registers each individual interrupt can be enabled
or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller.
The global enable flag if cleared to zero will disable all
interrupts.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Operation
A USB interrupt, Timer/Event Counter overflow, 8-bits of
data transmission or reception on either of the one SPI
interfaces or an active edge on the external interrupt pin
will all generate an interrupt request by setting their
corresponding request flag, if their appropriate interrupt
enable bit is set. When this happens, the Program
Counter, which stores the address of the next instruction
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
U S B In te rru p t
R e q u e s t F la g U S B F
E U I
E x te rn a l In te rru p t
R e q u e s t F la g E IF
E E I
T im e r /E v e n t C o u n te r O v e r flo w
In te r r u p t R e q u e s t F la g T F
E T I
S P I In te rru p t
R e q u e s t F la g S IF
E S II
E M I
P r io r ity
H ig h
In te rru p t
P o llin g
L o w
Interrupt Structure
Rev.1.30
22
January 14, 2011
HT82A520R/HT82A620R
b 7
T F
E IF
U S B F
E T I
E E I
E U I
b 0
E M I
IN T C 0 R e g is te r
M a s te r in te r r u p t g lo b a l e n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
U S B in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
E x te r n a l in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
U S B in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
E x te r n a l in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
F o r te s t m o d e u s e d o n ly
M u s t b e w r itte n a s " 0 " ; o th e r w is e m a y r e s u lt in u n p r e d ic ta b le o p e r a tio n
INTC0 Register
b 7
S IF
b 0
E S II
IN T C 1 R e g is te r
S P I S e r ia l In te r fa c e in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
S P I S e r ia l in te r fa c e d a ta tr a n s fe r r e d o r d a ta r e c e iv e d in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
N o t im p le m e n te d , r e a d a s " 0 "
INTC1 Register
Rev.1.30
23
January 14, 2011
HT82A520R/HT82A620R
Interrupt Priority
SPI Interrupt
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Priority
Vector
USB Interrupt
1
0004H
External Interrupt
2
0008H
Timer/Event Counter Overflow
Interrupt
3
000CH
For a SPI Interrupt to occur, the global interrupt enable
bit, EMI, and the corresponding SPI interrupt enable bit,
ESII must be first set. An actual SPI Interrupt will take
place when one of the two SPI interrupt request flags,
SIF is set, a situation that will occur when 8-bits of data
are transferred or received from either of the SPI interfaces. When the interrupt is enabled, the stack is not full
and an SPI interrupt occurs, a subroutine call to the SPI
interrupt vector at location 10H, will take place. When
the interrupt is serviced, the SPI interrupt request flag,
SIF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
SPI Interrupt
4
0010H
USB Interrupt
Interrupt Source
A USB interrupts will be triggered by the following USB
events, at which point the the related interrupt request
flag, USBF in the INTC0 register, will be set.
Suitable masking of the individual interrupts using the
interrupt registers can prevent simultaneous occurrences.
· Accessing the corresponding USB FIFO from the PC
External Interrupt
· A USB suspend signal from the PC
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, EEI,
must first be set. An actual external interrupt will take
place when the external interrupt request flag, EIF is set,
a situation that will occur when a high to low transition
appears on the interrupt pins. The external interrupt pin
is pin-shared with the I/O pins PA6 can only be configured as an external interrupt pin if the corresponding external interrupt enable bits in the interrupt control
register INTC0 have been set. The pins must also be
setup as inputs by setting the corresponding PAC.6 bits
in the port control register. When the interrupt is enabled, the stack is not full and a high to low transition appears on the external interrupt pin, a subroutine call to
the external interrupt vector at location 08H will take
place. When the interrupt is serviced, the external interrupt request flag, EIF will be automatically reset and the
EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor configuration
options on these pins will remain valid even if the pins
are used as external interrupt inputs.
· A USB resume signal from the PC
· A USB Reset signal
When the interrupt is enabled, the stack is not full and
the USB interrupt is active, a subroutine call to location
04H will occur. The interrupt request flag, USBF, and the
EMI bit will be cleared to disable other interrupts.
When PC Host accesses the FIFO of the device, the
corresponding request USR bit is set, and a USB interrupt is triggered. Therefore it can be determined which
FIFO has been accessed. When the interrupt has been
served, the corresponding bit should be cleared by the
program. When the device receive a USB Suspend signal from the Host PC, the suspend line, bit0 of USC, is
set and a USB interrupt is also triggered. Also when device receive a Resume signal from the Host PC, the resume line, bit3 of USC, is set and a USB interrupt is
triggered.
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt control register until the corresponding interrupt is serviced or until the request flag is
cleared by a software instruction.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ETI, must first be set. An actual
Timer/Event Counter interrupt will take place when the
Timer/Event Counter interrupt request flag, TF, is set, a
situation that will occur when the Timer/Event Counter
overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter overflow occurs, a
subroutine call to the timer interrupt vector at location
0CH , will take place. When the interrupt is serviced, the
timer interrupt request flag, TF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Rev.1.30
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode.
24
January 14, 2011
HT82A520R/HT82A620R
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing a
proper reset operation. In such cases it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
Only the Program Counter is pushed onto the stack. If
the contents of the accumulator or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents
should be saved in advance.
Reset and Initialisation
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
V D D
tR
S S T T im e - o u t
D D
S T D
In te rn a l R e s e t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
V D D
1 0 0 k W
R E S
0 .1 m F
V S S
Basic Reset Circuit
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F
1 0 0 k W
Reset Functions
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
0 .1 m F
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
V D D
R E S
1 0 k W
· Power-on Reset
Rev.1.30
0 .9 V
R E S
V S S
Enhanced Reset Circuit
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
25
January 14, 2011
HT82A520R/HT82A620R
· Watchdog Time-out Reset during Power Down
· RES Pin Reset
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point. Note that as the external reset pin
is also pin-shared with PA7, if it is to be used as a reset
pin, the correct reset configuration option must be selected.
0 .4 V
R E S
0 .9 V
D D
tR
S S T T im e - o u t
W D T T im e - o u t
D D
S T
WDT Time-out Reset during Power Down
Timing Chart
S T D
Reset Initial Conditions
In te rn a l R e s e t
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Power Down function or Watchdog Timer. The reset
flags are shown in the table:
RES Reset Timing Chart
· Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration
option. If the supply voltage of the device drops to
within a range of 0.9V~VLVR such as might occur when
changing the battery, the LVR will automatically reset
the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR
will ignore the low supply voltage and will not perform
a reset function. The actual VLVR value can be selected via configuration options.
L V R
S S T T im e - o u t
tR
TO PDF
0
RES reset during power-on
0
0
RES wake-up during Power Down
0
0
RES or LVR reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Note: ²u² stands for unchanged
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
S T D
Item
Low Voltage Reset Timing Chart
· Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
S S T T im e - o u t
RESET Conditions
0
In te rn a l R e s e t
tR
S T D
In te rn a l R e s e t
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer/Event
Counter
Timer Counter will be turned off
Prescaler
The Timer Counter Prescaler will
be cleared
Input/Output Ports I/O ports will be setup as inputs
WDT Time-out Reset during Normal Operation
Timing Chart
Rev.1.30
tS
S S T T im e - o u t
Stack Pointer
26
Stack Pointer will point to the top
of the stack
January 14, 2011
HT82A520R/HT82A620R
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller internal registers.
Reset
(Power-on)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
USB Reset
(Normal)
USB Reset
(HALT)
MP0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
MP1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
---- -111
---- -111
---- -111
---- -111
---- -111
---- -111
---- -uuu
Register
STATUS
--00 xxxx
--1u uuuu
--00 uuuu
--00 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
INTC0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
TMRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
TMRL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
TMRC
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
uu-u u---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PWM0DRL
0000 --00
0000 --00
0000 --00
0000 --00
uuuu --uu
0000 --00
0000 --00
PWM0DRH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PWMBR0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PWM1DRL
0000 --00
0000 --00
0000 --00
0000 --00
uuuu --uu
0000 --00
0000 --00
PWM1DRH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PWMBR1
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PWM2DRL
0000 --00
0000 --00
0000 --00
0000 --00
uuuu --uu
0000 --00
0000 --00
PWM2DRH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PWMBR2
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
ADRL(**)
xxxx ----
xxxx ----
xxxx ----
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH(**)
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR(**)
0100 0000
0100 0000
0100 0000
0100 0000
0100 0000
0100 0000
0100 0000
ACSR(**)
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
USB_STAT
--xx 0000
--xx 0000
--xx 0000
--xx 0000
--xx 0000
--xx 0000
--xx 0000
UINT
0000 1111
0000 uuuu
0000 1111
0000 1111
0000 uuuu
0000 1111
0000 1111
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
USC
1000 0000
uuuu xuux
1000 x00x
1000 x00x
uuuu xuux
1000 0000
1000 0000
USR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
00uu 0000
00uu 0000
Rev.1.30
27
January 14, 2011
HT82A520R/HT82A620R
Reset
(Power-on)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
USB Reset
(Normal)
USB Reset
(HALT)
UCC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0uu0 u000
0uu0 u000
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
STALL
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
SIES
0000 0000
uuxx xxuu
0000 0000
0000 0000
uuxx xxuu
0u00 u000
0u00 u000
MISC
0000 0000
xxuu uuuu
0000 0000
0000 0000
xxuu uuuu
0000 0000
0000 0000
UFIEN
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
FIFO0
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
FIFO1
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
FIFO2
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
FIFO3
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
UFOEN
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
UFC0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
UFC1
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
USVC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
SBCR
0110 0000
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
uuuu uuuu
SBDR
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
SPIR
---- 0000
---- 0000
---- 0000
---- 0000
---- 0000
---- 0000
---- 0000
Register
Note:
²*² means ²warm reset², ²-² not implemented
²u² means ²unchanged², ²x² means ²unknown²
²**² for HT82A620R
Rev.1.30
28
January 14, 2011
HT82A520R/HT82A620R
Oscillator
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required.
Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the microcontroller
to as low a value as possible, perhaps only in the order
of several micro-amps, there are other considerations
which must also be taken into account by the circuit designer if the power consumption is to be minimised.
The HT82A520R/HT82A620R can operate with 6MHz
or 12MHz system clocks. In order to make sure that the
USBSIE functions properly, the user should correctly
configure the SYSCLK bit of the UCC Register. The default system clock is 12MHz
Special attention must be made to the I/O pins on the
device. All high-impedance input pins must be connected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. Care must also be
taken with the loads, which are connected to I/O pins,
which are setup as outputs. These should be placed in a
condition in which minimum current is drawn or connected only to external circuits that do not draw current,
such as other CMOS inputs.
O S C 1
O S C 2
Crystal Oscillator
Power Down Mode and Wake-up
If the configuration options have enabled the Watchdog
Timer internal oscillator then this will continue to run
when in the Power Down Mode and will thus consume
some power. For power sensitive applications it may be
therefore preferable to use the system clock source for
the Watchdog Timer. If any I/O pins are configured as
A/D analog inputs using the channel configuration bits in
the ADCR register, then the A/D converter will be turned
on and a certain amount of power will be consumed. It
may be therefore desirable before entering te Power
Down Mode to ensure that the A/D converter is powered
down by ensuring that any A/D input pins are setup as
normal logic inputs with pull-high resistors.Note: A/D
function for HT82A620R.
Power Down Mode
All of the Holtek microcontrollers have the ability to enter
a Power Down Mode. When the device enters this
mode, the normal operating current, will be reduced to
an extremely low standby current level. This occurs because when the device enters the Power Down Mode,
the system oscillator is stopped which reduces the
power consumption to extremely low levels, however,
as the device maintains its present internal condition, it
can be woken up at a later stage and continue running,
without requiring a full reset. This feature is extremely
important in application areas where the microcontroller
must have its power supply constantly maintained to
keep the device in a known condition but where the
power supply capacity is limited such as in battery applications.
Wake-up
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
Entering the Power Down Mode
· An external reset
There is only one way for the device to enter the Power
Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is
executed, the following will occur:
· An external falling edge on any of the I/O pins
· A system interrupt
· A WDT overflow
· The system oscillator will stop running and the appli-
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
cation program will stop at the ²HALT² instruction.
· The Data Memory contents and registers will maintain
their present condition.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
oscillator. The WDT will stop if its clock source originates from the system clock.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Rev.1.30
29
January 14, 2011
HT82A520R/HT82A620R
Each pins on Port A or any nibble on the other ports can be
setup via an individual configuration option to permit a
negative transition on the pin to wake-up the system.
When a Port pins wake-up occurs, the program will resume execution at the instruction following the ²HALT² instruction.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack
is full, in which case the program will resume execution at
the instruction following the ²HALT² instruction. In this situation, the interrupt which woke-up the device will not be
immediately serviced, but will rather be serviced later
when the related interrupt is finally enabled or when a
stack level becomes free. The other situation is where the
related interrupt is enabled and the stack is not full, in
which case the regular interrupt response takes place. If
an interrupt request flag is set to ²1² before entering the
Power Down Mode, the wake-up function of the related interrupt will be disabled.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such
as electrical noise. It operates by providing a device reset
when the WDT counter overflows. The WDT clock is supplied by one of two sources selected by configuration option: its own self-contained dedicated internal WDT
oscillator, or the instruction clock which is the system clock
divided by 4. Note that if the WDT configuration option has
been disabled, then any instruction relating to its operation will result in no operation.
The internal WDT oscillator has an approximate period of
31ms at a supply voltage of 5V. If selected, it is first divided
by 256 via an 8-stage counter to give a nominal period of
8ms. Note that this period can vary with VDD, temperature
and process variations. For longer WDT time-out periods
the WDT prescaler can be utilized. By writing the required
value to bits 0, 1 and 2 of the WDTS register, known as
No matter what the source of the wake-up event is, once a WS0, WS1 and WS2, longer time-out periods can be
wake-up situation occurs, a time period equal to 1024 sys- achieved. With WS0, WS1 and WS2 all equal to 1, the ditem clock periods will be required before normal system vision ratio is 1:128 which gives a maximum time-out peoperation resumes. However, if the wake-up has origi- riod of about 1s.
nated due to an interrupt, the actual interrupt subroutine A configuration option can select the instruction clock,
execution will be delayed by an additional one or more cy- which is the system clock divided by 4, as the WDT clock
cles. If the wake-up results in the execution of the next in- source instead of the internal WDT oscillator. If the instrucstruction following the ²HALT² instruction, this will be tion clock is used as the clock source, it must be noted that
executed immediately after the 1024 system clock period when the system enters the Power Down Mode, as the
delay has ended.
system clock is stopped, then the WDT clock source will
also be stopped. Therefore the WDT will lose its protecting
C L R W D T 1 F la g
C L R W D T 2 F la g
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS
Y S
/4
W D T O s c illa to r
C L R
W D T C lo c k S o u r c e
C o n fig u r a tio n O p tio n
8 - b it C o u n te r
(¸ 2 5 6 )
W D T C lo c k S o u r c e
C L R
7 - b it P r e s c a le r
W S 0 ~ W S 2
8 -to -1 M U X
W D T T im e - o u t
Watchdog Timer
b 7
W S 2
W S 1
b 0
W S 0
W D T S R e g is te r
W D T p r e s c a le r r a te s e le c t
W S 2
W S 1
W S 0
W D T
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
:1
R a te
:2
:4
:8
:1 6
:3 2
:6 4
:1 2 8
N o t u s e d
Watchdog Timer Register
Rev.1.30
30
January 14, 2011
HT82A520R/HT82A620R
PWM Registers
purposes. In such cases the system cannot be restarted
by the WDT and can only be restarted using external
signals. For systems that operate in noisy environments, using the internal WDT oscillator is therefore the
recommended choice.
Three register, located in the Data Memory are assigned
to each Pulse Width Modulator output and are known as
the PWM registers. It is in each register pair that the
12-bit value, which represents the overall duty cycle of
one modulation cycle of the output waveform, should be
placed. The PWM registers also contain the enable/disable control bit for the PWM outputs. To increase the
PWM modulation frequency, each modulation cycle is
modulated into sixteen individual modulation
sub-sections, known as the 8+4 mode. Note that it is
only necessary to write the required modulation value
into the corresponding PWM register as the subdivision
of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware.
Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. However,
if the system is in the Power Down Mode, when a WDT
time-out occurs, only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT and the WDT prescaler.
The first is an external hardware reset, which means a
low level on the RES pin, the second is using the watchdog software instructions and the third is via a ²HALT² instruction.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the single ²CLR WDT² instruction while the second is to use
the two commands ²CLR WDT1² and ²CLR WDT2². For
the first option, a simple execution of ²CLR WDT² will
clear the WDT while for the second option, both ²CLR
WDT1² and ²CLR WDT2² must both be executed to
successfully clear the WDT. Note that for this second
option, if ²CLR WDT1² is used to clear the WDT, successive executions of this instruction will have no effect,
only the execution of a ²CLR WDT2² instruction will
clear the WDT. Similarly, after the ²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1²
instruction can clear the Watchdog Timer.
This method of dividing the original modulation cycle
into a further 16 sub-cycles enables the generation of
higher PWM frequencies, which allow a wider range of
applications to be served. As long as the periods of the
generated PWM pulses are less than the time constants
of the load, the PWM output will be suitable as such long
time constant loads will average out the pulses of the
PWM output. The difference between what is known as
the PWM cycle frequency and the PWM modulation frequency should be understood.
As the PWM clock is defined by register PWMBR and
the system clock fSYS or fSYS/4 (chosen via the PWM_S
bit), and as the PWM value is 12-bits wide, the overall
PWM cycle frequency ( fPWM ) as the following equation
and the corresponding PWM modulation frequency for
8+4 mode is fPWM /256 .
Pulse Width Modulator
1
, when PWM_S=0
(1/fSYS)x(PWMBRn+ 1)
1
fPWM=
, when PWM_S=1
(4/fSYS)x(PWMBRn+ 1)
fPWM=
The device contains three Pulse Width Modulation
PWM outputs. Useful for such applications such as motor speed control, the PWM function provides an output
with a variable frequency, and with a duty cycle that can
be varied by setting particular values into the corresponding register pair.
Channel
1
PWM
Mode
8+4
Output
Pin
Register
Names
PA4
PWM0DRL~
PWM0DRH
2
8+4
PA5
PWM1DRL~
PWM1DRH
3
8+4
PB0
PWM2DRL~
PWM2DRH
Rev.1.30
where PWMBRn=0~255 and f SYS may be 6MHz,
12MHz , n=0~2 , according register whether it is PWM0,
PWM1 or PWM2
31
PWM
Modulation
Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
fPWM/256
fPWM/4096
(PWM register
value)/4096
January 14, 2011
HT82A520R/HT82A620R
8+4 PWM Mode Modulation
PWM Output Control
Each full PWM cycle, as it is 12-bits wide, has 4096 clock
periods. However, in the 8+4 PWM mode, each PWM cycle is subdivided into sixteen individual sub-cycles known
as modulation cycle 0 ~ modulation cycle 15, denoted as
²i² in the table. Each one of these sixteen sub-cycles contains 256 clock cycles. In this mode, a modulation frequency increase of sixteen is achieved. The 12-bit PWM
register value, which represents the overall duty cycle of
the PWM waveform, is divided into two groups. The first
group which consists of bit4~bit11 is denoted here as the
DC value. The second group which consists of bit0~bit3
is known as the AC value. In the 8+4 PWM mode, the
duty cycle value of each of the two modulation sub-cycles
is shown in the following table.
The three outputs, PWM0, PWM1, and PWM2 are
shared with pins PA4, PA5 and PB0. To operate as a
PWM output and not as an I/O pin, bit 0 of the relevant
PWM low byte register bit must be set high. A zero must
also be written to the corresponding bit in the PAC and
PBC port control register, to ensure that the PWM0 output pin is setup as an output. After these two initial steps
have been carried out, and of course after the required
PWM 12-bit value has been written into the PWM register pair register, setting the corresponding bit in the PA
and PB data register high will enable the PWM data to
appear on the pin. Writing a zero to the bit will disable
the PWM output function and force the output low. In this
way, the Port A and Port B data output register bits, can
also be used as an on/off control for the PWM function.
Note that if the enable bit in the PWM register is set high
to enable the PWM function, but if the corresponding bit
in the PAC and PBC control register is high to configure
the pin as an input, then the pin can still function as a
normal input line, with pull-high resistor selections.
Parameter
Modulation cycle i
(i=0~15)
AC (0~15)
DC (Duty Cycle)
i<AC
DC+1
256
i³AC
DC
256
8+4 Mode Modulation Cycle Values
The accompanying diagram illustrates the waveforms
associated with the 8+4 mode of PWM operation. It is
important to note how the single PWM cycle is subdivided into 16 individual modulation cycles, numbered
0~15 and how the AC value is related to the PWM value.
PWM Programming Example
The following sample program shows how the output is setup and controlled.
mov
mov
clr
clr
set
set
:
:
clr
a,64h
pwm0h,a
pwm0l
pac.4
pwm0en
pa.4
:
:
pa.4
Rev.1.30
;
;
;
;
;
;
setup PWM0 value to 1600 decimal which is 640H
setup PWM0H register value
setup PWM0L register value
setup pin PA4 as an output
set the PWM0 enable bit
Enable the PWM0 output
; PWM0 output disabled - PA4 will remain low
32
January 14, 2011
HT82A520R/HT82A620R
fP
W M
[P W M ] = 1 6 0 0
P W M
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 1 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 1 /2 5 6
1 0 1 /2 5 6
1 0 1 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 1 /2 5 6
1 0 0 /2 5 6
1 0 1 /2 5 6
[P W M ] = 1 6 0 1
P W M
[P W M ] = 1 6 0 2
P W M
[P W M ] = 1 6 1 5
P W M
1 0 1 /2 5 6
P W M
1 0 1 /2 5 6
m o d u la tio n p e r io d : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
1 0 1 /2 5 6
M o d u la tio n c y c le 1
M o d u la tio n c y c le 2
c y c le : 4 0 9 6 /fP
P W M
M o d u la tio n c y c le 1 5
M o d u la tio n c y c le 0
W M
8+4 PWM Mode
P W M 0 D R H ~ P W M 2 D R H
H ig h B y te R e g is te r s
b 7
1 1
1 0
9
8
7
6
5
P W M 0 D R L ~ P W M 2 D R L
L o w B y te R e g is te r s
b 0
4
b 7
3
2
1
0
P W M _ S
b 0
P W M _ E N
P W M R e g is te r s
P W M O n /O ff C o n tro l
1 : P W M e n a b le
0 : I/O p in e n a b le
P W M n b a s e p e r io d r e g is te r fr e q u e n c y s o u r c e
1 : fS Y S /4
0 : fS Y S ( d e fa u lt)
N o t im p le m e n te d , r e a d a s " 0 "
P W M A C
b its 0 ~ 3
V a lu e
P W M D C V a lu e
b its 4 ~ 1 1
PWM Register Pairs
Bit
R/W
7~0
R/W
Description
Used to define the base period of the PWM
Range =1 ~ 256 ´ (1/fSYS or 4/fSYS chosen via the PWM_S bit)
where PWMBRn=0~255 (n= 0~2)
PWM Base Period Register PWMBR0 ~ PWMBR2
Rev.1.30
33
January 14, 2011
HT82A520R/HT82A620R
Analog to Digital Converter - HT82A620R
The need to interface to real world analog signals is a
common requirement for many electronic systems.
However, to properly process these signals by a
microcontroller, they must first be converted into digital
signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the
need for external components is reduced significantly
with the corresponding follow-on benefits of lower costs
and reduced component space requirements.
A/D Converter Control Register - ADCR
A/D Overview
One section of this register contains the bits
ACS3~ACS0 which define the channel number. As each
of the devices contains only one actual analog to digital
converter circuit, each of the individual analog inputs
must be routed to the converter. It is the function of the
ACS3~ACS0 bits in the ADCR register to determine
which analog channel is actually connected to the internal A/D converter.
To control the function and operation of the A/D converter, control registers known as ADCR and ADSR are
provided. These 8-bit registers define functions such as
the selection of which analog channel is connected to
the internal A/D converter, which pins are used as analog inputs and which are used as normal I/Os as well as
controlling the start function and monitoring the A/D converter end of conversion status.
The device contains a multi-channel channel analog to
digital converter which can directly interface to external
analog signals, such as that from sensors or other control signals and convert these signals directly into an
12-bit digital value. The number of available channels
depends upon which package type is chosen.
The A/D block diagram shows the overall internal structure of the A/D converter, together with its associated
registers.
The START bit in the ADCR register is used to start and
reset the A/D converter. When the microcontroller sets
this bit from low to high and then low again, an analog to
digital conversion cycle will be initiated. When the
START bit is brought from low to high but not low again,
the EOCB bit in the ADCR register will be set to a ²1²
and the analog to digital converter will be reset. It is the
START bit that is used to control the overall on/off operation of the internal analog to digital converter.
A/D Converter Data Registers - ADRL, ADRH
The device, which contain a single12-bit A/D converter,
requires two data registers, known as ADRL and ADRH.
After the conversion process takes place, these registers can be directly read by the microcontroller to obtain
the digitised conversion value.
In the following tables, D0~D7 are the A/D conversion
data result bits.
Register
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
ADRL
D3
D2
D1
D0
¾
¾
¾
¾
ADRH
D11 D10 D9
D8
D7
D6
D5
D4
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is complete. This bit will be automatically set to ²0² by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
Note: D11~D0 is the A/D conversion result data bit
MSB~LSB.
A/D Data Register
A D C S o u rc e
fS Y S /3 , fS Y S /6 ,
fS Y S /8 , fS Y S /1 6
C lo c k D iv id e
R a tio
A C S R R e g is te r
¸ N
V
P B 0 /A N 0 ~
P B 7 /A N 7
P C R 0 ~ P C R 3
P in C o n fig u r a tio n
B its
A /D
r e fe r e n c e v o lta g e
A D R L
A D C
P C 0 /A N 8 ~
P C 7 /A N 1 5
A D S R
R e g is te r
R E F
A D C S 0 ~ A D C S 3
C h a n n e l S e le c t
B its
S T A R T
A D R H
E O C B
A /D D a ta
R e g is te r s
A D C R
R e g is te r
S ta r t B it E n d o f
C o n v e r s io n B it
A/D Converter Structure
Rev.1.30
34
January 14, 2011
HT82A520R/HT82A620R
b 7
S T A R T E O C B
A C S 3
A C S 2
A C S 1
b 0
A C S 0
A D C R
R e g is te r
S e le c t A /D
A
A C S 3
0
0
0
0
:
:
1
c h a n n e l
C S 2
A C S 1
0
0
0
0
0
1
0
1
:
:
:
:
1
1
A C S 0
0
1
0
1
:
:
1
: A N
: A N
: A N
: A N
:
:
: A N
0
1
2
3
1 5
N o t im p le m e n te d , r e a d a s " 0 "
E n d o f A /D c o n v e r s io n fla g
1 : n o t e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n w a itin g o r in p r o g r e s s
0 : e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n e n d e d
S ta r t th e A /D c o n v e r s io n
0 ® 1 ® 0 : S ta rt
0 ® 1 : R e s e t A /D c o n v e rte r a n d s e t E O C B to "1 "
A/D Converter Control Register
²1111² or higher, then all 16 pins, namely AN0~ AN15 will
all be set as analog inputs. Note that if the PCR3~PCR0
bits are all set to zero, then all the Port B and Port C pins
will be setup as normal I/Os and the internal A/D converter circuitry will be powered off to reduce the power
consumption.
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detecting the end of an A/D conversion cycle.
A/D Converter Clock Source Register - ACSR
The clock source for the A/D converter, which originates
from the system clock fSYS, is first divided by a division
ratio, the value of which is determined by the ADCS1
and ADCS0 bits in the ACSR register.
Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS1 and ADCS0, there are
some limitations on the maximum A/D clock source speed
that can be selected. As the minimum value of permissible
A/D clock period, tAD, is 0.5ms, care must be taken for system clock speeds in excess of 4MHz. For system clock
speeds in excess of 4MHz, the ADCS1 and ADCS0 bits
should not be set to ²00². Doing so will give A/D clock peri-
The ACSR control register also contains the
PCR3~PCR0 bits which determine which pins on Port B
and Port C are used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins.
If the 4-bit address on PCR3~PCR0 has a value of
b 7
T E S T
P C R 3
P C R 2
P C R 1
P C R 0
A D O N
b 0
A D C S 1 A D C S 0
A C S R R e g is te r
S e le c t A /D c o n v e r te r
A D C S 0
A D C S 1
:
0
0
:
1
0
:
0
1
:
1
1
0 : d is a b le ( d e fa u lt)
1 : e n a b le
P B a n d P C A /D
P C R 2
P C R 3
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
c lo c k s o u r c e
s y s
s y s
s y s
s y s
te m
te m
te m
te m
c h a n n e l c o n
P
P C R 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
F o r te s t m o d e u s e o n ly
c lo
c lo
c lo
c lo
c k /3
c k /6
c k /8
c k /1 6
fig u r a tio n
C R 0
0
:
1
:
0
:
:
1
0
:
:
1
0
:
1
:
0
:
1
:
0
:
1
:
0
:
1
:
0
:
1
:
P B a n
P B 0 a
P B 0 ~
P B 0 ~
P B 0 ~
P B 0 ~
P B 0 ~
P B 0 ~
P B 0 ~
P B 0 ~
P B 0 ~
P B 0 ~
P B 0 ~
P B 0 ~
P B 0 ~
P B 0 ~
d P
s A
P B 1
P B 2
P B 3
P B 4
P B 5
P B 6
P B 7
P B 7
P B 7
P B 7
P B 7
P B 7
P B 7
P B 7
C A
N 0
a s
a s
a s
a s
a s
a s
a s
, P
, P
, P
, P
, P
, P
, P
C
C
C
C
C
C
C
/D c h a n n e l - a ll o ff
A N 0 ~
A N 0 ~
A N 0 ~
A N 0 ~
A N 0 ~
A N 0 ~
A N 0 ~
0 a s
0 ~ P C
0 ~ P C
0 ~ P C
0 ~ P C
0 ~ P C
0 ~ P C
A N 1
A N 2
A N 3
A N 4
A N 5
A N 6
A N 7
A N 0
1 a
2 a
3 a
4 a
5 a
7 a
~ A N
s A N
s A N
s A N
s A N
s A N
s A N
8
0 ~ A
0 ~ A
0 ~ A
0 ~ A
0 ~ A
0 ~ A
N 9
N 1 0
N 1 1
N 1 2
N 1 3
N 1 5
A/D Converter Clock Source Register
Rev.1.30
35
January 14, 2011
HT82A520R/HT82A620R
ods that are less than the minimum A/D clock period which
may result in inaccurate A/D conversion values. Refer to
the following table for examples, where values marked
with an asterisk * show where, depending upon the device, special care must be taken, as the values may be
less than the specified minimum A/D Clock Period
first be set high and then immediately cleared to zero.
This will ensure that the EOCB flag is correctly set to a
high condition.
Summary of A/D Conversion Steps
The following summarises the individual steps that
should be executed in order to implement an A/D conversion process.
A/D Input Pins
All of the A/D analog input pins are pin-shared with the
I/O pins on Port B and Port C. Bits PCR3~PCR0 in the
ACSR register, determine whether the input pins are
setup as normal Port B and Port C input/output pins or
whether they are setup as analog inputs. In this way, pins
can be changed under program control to change their
function from normal I/O operation to analog inputs and
vice versa. Pull-high resistors, which are setup through
configuration options, apply to the input pins only when
they are used as normal I/O pins, if setup as A/D inputs
the pull-high resistors will be automatically disconnected.
Note that it is not necessary to first setup the A/D pin as
an input in the PBC or PCC port control register to enable
the A/D input as when the PCR3~PCR0 bits enable an
A/D input, the status of the port control register will be
overridden.
· Step 1
Select the required A/D conversion clock by correctly
programming bits ADCS1 and ADCS0 in the ACSR
register.
· Step 2
Select which channel is to be connected to the internal
A/D converter by correctly programming the ACS3~
ACS0 bits which are also contained in the ADCR register.
· Step 3
Select which pins on Port B and Port C are to be used
as A/D inputs and configure them as A/D input pins by
correctly programming the PCR3~PCR0 bits in the
ACSR register.
· Step 4
The analog to digital conversion process can now be
initialised by setting the START bit in the ADCR register from ²0² to ²1² and then to ²0² again. Note that this
bit should have been originally set to ²0².
Initialising the A/D Converter
The internal A/D converter must be initialised in a special way. Each time the Port B and Port C A/D channel
selection bits are modified by the program, the A/D converter must be re-initialised. If the A/D converter is not
initialised after the channel selection bits are changed,
the EOCB flag may have an undefined value, which may
produce a false end of conversion signal. To initialise the
A/D converter after the channel selection bits have
changed, then, within a time frame of one to ten instruction cycles, the START bit in the ADCR register must
· Step 5
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register
can be polled. The conversion process is complete
when this bit goes low. When this occurs the A/D data
registers ADR can be read to obtain the conversion
value. As an alternative method if the interrupts are
enabled and the stack is not full, the program can wait
for an A/D interrupt to occur.
S T A R T b it s e t h ig h w ith in o n e to te n in s tr u c tio n c y c le s a fte r th e P C R 0 ~ P C R 2 b its c h a n g e s ta te
S T A R T
A /D
E O C B
8 tA
P C R 3 ~
P C R 0
A C S 3 ~
A C S 0
s a m p lin g tim e
A /D
0 0 0 B
0 0 0 B
8 tA
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
tA
D C
A /D c o n v e r s io n tim e
Y S
D
1 0 0 B
0 1 0 B
1 : D e fin e P B , P C c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
c lo c k m u s t b e fS
s a m p lin g tim e
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
A /D
A /D
D
0 1 1 B
P o w e r-o n
R e s e t
N o te :
s a m p lin g tim e
8 tA
D
/3 , fS
Y S
/6 , fS
Y S
/8 , fS
Y S
0 0 0 B
1 . P o rt B a n d P o rt C s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
D o n 't c a r e
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA
D C
c o n v e r s io n tim e
E n d o f A /D
c o n v e r s io n
A /D
tA
D C
c o n v e r s io n tim e
/1 6
A/D Conversion Timing
Rev.1.30
36
January 14, 2011
HT82A520R/HT82A620R
Note:
When checking for the end of the conversion process, if the method of polling the EOCB bit in the
ADCR register is used, the interrupt enable step
above can be omitted.
pulsing the START bit in the ADCR register immediately
after the channel selection bits have changed state. The
exception to this is where the channel selection bits are all
cleared, in which case the A/D converter is not required to
be re-initialised.
The A/D conversion timing diagram shows graphically the
various stages involved in an analog to digital conversion
A/D Programming Example
process and its associated timing.
The following two programming examples illustrate how to
The setting up and operation of the A/D converter function
setup and implement an A/D conversion. In the first examis fully under the control of the application program as
ple, the method of polling the EOCB bit in the ADCR registhere are no configuration options associated with the A/D
ter is used to detect when the conversion cycle is
converter. After an A/D conversion process has been initicomplete, whereas in the second example, the A/D interated by the application program, the microcontroller interrupt is used to determine when the conversion is comnal hardware will begin to carry out the conversion, during
plete.
which time the program can continue with other functions.
The time taken for the A/D conversion is 16tAD where tAD is A/D Transfer Function
equal to the A/D clock period.
As the device contain a 12-bit A/D converter, its full-scale
converted digitised value is equal to FFFH. Since the
Programming Considerations
full-scale analog input value is equal to the VDD voltage,
When programming, special attention must be given to
this gives a single bit analog input value of VDD/4096. The
the A/D channel selection bits in the ADSR register. If
diagram show the ideal transfer function between the anathese bits are all cleared to zero no external pins will be
log input value and the digitised output value for the A/D
selected for use as A/D input pins allowing the pins to be
converter.
used as normal I/O pins. When this happens the power
supplied to the internal A/D circuitry will be reduced result- Note that to reduce the quantisation error, a 2.5 LSB offset
ing in a reduction of supply current. This ability to reduce is added to the A/D Converter input. Except for the digitpower by turning off the internal A/D function by clearing ised zero value, the subsequent digitised values will
the A/D channel selection bits may be an important con- change at a point 2.5 LSB below where they would
change without the offset, and the last full scale digitised
sideration in battery powered applications.
value will change at a point 2.5 LSB below the VDD level.
Another important programming consideration is that
when the A/D channel selection bits change value, the
A/D converter must be re-initialised. This is achieved by
Example: using an EOCB polling method to detect the end of conversion
clr EADI
; disable ADC interrupt
mov a,00011001B
mov acsr,a
; setup the ACSR register to select fsys/6 as the A/D clock
; setup the ACSR register to configure Port PB0~PB2 as A/D
; Inputs
mov a,00000000B
mov adcr,a
; setup the ADCR register and select AN0 to be connected to
; the A/D converter
; As the Port B and Port C channel bits have changed the
; following START signal (0®1®0) must be issued within
; 10 instruction cycles
Set ADON
; A/D on
Start_conversion:
clr START
set START
; reset A/D
clr START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end
; of A/D conversion
jmp polling_EOC
; continue polling
mov a,ADR
; read conversion result value
mov adrl_buffer,a
; save result to user defined register
:
jmp start_conversion
; start next A/D conversion
Rev.1.30
37
January 14, 2011
HT82A520R/HT82A620R
1 .5 L S B
F F F H
F F E H
F F D H
A /D C o n v e r s io n
R e s u lt
0 .5 L S B
0 3 H
0 2 H
0 1 H
0
1
2
3
4 0 9 3 4 0 9 4
A n a lo g In p u t V o lta g e
(
4 0 9 5 4 0 9 6
V D D
)
4 0 9 6
Ideal A/D Transfer Function
SPI Serial Interface
The device includes one SPI Serial Interfaces. The SPI interface is a full duplex serial data link, originally designed
by Motorola, which allows multiple devices connected to
the same SPI bus to communicate with each other. The
devices communicate using a master/slave technique
where only the single master device can initiate a data
transfer. A simple four line signal bus is used for all communication.
SPI Interface Communication
Four lines are used for each function. These are, SDI Serial Data Input, SDO - Serial Data Output, SCK - Serial
Clock and SCS - Slave Select. Note that the condition of
the Slave Select line is conditioned by the CSEN bit in the
SBCR control register. If the CSEN bit is high then the
SCS line is active while if the bit is low then the SCS line
will be in a floating condition. The accompanying timing diagram depicts the basic timing protocol of the SPI bus.
SPI Registers
After Power on, the contents of the SBDR register will be
in an unknown condition while the SBCR register will default to the condition below:
CKS
M1
M0
SBEN
MLS
CSEN
WCOL
TRF
0
1
1
0
0
0
0
0
Note that data written to the SBDR register will only be
written to the TXRX buffer, whereas data read from the
SBDR register will actual be read from the register.
SPI Bus Enable/Disable
To enable the SPI bus, the SBEN bit should be set high,
then wait for data to be written to the SBDR (TXRX buffer)
register. For the Master Mode, after data has been written
to the SBDR (TXRX buffer) register then transmission or
reception will start automatically. When all the data has
been transferred, the TRF bit should be set. For the Slave
Mode, when clock pulses are received on SCK, data in the
TXRX buffer will be shifted out or data on SDI will be
shifted in.
There are three registers for control of the SPI Interface.
These are the SBCR register which is the control register To Disable the SPI bus SCK, SDI, SDO, SCS should be
and the SBDR which is the data register and SPIR register I/O mode.
which is the SPI mode control register. The SBCR register
is used to setup the required setup parameters for the SPI
bus and also used to store associated operating flags,
while the SBDR register is used for data storage.
The SPIR register is used to select SPI mode, clock polarity edge selection and SPI enable or disable selection.
Rev.1.30
38
January 14, 2011
HT82A520R/HT82A620R
Bit No.
0
Label
R/W
SPI_CPOL
Function
R/W
1: clock polarity rising
0: clock polarity falling (default falling)
1
SPI_MODE
R/W
0: SPI output the data in the rising edge(polarity=1) or falling edge (polarity=0);
SPI read data in the in the falling edge(polarity=1) or rising edge (polarity=0);
(default)
1: SPI first output the data immediately after the SPI is enable. And SPI output
the data in the falling edge(polarity=1) or rising edge (polarity=0); SPI read data
in the in the rising edge(polarity=1) or falling edge (polarity=0)
2
SPI_CSEN
R/W
1: SPI_CSEN Enable , this bit is used to enable/disable software CSEN function
0: SPI_CSEN disable, SCS define as GPIO (default disable)
3
SPI_EN
R/W
This bit control the shared PIN (SCS, SDI, SDO and SCK) is SPI or GPIO mode
0: I/O mode (default)
1: SPI mode
Reserved bit
R/W
Always 0
7~4
SPIR Register
D a ta B u s
S B D R
( R e c e iv e d D a ta R e g is te r )
D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
M
X
M L S
In te r n a l B a u d R a te C lo c k
S C K
E N
C lo c k P o la r ity
a n d , s ta rt
a n d , s ta rt
S D O
U
S D O
S B E N
M
U
X
M
B u ffe r
S D I
U
X
M a s te r o r S la v e
S B E N
a n d , s ta rt
E N
T R F
C 0 C 1 C 2
In te r n a l B u s y F la g
S B E N
A N D
W r ite S B D R
W r ite S B D R
W r ite S B D R
W C O L F la g
E n a b le /D is a b le
S C S
M a s te r o r S la v e
S B E N
C S E N
SPI Block Diagram
Note:
WCOL: set by SPI cleared by users
CSEN: enable/disable chip selection function pin
master mode: 1/0 = with/without SCS output function
Slave mode: 1/0 = with/without SCS input control function
SBEN: enable/disable serial bus (0: initialise all status flags)
when SBEN=0, all status flags should be initialised
when SBEN=1, all SPI related function pins should stay at floating state
TRF: 1 = data transmitted or received, 0= data is transmitting or still not received
CPOL: I/O = clock polarity rising/falling edge: For SPIR Register.
If clock polarity set to rising edge (SPI_CPOL=1), serial clock timing follow SCK, otherwise (SPI_CPOL=0)
SCK is the serial clock timing.
Rev.1.30
39
January 14, 2011
HT82A520R/HT82A620R
Step 6. Check the WCOL bit, if set high then a
collision error has occurred so return to step5.
If equal to zero then go to the following step.
Step 7. Check the TRF bit or wait for an SPI serial
bus interrupt.
SPI Operation
All communication is carried out using the 4-line interface for both Master or Slave Mode. The timing diagram
shows the basic operation of the bus.
The CSEN bit in the SBCR register controls the SCSB
line of the SPI interface. Setting this bit high, will enable
the SPI interface by allowing the SCS line to be active,
which can then be used to control the SPI inteface. If the
CSEN bit is low, the SCS line will be in a floating condition and can therefore not be used for control of the SPI
interface. The SBEN bit in the SBCR register must also
be high which will place the SDI line in a floating condition and the SDO line high. If in the Master Mode the
SCK line will be either high or low depending upon the
clock polarity configuration option. If in the Slave Mode
the SCK line will be in a floating condition. If SBEN is low
then the bus will be disabled and SCS, SDI, SDO and
SCK will all be in a floating condition.
Step 8. Read data from the SBDR register.
Step 9. Clear TRF.
Step10. Goto step 5.
· Slave Mode:
Step 1. The CKS bit has a don¢t care value in the
slave mode.
Step 2. Setup the M0 and M1 bits to 11 to select the
Slave Mode. The CKS bit is don¢t care.
Step 3. Setup the CSEN bit and setup the
MLS bit to choose if the data is MSB or LSB
first, this must be same as the Master device.
Step 4. Setup the SBEN bit in the SBCR
control register to enable the SPI interface.
Step 5. For write operations: write data to the
SBDR register, which will actually
place the data into the TXRX register, then
wait for the master clock and SCS signal.
After this goto Step 6.
For read operations: the data transferred in
on the SDI line will be stored in the
TXRX buffer until all the data has been
received at which point it will be latched into
the SBDR register.
Step 6. Check the WCOL bit, if set high then a
collision error has occurred so return to step5.
If equal to zero then goto the following step.
Step 7. Check the TRF bit or wait for an SPI serial bus
interrupt.
Step 8. Read data from the SBDR register.
Step 9. Clear TRF
Step10. step 5
In the Master Mode, the Master will always generate the
clock signal. The clock and data transmission will be initiated after data has been written to the SBDR register.
In the Slave Mode, the clock signal will be received from
an external master device for both data transmission or
reception. The following sequences show the order to
be followed for data transfer in both Master and Slave
Mode:
· Master Mode
Step 1. Select the clock source using the CKS bit in
the SBCR control register
Step 2. Setup the M0 and M1 bits in the SBCR control
register to select the Master
Mode and the required Baud rate. Values of
00, 01 or 10 can be selected.
Step 3. Setup the CSEN bit and setup the
MLS bit to choose if the data is MSB or LSB
first, this must be same as the Slave device.
Step 4. Setup the SBEN bit in the SBCR
control register to enable the SPI interface.
Step 5. For write operations: write the data to the
SBDR register, which will actually
place the data into the TXRX buffer. Then use
the SCK and SCS lines to output the data.
Goto to step 6.For read operations: the data
transferred in on the SDI line will be
stored in the TXRX buffer until all the data has
been received at which point it will be latched
into the SBDR register.
Rev.1.30
40
January 14, 2011
HT82A520R/HT82A620R
SPI Configuration Options and Status Control
One option is to enable the operation of the WCOL, write collision bit, in the SBCR register. Some control in SPIR register.
The SPI_CPOL select the clock polarity of the SCK line. The SPI_MODE select SPI data output mode.
SPI include four pins , can share I/O mode status . The status control combine with four bits for SPIR and SBCR register. Include SPI_CSEN , SPI_EN for SPIR register and CSEN, SBEN for SBCR register.
Control Bit for Register
SPI Share Function Pins Status
SPI_EN
SPI_CSEN
SBEN
CSEN
SCS
SCK
SDO
SDI
0
x
x
x
I/O mode
I/O mode
I/O mode
I/O mode
1
0
0
x
I/O mode
I/O mode
I/O mode
I/O mode
1
0
1
x
I/O mode
SPI mode
SPI mode
SPI mode (Z)
1
1
0
x
I/O mode
I/O mode
I/O mode
I/O mode
1
1
1
0
SPI mode (Z)
SPI mode
SPI mode
SPI mode (Z)
1
1
1
1
SPI mode
SPI mode
SPI mode
SPI mode (Z)
Note:
X: don¢t care
(Z) floating
Error Detection
Programming Considerations
The WCOL bit in the SBCR register is provided to indicate
errors during data transfer. The bit is set by the Serial Interface but must be cleared by the application program.
This bit indicates a data collision has occurred which happens if a write to the SBDR register takes place during a
data transfer operation and will prevent the write operation
from continuing. The bit will be set high by the Serial Interface but has to be cleared by the user application program. The overall function of the WCOL bit can be
disabled or enabled by a configuration option.
When the device is placed into the Power Down Mode
note that data reception and transmission will continue.
The TRF bit is used to generate an interrupt when the data
has been transferred or received.
b 7
C K S
M 1
M 0
S B E N
M L S
b 0
C S E N W C O L T R F
S B C R
R e g is te r
T r a n s m itt/R e c e iv e fla g
0 : N o t c o m p le te
1 : T r a n s m is s io n /r e c e p tio n c o m p le te
W r ite c o llis io n b it
0 : C o llis io n fr e e
1 : C o llis io n d e te c te d
S e le c tio n s ig n a l e n a b le /d is a b le b it
0 : S C S flo a tin g
1 : E n a b le
M S B /L S B fir s t b it
0 : L S B s h ift fir s t
1 : M S B s h ift fir s t
S e r ia l B u s e n a b le /d is a b le b it
0 : D is a b le
1 : E n a b le
M a s te r /S la
M 1
M 0
0
0
0
1
1
0
1
1
v e /B a u d r a te b its
M a s
M a s
M a s
S la v
te r,
te r,
te r,
e m
b a u d ra te : fS
b a u d ra te : fS
b a u d ra te : fS
o d e
P I
P I/
P I/
4
1 6
C lo c k s o u r c e s e le c t b it
0 : f S P I= f S Y S / 4
1 : f S P I= f S Y S
SPI Interface Control Register
Rev.1.30
41
January 14, 2011
HT82A520R/HT82A620R
S P I_ m o d e = 0
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R
P A 0 /S C S
(S P I_ C S E N = 1 )
S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
( if p u ll- h ig h e d )
P A 1 /S C L K
(S P I_ C P O L = 1 )
P A 1 /S C L K
(S P I_ C P O L = 0 )
P A 2 /S D I
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
P A 3 /S D O
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S P I_ m o d e = 1
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R
P A 0 /S C S
(S P I_ C S E N = 1 )
S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
( if p u ll- h ig h e d )
P A 1 /S C L K
(S P I_ C P O L = 1 )
P A 1 /S C L K
(S P I_ C P O L = 0 )
P A 2 /S D I
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
P A 3 /S D O
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SPI Bus Timing
Rev.1.30
42
January 14, 2011
HT82A520R/HT82A620R
A
S P I T ra n s fe r
M a s te r
M a s te r o r
S la v e
[M 1 , M 0 ]= 0 0 , 0 1 ,1 0
S e le c t c lo c k [C K S ]
W r ite D a ta in to
S B D R
C le a r W C O L
S la v e
Y e s
W C O L = 1 ?
[M 1 , M 0 ]= 1 1
N o
N o
C o n fig u r e
C S E N a n d M L S
T r a n s m is s io n
C o m p le te d ?
(T R F = 1 ? )
Y e s
S B E N = 1
re a d d a ta fro m
S B D R
A
c le a r T R F
T ra n s fe r
F in is h e d ?
N o
Y e s
E N D
SPI Transfer Control Flowchart
Rev.1.30
43
January 14, 2011
HT82A520R/HT82A620R
USB Interface
The device includes a USB interface function allowing for the host and the Suspend line in the USC register will
change to zero. So when the MCU detects the Suspend
the convenient design of USB peripheral products.
bit in the USC register, the condition of the Resume line
HT82A620R/HT82A520R Power Plane
should be noted and taken into consideration.
There are three power planes for the device: USB SIE
VDD, VDDIO and the MCU VDD. For the USB SIE VDD
will supply all circuits related to the USB SIE and be
sourced from pin ²UBUS². Once the USB is removed from
the USB and there is no power in the USB BUS, the USB
SIE circuit is no longer operational.
For the PB port, it can be configured using a configuration
option to define the if the pins PB0~PB7 are supplied by
either the MCU VDD, or if pins PB0~PB6 are supplied by
the power pin VDDIO, in which case power will be supplied on pin PB7. In the latter configuration, PB7 will be
configured as a power pin VDDIO and not a normal I/O
pin.
S U S P E N D
U S B R e s u m e S ig n a l
U S B _ IN T
The device has a remote wake up function which can
wake-up the USB Host by sending a wake-up pulse
through RMWK in the USC register. Once the USB Host
receives a wake-up signal from the device it will send a
Resume signal to the device.
S U S P E N D
For the MCU VDD, it supplies all the HT82A520R/
HT82A620R circuit except the USB SIE which is supply by
UBUS.
R M W K
M in . 1
U S B C L K
USB Suspend Wake-Up Remote Wake-Up
U S B R e s u m e S ig n a l
M in . 2 .5 m s
If there is no signal on the USB bus for over 3ms, the device will enter a suspend mode. The Suspend flag, SUSP,
in the USC register, will then be set high and a USB interU S B _ IN T
rupt will be generated to indicate that the device should
jump to the suspend state to meet the requirements of the
USB suspend current spec. In order to meet the require- USB Interface Operation
ments of the suspend current, the firmware should disable The device has 4 Endpoints, EP0~EP3. EP0 supports
the USB clock by clearing the USBCKEN bit to zero.
Control transfer. All EP1~EP3 support Interrupt or Bulk
The suspend current can be further decreased by setting transfer.
the SUSP2 bit in the UCC register. When the resume signal is sent out by the host, the device will be woken up the
by the USB interrupt and the Resume bit in the USC register will be set. To ensure correct device operation, the program must set the USBCKEN bit in the UCC register high
and clear the SUSP2 bit in the UCC register. The Resume
signal will be cleared before the Idle signal is sent out by
Rev.1.30
All endpoints except EP0 can be configured as 8, 16, 32 or
64 FIFO size using the register UFC0 and UFC1. EP0 has
an 8-byte FIFO size. The Total FIFO size is 64+8 bytes.
The URD in the USC register is the USB reset signal control function definition bit.
44
January 14, 2011
HT82A520R/HT82A620R
Bit No.
Label
R/W
Function
0
¾
¾
1
PUB
R/W
1: D+, and D- have a 500kW pull-high
0: no pull-high (default on MCU reset)
2
SE0
R/W
This bit is used to indicate the SIE has detect a SE0 noise in the USB bus. This
bit is set by SIE and clear by F/W.
3
SE1
R/W
This bit is used to indicate the SIE has detect a SE1 noise in the USB bus. This
bit is set by SIE and clear by F/W.
4
PS2/DAI
R
USBD-/DATA input.
5
PS2/CKI
R
USBD+/CLK input.
6
PS2/DAO
W
Output for driving USBD-/DATA pin, when work under 3D PS2 mouse function.
Default value is ²1².
7
PS2/CKO
W
Output for driving USBD+/CLK pin, when work under 3D PS2 mouse function.
Default value is ²1².
Unused bit, read as ²0²
USB_STAT Register
Bit No.
Label
R/W
Function
0
EP0EN
R/W
Controls the USB endpoint0 interrupt. Default value is ²0².
1: enabled
0: disabled
1
EP1EN
R/W
Controls the USB endpoint1 interrupt. Default value is ²0².
1: enabled
0: disabled
2
EP2EN
R/W
Controls the USB endpoint2 interrupt. Default value is ²0².
1: enabled
0: disabled
3
EP3EN
R/W
Controls the USB endpoint3 interrupt. Default value is ²0².
1: enabled
0: disabled
4~7
¾
¾
Unused bit, read as ²0²
UINT1 Register
Rev.1.30
45
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Bit No.
Label
R/W
Function
0
SUSP
R
Read only, USB suspend indication. When this bit is set to ²1² (set by SIE), it indicates that the USB bus has entered the suspend mode. The USB interrupt is also
triggered when this bit changes from low to high. Default value is ²0².
1
RMWK
R/W
USB remote wake-up command. It is set by MCU to leave the USB host leaving
the suspend mode.
R/W
USB reset indication. This bit is set/cleared by the USB SIE. This bit is used to detect a USB reset event on the USB bus. When this bit is set to ²1², this indicates
that a USB reset has occurred and that a USB interrupt will be initialized. Default
value is ²0². Default value is ²0².
USB resume indication. When the USB leaves the suspend mode, this bit is set to
²1² (set by SIE). When the RESUME is set by SIE, an interrupt will be generated
to wake-up the MCU. In order to detect the suspend state, the MCU should set
USBCKEN and clear SUSP2 (in the UCC register) to enable the SIE detect function. RESUME will be cleared when the SUSP goes to ²0². When the MCU is detecting the SUSP, the condition of RESUME (causes the MCU to wake-up)
should be noted and taken into consideration. Default value is ²0².
2
URST
3
RESUME
R
4
V33O
R/W
0/1: Turn-off/on V33O output. Default value is ²0².
5
PLL
R/W
0: Turn-on PLL (default), 1: turn off PLL. Default value is ²0².
6
SELPS2
R/W
When set to ¢1¢, indicated the chip work under PS2 mode. Default value is ²0².
Default value is ²0².
7
URD
R/W
USB reset signal control function definition.
1: USB reset signal will reset MCU. (Default)
0: USB reset signal cannot reset MCU.
USC Register
The USR register which is the endpoint interrupt status register, is used to indicate which endpoint is accessed and to
select the USB bus. The endpoint request flags, EP0F, EP1F, EP2F and EP3F, are used to indicate which endpoints
are accessed. If an endpoint is accessed, the related endpoint request flag will be set high and a USB interrupt will be
generated, if the USB interrupt is enabled and the stack is not full. When the active endpoint request flag is serviced,
the endpoint request flag has to be cleared to zero using the program.
Bit No.
Label
R/W
Function
0
EP0F
R/W
When this bit is set to ²1² (set by SIE), it indicates that endpoint 0 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this
bit should be cleared by software. Default value is ²0².
1
EP1F
R/W
When this bit is set to ²1² (set by SIE), it indicates that endpoint 1 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this
bit should be cleared by software. Default value is ²0².
2
EP2F
R/W
When this bit is set to ²1² (set by SIE), it indicates that endpoint 2 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this
bit should be cleared by software. Default value is ²0².
3
EP3F
R/W
When this bit is set to ²1² (set by SIE), it indicates that endpoint 3 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this
bit should be cleared by software. Default value is ²0². Default value is ²0².
4~7
¾
¾
Unused bit, read as ²0²
USR Register
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There is a system clock control register to select the clock used in the MCU. This register consists of a USB clock control bit, USBCKEN, a second suspend mode control bit, SUSP2, and a system clock selection bit, SYSCLK.
The endpoint selection is determined by EPS2, EPS1 and EPS0.
Bit No.
Label
R/W
Function
0
1
2
EPS0
EPS1
EPS2
R/W
Accessing endpoint FIFO selection. Default value is ²000².
EPS2, EPS1, EPS0:
000: Select endpoint 0 FIFO (control)
001: Select endpoint 1 FIFO
010: Select endpoint 2 FIFO
011: Select endpoint 3 FIFO
If the selected endpoints do not exist, the related functions will be absent.
3
USBCKEN
R/W
USB clock control bit. When this bit is set to ²1², it indicates that the USB clock
is enabled. Otherwise, the USB clock is turned-off. Default value is ²0².
4
SUSP2
R/W
This bit is used for reducing power consumption in suspend mode.
In normal mode, clean this bit to ²0². (default)
In halt mode, set this bit to ²1² for reducing power consumption.
5
FSYS16MHz
R/W
This bit is used to define if the MCU system clock comes form an external
OSC or comes from the PLL output 16MHz clock.
0: system clock sourced from OSC. (default)
1: system clock sourced from the PLL output 16MHz.
6
SYSCLK
R/W
This bit is used to specify the MCU system clock oscillator frequency.
For a 6MHz crystal oscillator or resonator, set this bit to ²1².
For a 12MHz crystal oscillator or resonator, clear this bit to ²0². (default)
R/W
This bit is used to control whether there is 7.5kW resistor between D+ and
Vbus.
0: no 7.5kW between D+ and Vbus (default)
1: has 7.5kW between D+ and Vbus
7
RCTRL
UCC Register
The AWR register contains the current address and a remote wake up function control bit. The initial value of AWR is
²00H². The address value extracted from the USB command has not to be loaded into this register until the SETUP
stage has finished.
Bit No.
Label
R/W
Function
0
WKEN
R/W
USB remote-wake-up enable/disable (1/0). Default value is ²0².
1~7
AD0~AD6
R/W
USB device address. Default value is ²0000000².
AWR Register
The STALL register shows if the corresponding endpoint has worked properly or not. As soon as endpoint improper operation occurs, the related bit in the STALL register has to be set high. The STALL register bits will be cleared by a USB
reset signal and a setup token event.
Bit No.
Label
R/W
Function
0~3
STL0~
STL3
R/W
Set by the users when related USB endpoints were stalled. Cleared by a USB reset.
The STL0 is also cleared by a Setup Token event. Default value is ²0000².
4~7
¾
¾
Unused bit, read as ²0²
STALL Register
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The SIES register is only used for EP0 except for the NMI bit, which can control all endpoints
Bit No.
Label
R/W
Function
0
ASET
R/W
This bit is used to configure the SIE to automatically change the device address by the
value stored in the AWR register. When this bit is set to ²1² by firmware, the SIE will update the device address by the value stored in the AWR register after the PC host has
successfully read the data from he device by an IN operation. Otherwise, when this bit
is cleared to ²0², the SIE will update the device address immediately after an address is
written to the AWR register. So, in order to work properly, the firmware has to clear this
bit after a next valid SETUP token is received. Default value is ²0².
1
ERR
R/W
This bit is used to indicate that some errors have occurred when the FIFO is accessed.
This bit is set by SIE and should be cleared by firmware. This bit is used for all endpoint.
Default value is ²0².
2
OUT
R/W
This bit is used to indicate the OUT token (except the OUT zero length token) has been
received. The firmware clears this bit after the OUT data has been read. Also, this bit
will be cleared by SIE after the next valid SETUP token is received. Default value is ²0².
3
IN
R
This bit is used to indicate the current USB receiving signal from PC host is IN token.
4
NO ACK
R
This bit will set to ²1² once SIE discover ther are some error condition so the SIE is not
response (NAK or ACK or DATA) for the USB token. This bit is set by SIE and clear by
F/W.
5
¾
¾
Unused bit, read as ²0²
6
CRCF
R/W
This bit will set to ²1² when there are the following three condition is happened: CRC error, PID error, Bit stuffing error.
This bit is set by SIE and clear by F/W. Default value is ²0².
R/W
NAK token interrupt mask flag. If this bit set, when the device sent a NAK token to the
host, an interrupt will be disabled. Otherwise if this bit is cleared, when the device
sends a NAK token to the host, it will enter the interrupt sub-routine. This bit is used for
all endpoint. Default value is ²0².
7
NMI
SIES Register
The MISC register combines command and status to control the desired endpoint FIFO action and to show the status of
the desired endpoint FIFO. MISC will be cleared by a USB reset signal.
Bit No.
Label
R/W
Function
0
REQUEST
R/W
After setting the status of the desired one, FIFO can be requested by setting this bit
high. After finishing, this bit must be set low. Default value is ²0².
1
TX
R/W
To represent the direction and transition end MCU access. When set to logic 1, the
MCU desires to write data to the FIFO. After finishing, this bit must be set to logic 0
before terminating request to represent transition end. For an MCU read operation,
this bit must be set to logic 0 and set to logic 1 after finishing. Default value is ²0².
2
CLEAR
R/W
MCU requests to clear the FIFO, even if the FIFO is not ready. After clearing the
FIFO, the USB interface will send force_tx_err to tell the Host that data under-run if
the Host wants to read data. Default value is ²0².
3~4
¾
¾
5
SETCMD
R/W
6
READY
R
To show that the desired FIFO is ready.
7
LEN0
R
To show that the host sent a 0-sized packet to the MCU. This bit must be cleared by a
read action to the corresponding FIFO.
Unused bit, read as ²0²
To show that the data in the FIFO is a setup command. This bit is set by Hardware
and clear by Firmware. Default value is ²0².
MISC Register
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Bit No.
Label
R/W
Function
0
FIFO_def
R/W
Once this bit set to ²1² by Firmware, The SIE should redefine the FIFO configuration. This bit is automatically cleared by SIE
1
SETI1*
R/W
Input FIFO for EP1 enable 1/disable 0; default disable
2
SETI2*
R/W
Input FIFO for EP2 enable 1/disable 0; default disable
3
SETI3*
R/W
Input FIFO for EP3 enable 1/disable 0; default disable
4~7
¾
¾
Note:
Unused bit, read as ²0²
²*² It is only required to set the data pipe as an input pile or output pile. The purpose of this function is to avoid
the host sending an abnormal IN or OUT token and disabling the endpoint.
UFIEN Register, USB Endpoint 1~Endpoint 3 set IN Pipe Enable Register.
Bit No.
Label
R/W
Function
0
¾
¾
1
SETO1**
R/W
Output FIFO for EP1 enable 1/disable 0; default disable
2
SETO2**
R/W
Output FIFO for EP2 enable 1/disable 0; default disable
3
SETO3**
R/W
Output FIFO for EP3 enable 1/disable 0; default disable
4~7
¾
¾
Note:
Unused bit, read as ²0²
Unused bit, read as ²0²
²*² USB definition: when the host sends a ²set Configuration², the Data pipe should send the DATA0 (about the
Data toggle) first. So, when the Device receives a ²set configuration² setup command, the user needs to toggle
this bit as the following data will send a Data0 first.
²**² It is only required to set the data pipe as an input pile or output pile. The purpose of this function is to avoid
the host sending a abnormal IN or OUT token and disabling the endpoint.
UFOEN Register, USB Endpoint 1~Endpoint 3 set OUT pipe enable register
Bit No.
Label
0
1
RAM_def0
RAM_def1
2
3
4
5
6
7
E1FS0
E1FS1
E2FS0
E2FS1
E3FS0
E3FS1
R/W
Function
R/W
00: RAM0 input FIFO, RAM1 output FIFO (default)
01: Both RAM0 and RAM1 are output FIFO
10: Both RAM0 and RAM1 are input FIFO
11: RAM0 output FIFO, RAM1 input FIFO
R/W
Define endpoint 1 FIFO size
E1FS1, E1FS0:
00: 8-byte (default)
01: 16-byte
10: 32-byte
11: 64-byte
R/W
Define endpoint 2 FIFO size
E2FS1, E2FS0:
00: 8-byte (default)
01: 16-byte
10: 32-byte
11: 64-byte
R/W
Define endpoint 3 FIFO size
E3FS1, E3FS0:
00: 8-byte (default)
01: 16-byte
10: 32-byte
11: 64-byte
UFC0 USB FIFO Size Control Register 0
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The total FIFO size is 64+8 bytes. All endpoints except EP0 can be defined by registers UFOEN, UFIEN, UFC0 and
UFC. There are three FIFO mapped as follow:
8 bytes FIFO for Endpoint0
RAM0 FIFO for other input Endpoint (1~3)
RAM1 FIFO for other output Endpoint (1~3)
Label
R/W
Function
FIFO0~FIFO3
R/W
EPi accessing register (i=0~3). When an endpoint is disabled, the corresponding accessing register should be disabled.
FIFO0~FIFO3 USB Endpoint Accessing Registers Definitions
Configuration Options
No.
Options
1
PA pull-high enable/disable by bit
2
PB pull-high enable/disable by nibble
3
PC pull-high enable/disable by nibble
4
PB wake-up enable/disable by nibble
5
PC wake-up enable/disable by nibble
6
USB D- pin internal 1.5kW resistor enable/disable
7
USB D+ pin internal 7.5kW resistor enable/disable
8
TBHP enable or disable
9
Low voltage reset: enable/disable
10
WDT enable/disable
11
WDT clock source: fSYS/4 or WDTOSC (32K RC)
12
CLR WDT instructions: one or two clear WDT instruction(s)
13
PA NMOS or CMOS output type
14
PA wake-up enable/disable by bit
16
PB7 mode: GPIO or VDDIO pin for PB0~PB6 power source
17
VDD PB0~PB6: PB0~PB6 power source from VDD or VDDIO
18
SPI_WCOL: enable/disable
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Application Circuits
Crystal or Ceramic Resonator for Multiple I/O Applications
0 .1 m F *
V D D
U S B -
1 0 m F *
U S B +
1 0 0 k W
0 .1 m F * *
V S S
V D D
P B 0 ~ P B 7
P C 0 ~ P C 7
O S C 1
X 1
O S C 2
0 .1 m F
P A 0 ~ P A 7
R E S
V S S
V 3 3 O
U S B D -/D A T A
U S B D + /C L K
1 .5 k W
0 .1 m F
3 3 W
3 3 W
H T 8 2 A 5 2 0 R /H T 8 2 A 6 2 0 R
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that VDD is stable and remains within a valid operating voltage range before bringing RES high.
X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible.
* These capacitors should be placed close to the USB connector.
** This capacitor should be placed close to the MCU.
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Central t o t h e s u c c e s s f u l o p e r a t i o n o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev.1.30
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
2Note
2Note
2Note
None
None
None
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m](4) Read ROM code (locate by TBLP and TBHP) to data memory and TBLH
TABRDC [m](5) Read ROM code (current page) to data memory and TBLH
Read table (last page) to TBLH and Data Memory
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
4. Configuration option ²TBHP option² is enabled
5. Configuration option ²TBHP option² is disabled
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HT82A520R/HT82A620R
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev.1.30
55
January 14, 2011
HT82A520R/HT82A620R
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev.1.30
56
January 14, 2011
HT82A520R/HT82A620R
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev.1.30
57
January 14, 2011
HT82A520R/HT82A620R
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev.1.30
58
January 14, 2011
HT82A520R/HT82A620R
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev.1.30
59
January 14, 2011
HT82A520R/HT82A620R
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev.1.30
60
January 14, 2011
HT82A520R/HT82A620R
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev.1.30
61
January 14, 2011
HT82A520R/HT82A620R
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev.1.30
62
January 14, 2011
HT82A520R/HT82A620R
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDC [m]
Move the ROM code (locate by TBLP and TBHP) to TBLH and data memory (ROM code
TBHP is enabled)
Description
The low byte of ROM code addressed by the table pointers (TBLP and TBHP) is moved to
the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev.1.30
63
January 14, 2011
HT82A520R/HT82A620R
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev.1.30
64
January 14, 2011
HT82A520R/HT82A620R
Package Information
20-pin SSOP (150mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
D
E
Symbol
a
F
Dimensions in inch
Min.
Nom.
Max.
A
0.228
¾
0.244
B
0.150
¾
0.158
C
0.008
¾
0.012
C¢
0.335
¾
0.347
D
0.049
¾
0.065
E
¾
0.025
¾
F
0.004
¾
0.010
G
0.015
¾
0.050
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
Rev.1.30
H
Dimensions in mm
Min.
Nom.
Max.
A
5.79
¾
6.20
B
3.81
¾
4.01
C
0.20
¾
0.30
C¢
8.51
¾
8.81
D
1.24
¾
1.65
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.38
¾
1.27
H
0.18
¾
0.25
a
0°
¾
8°
65
January 14, 2011
HT82A520R/HT82A620R
24-pin SSOP (150mil) Outline Dimensions
1 3
2 4
A
B
1
1 2
C
C '
G
D
E
Symbol
a
F
Dimensions in inch
Min.
Nom.
Max.
0.228
¾
0.244
B
0.150
¾
0.157
C
0.008
¾
0.012
C¢
0.335
¾
0.346
D
0.054
¾
0.060
E
¾
0.025
¾
F
0.004
¾
0.010
G
0.022
¾
0.028
H
0.007
¾
0.010
a
0°
¾
8°
A
Symbol
Dimensions in mm
Min.
Nom.
Max.
5.79
¾
6.20
B
3.81
¾
3.99
C
0.20
¾
0.30
C¢
8.51
¾
8.79
D
1.37
¾
1.52
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.56
¾
0.71
H
0.18
¾
0.25
a
0°
¾
8°
A
Rev.1.30
H
66
January 14, 2011
HT82A520R/HT82A620R
28-pin SSOP (150mil) Outline Dimensions
1 5
2 8
A
B
1
1 4
C
C '
G
D
E
Symbol
a
F
Dimensions in inch
Min.
Nom.
Max.
0.228
¾
0.244
B
0.150
¾
0.157
C
0.008
¾
0.012
C¢
0.386
¾
0.394
D
0.054
¾
0.060
E
¾
0.025
¾
F
0.004
¾
0.010
G
0.022
¾
0.028
H
0.007
¾
0.010
a
0°
¾
8°
A
Symbol
A
Rev.1.30
H
Dimensions in mm
Min.
Nom.
Max.
5.79
¾
6.20
B
3.81
¾
3.99
C
0.20
¾
0.30
C¢
9.80
¾
10.01
D
1.37
¾
1.52
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.56
¾
0.71
H
0.18
¾
0.25
a
0°
¾
8°
67
January 14, 2011
HT82A520R/HT82A620R
SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions
D
2 5
D 2
3 2
2 4
b
1
E
E 2
e
1 7
8
1 6
A 1
A 3
L
9
K
A
Symbol
Min.
Nom.
Max.
A
0.028
¾
0.031
A1
0.000
¾
0.002
A3
¾
0.008
¾
b
0.007
¾
0.012
D
¾
0.197
¾
E
¾
0.197
¾
e
¾
0.020
¾
D2
0.049
¾
0.128
E2
0.049
¾
0.128
L
0.012
¾
0.020
K
¾
¾
¾
Symbol
Rev.1.30
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
0.70
¾
0.80
A1
0.00
¾
0.05
A3
¾
0.20
¾
b
0.18
¾
0.30
D
¾
5.00
¾
E
¾
5.00
¾
e
¾
0.50
¾
D2
1.25
¾
3.25
E2
1.25
¾
3.25
L
0.30
¾
0.50
K
¾
¾
¾
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HT82A520R/HT82A620R
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SSOP 20S (150mil), SSOP 24S (150mil), SSOP 28S (150mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev.1.30
13.0
+0.5/-0.2
2.0±0.5
16.8
+0.3/-0.2
22.2±0.2
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January 14, 2011
HT82A520R/HT82A620R
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
D 1
P
B 0
C
K 0
A 0
R e e l H o le
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SSOP 20S (150mil)
Symbol
Description
Dimensions in mm
16.0
+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
E
Perforation Position
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.5
D1
Cavity Hole Diameter
1.50
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
9.0±0.1
K0
Cavity Depth
2.3±0.1
8.0±0.1
1.75±0.10
7.5±0.1
+0.1/-0.0
+0.25/-0.00
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
Rev.1.30
70
January 14, 2011
HT82A520R/HT82A620R
SSOP 24S (150mil)
Symbol
Description
W
Carrier Tape Width
P
Cavity Pitch
E
Perforation Position
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
Dimensions in mm
16.0
+0.3/-0.1
8.0±0.1
1.75±0.10
7.5±0.1
1.5
1.50
+0.1/-0.0
+0.25/-0.00
D1
Cavity Hole Diameter
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
9.5±0.1
K0
Cavity Depth
2.1±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
SSOP 28S (150mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
16.0±0.3
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
7.5±0.1
D
Perforation Diameter
1.55
+0.10/-0.00
D1
Cavity Hole Diameter
1.50
+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
10.3±0.1
K0
Cavity Depth
2.1±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
Rev.1.30
71
January 14, 2011
HT82A520R/HT82A620R
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev.1.30
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January 14, 2011