GSI GS841E18AT-180I 256k x 18 sync cache tag Datasheet

GS841E18AT/B-180/166/150/130/100
180 MHz–100 MHz
3.3 V VDD
3.3 V and 2.5 V I/O
256K x 18 Sync
Cache Tag
TQFP, BGA
Commercial Temp
Industrial Temp
Features
• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O
supply
• Dual Cycle Deselect (DCD)
• Intergrated data comparator for Tag RAM application
• FT mode pin for flow through or pipeline operation
• LBO pin for Linear or Interleave (PentiumTM and X86) Burst
mode
• Synchronous address, data I/O, and control inputs
• Synchronous Data Enable (DE)
• Asynchronous Output Enable (OE)
• Asynchronous Match Output Enable (MOE)
• Byte Write (BWE) and Global Write (GW) operation
• Three chip enable signals for easy depth expansion
• Internal self-timed write cycle
• JTAG Test mode conforms to IEEE standard 1149.1
• JEDEC-standard 100-lead TQFP package and 119-BGA
• Pb-Free 100-lead TQFP package available
Functional Description
The GS841E18A is a 256K x 18 high performance synchronous DCD
SRAM with integrated Tag RAM comparator. A 2-bit burst counter is
included to provide burst interface with PentiumTM and other high
performance CPUs. It is designed to be used as a Cache Tag SRAM,
as well as data SRAM. Addresses, data IOs, match output, chip
enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC,
ADV), and write control inputs (BW1, BW2, BWE, GW, DE) are
synchronous and are controlled by a positive-edge-triggered clock
(CLK).
Output Enable (OE), Match Output Enable, and power down control
(ZZ) are asynchronous. Burst can be initiated with either ADSP or
ADSC inputs. Subsequent burst addresses are generated internally and
are controlled by ADV. The burst sequence is either interleave order
(PentiumTM or x86) or linear order, and is controlled by LBO.
Output registers and the Match output register are provided and
controlled by the FT mode pin (Pin 14). Through use of the FT mode
pin, I/O registers can be programmed to perform pipeline or flow
through operation. Flow Through mode reduces latency.
Byte write operation is performed by using Byte Write Enable (BWE)
input combined with two individual byte write signals BW1-2. In
addition, Global Write (GW) is available for writing all bytes at one
time.
Compare cycles begin as a read cycle with output disabled so that
compare data can be loaded into the data input register. The
comparator compares the read data with the registered input data and a
match signal is generated. The match output can be either in Pipeline
or Flow Through modes controlled by the FT signal.
Low power (Standby mode) is attained through the assertion of the ZZ
signal, or by stopping the clock (CLK). Memory data is retained
during Standby mode.
JTAG boundary scan interface is provided using IEEE standard
1149.1 protocol. Four pins—Test Data In (TDI), Test Data Out
(TDO), Test Clock (TCK) and Test Mode Select (TMS)—are used to
perform JTAG function.
The GS841E18A operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate output
(VDDQ) pins are used to allow both 3.3 V or 2.5 V IO interface.
Dual Cycle Deselect (DCD)
The GS841E18A is a DCD pipelines synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. DCD SRAMs hold the deselect command for one full
cycle and then begin turning off their outputs just after the second
rising edge of the clock.
Parameter Synopsis
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.03 4/2005
–180
-166
-150
-133
-100
tcycle
tKQ
IDD
5.5 ns
3.2 ns
335 mA
6.0 ns
3.5 ns
310 mA
6.6 ns
3.8 ns
275 mA
7.5 ns
4.0 ns
250 mA
10 ns
4.5 ns
190 mA
tKQ
8 ns
9.1 ns
210 mA
8.5 ns
10 ns
190 mA
10 ns
10 ns
190 mA
11 ns
15 ns
140 mA
12 ns
15 ns
140 mA
tcycle
IDD
1/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. * Pentium is a trademark of Intel
GS841E18AT/B-180/166/150/130/100
A
A
CE1
CE2
NC
NC
BW2
BW1
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Pin Configuration (Package T)
NC
NC
NC
VDDQ
A
NC
NC
VDDQ
VSS
NC
DQP
DQ
DQ
VSS
VDDQ
DQ
DQ
VSS
NC
VDD
ZZ
DQ
DQ
VDDQ
VSS
DQ
DQ
NC
NC
VSS
VDDQ
MATCH
DE
MOE
LBO
A
A
A
A
A1
A0
TMS
TDI
VSS
VDD
TDO
TCK
A
A
A
A
A
A
A
VSS
NC
NC
D
DQ
VSS
VDDQ
DQ
DQ
FT
VDD
NC
VSS
DQ
DQ
VDDQ
VSS
DQ
DQ
DQP
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03 4/2005
2/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
GS841E18A PadOut—119-Bump BGA—Top View (Package B)
Rev: 1.03 4/2005
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
NC
E2
A
ADSC
A
E3
NC
C
NC
A
A
VDD
A
A
NC
D
DQB
NC
VSS
NC
VSS
DQP
NC
E
NC
DQB
VSS
E1
VSS
NC
DQA
F
VDDQ
NC
VSS
G
VSS
DQA
VDDQ
G
NC
DQB
BB
ADV
NC
NC
DQA
H
DQB
NC
VSS
GW
VSS
DQA
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
DQB
VSS
CK
VSS
NC
DQA
L
DQB
NC
NC
NC
BA
DQA
NC
M
VDDQ
DQB
VSS
BW
VSS
MATCH
VDDQ
N
DQB
NC
VSS
A1
VSS
DQA
DE
P
NC
DQP
VSS
A0
VSS
MOE
DQA
R
NC
A
LBO
VDD
FT
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
3/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
TQFP Pin Description
Symbol
Description
An
Address Input Signals—Inputs are registered and must meet setup and hold times, as specified on
page 11.
CLK
Clock Input Signal
BWE
Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the four
byte write signals for a write operation to occur.
BW1
Byte Write signal for data outputs 1 thru 8
BW2
Byte Write signal for data outputs 9 thru 16
GW
Global Write Enable
CE1,CE2, CE3
Chip Enables
OE
Output Enable
ADV
Burst address advance
ADSP, ADSC
Address status signals
DQ
Data Input and Output pins
DQP
Parity Input and Output pins
MATCH
Match Output
MOE
Match Output Enable
DE
Data Enable—Data input registers are updated only when DE is active.
ZZ
Power down control—Application of ZZ will result in a low standby power consumption.
FT
Flow Through or Pipeline mode
LBO
Linear Order Burst mode
TMS
Test Mode Select
TDI
Test Data In
TDO
Test Data Out
TCK
Test Clock
VDD
3.3 V power supply
VSS
Ground
VDDQ
2.5 V/3.3 V output power supply
NC
No Connect
Rev: 1.03 4/2005
4/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
PBGA Pin Description
Symbol
Description
An
Address Input Signals—Inputs are registered and must meet setup and hold times, as specified on
page 11.
CLK
Clock Input Signal
BWE
Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the four
byte write signals for a write operation to occur.
BW1
Byte Write signal for data outputs 1 thru 8
BW2
Byte Write signal for data outputs 9 thru 16
GW
Global Write Enable
CE1,CE2, CE3
Chip Enables
OE
Output Enable
ADV
Burst address advance
ADSP, ADSC
Address status signals
DQ
Data Input and Output pins
DQP
Parity Input and Output pins
MATCH
Match Output
MOE
Match Output Enable
DE
Data Enable—Data input registers are updated only when DE is active.
ZZ
Power down control—Application of ZZ will result in a low standby power consumption.
FT
Flow Through or Pipeline mode
LBO
Linear Order Burst mode
TMS
Test Mode Select
TDI
Test Data In
TDO
Test Data Out
TCK
Test Clock
VDD
3.3 V power supply
VSS
Ground
VDDQ
2.5 V/3.3 V output power supply
NC
No Connect
Rev: 1.03 4/2005
5/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Functional Block Diagram
18
A0-17
REGISTER
D
Q
A0
A1
A0
D0
D1
Q0
BINARY
COUNTER
A1
18
Q1
A
Load
LBO
ADV
256K X 18
Memory
Array
CLK
ADSC
ADSP
Q
D
GW
Register
D
Q
BWE
18
BW1
18
2
Register
D
Q
BW2
Q
Register
D
D
Register
Q
Q
Register
D
DE
Register
D
Q
Register
D
Q
CE1
CE2
CE3
Powerdown
ZZ
FT
OE
MOE
A, DQ,
Control
Control
Register
D
Q
18
54
TDI
Boundary Scan
Registers
Bypass Reg
TDO
always (Ø)
DQ1-16
DQP1-2
Match
ID Reg.
Instruction Reg.
TMS
TCK
Rev: 1.03 4/2005
TAP
Controller
6/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Mode Pin Function
LBO
Function
FT
Function
L
Linear Burst
L
Flow Through
H or NC
Interleaved Burst
H or NC
Pipeline
Power Down Control
ZZ
Function
L or NC
Active
H
Standby, IDD = ISB
Note:
There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
1st address
00
01
10
11
2nd address
01
10
11
00
2nd address
01
00
11
10
3rd address
10
11
00
01
3rd address
10
11
00
01
4th address
11
00
01
10
4th address
11
10
01
00
Byte Write Function
Function
GW
BWE
BW1
BW2
Read
H
H
X
X
Read
H
L
H
H
Write all bytes
L
X
X
X
Write all bytes
H
L
L
L
Write byte 1
H
L
L
H
Write byte 2
H
L
H
L
Note: H = logic high, L = logic low, NC = no connect
Rev: 1.03 4/2005
7/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Synchronous Truth Table
Operation
Address Used
CE1
CE2
CE3
ADSP
ADSC
ADV
Write
OE CLK
DQ
Deselect Cycle, Power Down
none
H
X
X
X
L
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
L
X
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
X
H
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
L
X
H
L
X
X
X
L-H
High-Z
Deselect Cycle, Power Down
none
L
X
H
H
L
X
X
X
L-H
High-Z
Read Cycle, Begin Burst
external
L
H
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
external
L
H
L
L
X
X
X
H
L-H
High-Z
Read Cycle, Begin Burst
external
L
H
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
external
L
H
L
H
L
X
H
H
L-H
High-Z
Write Cycle, Begin Burst
external
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Continue Burst
next
X
X
X
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
next
X
X
X
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
next
H
X
X
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
next
H
X
X
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
next
X
X
X
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
next
H
X
X
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
current
X
X
X
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
current
X
X
X
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
current
H
X
X
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
current
H
X
X
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
current
X
X
X
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
current
H
X
X
X
H
H
L
X
L-H
D
Notes:
1. X means “don’t care,” H means “logic high,” L means “logic low.”
2.
3.
4.
5.
6.
Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
All inputs, except OE, must meet setup and hold on rising edge of CLK.
Suspending busrt generates a wait cycle.
ADSP LOW along with SRAM being selected always initiates a Read cycle at the L-H edge of the clock (CLK).
A Write cycle can only be performed by setting Write low for the clock L-H edge of the subsequent wait cycle.
Refer to page 12 for the Write timing diagram.
Rev: 1.03 4/2005
8/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Truth Table For Read/Write/Compare/Fill Write Operation
CE
Write
DE
MOE
OE
Match
DQ
Read
L
H
X
X
L
—
Q
Write
L
L
L
X
H
—
D
Compare
L
H
L
L
H
Data Out
D
Fill Write
L
L
H
X
X
—
X
Match Deselect
H
X
X
L
X
High
High Z
Deselect
H
X
X
H
X
High Z
High Z
Notes:
1. X means “don’t care,” H means “logic high,” L means “logic low.”
2. Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
3. CE is defined as CE1=L, CE2=H and CE3=L
4. All signals are synchronous and are sampled by CLK except OE and MOE. OE and MOE are asynchronous and drive the bus immediately.
)
Absolute Maximum Ratings (Voltage reference to VSS = 0 V)
Symbol
Description
Commerical
Unit
VDD
Supply Voltage
–0.5 to 4.6
V
VDDQ
Output Supply Voltage
–0.5 to VDD
V
VCLK
CLK Input Voltage
–0.5 to 6
V
Vin
Input Voltage
–0.5 to VDD + 0.5
(≤ 4.6 V max. )
V
Vout
Output Voltage
–0.5 to VDD + 0.5
(≤ 4.6 V max. )
V
Iout
Output Current per I/O
+/–20
mA
PD
Power Dissipation
1.5
W
TOPR
Operating Temperature
0 to 70
o
C
TSTG
Storage Temperature
–55 to 125
o
C
Note:
Permanent damage to the device may occur if the Absolute Maximun Ratings are exceeded. Functional operation should be restricted to the
recommended operation conditions. Exposure to higher than recommended voltages, for an extended period of time, could effect the
performance and reliability of this component.
Rev: 1.03 4/2005
9/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Package Thermal Characteristics
Rating
Layer Board
Symbol
TQFP max
PBGA max
Unit
Notes
Junction to Ambient (at 200 lfm)
single
RΘJA
32
28
°C/W
1,2
Junction to Ambient (at 200 lfm)
four
RΘJA
20
18
°C/W
1,2
Junction to Case (TOP)
—
RΘJC
7
4
°C/W
3
Notes:
1.
Junction temperature is a function of SRAM power dissapation, package thermal resistance, mounting board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.
2.
3.
SCMI G-38-87.
Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
Output load 1
AC Test Conditions
(VDD = 3.135 V–3.6 V, Ta = 0–70°C)
DQ
Parameter
Conditions
Input high level
VIH = 2.3 V
Input low level
VIL = 0.2 V
Input slew rate
TR = 1 V/ns
Input reference level
1.25 V
Output reference level
1.25 V
Output load
Fig. 1& 2
50W
VT = 1.25 V
FIG. 1
Output load 2
2.5 V
5pF1
Include scope and jig capacitance.
2.
Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
Output load 2 for tLZ, tHZ, tOLZ and tOHZ.
Device is deselected as defined by the Truth Table.
3.
4.
Rev: 1.03 4/2005
225W
DQ
Notes:
1.
30pF1
10/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
225W
FIG. 2
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
DC Characteristics and Supply Currents (Voltage reference to VSS = 0 V)
(VDD = 3.135 V–3.6 V, Ta = 0–70°C for Commercial Temperature Offering)
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except ZZ, FT, LBO pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
ZZ Input Current
IinZZ
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
300 uA
Mode Input Current
(FT & LBO pins)
IinM
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–30 0uA
–1 uA
1 uA
1 uA
Output Leakage Current
Iol
Output Disable,
VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH
IOH = –4 mA, VDDQ = 2.375 V
1.7 V
Output High Voltage
VOH
IOH = –4 mA, VDDQ = 3.135 V
2.4 V
Output Low Voltage
VOL
IOL = +4 mA
Rev: 1.03 4/2005
0.4 V
11/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Operating Currents
-180
Parameter
Test Conditions
Operating
Current
Device Selected;
All other inputs
≥ VIH Or ≤ VIL
Output open
Standby
Current
ZZ ≥ VDD – 0.2 V
Deselect
Supply Current
Rev: 1.03 4/2005
Device Deselected;
All other inputs
≥ VIH OR ≤ VIL
-166
-150
-133
-100
0
to
70°C
–40
to
85°C
0
–40
0
–40
0
–40
0
–40 Unit
to
to
to
to
to
to
to
to
70°C +85°C 70°C +85°C 70°C +85°C 70°C +85°C
IDD
Pipeline
335
345
310
320
275
285
250
260
190
200
mA
IDD
Flow
Through
210
220
190
200
190
200
140
150
140
150
mA
ISB
Pipeline
20
30
30
40
30
40
30
40
30
40
mA
ISB
Flow
Through
20
30
30
40
30
40
30
40
30
40
mA
IDD
Pipeline
55
65
110
120
105
115
100
110
80
90
mA
IDD
Flow
Through
40
50
80
90
80
90
65
75
65
75
mA
Symbol
12/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
AC Electrical Characteristics
Pipeline
Flow
Through
Parameter
Symbol
Clock Cycle Time
-180
-166
-150
-133
-100
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tKC
5.5
—
6.0
—
6.7
—
7.5
—
10
—
ns
Clock to Output Valid
tKQ
—
3.2
—
3.5
—
3.8
—
4
—
4.5
ns
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Output in Low-Z
tLZ1
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Match Valid
tKM
—
3.2
—
3.5
—
3.8
—
4
—
4.5
ns
Clock to Match Invalid
tKMX
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Match in Low-Z
tMLZ1
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock Cycle Time
tKC
9.1
—
10.0
—
10.0
—
15.0
—
15.0
—
ns
Clock to Output Valid
tKQ
—
8.0
—
8.5
—
10.0
—
11.0
—
12.0
ns
Clock to Output Invalid
tKQX
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock to Output in Low-Z
tLZ1
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock to Match Valid
tKM
—
8.5
—
8.5
—
10.0
—
11.0
—
12.0
ns
Clock to Match Invalid
tKMX
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock to Match in Low-Z
tMLZ1
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock HIGH Time
tKH
1.3
—
1.3
—
1.5
—
1.7
—
2
—
ns
Clock LOW Time
tKL
1.5
—
1.5
—
1.7
—
1.9
—
2.2
—
ns
Clock to Output in High-Z
tHZ1
1.5
3.2
1.5
3.5
1.5
3.8
1.5
4
1.5
5
ns
OE to Output Valid
tOE
—
3.2
—
3.5
—
3.8
—
4
—
5
ns
OE to output in Low-Z
tOLZ1
0
—
0
—
0
—
0
—
0
—
ns
OE to output in High-Z
tOHZ1
—
3.2
—
3.5
—
3.8
—
4
—
5
ns
MOE to Match Valid
tMOE
—
3.2
—
3.5
—
3.8
—
4
—
5
ns
MOE to Match in Low-Z
tMOLZ1
0
—
0
—
0
—
0
—
0
—
ns
MOE to Match in High-Z
tMOHZ1
—
3.2
—
3.5
—
3.8
—
4
—
5
ns
Setup time
tS
1.5
—
1.5
—
1.5
—
2.0
—
2.0
—
ns
Hold time
tH
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
ZZ setup time
tZZS2
5
—
5
—
5
—
5
—
5
—
ns
ZZ hold time
tZZH2
1
—
1
—
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
20
—
20
—
ns
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.03 4/2005
13/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Pipeline Mode Timing
Begin
Read A
Cont
Deselect Deselect Write B
Read C
Read C+1 Read C+2 Read C+3 Cont
Deselect Deselect
tKL
tKH
tKC
CK
ADSP
tS
ADSC initiated read
tH
ADSC
tS
tH
ADV
tS
tH
Ao–An
A
B
C
tS
GW
tS
tH
BW
tH
tS
Ba–Bd
tS
Deselected with E1
tH
E1
tS
E2 and E3 only sampled with ADSC
tH
E2
tS
tH
E3
G
tS
tOE
DQa–DQd
Hi-Z
Rev: 1.03 4/2005
tOHZ
Q(A)
tKQ
tH
D(B)
tHZ
tLZ
tKQX
Q(C)
Q(C+1)
14/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q(C+2)
Q(C+3)
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Flow Through Mode Timing
Begin
Read A
Cont
Deselect Write B
Read C
Read C+1 Read C+2 Read C+3 Read C
Deselect
tKL
tKH
tKC
CK
ADSP
Fixed High
tS
tH
tS
tH
ADSC
initiated read
ADSC
tH
tS
tS
tH
ADV
tS
tH
Ao–An
A
B
C
tS
tH
GW
tS
tH
BW
tH
tS
Ba–Bd
tS
Deselected with E1
tH
E1 masks ADSP
E1
tS
tH
E2 and E3 only sampled with ADSP and ADSC
E2
tS
tH
E1 masks ADSP
E3
G
tH
tS
tOE
tKQ
DQa–DQd
Rev: 1.03 4/2005
tOHZ
Q(A)
tKQX
tHZ
tLZ
D(B)
Q(C)
Q(C+1)
Q(C+2)
15/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q(C+3)
Q(C)
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Pipeline Compare Fill Write Cycle
Hit
Miss
Fill Write
K
tH
tS
Address
A
B
B
tH
tS
DQ
A
A
tH
tS
CE
tH
tS
W
G
tH
tS
DE
MOE
tKM
tMOE
tMLZ
tKM
tKMX
tKM
Match
Rev: 1.03 4/2005
16/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Flow Through Compare Fill Write Cycle
Hit
Miss
Fill Write
K
tH
tS
Address
A
B
B
tH
tS
DQ
A
A
tH
tS
CE
tH
tS
W
G
tH
tS
DE
MOE
tKM
tMOE
tMLZ
tKM
tKMX
tKM
Match
Rev: 1.03 4/2005
17/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
TQFP Package Drawing (Package T)
Min. Nom. Max
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
—
0.20
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
—
0.65
—
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
—
1.00
—
Y
Coplanarity
θ
Lead Angle
0.10
0°
—
L1
c
e
D
D1
Description
θ
Pin 1
Symbol
L
b
A1
A2
7°
Y
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.03 4/2005
18/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
E1
E
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
TOP VIEW
A1
1
2
3
4
5
6
BOTTOM VIEW
A1
Ø0.10S C
Ø0.30S C AS B S
Ø0.60~0.90 (119x)
7
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
20.32
22±0.10
1.27
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
B
0.15 C
7.62
C
Rev: 1.03 4/2005
SEATING PLANE
A
0.20(4x)
14±0.10
0.50~0.70
1.86.±0.13
0.56±0.05
0.70±0.05
0.15 C
1.27
19/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
Ordering Information
Org
Part Number1
Type
Package
Speed2
(MHz/ns)
TA
256K x 18
GS841E18AT-180
DCD Pipeline/Flow Through
TQFP
180/8
C
256K x 18
GS841E18AT-166
DCD Pipeline/Flow Through
TQFP
166/8.5
C
256K x 18
GS841E18AT-150
DCD Pipeline/Flow Through
TQFP
150/10
C
256K x 18
GS841E18AT-133
DCD Pipeline/Flow Through
TQFP
133/11
C
256K x 18
GS841E18AT-100
DCD Pipeline/Flow Through
TQFP
100/12
C
256K x 18
GS841E18AT-180I
DCD Pipeline/Flow Through
TQFP
180/8
I
256K x 18
GS841E18AT-166I
DCD Pipeline/Flow Through
TQFP
166/8.5
I
256K x 18
GS841E18AT-150I
DCD Pipeline/Flow Through
TQFP
150/10
I
256K x 18
GS841E18AT-133I
DCD Pipeline/Flow Through
TQFP
133/11
I
256K x 18
GS841E18AT-100I
DCD Pipeline/Flow Through
TQFP
100/12
I
256K x 18
GS841E18AGT-180
DCD Pipeline/Flow Through
Pb-Free TQFP
180/8
C
256K x 18
GS841E18AGT-166
DCD Pipeline/Flow Through
Pb-Free TQFP
166/8.5
C
256K x 18
GS841E18AGT-150
DCD Pipeline/Flow Through
Pb-Free TQFP
150/10
C
256K x 18
GS841E18AGT-133
DCD Pipeline/Flow Through
Pb-Free TQFP
133/11
C
256K x 18
GS841E18AGT-100
DCD Pipeline/Flow Through
Pb-Free TQFP
100/12
C
256K x 18
GS841E18AGT-180I
DCD Pipeline/Flow Through
Pb-Free TQFP
180/8
I
256K x 18
GS841E18AGT-166I
DCD Pipeline/Flow Through
Pb-Free TQFP
166/8.5
I
256K x 18
GS841E18AGT-150I
DCD Pipeline/Flow Through
Pb-Free TQFP
150/10
I
256K x 18
GS841E18AGT-133I
DCD Pipeline/Flow Through
Pb-Free TQFP
133/11
I
256K x 18
GS841E18AGT-100I
DCD Pipeline/Flow Through
Pb-Free TQFP
100/12
I
256K x 18
GS841E18AB-180
DCD Pipeline/Flow Through
119 BGA (var. 2)
180/8
C
256K x 18
GS841E18AB-166
DCD Pipeline/Flow Through
119 BGA (var. 2)
166/8.5
C
256K x 18
GS841E18AB-150
DCD Pipeline/Flow Through
119 BGA (var. 2)
150/10
C
256K x 18
GS841E18AB-133
DCD Pipeline/Flow Through
119 BGA (var. 2)
133/11
C
256K x 18
GS841E18AB-100
DCD Pipeline/Flow Through
119 BGA (var. 2)
100/12
C
256K x 18
GS841E18AB-180I
DCD Pipeline/Flow Through
119 BGA (var. 2)
180/8
I
256K x 18
GS841E18AB-166I
DCD Pipeline/Flow Through
119 BGA (var. 2)
166/8.5
I
256K x 18
GS841E18AB-150I
DCD Pipeline/Flow Through
119 BGA (var. 2)
150/10
I
256K x 18
GS841E18AI-133I
DCD Pipeline/Flow Through
119 BGA (var. 2)
133/11
I
3
Status
256K x 18
GS841E18AB-100I
DCD Pipeline/Flow Through
119 BGA (var. 2)
100/12
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS841E18AT-166T.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Rev: 1.03 4/2005
20/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
4Mb Synchronous Tag RAM Datasheet Revision History
Rev. Code: Old;New
Types of Changes
Page /Revisions;Reason
Format or Content
• Creation of new datasheet
GS841E18A_r1
GS841E18A_r1;
GS841E18A_r1_01
Content
GS841E18A_r1_01;
GS841E18A_r1_02
Format/Content
GS841E18A_r1_02;
GS841E18A_r1_03
Content
Rev: 1.03 4/2005
• Moved TCK from U6 (incorrect placement) to U4 (correct
placement) on BGA
• Changed U6 to NC
• Updated format
• Added 180 MHz speed bin
• Updated timing diagrams
• Updated mechanical drawings
• Added Pb-Free info for TQFP
• Added Pipeline Compare Fill Write Cycle and Flow Through
Compare Fill Write Cycle timing diagrams
21/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology