LMH6518
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SNOSB21A – MAY 2008 – REVISED OCTOBER 2008
LMH6518 900 MHz, Digitally Controlled, Variable Gain Amplifier
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FEATURES
DESCRIPTION
•
•
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The LMH6518 is a digitally controlled variable gain
amplifier whose total gain can be varied from −1.16
dB to 38.8 dB for a 40 dB range in 2 dB steps. The
−3 dB bandwidth is 900 MHz at all gains. Gain
accuracy at each setting is typically 0.1 dB. When
used in conjunction with a National Semiconductor
Gsample/second (Gsps) ADC with adjustable full
scale (FS) range, the LMH6518 gain adjustment will
accommodate full scale input signals from 6.8 mVPP
to 920 mVPP to get 700 mVPP nominal at the ADC
input. The Auxiliary output (“+OUT Aux” and “−OUT
Aux”) follows the Main output and is intended for use
in Oscilloscope trigger function circuitry but may have
other uses in other applications.
1
2
•
•
•
•
•
•
•
•
•
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Gain Range 40 dB
Gain Step Size 2 dB
Combined Gain Resolution with
Gsample/Second ADC’s 8.5 mdB
Min Gain −1.16 dB
Max Gain 38.8 dB
−3 dB BW 900 MHz
Rise/Fall Time <500 ps
Recovery Time <5 ns
Propagation Delay Variation 100 ps
HD2 @ 100 MHz −50 dBc
HD3 @ 100 MHz −53 dBc
Input-Referred Noise (Max Gain) 0.98 nV/√Hz
Over-Voltage Clamps for Fast Recovery
Power Consumption — Auxiliary Turned Off
1.1W0.75W
APPLICATIONS
•
•
•
•
•
•
Oscilloscope Programmable Gain Amplifier
Differential ADC Drivers
High Frequency Single-Ended Input to
Differential Conversion
Precision Gain Control Applications
Medical Applications
RF/IF Applications
The LMH6518 gain is programmed via a SPI-1
compatible serial bus. A signal path combined gain
resolution of 8.5 mdB can be achieved when the
LMH6518’s gain and the Gsps ADC’s FS input are
both manipulated. Inputs and outputs are DCcoupled. The outputs are differential with individual
Common Mode (CM) voltage control (for Main and
Auxiliary outputs) and have a selectable bandwidth
limiting circuitry (common to both Main and Auxiliary)
of 20, 100, 200, 350, 650, 750 MHz or full bandwidth.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
LMH6518
SNOSB21A – MAY 2008 – REVISED OCTOBER 2008
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Functional Block Diagram
GND
VDD
VCC
5,8
12
3,4
Bandwidth
Limiting
Circuitry
Overvoltage
Clamp
VCM
Overvoltage
Clamp
50:
Ladder
Attenuator
-IN
7
13
10 Step
2 dB/Step
6
+IN
16
Common Mode
Control
LMH6518
Hi Gain
or
Low Gain
VCM_Aux
Input
Preamp
Output Amp
50:
50:
Aux Amp
10
9
CS
14
+OUT
-OUT
MAIN OUT
72 µ$'&¶
Overvoltage
Clamp
Serial Peripheral
Interface
SDIO
15
50:
1
2
+OUT Aux
-OUT Aux
AUXILIARY
OUTPUT
11
SCLK
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
ESD Tolerance
(1) (2)
(3)
Human Body Model
2000V
Machine Model
200V
Charge Device Model
1000V
Supply Voltage
VCC (5V nominal)
5.5V
VDD (3.3V nominal)
3.6V
Differential Input
±1V
Input Common Mode Voltage
1V to 4V
VCM and VCM_Aux
2V
SPI Inputs
3.6V
Maximum Junction Temperature
150°C
−65°C to 150°C
Storage Temperature Range
Soldering Information
Infrared or Convection (20 sec.)
235°C
Wave Soldering (10 sec.)
260°C
(1)
(2)
(3)
2
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the
Electrical Characteristics tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
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Operating Ratings
(1)
Supply Voltage
VCC = 5V (±5%)
VDD = 3.3V (±5%)
−40°C to 85°C
Temperature Range
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the
Electrical Characteristics tables.
Thermal Properties
Temperature Range
(1)
−40°C to 85°C
Junction-to-Ambient
Thermal Resistance (θJA), WQFN
(1)
(1)
40°C/W
The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow.
Package should be soldered unto a 6.8 mm2 copper area as shown in the “recommended land pattern” shown in the package drawing.
Electrical Characteristics
(1)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, Input CM = 2.5V, VCM = 1.2V, VCM_Aux = 1.2V, Singleended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential
(both Main & Auxiliary Outputs), both Main and Auxiliary Output Specifications, full bandwidth setting, gain = 18.8 dB (Preamp
LG, 0 dB ladder attenuation), Full Power setting (2). Electrical Characteristics Definition of Terms and Specifications for
abbreviations used in the datasheet. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min (3)
Typ (4)
Max (3)
Units
Dynamic Performance
LSBW
−3 dB Bandwidth
All Gains
Peaking
Peaking
All Gains
1
dB
GF_0.1 dB
±0.1 dB Gain Flatness
All Gains
150
MHz
GF_1 dB
±1 dB Gain Flatness
All Gains
400
MHz
TRS
Rise Time
460
TRL
Fall Time
450
OS
Overshoot
Main Output
9
ts_1
Settling Time
Main Output, ±0.5%
10
Main Output, ±0.05%
14
ts_2
900
MHz
ps
%
ns
t_recover
Recovery Time (5)
All Gains
<5
ns
PD
Propagation Delay
VOUT = 0.7 VPP, All Gains
1.2
ns
PD_VAR
Propagation Delay Variation
Gain Varied
100
ps
Max Gain, 10 MHz
0.98
nV/√Hz
Preamp LG and 0 dB Ladder,
10 MHz
4.1
Noise, Distortion, and RF Specifications
en_1
Input Noise Spectral Density
en_2
eno_1
RMS Output Noise
eno_2
(1)
(2)
(3)
(4)
(5)
Max Gain, 100 Hz to 400 MHz
1.7
mV
Preamp LG, 0 dB Ladder, 100 Hz
to 400 MHz
940
μV
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
“Full Power” setting is with Auxiliary output turned on.
Limits are 100% production tested at 25°C unless otherwise specified. Limits over the operating temperature range are guaranteed
through correlation using Statistical Quality Control (SQC) methods.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
Recovery time” is the slower of the Main and Auxiliary outputs. Output swing of 700 mVPP shifted up or down by 50% (0.35V) by
introducing an offset. Measured values correspond to the time it takes to return to within ±1% of 0.7 VPP (±7 mV).
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Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, Input CM = 2.5V, VCM = 1.2V, VCM_Aux = 1.2V, Singleended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential
(both Main & Auxiliary Outputs), both Main and Auxiliary Output Specifications, full bandwidth setting, gain = 18.8 dB (Preamp
LG, 0 dB ladder attenuation), Full Power setting (2). Electrical Characteristics Definition of Terms and Specifications for
abbreviations used in the datasheet. Boldface limits apply at the temperature extremes.
Symbol
NF_1
Parameter
Min (3)
Condition
Noise Figure
NF_2
2nd/ 3rd Harmonic Distortion (6)
Typ (4)
Max Gain, RS = 50Ω each Input,
10 MHz
3.8
Preamp LG, 0 dB Ladder, RS = 50Ω
each Input, 10 MHz
13.5
Main Output, 100 MHz, All Gains
−50/ −53
HD2/ HD3_2
Auxiliary Output, 100 MHz, All Gains
−48/ −50
HD2/ HD3_3
Main Output, 250 MHz, All Gains
−44/ −50
Auxiliary Output, 250 MHz, All Gains
−42/ −42
HD2/ HD3_1
HD2/ HD3_4
IMD3
Intermodulation Distortion
OIP3_1
Intermodulation Intercept
P_1dB_main
−1 dB Compression
(6)
P_1dB_aux
Units
dB
dBc
−65
dBc
Main Output, 250 MHz
26
dBm
Main Output, 250 MHz, 0 dB Ladder
1.8
f = 250 MHz, Main output
(6)
Max (3)
Main Output, 250 MHz, 20 dB Ladder
1.0
Auxiliary Output, 250 MHz,
0 dB Ladder
1.65
Auxiliary Output, 250 MHz,
20 dB Ladder
1.0
VPP
Gain Parameters
AV_DIFF_MAX
Max Gain
AV_DIFF_MIN
Min Gain
Gain_Step
Gain Step Size
All Gains including Preamp Step
Gain
Step
Size with
Applications Information)
38.1
38.8
39.5
dB
−1.91
−1.16
−0.40
dB
1.8
2
2.2
ADC(See ADC FS Adjusted
Gain_Range
Gain Range
TC_AV_DIFF
Gain Temp Coefficient
Gain_ACC
Absolute Gain Accuracy
Compared to theoretical from
Max Gain in 2 dB steps
Gain_match
Gain Matching Main/Auxiliary
BW_match
8.5
39
(7)
40
41
−0.8
All Gains
0.75
dB
mdB
dB
mdB/°C
—
+0.75
dB
All Gains
±0.1
±0.2
dB
−3 dB Bandwidth Matching
Main/Auxiliary
All Gains
5
RT_match
Rise Time Matching Main/ Auxiliary
All Gains
5
%
PD_match
Propagation Delay Matching
Main/Auxiliary
All Gains
100
ps
CM Rejection Ratio (see Table 1)
Preamp HG, 0 dB Ladder, 1.9V <
CMVR < 3.1V
45
86
Preamp LG, 0 dB Ladder, 1.9V <
CMVR < 3.1V
40
55
Preamp HG, All Ladder Steps, CMRR
≥ 45 dB
1.9
—
3.1
Preamp LG, All Ladder Steps, CMRR
≥ 40 dB
1.9
—
3.1
All Gains, 2V < CMVR < 3V
−60
−100
dB
101
dB
Matching
%
Analog I/O
CMRR_1
CMRR_2
CMVR_1
Input Common Mode Voltage Range
CMVR_2
|ΔVO_CM|ΔI_CM|
CMRR_CM
(6)
(7)
4
CM Rejection Ratio relative to VCM (see Preamp LG, 0 dB
Table 1)
dB
V
Distortion data taken under single ended input condition.
Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
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Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, Input CM = 2.5V, VCM = 1.2V, VCM_Aux = 1.2V, Singleended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential
(both Main & Auxiliary Outputs), both Main and Auxiliary Output Specifications, full bandwidth setting, gain = 18.8 dB (Preamp
LG, 0 dB ladder attenuation), Full Power setting (2). Electrical Characteristics Definition of Terms and Specifications for
abbreviations used in the datasheet. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Min (3)
Condition
Typ (4)
Zin_diff
Differential Input Impedance
All Gains
150||1.5
Zin_CM
CM Input impedance
Preamp HG
420||1.7
FSOUT1
Full Scale Voltage Swing
Preamp LG
Main Output, Clamped, 0 dB Ladder
FSOUT3
Auxiliary Output, THD @ 100 MHz ≤
−40 dBc All Gains
FSOUT4
Auxiliary
Ladder
VOUT_MAX2
Voltage range at each output pin
(clamped)
Units
KΩ ||
pF
900||1.7
770 (8)
Main Output, THD @ 100 MHz ≤
−40 dBc, All Gains
FSOUT2
VOUT_MAX1
Max (3)
Output,
Clamped,0
800
1800
770 (8)
dB
1960
mVPP
800
1600
1760
Main Output, All gains, VCM = 1.2V
0.5
1.8
Auxiliary Output, All Gains,
VCM = 1.2V
0.8
2.2
VOUT_MAX3
Main Output, All Gains, VCM = 1.45V
2.05
VOUT_MAX4
Auxiliary output, All gains,
VCM = 1.45V
2.45
V
ZOUT_DIFF
Differential Output Impedance
All Gains
100
108
Ω
VOOS
Output Offset Voltage
All Gains
±15
±40
mV
VOOS_shift1
Output Offset Voltage Shift
Preamp LG to Preamp HG
13.7
All Gains, Excluding Preamp Step
12.7
Preamp HG, 0 dB Ladder
−24
VOOS_shift2
TCVOOS
Output Offset Voltage Drift (9)
IB
Input Bias Current (10)
VOCM
Output CM Voltage Range
All Gains
VOS_CM
Output CM Offset Voltage
TC_VOS_CM
CM Offset Voltage Temp Coefficient
BAL_Error_DC
Output Gain Balance Error
92
mV
µV/°C
−7
Preamp LG, 0 dB Ladder
+40
+100
+140
µA
1.20
1.45
V
All Gains
±15
±30
All Gains
+55
0.95
mV
µV/°C
−78
'VO_CM
DC,
'VOUT
dB
−45
BAL_Error_AC
250 MHz,
vO_CM
vOUT
PB
Phase Balance Error (See Table 1)
250 MHz
PSRR
Differential Power Supply Rejection(see
Table 1)
Preamp HG, 0 dB Ladder
−60
±0.8
−87
deg
Preamp HG, 0 dB Ladder
−50
−70
PSRR_CM
CM Power Supply Rejection(see
Table 1)
Preamp LG, 0 dB
−55
−71
VCM_I
VCM Input Bias Current (10)
All Gains
±1
±10
±20
VCM_AUX_I
VCM_AUX Input Bias Current (10)
All Gains
±1
±10
±20
dB
dB
nA
(8) Guaranteed by design.
(9) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(10) Positive current is current flowing into the device.
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Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, Input CM = 2.5V, VCM = 1.2V, VCM_Aux = 1.2V, Singleended input drive, VCC = 5V, VDD = 3.3V, RL = 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential
(both Main & Auxiliary Outputs), both Main and Auxiliary Output Specifications, full bandwidth setting, gain = 18.8 dB (Preamp
LG, 0 dB ladder attenuation), Full Power setting (2). Electrical Characteristics Definition of Terms and Specifications for
abbreviations used in the datasheet. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Min (3)
Condition
Typ (4)
Max (3)
Units
Digital I/O & Timing
VIH
Input Logic High
VIL
Input Logic Low
VDD-0.6
V
VOH
Output Logic High
VOL
Output Logic Low
RHi_Z
Output Resistance
I_in
Input Bias Current
FSCLK
SCLK Rate
FSCLK_DT
SCLK Duty Cyle
45
TS
SDIO Setup Time
25
ns
TH
SDIO Hold Time
25
ns
TCES
CS Enable Setup Time
From CS asserted to rising edge of
SCLK
25
ns
tCDS
CS Disable Setup Time
From CS de-asserted to rising edge
of SCLK
25
ns
TIAG
Inter-Acess Gap
3
Cycles
of
SCLK
0.5
VDD
High Impedance Mode
V
V
0
V
5
MΩ
<1
μA
10
50
55
MHz
%
Power Requirements
IS1
Supply Current
VCC
195
210
225
230
mA
IS1_off
VCC Aux off
150
165
170
IDD
VDD
180
350
400
μA
Typ
Max
Units
Bandwidth Limiting Filter Specifications
Filter
Parameter
Condition
Min
20 MHz
Pass Band Tolerance (All Gains)
−3 dB Bandwidth
−0, +20
%
100 MHz
Pass Band Tolerance (All Gains)
−3 dB Bandwidth
−0, +20
%
200 MHz
Pass Band Tolerance (All Gains)
−3 dB Bandwidth
−0, +20
%
350 MHz
Pass Band Tolerance (Preamp LG, 0 dB −3 dB Bandwidth
Ladder)
±10
Pass Band Tolerance (All Gains)
±25
Pass Band Tolerance (Preamp LG, 0 dB −3 dB Bandwidth
Ladder)
±10
Pass Band Tolerance (All Gains)
±25
Pass Band Tolerance (Preamp LG, 0 dB −3 dB Bandwidth
Ladder)
±10
Pass Band Tolerance (All Gains)
±25
650 MHz
750 MHz
6
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Table 1. Definition of Terms and Specifications
1.
AV_CM (dB)
Change in output offset voltage (ΔVOOS) with respect to the change in input common mode
voltage (ΔVI_CM)
2.
AV_DIFF (dB)
Gain with 100Ω differential load
3.
CM
Common Mode
4.
CMRR (dB)
Common Mode rejection defined as: AV_DIFF (dB) - AV_CM (dB)
5.
CMRR_CM
Common
ΔVOOS /ΔVCM
6.
HG
Preamp High Gain
7.
Ladder
Ladder Attenuator setting (0-20 dB)
8.
LG
Preamp Low Gain
9.
Max Gain
Gain = 38.8 dB
10.
Min Gain
Gain = −1.16 dB
11.
+Out
Positive Main Output
12.
−Out
Negative Main Output
13.
+Out Aux
Positive Auxiliary Output
14.
−Out Aux
Negative Auxiliary Output
15.
PB
Phase Balance defined as the phase difference between the complimentary outputs relative to
180°
16.
PSRR
Input referred VOOS shift divided by change in VCC
17.
PSRR_CM
Output common mode voltage change (ΔVO_CM) with respect to VCC voltage change (ΔVCC)
18.
VCM
Input pin voltage that sets Main output CM
19.
VCM_Aux
Input pin voltage that sets Auxiliary output CM
20.
VI_CM
Input CM voltage (average of +IN and −IN)
21.
ΔVIN (V)
Differential voltage across device inputs
22.
VOOS
DC offset voltage. Differential output voltage measured with inputs shorted together to VCC/2
23.
VO_CM
Output common mode voltage (DC average of V+OUT and V−OUT)
24.
VOS_CM
CM offset voltage: VO_CM - VCM
25.
ΔVO_CM
Variation in output common mode voltage (VO_CM)
26.
27.
'VO_CM
'VOUT
ΔVOUT
Mode
rejection
relative
to
VCM
defined
as:
Balance Error. Measure of the output swing balance of “+OUT” and “−OUT”, as reflected on
the output common mode voltage (VO_CM), relative to the differential output swing (VOUT).
Calculated as output common mode voltage change (ΔVO_CM) divided by the output differential
voltage change (ΔVOUT, which is nominally around 700 mVPP)
Change in differential output voltage (Corrected for DC offset (VOOS))
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PIN OUT
Pin Out
Function
P1 = +OUT Aux
Auxiliary positive output
P2 = −OUT Aux
Auxiliary negative output
P3 = VCC (5V)
Analog power supply
P4 = VCC (5V)
Analog power supply
P5 = GND
Ground, electrically connected to the WQFN heat sink
P6 = +IN
Positive Input
P7 = −IN
Negative Input
P8 = GND
Ground, electrically connected to the WQFN heat sink
P9 = CS
SPI interface, Chip Select, Active low
P10 = SDIO
SPI interface, Serial Data Input/Output
P11 = SCLK
SPI interface, Clock
P12 = VDD (3.3V)
Digital power supply
P13 = VCM
Input from ADC to control main output CM
P14 = −OUT
Main negative output
P15 = +OUT
Main positive output
P16 = VCM_Aux
Input to control auxiliary output CM
VCC
VCC
-OUT AUX
+OUT AUX
Connection Diagram
4
3
2
1
6
15 +OUT
-IN
7
14
GND
8
13 VCM
9
10
11
12
VDD
+IN
SCLK
16 VCM_AUX
SDIO
5
CS
GND
-OUT
Figure 1. 16-Pin-Top View
See Package Number RGH0016A
8
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Typical Performance Characteristics
Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL
= 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output
specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full
Power setting (1).
Response (LG, 0 dB)
Phase (LG, 0 dB)
0
5
20 MHz
-50
0
750 MHz
-5
350 MHz
-10
200 MHz
200 MHz
350 MHz
650 MHz
-150
-200
-15
100 MHz
-250
-20
20 MHz
Phase (LG, 0 dB)
-300
-25
1
10
100
1G
1
10
Figure 2.
Small Signal Response (LG, 0 dB)
5
Full BW
Response (HG, 0 dB)
0
NORMALIZED GAIN (dB)
0
750 MHz
-5
650 MHz
-10
350 MHz
200 MHz
-15
100 MHz
-20
Response (LG, 0 dB)
750 MHz
-5
650 MHz
-10
350 MHz
200 MHz
-15
100 MHz
20 MHz
20 MHz
-25
1
10
100
1
1G
10
FREQUENCY (MHz)
100
Figure 5.
Small Signal Response (HG, 0 dB)
Response
vs.
Gain
Response (HG, 0 dB)
3
Full BW
NORMALIZED GAIN (dB)
2
750 MHz
650 MHz
-10
350 MHz
200 MHz
-15
HG, 0 dB
Full BW
VOUT = 0.1 VPP
-5
1G
FREQUENCY (MHz)
Figure 4.
0
NORMALIZED GAIN (dB)
Full BW
VOUT = 0.1 VPP
-20
-25
5
1G
Figure 3.
Response (HG, 0 dB)
5
100
FREQUENCY (MHz)
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
750 MHz
100 MHz
-100
650 MHz
PHASE (°)
NORMALIZED GAIN (dB)
Full BW
Full BW
Response (LG, 0 dB)
100 MHz
HG, 20 dB
1
0
LG, 0 dB
-1
LG, 20 dB
-2
-3
-4
-20
-5
20 MHz
-6
10
-25
1
10
100
1G
FREQUENCY (MHz)
Figure 6.
(1)
100
1G
FREQUENCY (MHz)
Figure 7.
“Full Power” setting is with Auxiliary output turned on.
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Typical Performance Characteristics (continued)
Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL
= 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output
specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full
Power setting (1).
Phase
vs.
Gain
Response Over Temperature
0
2
25°C, HG
Full BW
1
NORMALIZED GAIN (dB)
-50
-150
-200
LG, 0 dB
HG, 20 dB
-250
-300
0
-2
-3
-4
-5
LG, 20 dB
HG, 0 dB
0
200
400
600
85°C, LG
-40°C, HG
-40°C, LG
-1
800
10 dB Ladder
-6
10
1000
Figure 9.
Auxiliary Response Over Temperature
Main
vs.
Auxiliary Response
2
85°C, HG
25°C, HG
1
0
25°C, LG
-1
-40°C, HG
-40°C, LG
-2
Aux, HG
Phase
85°C, LG
NORMALIZED GAIN (dB)
1
NORMALIZED GAIN (dB)
1G
Figure 8.
2
-3
-4
Main, HG
50
0
Main, LG
-50
0
Gain
Aux, LG
-1
-2
-100
-150
Aux, HG
Main, LG
-3
-200
-250
-4
-300
-5
-5
10 dB Ladder
-6
10
-6
10
10 dB Ladder
100
1G
-350
100
FREQUENCY (MHz)
1G
FREQUENCY (MHz)
Figure 10.
Figure 11.
Response
vs.
Gain
Phase
vs.
Gain
0.5
20
All Gains
20 MHz Filter
0
20 MHz Filter
-30
-0.5
PHASE (°)
NORMALIZED GAIN (dB)
100
FREQUENCY (MHz)
FREQUENCY (MHz)
PHASE (°)
PHASE (°)
-100
85°C, HG
25°C, LG
-1
-1.5
-2
LG, 0 dB, 10 dB, 20 dB
-80
HG, 0 dB, 10 dB, 20 dB
-130
-2.5
-180
-3
0
2
4
6
8
10 12 14 16 18 20
Figure 12.
10
0
50
100
150
200
250
300
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13.
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Typical Performance Characteristics (continued)
Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL
= 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output
specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full
Power setting (1).
Response
vs.
Gain
Phase
vs.
Gain
1
0
HG, 0 dB
650 MHz Filter
-50
HG, 20 dB
-1
-100
LG, 0 dB
-2
PHASE (°)
NORMALIZED GAIN (dB)
0
LG, 20 dB
-3
-150
-200
LG, 0 dB
-4
HG, 20 dB
-250
-5
LG, 20 dB
HG, 0 dB
650 MHz Filter
-6
-300
100
10
1G
0
200
400
600
800
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14.
Figure 15.
Balance Error
Linear Phase Deviation and Group Delay
-10
1
15
18
10
15
-40
-3
-60
-4
1
10
100
1G
-7
10
100
FREQUENCY (MHz)
Figure 17.
Noise
vs.
Ladder Attenuation
Noise
vs.
Ladder Attenuation
f = 10 MHz
Preamp HG
2.1
1.7
60
1.5
1.3
40
1.1
0.9
20
Input Referred
Output Referred
0.5
6
8
45
f = 10 MHz
Preamp LG
16
1.9
0
1000
18
100
80
4
1
Figure 16.
2.3
2
-15
3
Group Delay
FREQUENCY (MHz)
2.5
0
9
6
-10
-6
0.7
0
-5
INPUT REFERRED (nV/ Hz)
-90
12
Linear Phase Deviation
-5
Gain
-80
Hz)
PHASE (°)
-50
-70
INPUT REFERRED (nV/
5
-2
LG, 0 dB
0
10 12 14 16 18 20
LADDER ATTENUATION (dB)
40
14
35
12
30
10
25
8
20
6
15
4
10
Input Referred
2
0
GROUP DELAY (ns)
-1
5
Output Referred
0
2
4
6
8
10 12 14 16 18 20
OUTPUT REFERRED (nV/ Hz)
0
-30
PHASE (°)
-20
OUTPUT REFERRED (nV/ Hz)
GAIN (dB)
Phase
0
LADDER ATTENUATION (dB)
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL
= 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output
specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full
Power setting (1).
Input Voltage Noise
vs.
Frequency
1000
28
26 f = 10 MHz
24 RS = 50: on each input
22
20
18
16 Preamp LG
14
12
10
8
6
4
2
0
10
0
5
VOLTAGE NOISE (nV/ Hz)
NOISE FIGURE (dB)
Noise Figure
vs.
Gain
100
LG, 20 dB
10
LG, 0 dB
HG, 20 dB
1
HG, 0 dB
Preamp HG
0
15
1
20
100
10
LADDER ATTENUATION (dB)
Figure 21.
Input Current Noise
vs.
Frequency
HD2
vs.
Ladder Attenuation
10 MHz
20 MHz
-65
-60
10
HD (dBc)
CURRENT NOISE (pA/ Hz)
1M
-75
-70
LG
50 MHz
-55 100 MHz
-50
250 MHz
-45 500 MHz
HG
-40
-35
1
LG
-30
1
10
1k
100
10k
100k
0
1M
4
FREQUENCY (kHz)
12
16
Figure 22.
Figure 23.
HD3
vs.
Ladder Attenuation
HD2
vs.
Ladder Attenuation
-70
LG
20
20 MHz
10 MHz
-65
-80
10 MHz
-60
HD (dBc)
20 MHz
-75
-70
250 MHz
-65
-60
8
LADDER ATTENUATION (dB)
-85
HD (dBc)
100k
10k
Figure 20.
100
250 MHz
-55
50 MHz
100 MHz
-50
-45
500 MHz
500 MHz
-55
-40
50 MHz
-35
100 MHz
HG
-30
-50
0
12
1k
FREQUENCY (kHz)
4
8
12
16
20
0
4
8
12
16
LADDER ATTENUATION (dB)
LADDER ATTENUATION (dB)
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL
= 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output
specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full
Power setting (1).
HD3
vs.
Ladder Attenuation
Main and Auxiliary Distortion Comparison
-75
-85
HG
HG, 65 MHz
HARMONIC DISTORTION (dBc)
10 MHz
-70
HD (dBc)
20 MHz
-65
250 MHz
100 MHz
-60
500 MHz
-55
50 MHz
-50
0
4
8
12
16
-80
Aux
HD2
-75
Main
-70
-65
HD3
Aux
-60
-55
-50
20
0
LADDER ATTENUATION (dB)
4
8
12
16
Figure 26.
Figure 27.
Main and Auxiliary Distortion Comparison
Distortion
vs.
Output Power
-95
-85
HD3
-80
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
LG, 65 MHz
-90
-85
Main
Aux
-75
-70
-65
-60
HD2
-55
4
8
HG, 10 dB
65 MHz
-83
-81
HD2
-79
-77
HD3
-75
-73
-71
-69
-67
Aux
-50
0
12
16
-65
20
-7
-6
-5
-4
-3
-2
-1
LADDER ATTENUATION (dB)
OUTPUT POWER (dBFS)
Figure 28.
Figure 29.
Gain
vs.
Ladder Attenuation
Gain Accuracy
vs.
Ladder Attenuation
0
0.25
42
-40°C to 85°C
HG
38
-40°C
LG
0.2
25°C
GAIN ACCURACY (dB)
34
30
26
GAIN (dB)
20
LADDER ATTENUATION (dB)
22
LG
18
14
10
0.15
85°C
0.1
-40°C
0.05
25°C
0
85°C
-0.05
6
HG
-0.1
2
Relative to HG/0 dB @ 25°C
-0.15
-2
0
4
8
12
16
0
20
4
8
12
16
20
LADDER ATTENUATION (dB)
LADDER ATTENUATION (dB)
Figure 30.
Figure 31.
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Typical Performance Characteristics (continued)
Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL
= 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output
specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full
Power setting (1).
Auxiliary Gain Accuracy
vs.
Ladder Attenuation
0.25
-0.088
-40°C
LG
0.2
Aux Gain ± Main Gain
25°C
-0.089
0.15
85°C
-0.09
0.1
0.05
GAIN (dB)
GAIN ACCURACY (dB)
Gain Matching
vs.
Ladder Attenuation
-40°C
25°C
0
LG
-0.091
-0.092
85°C
-0.05
HG
-0.093
HG
-0.1
Relative to HG/0 dB @ 25°C
-0.15
-0.094
0
4
8
12
16
20
0
4
LADDER ATTENUATION (dB)
Figure 32.
AV_CM
16
20
AV_CM
20
LG, 0 dB
LG, 0 dB
LG, 20 dB
10
LG, 20 dB
10
0
0
VOOS (mV)
VOOS (mV)
12
Figure 33.
20
-10
8
LADDER ATTENUATION (dB)
HG, 20 dB
HG, 0 dB
-20
-30
-10
HG, 20 dB
-20
HG, 0 dB
-30
-40
-40
-40°C
-50
1.5
25°C
5
2.5
3
-50
1.5
3.5
5
2.5
VI_CM
VI_CM
Figure 34.
Figure 35.
AV_CM
−1 dB Compression
vs.
Ladder Attenuation
20
2.0
3.5
LG
LG, 0 dB
1.9
LG, 20 dB
10
3
1.8 HG
1.7 Aux, LG
VOUT (VPP)
VOOS (mV)
0
-10
HG, 20 dB
-20
HG, 0 dB
1.6
Aux, HG
1.5
1.4
1.3
-30
1.2
-40
-50
1.5
5
2.5
3
3.5
VI_CM
1.0
0
4
8
12
16
20
LADDER ATTENUATION (dB)
Figure 36.
14
f = 250 MHz
RL = 100
1.1
85°C
Figure 37.
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Typical Performance Characteristics (continued)
Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL
= 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output
specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full
Power setting (1).
Step Response
Step Response
0.4
0.4
0.3 HI to LO
0.3 HI to LO
LO to HI
0.1
0
LO to HI
0.2
Output
VOUT (V)
VOUT (V)
0.2
Input = 20 mV/DIV
LG, 0 dB
Input
-0.1
0.1
0
Output
Input = 20 mV/DIV
HG, 20 dB
Input
-0.1
LO to HI
-0.2
LO to HI
-0.2
HI to LO
-0.3
HI to LO
-0.3
-0.4
-0.4
TIME (1 ns/DIV)
TIME (1 ns/DIV)
Figure 38.
Figure 39.
Step Response
Step Response
0.4
LO to HI
HI to LO
LO to HI
0.2
0.2
Input = 0.2V/DIV
LG, 20 dB
Input
VOUT (V)
0.3 HI to LO
0.1
VOUT (V)
0.3
0.4
Output
0
LO to HI
-0.1
Output
-0.1
-0.2
-0.3
HI to LO
-0.3
-0.4
-0.4
TIME (1 ns/DIV)
TIME (1 ns/DIV)
Figure 40.
Figure 41.
Output Offset Voltage (Typical Unit 1)
Output Offset Voltage (Typical Unit 2)
20
20
15
15
-40°C
LG
10
10
5
VOOS (mV)
VOOS (mV)
Input = 2 mV/DIV
HG, 0 dB
Input
0
LO to HI
HI to LO
-0.2
0.1
HG
0
85°C
25°C
-5
5
-10
-15
-15
0
4
8
12
16
20
HG
85°C
-5
-10
-20
25°C
0
LG
-40°C
-20
0
4
8
12
16
LADDER ATTENUATION (dB)
LADDER ATTENUATION (dB)
Figure 42.
Figure 43.
20
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Typical Performance Characteristics (continued)
Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL
= 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output
specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full
Power setting (1).
VOS_CM
vs.
VCM
Output Offset Voltage (Typical Unit 3)
20
5
HG
15
3
85°C
1
10
-1
-40°C
VOS_CM (mV)
VOOS (mV)
25°C
5
0
LG
-5
85°C
25°C
-3
-5
-7
-40°C
-9
-10
-11
-15
-13
-20
0
4
8
12
16
-15
0.7
20
1.3
1.5
Figure 44.
Figure 45.
Supply Current
vs.
Supply Voltage
Supply Current
vs.
Supply Voltage
0.22
220
0.2
215
1.7
0.18
IDD (mA)
ICC (mA)
1.1
VCM (V)
225
-40°C
25°C
210
0.9
LADDER ATTENUATION (dB)
85°C
0.16
205
0.14
200
0.12
85°C
25°C
195
4.5
4.7
4.9
5.1
5.3
-40°C
0.1
2.8
5.5
2.9
3
3.1
VCC (V)
Figure 46.
3.6
RL = 100:
2200 VCM_Aux = 1.2V
AUXILIARY VOLTAGE (mV)
INPUT BIAS CURRENT (mA)
3.5
Auxiliary Output Voltage (Hi-Z Mode)
0.18
0.16
0.14
0.12
0.1
85°C
0.06
25°C
0.04
-40°C
No CM Load
2000 +OUT Aux and -OUT Aux
85°C
1800
25°C
1600
1400
-40°C
1200
0.02
2
2.5
3
3.5
1000
4.5
4.7
4.9
5.1
5.3
5.5
VCC (V)
VI_CM (V)
Figure 48.
16
3.4
2400
0.2
0
1.5
3.3
Figure 47.
Input Bias Current
vs.
Input CM
0.08
3.2
VDD (V)
Figure 49.
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Typical Performance Characteristics (continued)
Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL
= 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output
specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full
Power setting (1).
Filter BW
vs.
Gain
Output
vs.
Input
1600
-40°C
750 MHz
15
LG
10
5
650 MHz
750 MHz
350 MHz
0 350 MHz
-5
Main or Auxiliary Output
LG, 20 dB
1500
HG
20
OUTPUT VOLTAGE (V)
ERROR from NOMINAL FILTER BW (%)
25
650 MHz
1400
25°C, 85°C
+OUT
25°C, 85°C
-OUT
1300
1200
1100
1000
900
-40°C
-10
-5
0
5
10
15
20
25
30
35
800
-1
40
-0.6
GAIN (dB)
Figure 51.
Output
vs.
Input
Output
vs.
Input
1600
Main or Auxiliary Output
LG, 0 dB
-40°C
25°C
85°C
+OUT
1200
-OUT
1000
-40°C
800
600
-100
-60
-20
20
60
1400
1300
25°C, 85°C
+OUT
25°C, 85°C
-OUT
1200
1100
1000
800
-100
100
-60
-20
20
60
100
DELTA-VIN (mV)
Figure 52.
Figure 53.
Output
vs.
Input
Overdrive Recovery Time (Return to Zero)
1.5
Main or Auxiliary Output
HG, 0 dB
-40°C
1600
-40°C
DELTA-VIN (mV)
1800
0 dB Ladder Attenuation
50% Overdrive
Preamp HG or LG
1.0
25°C
1400
+OUT
85°C
ERROR (%)
OUTPUT VOLTAGE (V)
1
900
25°C, 85°C
1200
1000
0.6
Main or Auxiliary Output
HG, 20 dB
-40°C
1500
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1600
0.2
Figure 50.
1800
1400
-0.2
DELTA-VIN (V)
-OUT
-40°C
0.5
0
-0.5
800
-1.0
25°C, 85°C
600
-10
-6
-2
2
6
10
DELTA-VIN (mV)
-1.5
0
100
200
300
400
500
TIME (ns)
Figure 54.
Figure 55.
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Typical Performance Characteristics (continued)
Unless otherwise specified, Input CM = 2.5V, VCM = 1.2V, VCM AUX = 1.2V, Single-ended input drive, VCC = 5V, VDD = 3.3V, RL
= 100Ω differential (both Main & Auxiliary Outputs), VOUT = 0.7 VPP differential (both Main and Auxiliary Outputs), Main output
specification (Auxiliary is labeled “Auxiliary”), full bandwidth setting, gain = 18.8 dB (Preamp LG, 0 dB ladder attenuation), Full
Power setting (1).
Overdrive Recovery Time (Return to Zero)
1.5
20 dB Ladder Attenuation
50% Overdrive
Preamp HG or LG
ERROR (%)
1.0
0.5
0
-0.5
-1.0
-1.5
0
100
200
300
400
500
TIME (ns)
Figure 56.
18
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APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION AND DYNAMIC RANGE IN OSCILLOSCOPE APPLICATIONS
Here is a block diagram of the LMH6518’s Main Output signal path:
50:
+In
Ladder Attenuator
10 Steps, 2 dB/ Step
Pre-amp
10 dB or 30 dB
0 to -20 dB
-In
+Out
Output
Amp
8.86 dB
-Out
50:
Figure 57. LMH6518 Signal Path Block Diagram
The Auxiliary output (not shown) uses another but similar Output Amp that taps into the Ladder Attenuator
output. In this document, Preamp gain of 30 dB is referred to as “Preamp HG” (High Gain) and Preamp gain of
10 dB as “Preamp LG” (Low Gain).
The LMH6518’s 2 dB/step gain resolution and 40 dB adjustment range (from −1.16 dB to 38.8 dB) allows this
device to be used with the National GSample/second ADCs which have Full Scale, FS, adjustment (through their
Extended Control Mode or ECM) to provide near-continuous variability (8.5 mdB resolution) to cover a 42.6 dB
(20 x log
920 mVPP
6.8 mVPP
= 42.6 dB)
(1)
FS input range. The National Semiconductor GSample/second ECM control allows the ADC FS to be set using
the ADC SPI bus. The ADC FS voltage range is from 560 mV to 840 mV with 9 bits of FS voltage control.
The ADC ECM gain resolution can be calculated as follows:
0.56 ±
§
¨
¨
©
Gain Resolution = 20 log
0.84 ± 0.56
2 x 512
§
¨
¨
©
§ 0.84 ± 0.56
¨
¨
© 2 x 512
§
¨
¨
©
0.56 +
= 8.5 mdB
(2)
The recommended ADC FS operating range is, however, narrower and it is from 595 mV to 805 mV with 700
mVPP as the mid-point. Raising the value of ADC FS voltage is tantamount to reducing the signal path gain to
accommodate a larger input and vice versa, thus providing a method of gain fine-adjust. The ADC ECM gain
adjustment is −1.21 dB
(= 20 x log
700 mV
) to +1.41 dB
805 mV
(= 20 x log
700 mV
)
595 mV
(3)
Because the ADC FS fine-adjust range of 2.62 dB (= 1.41 dB + 1.21 dB) is larger than the LMH6518’s 2 dB/step
resolution, there is always at least one LMH6518 gain setting to accommodate any FS signal from 6.8 mVPP to
920 mVPP, at the LMH6518 input, with 0.62 dB (= 2.62-2) overlap.
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Assuming a nominal 0.7VPP output, the LMH6518’s minimum FS input swing is limited by the maximum signal
path gain possible and vice versa:
0.7 VPP
Minimum LMH6518 FS Input = (38.8 + 1.41) dB = 6.8 mVPP
10
20
(4)
(or 8 mVPP with no ADC fine adjust)
Maximum LMH6518 FS Input =
10
0.7 VPP
(-1.16 ± 1.21) dB
20
= 920 mVPP
(5)
(or 800 mVPP with no ADC FS adjust)
To accommodate a higher FS input, an additional attenuator is needed before the LMH6518. This front-end
attenuator is shown in the Figure 62 with its details shown in Figure 71. The highest minimum attenuation level is
determined by the largest FS input signal (FSmax):
FSMAX (VPP)
Attenuation (dB) = 20 x log
800 mVPP
(6)
So, to accommodate 80 VPP, 40 dB minimum attenuation is needed before the LMH6518.
In a typical oscilloscope application, the voltage range encountered is from 1 mV/DIV to 10 V/DIV with 8 vertical
divisions visible on the screen. One of the primary concerns in a digital oscilloscope is SNR which translates to
display trace width/ thickness. Typically, oscilloscope manufacturers need the noise level to be low enough so
that the “no-input” visible trace width is less than 1% of FS. Experience has shown that this corresponds to a
minimum SNR of 52 dB.
The factors that influence SNR are:
• Scope front end noise (Front-end attenuator + scope probe Hi-Z buffer which is discussed later in this
document and shown in Figure 62)
• LMH6518
• ADC
LMH6518 related SNR factors are:
• Bandwidth
• Preamp used (Preamp High Gain or Low Gain)
• Ladder Attenuation
• Signal level
SNR increases with the inverse square root of the bandwidth. So, reducing bandwidth from 450 MHz to 200
MHz, for example, improves SNR by 3.5 dB
(20 x log
450 MHz
= 3.5 dB)
200 MHz
(7)
The other factors listed above, preamp and ladder attenuation, depend on the signal level and also impact SNR.
The combined effect of these factors is summarized in Figure 58 where SNR is plotted as a function of the
LMH6518 FS input voltage (assuming scope bandwidth of 200 MHz) and not including the ADC and the front end
noise:
20
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22
20
58
18
56
16
54
14
52
12
50
10
48
8
46
6
44
4
42
2
40
38
0.001
Preamp LG
0
-2
Preamp HG
0.01
0.1
LADDER ATTENUATION (dB)
SNR (dBFS)
62
60 200 MHz Filter
1
INPUT FS (V)
Figure 58. LMH6518 SNR & Ladder Attenuation used vs. Input
As can be seen from Figure 58, SNR of at least 52 dB is maintained for FS inputs above 24 mVPP (3 mV/DIV on
a scope) assuming the LMH6518’s internal 200 MHz filter is enabled. Most oscilloscope manufacturers relax the
SNR specifications to 40 dB for the highest gain (lowest scope voltage setting). From Figure 58, LMH6518’s
minimum SNR is 43.5 dB, thereby meeting the relaxed SNR specification for the lower range of scope front panel
voltages.
In Figure 58, the step-change in SNR near Input FS of 90 mVPP is the transition point from Preamp LG to
Preamp HG with a subsequent 3 dB difference due to the Preamp HG/ 20 dB ladder attenuation’s lower output
noise compared to Preamp LG/ 2 dB ladder attenuation’s noise. Judicious choice of front end attenuators can
ensure that the 52 dB SNR specification is maintained for scope FS inputs ≥ 24 mVPP by confining the LMH6518
gain range to the lower 30.5 dB
(= 20 x log
0.8 VPP
)
24 mVPP
(8)
from the total range of 40 dB (= 38.8 - (−1.16)) possible.
Here is an example:
To cover the range of 1 mV/DIV to 10 V/DIV (80 dB range), here is a configuration which affords good SNR:
Table 2. Oscilloscope Example Including Front-End Attenuators
Row
Scope FS Input
(VPP)
“S”, Scope Vertical
Scale (V/DIV)
Preamp
Ladder Attenuation
Range (dB)
“A”, Front-end
attenuation (V/V)
Minimum SNR (dB)
with 200 MHz filter
1
8m-24m
1m-3m
HG
0-10
1
44
2
24m-80m
3m-10m
HG
10-20
1
52.0
3
80m-0.8
10m-0.1
LG
0-20
1
53.4
4
0.8-8
0.1-1
LG
0-20
10
53.4
5
8-80
1-10
LG
0-20
100
53.4
In Table 2, the highest FS input in Row 5, Column 2 (80 VPP), and the LMH6518’s highest FS input allowed (0.8
VPP) set the
80 VPP
)
100x (=
0.8 VPP
(9)
front-end attenuator value. The 100x attenuator will allow high SNR operation to 30.5 dB down, as explained
earlier, or 2.4 VPP at scope input. In that same table, Rows 1-3 with no front-end attenuation (1x) cover the scope
FS input range from 8 mVPP-800 mVPP. That leaves the scope FS input range of 0.8 VPP-2.4 VPP. If the 100x
attenuator were used for the entire scope FS range of 0.8 VPP-80 VPP, SNR would dip below 52 dB for a portion
of that range. Another attenuation level is thus required to maintain the SNR specification requirement of 52 dB.
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One possible attenuation partitioning is to select the additional attenuator value to cover a 20 dB range above 0.8
VPP FS (to 8 VPP) with the 100x attenuator covering the remaining 20 dB range from 8 VPP to 80 VPP. Mapping 8
VPP FS scope input to 0.8 VPP at LMH6518 input means the additional attenuator is 10x, as shown in Table 2,
Row 4. The remaining scope input range of 8 VPP-80 VPP would then be covered by the 100x front-end
attenuator derived earlier. The entire scope input range is now covered with SNR maintained about 52 dB for
scope FS input ≥ 24 mVPP, as shown in Table 2.
SETTINGS AND ADC SPI CODE (ECM)
Covering the range from 1 mV/DIV to 10 V/DIV requires the following to be adjusted within the digital
oscilloscope:
• Front-End Attenuator
• LMH6518 Preamp
• LMH6518 Ladder Attenuation
• ADC FS Value (ECM)
The LMH6518 Product Folder contains a spreadsheet which allows one to calculate the front-end attenuator,
LMH6518 Preamp gain (HG or LG) and ladder attenuation, and ADC FS setting based on the scope vertical
scale (S in V/DIV).
Here is the step by step procedure that explains the operations performed by the said spreadsheet based on the
scope vertical scale setting (S in V/div) and front-end attenuation “A” (from Table 2). A numerical example is also
worked out for more clarification:
1. Determine the required signal path gain, K:
0.95 x 700 mVPP
A
K = 20 x log
= -21.6 + 20 x log
8 x S(V/div)
S(V/div)
A
(10)
assuming the full scale signal occupies 95% of the 0.7 VPP FS (for 5% overhead) which occupies 8 vertical
scope divisions).
Required condition: −2.37 dB ≤ K ≤ 40.3 dB
Example: With S = 110 mV/DIV, Table 2 shows that A = 10 V/V:
10
o K = -21.6 + 20 x log 110 mV = 17.57 dB
(11)
2. Determine the LMH6518 gain, G:
– G is the closest LMH6518 gain, to the value of K where:
– G = (38.8 – 2n)dB; n = 0, 1, 2, …, 20
– For this example, the closest G to K = 17.57 dB is 16.8 dB (with n = 11). The next LMH6518 gain, 18.8
dB (with n = 10) would be incorrect as 16.8 is closer. If 18.8 dB were mistakenly chosen, the ADC FS
setting would be out of range.
– Therefore: G = 16.8 dB
3. Determine Preamp (HG or LG) & Ladder Attenuation:
– If G ≥ 18.8 dB → Preamp is HG and Ladder Attenuation = 38.8 - G
– If G < 18.8 dB → Preamp is LG and Ladder Attenuation = 18.8 - G
– For this example, with G = 16.8 → Preamp LG and Ladder Attenuation = 2 dB (= 18.8-16.8).
4. Determine the required ADC FS voltage, FSE:
G
Sx8
20
x 1.05 x 10
FSE =
A
22
(12)
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The “1.05” factor is to add 5% FS overhead margin to avoid ADC overdrive.
16.8
Sx8
x 1.05 x 1020 = 639.3 mV
FSE =
10
(13)
Required condition: 0.56V ≤ FSE ≤ 0.84V
Recommend condition: 0.595V ≤ FSE ≤ 0.805V for optimum ADC FS
5. Determine the ADC ECM code ratio:
FSE - 0.56
ECM (ratio) =
0.28
where
•
•
•
0.28V= (0.84-0.56)V
0.56V is the lower end of the ADC FS adjustability
For this example:
ECM (ratio) =
0.6393 - 0.56
= 0.283
0.28
(14)
– Required condition: 0 ≤ ECM (ratio) ≤ 1
6. Determine the ECM binary code to be sent on ADC SPI bus:
– Convert the ECM value represented by the ratio calculated above, to binary:
– ECM (binary) = DEC2BIN{ECM(ratio)* 511, 9}
– Where “DEC2BIN” is a spreadsheet function which converts the decimal ECM ratio, from step 5 above,
multiplied by 511 distinct levels, into binary 9 bits.
NOTE
The Web based spreadsheet computes ECM without the use of “DEC2BIN” function to
ease usage by all spreadsheet users who may not have this function installed.
– For this example: ECM (binary) = DEC2BIN(0.283*511, 9) = 010010000. This would be the number to be
sent to the ADC on the SPI bus to program the ADC to the proper FS voltage.
INPUT/OUTPUT CONSIDERATIONS
The LMH6518’s ideal Input/Output Conditions, considered individually, are listed below:
Table 3. LMH6518's Ideal Input/Output Conditions
Impedance from
each input to
ground (Ω)
Common Mode
Input (V)
Differential Input
(VPP)
Load Impedance (Ω)
Differential Output
(V)
Common Mode
Output (V)
≤50
1.5 to 3.1
<0.8
100 (differential)/ 50
(single ended)
<0.77
0.95-1.45
In addition to the individual conditions listed in Table 3, the Input/Output terminal conditions should match
differentially (i.e. +IN to −IN and +OUT to −OUT), as well, for best performance.
The input is differential but can be driven single-ended as long as the conditions of Table 3 are met and there is
good matching between the driven and the undriven inputs from DC to the highest frequency of interest. If not,
there could be a settling time impact among other possible performance degradations. The datasheet
specifications are with single-ended input, unless specified. Here is the recommended bench-test schematic to
drive one input and to bias the other input with good matching in mind:
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C1
1 nF
J1
Input (from 50: source)
(2.5V CM)
+IN
R1
+5V
R2
R5
100:
LMH6518
49.9:
200:
-IN
R4
C2
200:
R3
1 nF
24.9:
Figure 59. Recommended Single-Ended Bench-Test Input Drive from 50Ω Source
With the schematic of Figure 59, each LMH6518 input sees 25Ω to ground at the higher frequencies when the
capacitors look like shorts. This impedance increases to 125Ω at DC for both inputs, thereby preserving the
required matching at any frequency. This configuration, using properly selected R’s and C’s, allows four times
less biasing power dissipation than when the undriven input is biased with an effective 25Ω from the LMH6518
input to ground.
It is possible to drive the LMH6518 input from a ground referenced 50Ω source by providing level shift circuitry
on the driven input. Figure 60 shows a circuit where ½ the input signal reaches the LMH6518 input while the
negative supply voltage (VEE) ensures that the 50Ω source at J1 does not experience any biasing current while
providing 50Ω termination to the source. The driven input (+IN) is biased to 2.5V (VCC/2):
R1
63.4:
+5V
+IN
R2
J1
Input (from 50: source)
(Ground Referenced)
63.4:
LMH6518
R5
76.8:
R3
-IN
82.5:
R4
VEE
76.8:
(-3.3V)
Figure 60. LMH6518 Driven by a Ground Referenced Source
In the schematic of Figure 60, the equivalent impedance from each LMH6518 input to ground is around 38Ω.
This configuration’s power consumption of ∼0.5W (in R1 - R5) is higher than that of Figure 59 because of
additional power dissipated to perform the level shifting. Additional 50Ω attenuators can be placed between J1
and R2/R3 junction in Figure 60 in order to accommodate higher input voltages.
It is also possible to shift the LMH6518 output common mode level using a level shift approach similar to that of
Figure 60. The circuit in Figure 61 shows an implementation where the LMH6518’s nominal 1.2V CM output, set
by a 1.2V on VCM input from the Gsample/s ADC, is shifted lower for proper interface to different ADC's which
require VCM = 0V and have high input impedance:
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0.43 VPP, 1.2V DC
+5V
-5V
0.35 VPP, 0V DC
R1
R3
0.7 VPP, 1.2V DC
50:
+OUT
Vx
R2
VOUT
To ADC
R2
41.4:
50:
-OUT
LMH6518
R3
R1
131.3:
172.7:
+5V
-5V
Figure 61. Output CM Shift Scheme
With the scheme of Figure 61, Vx is kept at 1.2V, by proper selection of external resistor values, so that the
LMH6518 outputs are not CM-loaded. As was the case with input level shifting, this output level shifting also
consumes additional power (0.58W).
Output Swing, Clamping, and Operation Beyond Full Scale
One of the major concerns in interfacing to low voltage ADC’s (such as the Gsample/s ADC’s that the LMH6518
is intended to drive) is ensuring that the ADC input is not violated with excessive drive. For this reason, plus the
very important requirement of an oscilloscope to recover quickly and gracefully from an overdrive condition, the
LMH6518 is fitted with three overvoltage clamps; one at the Preamp output and one at Main and Auxiliary
outputs each. The Preamp clamp is responsible for preventing the Preamp from saturation (to minimize recovery
time) with large ladder attenuation when Preamp output swing is at its highest. On the other hand, the output
clamps, perform this function when the Ladder attenuation is lower and hence the output amplifier is closer to
saturation, and prolonged recovery, if not properly clamped. The combination of these clamps results in
Figure 51, Figure 52, Figure 53, and Figure 54 where it is possible to observe where output limiting starts due to
the clamp action. LMH6518 owes its fast recovery time (< 5 ns) from 50% overdrive to the said clamps.
Figure 51, Figure 52, Figure 53, and Figure 54, in Typical Performance Characteristics, can be used to determine
the LMH6518 linear swing beyond full scale. This information sets the overdrive limit for both oscilloscope
waveform capture and for signal triggering. The Preamp clamp is set tighter than the output clamp, evidenced by
lower output swing with 20 dB Ladder attenuation than with 0 dB. With high ladder attenuation (20 dB) defining
the limit, the graphs show that the “+Out” and “−Out” difference of 0.4V is well inside the clamp range, thereby
ensuring 0.8 VPP of unhindered output swing. This corresponds to an overdrive capability of approximately ±7%
beyond full scale.
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Here is a block diagram for how the LMH6518 is used in an oscilloscope:
Attenuation = 10x
J1
Oscilloscope
Input
>
Switch
VCC
Attenuation = 1x
JFET Lo-Noise
Amp
900 k:
LNA
+IN
90 k:
Channel 1
50:
10 k:
Hi-Z/50:
Switch
+OUT
+IN 1
-OUT
-IN 1
LMH6518
U1
VCM
Attenuation = 100x
-IN
Attenuator
Block
DAC
FPGA
or
MPU
SPI
VCMO
+OUT Aux
Gsample/sec
8-Bit ADC
-OUT Aux
VCM_Aux
Trigger
Circuit
SPI (Full Scale
Voltage Control)
Fine Gain Adjust
VCC
200:
1 nF
200:
Figure 62. Digital Oscilloscope Front-End
From Figure 62, the signal path consists of the input impedance switch, the attenuator switch, Low Noise
Amplifier (LNA, JFET amplifier) to drive the LMH6518 input (+IN), and the DAC to provide offset adjust. The LNA
must have the following characteristics:
• Set U1’s common mode level to VCC/2 (∼2.5V)
• Very low drift (1 mV shift at LNA output could translate into 88 mV shift at LMH6518 output at max gain, or
∼13% of FS).
• Low output impedance (≤ 50Ω) to drive U1, for good settling behavior
• Low Noise (<0.98 nV/√Hz) to reduce the impact on the LMH6518 Noise Figure. Note that Figure 62 does not
show the necessary capacitors across the resistors in the front-end attenuators (see Figure 71). These
capacitors provide frequency response compensation and limit the noise contribution from the resistors so
that they do not impact the signal path noise. For more information about front-end attenuator design,
including frequency compensation, see REFERENCE for additional resources.
• Gain of 1 V/V (or very close to 1 V/V)
• Excellent frequency response flatness from DC to > 500-800 MHz to not impact the time domain performance
The undriven input (−IN) is biased to VCC/2 using a voltage driver. The impedance driving the LMH6518’s −IN
should be closely matched to the LNA’s output impedance for good settling time performance.
APPENDIX A shows one possible implementation of the LNA buffer along with performance data.
When the LMH6518’s Auxiliary output is not used, it is possible to disable this output using SPI-1 (see LOGIC
FUNCTIONS for SPI register map). Electrical Characteristics shows that by doing so, device power dissipation
decreases by the reduction in supply current of about 60 mA. As can be seen in Figure 63, in the absence of
heavy common loading, the Auxiliary output will be at a voltage close to 1.7V (VCC = 5V). With higher supply
voltages, the Auxiliary voltage will also increase and it is important to make sure any circuitry tied to this output is
capable of handling the 2.3V possible under VCC worst case condition of 5.5V.
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2400
RL = 100:
AUXILIARY VOLTAGE (mV)
2200 VCM_Aux = 1.2V
No CM Load
2000 +OUT Aux and -OUT Aux
85°C
1800
25°C
1600
1400
-40°C
1200
1000
4.5
4.7
4.9
5.1
5.3
5.5
VCC (V)
Figure 63. Auxiliary Output Voltage as a Function of VCC
LOGIC FUNCTIONS
The following LMH6518 functions are controlled using the SPI-1 compatible bus:
• Filters (20, 100, 200, 350, 650, 750 MHz or full bandwidth)
• Power Mode (Full Power or Auxiliary Hi-Z (high impedance)
• Preamp (HG or LG)
• Attenuation Ladder (0-20 dB, 10 states)
• LMH6518 state “Write” or “Read” back
The SPI-1 bus uses 3.3V logic. “SDIO” is the serial digital input-output which can write to the LMH6518 or read
back from it. “SCLK” is the bus clock with chip select function controlled by “CS”
SPI-1 PIN DESCRIPTIONS
Pin Name
Type
Function and Connection
CS
Input
Serial Chip Select: While this signal is asserted SCLK is used to accept serial data
present on SDIO and to source serial data on SDIO. When this signal is de-asserted,
SDIO is ignored and SDIO is in TRI-STATE mode.
SCLK
Input
Serial Clock: Serial data are shifted into and out of the device synchronous with this
clock signal. SCLK transitions with CS de-asserted are ignored. SCLK to be stopped
when not needed to minimize digital crosstalk.
SDIO
Input-Output
Serial Data-In or Data-out: Serial data are shifted into the device (8 bit Command and 16
bit Data) on this pin while CS signal is asserted during Write operation. Serial data are
shifted out of the device on this pin during a read operation while CS signal is asserted.
At other times, and after one complete Access Cycle (24 bits, see Figure 64 and
Figure 65), this input is ignored. This output is in TRI-STATE mode when CS is deasserted. This pin is bi-directional.
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SCLK
1
2
3
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8
4
24
9
25
CS
Command Field
LMH6518 Bus
in Tri-State
SDIO
XXX
Data Field
C7
C6
C5
C4
C3
C2
C1
C0
1
X
X
X
X
X
X
X
MSB
Inter-Access Gap
LSB
16 bits
D15
D1
D0
LMH6518 Bus
in Tri-State
XXX
Single Access Cycle
Figure 64. Serial Interface Protocol- Read Operation
SCLK
1
2
3
8
4
24
9
25
CS
Command Field
LMH6518 Bus
in Tri-State
SDIO
XXX
Data Field
C7
C6
C5
C4
C3
C2
C1
C0
0
X
X
X
X
X
X
X
MSB
DI5
LSB
16 bits
D1
D0
Inter-Access Gap
LMH6518 Bus
in Tri-State
XXX
Single Access Cycle
Figure 65. Serial Interface Protocol- Write Operation
SCLK
Tod
SDIO
Valid
Data
Valid
Data
Figure 66. Read Timing
SCLK
Tsu
SDIO
Th
Valid
Data
Figure 67. Write Timing
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Table 4. Data Field
Filter
D15
(MSB)
D14
D13
D12
D11
X
0
0
0
0
D10
D9
0=Full Power
1=Aux Hi-Z
0
D8
D7
Pre-amp
D6
D5
D4
0
0=LG
1=HG
See Table 6
Ladder Attenuation
D3
D2
D1
D0
(LSB)
See Table 7
NOTE
Bits D5, D9, D11-D14 must be “0”. Otherwise, device operation is undefined and
specifications are not guaranteed.
Table 5. Default Power-On Reset Condition
Filter
Pre-amp
Ladder Attenuation
D15
(MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
Table 6. Filer Selection Data Field
Filter
Filter BW
D8
D7
D6
(MHz)
0
0
0
Full
0
0
1
20
0
1
0
100
0
1
1
200
1
0
0
350
1
0
1
650
1
1
0
750
1
1
1
Unallowed
NOTE
All filters are low pass single pole roll-off and operate on both Main and Auxiliary outputs.
These filters are intended as signal path bandwidth and/ or noise limiting.
Table 7. Ladder Attenuation Data Field
Ladder Attenuation
Ladder Attenuation (dB)
D3
D2
D1
D0
0
0
0
0
0
0
0
0
1
−2
0
0
1
0
−4
0
0
1
1
−6
0
1
0
0
−8
0
1
0
1
−10
0
1
1
0
−12
0
1
1
1
−14
1
0
0
0
−16
1
0
0
1
−18
1
0
1
0
−20
1
0
1
1
Unallowed
1
1
0
0
Unallowed
1
1
0
1
Unallowed
1
1
1
0
Unallowed
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Table 7. Ladder Attenuation Data Field (continued)
Ladder Attenuation
1
1
Ladder Attenuation (dB)
1
1
Unallowed
NOTE
An “Unallowed” SPI-1 state may result in undefined operation where device behavior is
not guaranteed.
OSCILLOSCOPE TRIGGER APPLICATIONS
With the Auxiliary output of the LMH6518 offering a second output that follows the Main one (except for a slightly
reduced distortion performance), the oscilloscope trigger function can be implemented by tapping this output. The
“VCM_Aux” input of the LMH6518 allows the Auxiliary common mode to be set. The trigger function can be
physically located at a distance from the main signal path, if need be, by taking advantage of the differential
Auxiliary output and rejecting any board related common mode interference pick-up at the receive end.
If Trigger circuitry is physically close to the LMH6518, the circuit diagram shown in Figure 68 allows operation
using only one of two Auxiliary outputs. The unused output does need to be terminated properly using R1, R11
combination. U3 (DAC101C085) generates a 0- 2.5V trigger level, with 2.4 mV resolution
2.5V
(= 10 )
2
(15)
or 0.7% (= 2.4 mV x 100/0.35 VPP) of FS, which is compared to the LMH6518 “+Out Aux” by using an ultra-fast
comparator, U2 (LMH7220). U2’s complimentary LVDS output is terminated in the required 100Ω load (R10), for
best performance, where the LVDS Trigger output is available. The LMH7220’s offset voltage (±9.5 mV) and
offset voltage drift (±50 µV/°C) error will be 5.9 LSB
(9.5 mV + 50
PV
°C
x 100°C = 1.45 mV { 5.9 LSB)
(16)
of the Trigger DAC (U3). The offset voltage related portion of this error can be nulled-out, if necessary, during the
oscilloscope initial calibration. To do so, the LMH6518 input is terminated properly with no input applied and U3
output is adjusted around VCM_Aux voltage (1.2V ±10 mV) while looking for U2’s output transition. U3’s output,
relative to VCM_Aux at transition corresponds to U2’s offset error which can be factored into the Trigger readings
and thus eliminated, leaving only the Offset voltage temperature drift component (= 2 LSB).
30
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SNOSB21A – MAY 2008 – REVISED OCTOBER 2008
+5V
+5V
3,4
U1
LMH6518
1
2
R11
R12
237:
237:
+5V
+OUT Aux
6
-OUT Aux
1
16
5,8
+5V
VCM_Aux
R1
R2
75:
75:
+
5
4
U2
LMH7220
-
2
R10
100:
3
Trigger Output (LVDS)
R3
3.83 k:
1%
+5V
R4
1.20 k:
1%
U4
LP3985
2.5V
0-2.5V
VA
VREF
VOUT
SDA
SCL
U3
DAC101
C085
10 bit DAC
2
(I C)
Figure 68. Single-Ended Trigger from LMH6518 Auxiliary Output
U2’s minimum Toggle Rate specification of 750 Mb/s with ±50 mV overdrive allow the oscilloscope to trigger on
repetitive waveforms well above the 500 MHz oscilloscope bandwidth applications, when the input signal is at
least 14.3% of FS swing
(=
50 mV
x 100)
0.7V
2
(17)
The worst case single event minimum discernable pulse width is set by the LMH7220’s propagation delay
specification of 3.63 ns (20 mV overdrive).
Both the Main and the Auxiliary outputs can recover gracefully and quickly from a 50% overdrive condition as
tabulated in Electrical Characteristics under overdrive Recovery Time. Overdrive conditions beyond 50%,
however, could result in longer recovery times due to the interaction between an internal clamp and the common
mode feedback loop that sets the output common mode voltage. This may have an impact on both the displayed
waveform and the oscilloscope Trigger. The result could be a loss of Trigger pulse and/or visual distortion of the
displayed waveform. To avoid this scenario, the oscilloscope should detect an excessive overdrive and go into
trigger-loss mode. Done this way, the oscilloscope display would show the last waveform that did not violate the
overdrive condition. Preferably there would be a visual indicator on the screen that alerts the user of the situation
so that he can correct the excessive condition to return to normal display.
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APPENDIX A
Here is the schematic drawing for a possible implementation of the LNA buffer shown in Figure 62:
+10V
C7
20 nF
J10
MMBF5486
Scope Input
C6
Input Attenuators
Not Shown
R21
5 pF
R22
678 k:
1 M:
+
R14
322 k:
C5
Q0
BFQ67
1 nF
R16
R17
R49
100:
15:
½ U1
LMV842
LMH6518 +IN
-
R15
678 k:
20:
R20
J8
MMBF5486
500:
C3
R8
0:
R11
100 nF
322 k:
-10V
R2
R5
-5V
+5V
500 k:
+
Adjust R2 for gain matching
between DC and AC
R9
½ U1
LMV842
200:
+5V
R1
R3
500 k:
500 k:
LMH6518 -IN
R0
500 k:
C0
R6
R50
1 nF
200:
15:
R4
500 k:
Offset Control
DAC
Figure 69. JFET LNA Implementation
CIRCUIT OPERATION
This circuit uses an N-Channel JFET (J10) in Source-Follower configuration, to buffer the input signal, with J8
acting as a constant current source. This buffer presents a fixed input impedance (1 MΩ||10 pF) with a gain close
to 1 V/V.
The signal path is AC coupled through C7 with DC (and low frequency) at LMH6518 +IN maintained through the
action of U1. NPN transistor Q0 is an emitter follower which isolates the buffer from the load (LMH6518 input and
board traces).
The undriven input of the LMH6518, −IN, is biased to 2.5V by R6, R9 voltage divider. The Lower ½ of U1 inverts
this voltage and the upper ½ of U1 compares it to the combination of the driven output level at LMH6518 +IN and
the scaled version of scope input at R14, R21 junction, and adjusts J10 Gate accordingly to set the LMH6518 +IN.
This control loop has a frequency response that covers DC to a few Hz, limited by the roll-off capacitor C3 and
R15 combination (1st order approximation). DC and low frequency gain is given by:
§
¨
¨
©
Gain (DC) =
§
R14
R5
¨
# 1 V/V
¨1 +
R1 || R2
R14 + R21 ©
(18)
With the values in Figure 69 → R2 ≈ 452 kΩ:
32
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For a flat frequency response, the DC (low frequency) gain needs to be lowered to match the less-than-1 V/V AC
(high frequency) path gain through the JFETs. This can be done by increasing the value of R2.
By choosing the values of R15 and R11 so that
R21 R15
=
R14 R11
(19)
the frequency response at J10 Gate (and consequently the output) will remain flat when C7 starts to conduct.
Offset correction is done by varying the voltage at R4, using a DAC or equivalent as shown, in order to shift the
LMH6518 +IN voltage relative to −IN. The result is a circuit which shifts the ground referenced scope input to
2.5V (VCC/2) CM with adjustable offset and without any JFET or BJT related offsets.
Note that the front-end attenuator (not shown) lower leg resistance should be increased for proper divider-ratio to
account for the 1 MΩ shunt due to the series combination of R21 and R14. For example, a 10:1 front-end
attenuator could be formed by a series 900 kΩ and a shunt 111 kΩ for a scope BNC input impedance of 1 MΩ (=
900K + (111K || 1M)).
Table 8 lists other possible JFET candidates that fall in the range of speed (ft) and low noise needed:
Table 8. Suitable JFET Candidates Specifications
Part Number
VP (V)
Idss
(mA)
gm (mS)
Input C
(pF)
noise (1)
(nV/RtHz)
Break
down (V)
Calculated ft
(MHz)
Interfet
IF140
−2.2
10
5.5
2.3
4
−20
380
Interfet
IF142
−2.2
10
5.5
2.3
4
−25
380
Interfet
2N5397/8
−2.5
13
8
5
2.5
−25
254
Interfet
2N5911/2
−2.5
13
8
5
2.5
Interfet
J308/9/10
−2.3
21
17
5.8
Company
Philips
254
−25
466
BF513
-3
15
10
5
Fairchild
MMBF5486
−4
14
7
4
2.5
−25
278
Vishay
Siliconix
SST441
−3.5
13
6
3.5
4
−35
272
(1)
318
Noise data at ∼ Idss/2
The LNA noise could degrade the scope’s SNR if it is comparable to the input referred noise of the LMH6518.
LNA noise is influenced by the following operating conditions:
a. JFET equivalent input noise
b. BJT Base current
Reducing either “a” or “b” above, or both, reduces noise. One way to reduce “a” is to increase R8 (currently set to
0Ω). This will reduce the noise impact of J8 but requires a JFET which has a higher Idss rating in order to
maintain the operating current of J10 so that J10’s noise contribution is minimized. Reducing the BJT Base
current can be accomplished with increasing R20 at the expenses of higher rise/fall times. A higher β will also
reduce the Base current (keep in mind that β and ft at the operating Collector current is what matters).
Figure 70 shows the impact of the JFET buffer noise on SNR, compared to SNR in Figure 58, assuming either 3
nV/√Hz or 1.5 nV/√Hz buffer noise for comparison:
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12
SNR IMPACT (dB)
10
8
6
LNA Noise = 3 nV/ Hz
4
2
LNA Noise = 1.5 nV/ Hz
0
-2
2
6 10 14 18 22 26 30 34 38 42
GAIN (dB)
Figure 70. LNA Buffer SNR Impact
ATTENUATOR DESIGN
Figure 71 shows a front-end attenuator designed to work with the JFET LNA of Figure 69.
1:1
10:1
C5
2-5 pF
100:1
C6
2-5 pF
R1
900 k:
C1
8 pF
R2
111 k:
C2
65 pF
R3
990 k:
C3
8 pF
R4
10.1 k:
C4
780 pF
JFET LNA
10:1
1:1
100:1
R_LNA
1 M:
C_LNA
10 pF
Figure 71. Front End Attenuator for Figure 69 JFET LNA
R_LNA” and “C_LNA” are the input impedance components of the JFET LNA. The 10:1 and 100:1 attenuators
bottom resistors (R2 and R4) are adjusted higher to compensate for the LNA’s 1 MΩ input impedance, compared
to the case where a high-input-impedance LNA is used. The two switches used on the input and output of the
attenuator block must be low capacitance, high isolation switches in order to reduce any speed or crosstalk
impact. C1-C4 provide the proper frequency response (and step response) by creating “zeros” that flatten the
response for wide-band operation. For the 10:1 attenuator, R1C1 = R2C2. The same applies to the 100:1
attenuator. The shunt capacitors C1-C4 have a very important other benefit in that they roll-off the resistor thermal
noise at a low frequency (low pass response, −3 dB down at ∼20 kHz) thereby eliminating any significant noise
contribution from the attenuation resistors. Otherwise, the channel noise would be dominated by the attenuator
resistor thermal noise. C2 and C6 trimmer capacitors can be adjusted to match the input capacitance regardless
of attenuator used.
REFERENCE
1. Wideband amplifiers by Peter Staric and Erik Margan, published by Springer in 2006. (Section 5.2).
34
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMH6518SQ/NOPB
ACTIVE
WQFN
RGH
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L6518SQ
LMH6518SQE/NOPB
ACTIVE
WQFN
RGH
16
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L6518SQ
LMH6518SQX/NOPB
ACTIVE
WQFN
RGH
16
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L6518SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMH6518SQ/NOPB
WQFN
RGH
16
LMH6518SQE/NOPB
WQFN
RGH
LMH6518SQX/NOPB
WQFN
RGH
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
16
250
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
16
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH6518SQ/NOPB
WQFN
RGH
16
1000
203.0
190.0
41.0
LMH6518SQE/NOPB
WQFN
RGH
16
250
203.0
190.0
41.0
LMH6518SQX/NOPB
WQFN
RGH
16
4500
358.0
343.0
63.0
Pack Materials-Page 2
MECHANICAL DATA
RGH0016A
SQA16A (Rev A)
www.ti.com
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