DG406, DG407 Data Sheet Single 16-Channel/Differential 8-Channel, CMOS Analog Multiplexers The DG406 and DG407 monolithic CMOS analog multiplexers are drop-in replacements for the popular DG506A and DG507A series devices. They each include an array of sixteen analog switches, a TTL and CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds, and an ENABLE input for device selection when several multiplexers are present. These multiplexers feature lower signal ON resistance (<100Ω) and faster transition time (tTRANS < 300ns) compared to the DG506A and DG507A. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the DG406 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 30VP-P signals when operating with ±15V power supplies. The sixteen switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range. 1 June 1999 File Number 3116.5 Features • ON-Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . 100Ω • Low Power Consumption (PD) . . . . . . . . . . . . . . <1.2mW • Fast Transition Time (Max) . . . . . . . . . . . . . . . . . . . . 300ns • Low Charge Injection • TTL, CMOS Compatible • Single or Split Supply Operation Applications • Battery Operated Systems • Data Acquisition • Medical Instrumentation • Hi-Rel Systems • Communication Systems • Automatic Test Equipment Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. DG406DJ -40 to 85 28 Ld PDIP E28.6 DG406DY -40 to 85 28 Ld SOIC M28.3 DG407DJ -40 to 85 28 Ld PDIP E28.6 DG407DY -40 to 85 28 Ld SOIC M28.3 DG407DN -40 to 85 28 Ld PLCC N28.45 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 DG406, DG407 Pinouts DG406 (PDIP, SOIC) TOP VIEW DG407 (PDIP, SOIC) TOP VIEW V+ 1 28 D V+ 1 28 DA NC 2 27 V- DB 2 27 V- NC 3 26 S8 NC 3 26 S8A S16 4 25 S7 S8B 4 25 S7A S15 5 24 S6 S7B 5 24 S6A S14 6 23 S5 S6B 6 23 S5A S13 7 22 S4 S5B 7 22 S4A S12 8 21 S3 S4B 8 21 S3A S11 9 20 S2 S3B 9 20 S2A S10 10 19 S1 S2B 10 19 S1A S9 11 18 EN S1B 11 18 EN GND 12 17 A0 GND 12 17 A0 NC 13 16 A1 NC 13 16 A1 A3 14 15 A2 NC 14 15 A2 2 S8B NC DB +VSUPPLY DA -VSUPPLY S8A DG407 (PLCC) TOP VIEW 4 3 2 1 28 27 26 22 S4A S3B 9 21 S3A S2B 10 20 S2A S1B 11 19 S1A 12 13 14 15 16 17 18 ENABLE S4B 8 A0 23 S5A A1 S5B 7 A2 24 S6A NC S6B 6 NC 25 S7A GND S7B 5 DG406, DG407 Schematic Diagram (Typical Channel) V+ VREF GND D A0 V+ LEVEL SHIFT AX V- DECODE/ DRIVE S1 V+ EN SN V- Functional Diagrams DG406 DG407 S1A S1 S2A S2 S3A S3 S4A S4 S6A S6 S7A S7 S8A S8 D S9 S1B S10 S2B S11 S3B S12 S4B S13 S6B S15 S7B S16 S8B TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING ADDRESS DECODER 1 OF 16 A1 DB S5B S14 A0 DA S5A S5 A2 A3 3 TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING ENABLE EN ADDRESS DECODER 1 OF 8 A0 A1 A2 ENABLE EN DG406, DG407 DG406 TRUTH TABLE DG407 TRUTH TABLE A3 A2 A1 A0 EN ON SWITCH A2 A1 A0 EN ON SWITCH PAIR X X X X 0 None X X X 0 None 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 2 0 0 1 1 2 0 0 1 0 1 3 0 1 0 1 3 0 0 1 1 1 4 0 1 1 1 4 0 1 0 0 1 5 1 0 0 1 5 0 1 0 1 1 6 1 0 1 1 6 0 1 1 0 1 7 1 1 0 1 7 0 1 1 1 1 8 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16 4 Logic “0” = VAL < 0.8V. Logic “1” = VAH > 2.4V. X = Don’t Care. DG406, DG407 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Digital Inputs, VS , VD (Note 1). . . . . . (V-) -2V to (V+) +2V or 20mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 100mA Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (PLCC and SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on SX , DX , EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (oC) (NOTE 3) MIN (NOTE 4) TYP (NOTE 3) MAX UNITS 25 - 200 300 ns Full - - 400 ns 25 25 50 - ns Full 10 - - ns 25 - 150 200 ns Full - - 400 ns 25 - 70 150 ns Full - - 300 ns DYNAMIC CHARACTERISTICS (See Figure 1) Transition Time, tTRANS Break-Before-Make Interval, tOPEN Enable Turn-ON Time, tON(EN) (See Figure 3) (See Figure 2) Enable Turn-OFF Time, tOFF(EN) Charge Injection, Q CL = 1nF, VS = 0V, RS = 0Ω 25 - 40 - pC OFF Isolation, OIRR VEN = 0V, RL = 1kΩ, f = 100kHz (Note 7) 25 - -69 - dB Logic Input Capacitance, CIN f = 1MHz 25 - 7 - pF Source OFF Capacitance, CS(OFF) VEN = 0V, VS = 0V, f = 1MHz 25 - 8 - pF Drain OFF Capacitance, CD(OFF) VEN = 0V, VD = 0V, f = 1MHz 25 - 160 - pF 25 - 80 - pF 25 - 180 - pF 25 - 90 - pF Logic High Input Voltage, VINH Full 2.4 - - V Logic Low Input Voltage, VINL Full - - 0.8 V DG406 DG407 Drain ON Capacitance, CD(ON) VEN = 5V, VD = 0V, f = 1MHz DG406 DG407 DIGITAL INPUT CHARACTERISTICS Logic High Input Current, IAH VA = 2.4V, 15V Full -1 - 1 µA Logic Low Input Current, IAL VEN = 0V, 2.4V, VA = 0V Full -1 - 1 µA 5 DG406, DG407 Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified PARAMETER (Continued) TEST CONDITIONS TEMP (oC) (NOTE 3) MIN (NOTE 4) TYP (NOTE 3) MAX UNITS VD = ±10V, IS = +10mA (Note 5) 25 - 50 100 Ω Full - - 125 Ω ANALOG SWITCH CHARACTERISTICS Drain-Source ON Resistance, rDS(ON) rDS(ON) Matching Between Channels, ∆rDS(ON) VD = 10V, -10V (Note 6) 25 - 5 - % Source OFF Leakage Current, IS(OFF) VEN = 0V, VS = ±10V, VD = +10V 25 -0.5 0.01 0.5 nA Full -5 - 5 nA 25 -1 0.04 1 nA Full -40 - 40 nA 25 -1 0.04 1 nA Full -20 - 20 nA 25 -1 0.04 1 nA Full -40 - 40 nA 25 -1 0.04 1 nA Full -20 - 20 nA 25 - 13 30 µA Full - - 75 µA 25 -1 -0.01 - µA Full -10 - - µA 25 - -0.01 100 µA Full - - 200 µA 25 -1 - - µA Full -10 - - µA Drain OFF Leakage Current, ID(OFF) DG406 DG407 VS = VD = ±10V (Note 5) Drain ON Leakage Current, ID(ON) DG406 DG407 POWER SUPPLY CHARACTERISTICS VEN = VA = 0V or 5V (Standby) Positive Supply Current, I+ Negative Supply Current, I- VEN = 2.4V, VA = 0V (Enabled) Positive Supply Current, I+ Negative Supply Current, I- Electrical Specifications Single Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified TEST CONDITIONS PARAMETER TEMP (oC) (NOTE 3) MIN (NOTE 4) TYP (NOTE 3) MAX UNITS DYNAMIC CHARACTERISTICS Switching Time of Multiplexer, tTRANS VS1 = 8V, VS8 = 0V, VIN = 2.4V 25 - 300 450 ns Enable Turn-ON Time, tON(EN) VINH = 2.4V, VINL = 0V, VS1 = 5V 25 - 250 600 ns 25 - 150 300 ns CL = 1nF, VS = 6V, RS = 0Ω 25 - 20 - pC Enable Turn-OFF Time, tOFF(EN) Charge Injection, Q 6 DG406, DG407 Electrical Specifications Single Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified (Continued) TEMP (oC) (NOTE 3) MIN (NOTE 4) TYP (NOTE 3) MAX UNITS Full 0 - 12 V 25 - 90 120 Ω 25 - 5 - % 25 - 0.01 - nA DG406 25 - 0.04 - nA DG407 25 - 0.04 - nA DG406 25 - 0.04 - nA DG407 25 - 0.04 - nA 25 - 13 30 µA Full - 13 75 µA 25 -1 -0.01 - µA Full -5 -0.01 - µA TEST CONDITIONS PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG VD = 3V, 10V, IS = -1mA (Note 5) Drain-Source ON-Resistance, rDS(ON) rDS(ON) Matching Between Channels (Note 6), ∆rDS(ON) VEN = 0V, VD = 10V or 0.5V, VS = 0.5V or 10V Source Off Leakage Current, IS(OFF) Drain Off Leakage Current, ID(OFF) VS = VD = ±10V (Note 5) Drain On Leakage Current, ID(ON) POWER SUPPLY CHARACTERISTICS VEN = 0V or 5V, VA = 0V or 5V Positive Supply Current (I+) (Standby) Negative Supply Current (I-) (Enabled) NOTES: 3. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 4. Typical values are for Design Aid Only, not guaranteed nor production tested. 5. Sequence each switch ON. 6. ∆rDS(ON) = (rDS(ON)(Max) - rDS(ON)(Min)) ÷ rDS(ON) average. 7. Worst case isolation occurs on channel 8B due to proximity to the drain pin. Test Circuits and Waveforms +15V +15V A2 LOGIC INPUT V+ +2.4V ±10V S1 S2 - S15 A1 A0 GND V- 50Ω EN A2 DG406 S 16 LOGIC INPUT ± EN A3 10V A1 300Ω -15V 35pF S1B ±10V † DG407 A0 GND VO D V+ S8B V- 50Ω ± +2.4V 10V DB VO 300Ω -15V † = S1A - S8A , S2B - S7B , DA FIGURE 1A. DG406 TEST CIRCUIT 7 FIGURE 1B. DG407 TEST CIRCUIT 35pF DG406, DG407 Test Circuits and Waveforms (Continued) tr < 20ns tf < 20ns 3V LOGIC INPUT 50% 50% 0V VS1B SWITCH OUTPUT VO S1 ON 80% VS1 0V 80% VS8 VS8B tTRANS tTRANS S8 ON FIGURE 1C. MEASUREMENT POINTS FIGURE 1. TRANSITION TIME +15V +15V A3 A2 LOGIC INPUT VIN A1 V+ A2 -5V S1 A1 S2 - S16 LOGIC INPUT VIN DG406 A0 EN GND V- VO D 50Ω 300Ω A0 EN V+ -5V S1B † DG407 DA AND DB GND V- 50Ω VO 35pF 300Ω 35pF -15V -15V † = S1A - S8A , S2B - S8B , DA FIGURE 2A. DG406 TEST CIRCUIT LOGIC INPUT VIN FIGURE 2B. DG407 TEST CIRCUIT tr < 20ns tf < 20ns 3V 50% 50% 0V tON(EN) tOFF(EN) 0V SWITCH OUTPUT VO VO 90% VO FIGURE 2C. MEASUREMENT POINTS FIGURE 2. ENABLE SWITCHING TIMES +15V tr < 20ns tf < 20ns 3V +2.4V EN A3 LOGIC INPUT V+ ALL S AND DA +5V (VS) 0V DG406 DG407 A1 D, A0 GND V- DB A2 LOGIC INPUT 50Ω VO 300Ω 35pF SWITCH OUTPUT VO VS 0V tOPEN -15V FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE INTERVAL 8 80% DG406, DG407 160 80 140 70 rDS(ON) , ON-RESISTANCE (Ω) rDS(ON) , ON RESISTANCE (Ω) Typical Performance Curves 120 ±5V 100 80 60 40 20 0 -20 ±8V ±10V ±12V ±15V ±20V -16 125oC 60 85oC 50 25oC 40 30 -40oC 20 -55oC 0oC V+ = 15V V- = -15V 10 -12 -8 -4 0 4 8 VD , DRAIN VOLTAGE (V) 12 16 0 -15 20 FIGURE 4. rDS(ON) vs VD AND SUPPLY -10 -5 0 5 VD , DRAIN VOLTAGE (V) 10 15 FIGURE 5. rDS(ON) vs VD AND TEMPERATURE 120 V- = 0V 160 10V 120 12V 80 15V 20V 22V 40 IS(OFF) 0 -40 DG406 ID(ON) , ID(OFF) DG407 ID(ON) , ID(OFF) -80 40 0 V+ = 15V, V- = -15V VS = -VD FOR ID(OFF) VD = VS(OPEN) FOR ID(ON) 80 V+ = 7.5V 200 ID , IS , CURRENT (pA) rDS(ON) , ON-RESISTANCE (Ω) 240 0 4 8 12 16 20 -120 -15 FIGURE 6. rDS(ON) vs VD AND SUPPLY 100nA 5 10 15 300 250 tTRANS 1nA TIME (ns) ID , IS , CURRENT (A) 0 350 10nA ID(ON) , ID(OFF) 10pA IS(OFF) 200 tON(EN) 150 100 tOFF(EN) 1pA 0.1pA -55 -5 FIGURE 7. ID, IS LEAKAGE CURRENTS vs ANALOG VOLTAGE V+ = 15V, V- = -15V VS OR VD = ±10V 100pA -10 VS , VD , SOURCE DRAIN VOLTAGE (V) VD , DRAIN VOLTAGE (V) 50 -35 -15 5 25 45 65 85 105 TEMPERATURE (oC) FIGURE 8. ID , IS LEAKAGE vs TEMPERATURE 9 125 0 5 10 15 VSUPPLY , SUPPLY VOLTAGE (±V) FIGURE 9. SWITCHING TIMES vs BIPOLAR SUPPLIES 20 DG406, DG407 Typical Performance Curves (Continued) -140 700 600 -120 500 -100 ISOL (dB) TIME (ns) V- = 0V tTRANS 400 300 tON(EN) -80 -60 -40 200 tOFF(EN) -20 100 0 5 10 15 0 100 20 1K 10K FIGURE 10. SWITCHING TIMES vs SINGLE SUPPLY 280 V+ = 15V, V- = -15V 260 240 I+ 4 220 2 TIME (ns) I, CURRENT (mA) 10M 300 EN = 5V, AX = 0V OR 5V 6 0 IGND -2 tTRANS 200 180 tON(EN) 160 140 -4 120 I- -6 100 -8 -10 10 1M FIGURE 11. OFF ISOLATION vs FREQUENCY 10 8 100K f, FREQUENCY (Hz) V+, SUPPLY VOLTAGE (V) tOFF(EN) 80 100 1K 10K 100K 1M 60 -55 10M -35 -15 5 45 65 85 TEMPERATURE (oC) f, FREQUENCY (Hz) FIGURE 12. SUPPLY CURRENTS vs SWITCHING FREQUENCY FIGURE 13. tON /tOFF vs TEMPERATURE 3 VA , (V) 2 1 0 0 5 10 15 20 VSUPPLY, SUPPLY VOLTAGE (±V) FIGURE 14. SWITCHING THRESHOLD vs SUPPLY VOLTAGE 10 25 105 125 DG406, DG407 Die Characteristics DIE DIMENSIONS: PASSIVATION: 2490µm x 4560µm x 485µm Type: Nitride Thickness: 8kÅ ±1kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: SiAl Thickness: 12kÅ ±1kÅ 9.1 x 104 A/cm2 Metallization Mask Layout DG406 NC D V- S16 S5 S15 S7 S14 S6 S13 S5 S12 S4 S11 S3 S10 S2 S9 S1 GND A3 11 V+ A2 A1 A0 EN DG406, DG407 Die Characteristics DIE DIMENSIONS: PASSIVATION: 2490µm x 4560µm x 485µm Type: Nitride Thickness: 8kÅ ±1kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: SiAl Thickness: 12kÅ ±1kÅ 9.1 x 104 A/cm2 Metallization Mask Layout DG407 DB V+ DA V- S8A S8B S7A S7B S6A S6B S5A S5B S4A S4B S3A S3B S2A S2B S1A S1B GND NC 12 A2 A1 A0 EN DG406, DG407 Dual-In-Line Plastic Packages (PDIP) E28.6 (JEDEC MS-001-BF ISSUE D) N 28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 N/2 INCHES -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 eA A1 eC B 0.010 (0.25) M C L C A B S C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 13 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 D 1.380 1.565 D1 0.005 - 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.204 0.381 35.1 0.100 BSC - 39.7 5 - 5 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 7 L 0.115 0.200 2.93 N 28 17.78 5.08 28 4 9 Rev. 0 12/93 DG406, DG407 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 14 MAX MILLIMETERS MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e α MIN 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 28 0o 28 7 8o Rev. 0 12/93 DG406, DG407 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N28.45 (JEDEC MS-018AB ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” A1 A D1 D 0.020 (0.51) MAX 3 PLCS 0.020 (0.51) MIN 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.485 0.495 12.32 12.57 - D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5 E 0.485 0.495 12.32 12.57 - E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5 N 28 28 6 Rev. 2 11/97 SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 15 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029