NCP81172 2-Phase Synchronous Buck Controller with Integrated Gate Drivers and PWM VID Interface http://onsemi.com The NCP81172, a general−purpose two−phase synchronous buck controller, integrates gate drivers and PWM VID interface in a QFN−24 package and provides a compact−footprint power management solution for new generation computing processors. It receives power save command (PSI) from processors and operates in 1−phase diode emulation mode to obtain high efficiency in light−load condition. Operating in high switching frequency up to 800 kHz allows employing small size inductor and capacitors. The part is able to support all−ceramic−capacitor applications. 1 24 QFN24 CASE 485L MARKING DIAGRAM 81172 ALYWG G Features 4.5 V to 24 V Input Voltage Range Output Voltage up to 2.0 V with PWM VID Interface Differential Output Voltage Sense Integrated Gate Drivers 200 kHz ~ 800 kHz Switching Frequency Power Saving Interface (PSI) Power Good Output Programmable Over Current Protection Over Voltage Protection Under Voltage Protection Temperature Sense and Alert Output Thermal Shutdown Protection QFN−24, 4 x 4 mm, 0.5 mm Pitch Package This is a Pb−Free Device 81172 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package 18 17 16 15 14 13 BST2 HG2 PGOOD VCC TALERT# TSNS PINOUT 19 PH2 COMP 12 FB 11 FBRTN 10 20 LG2 21 PVCC Typical Applications 25 GND 8 24 PH1 REFIN 7 VIDBUF VREF VID 23 LG1 PSI 9 EN FS HG1 22 PGND GPU and CPU Power Graphics Card Applications Desktop and Notebook Applications BST1 1 2 3 4 5 6 (Top View) ORDERING INFORMATION Device Package Shipping† NCP81172MNTXG QFN24 (Pb−Free) 4000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2013 April, 2013 − Rev. 1 1 Publication Order Number: NCP81172/D NCP81172 +5 V +5 V 15 VCC PVCC 21 25 GND PGND 22 VIN +3.3 V HG1 2 BST1 1 VOUT PH1 24 EN 3 EN PSI 4 PSI PG LG1 23 VIN 16 PGOOD NCP81172 TALT 14 TALERT# HG2 17 VID 5 VID BST2 18 13 TSNS PH2 19 LG2 20 8 VREF 7 REFIN 6 VIDBUF 9 FS FBRTN 10 FB 11 COMP 12 Figure 1. Typical Application Circuit with PWM−VID Interface http://onsemi.com 2 NCP81172 +5 V +5 V 15 VCC PVCC 21 25 GND PGND 22 VIN +3.3 V HG1 2 BST1 1 VOUT PH1 24 EN 3 EN PSI 4 PSI PG LG1 23 VIN 16 PGOOD NCP81172 TALT 14 TALERT# HG2 17 5 VID BST2 18 13 TSNS PH2 19 LG2 20 8 VREF 7 REFIN 6 VIDBUF 9 FS FBRTN 10 FB 11 COMP 12 Figure 2. Typical Application Circuit without PWM−VID Interface http://onsemi.com 3 NCP81172 15 3 16 13 14 PVCC VCC EN UVLO & PGOOD BST1 FAULT HG1 PGOOD PWM1 TSNS TALERT# Thermal Management PH1 Gate Drive 1 PVCC LG1 PGND 4 PSI PSI Control 2/1 Phase RAMP1 9 8 5 6 FS VREF Ramp Generator PH1 11 10 25 12 1 2 24 23 22 PVCC PWM Control & Protections (OVP, UVP, OCP) BST2 HG2 RAMP2 PWM2 Reference Voltage PH2 Gate Drive 2 PVCC PGND VID VIDBUF PWM1 CS1 7 21 PH1 REFIN Current Sense FB CS2 LG1 PWM2 PH2 LG2 FBRTN GND GND COMP Figure 3. Functional Block Diagram http://onsemi.com 4 LG2 18 17 19 20 NCP81172 PIN DESCRIPTION Pin Name Type 1 BST1 Analog Power Bootstrap 1. Provides bootstrap voltage for the high−side gate drive of phase 1. A 0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH1 (pin 24). Description 2 HG1 Analog Output High−Side Gate 1. Directly connected with the gate of the high−side power MOSFET of phase 1. 3 EN Logic Input Enable. Logic high enables the device and logic low makes the device in standby mode. 4 PSI Logic Input Power Saving Interface. Logic high enables 2 phase CCM operation, mid level enables 1−phase CCM operation, and logic low enables 1−phase CCM/DCM operation. 5 VID Logic Input Voltage ID. Voltage ID input from processor. 6 VIDBUF Analog Output 7 REFIN Analog Input Reference Input. Reference voltage input for output voltage regulation. The pin is connected to a non−inverting input of internal error amplifier. 8 VREF Analog Output Output Reference Voltage. Precise 2 V reference voltage output. A 10 nF ceramic capacitor is required from this pin to GND. Voltage ID Buffer. VID PWM pulse output from an internal buffer. 9 FS Analog Input Frequency Selection. A resistor from this pin to ground programs switching frequency. 10 FBRTN Analog Input Voltage Feedback Return Input. An inverting input of internal error amplifier. 11 FB Analog Input Feedback. An inverting input of internal error amplifier. 12 COMP Analog Output 13 TSNS Analog Input Temperature Sensing. Temperature sensing input. 14 TALERT# Logic Output Thermal Alert. Open drain output and active low indicates over temperature. 15 VCC Analog Power Voltage Supply of Controller. Power supply input pin of control circuits. A 1 mF or larger ceramic capacitor bypasses this input to GND. This capacitor should be placed as close as possible to this pin. 16 PGOOD Logic Output Power GOOD. Open−drain output. Provides a logic high valid power good output signal, indicating the regulator’s output is in regulation window. 17 HG2 Analog Output High−Side Gate 2. Connected with the gate of the high−side power MOSFET in phase 2. 18 BST2 Analog Power Bootstrap 2. Provides bootstrap voltage for the high−side gate drive of phase 2. A 0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH2 (pin 19). 19 PH2 Analog Input Phase Node 2. Connected to interconnection between high−side MOSFET and low−side MOSFET in phase 2. 20 LG2 Analog Output Low−Side Gate 2. Connected with the gate of the low−side power MOSFET in phase 2. 21 PVCC Analog Power Voltage Supply of Gate Drivers. Power supply input pin of internal gate drivers. A 4.7 mF or larger ceramic capacitor bypasses this input to ground. This capacitor should be placed as close as possible to this pin. 22 PGND Analog Ground Power Ground. Power ground of internal gate drivers. Must be connected to the system ground. 23 LG1 Analog Output Low−Side Gate 1. Connected with the gate of the low−side power MOSFET in phase 1. A resistor may be applied between this pin and GND to program OCP threshold. 24 PH1 Analog Input Phase Node 1. Connected to interconnection between high−side MOSFET and low−side MOSFET in phase 1. 25 THERM/GND Analog Ground Compensation. Output pin of error amplifier. Thermal Pad and Analog Ground. Ground of internal control circuits. Must be connected to the system ground. http://onsemi.com 5 NCP81172 MAXIMUM RATINGS Value Symbol MIN MAX Unit VPH −2 −8 (<100 ns) 30 V Gate Driver Supply Voltage PVCC to GND VPVCC −0.3 6.5 V Supply Voltage VCC to GND VVCC −0.3 6.5 V VBST_PGND −0.3 35 V BST to PH VBST_PH −0.3 6.5 V HG to PH VHG −0.3 −2 (<200 ns) BST+0.3 V LG to GND VLG −0.3 −2 (<200 ns) PVCC+0.3 V PGND to GND VPGND −0.3 0.3 V FBRTN to GND VFBRTN −0.3 0.3 V −0.3 VCC+0.3 V V Rating PH to PGND BST to PGND Other Pins to GND Human Body Model (HBM) ESD Rating Are (Note 1) ESD HBM 2000 Machine Model (MM) ESD Rating Are (Note 1) ESD MM 200 Latch up Current: (Note 2) All pins, except digital pins Digital pins ILU Operating Junction Temperature Range (Note 4) Operating Ambient Temperature Range V mA −100 −10 100 10 TJ −40 125 C TA −40 100 C Storage Temperature Range TSTG −40 Thermal Resistance Junction to Top Case (Note 5) RΨJC 6.0 C/W Thermal Resistance Junction to Board (Note 5) RΨJB 7.5 C/W Thermal Resistance Junction to Ambient (Note 4) RJA 50 C/W PD 2.0 W MSL 1 − Power Dissipation (Note 6) Moisture Sensitivity Level (Note 7) 150 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device is ESD sensitive. Handling precautions are needed to avoid damage or performance degradation. 2. Latch up Current per JEDEC standard: JESD78 class II. 3. The thermal shutdown set to 150C (typical) avoids potential irreversible damage on the device due to power dissipation. 4. EDEC standard JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM. 5. JEDEC standard JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM. For checking junction temperature using external measurement. 6. The maximum power dissipation (PD) is dependent on input voltage, maximum output current and external components selected. T ambient = 25C, Tjunc_max = 125C, PD = (Tjunc_max−T_amb)/Theta JA 7. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A. ELECTRICAL CHARACTERISTICS (VIN = 12 V, VVCC = VPVCC = 5 V, VREFIN = 1.0 V, VPSI = 3.3 V, typical values are referenced to TJ = 25C, Min and Max values are referenced to TJ from −40C to 100C. unless other noted) Test Conditions Symbol Min Typ Max Unit VIN Supply Voltage Range (Note 8) VIN 4.5 12 24 V VCC Supply Voltage Range (Note 8) VCC 4.5 5 5.5 V Characteristics SUPPLY VOLTAGE 8. Guaranteed by design, not tested in production. http://onsemi.com 6 NCP81172 ELECTRICAL CHARACTERISTICS (continued) (VIN = 12 V, VVCC = VPVCC = 5 V, VREFIN = 1.0 V, VPSI = 3.3 V, typical values are referenced to TJ = 25C, Min and Max values are referenced to TJ from −40C to 100C. unless other noted) Characteristics Test Conditions Symbol Min Typ Max Unit (Note 8) VPCC 4.5 5 5.5 V VCC Under−Voltage (UVLO) Threshold VCC falling VCCUV− 4.0 4.05 4.2 V VCC OK Threshold VCC rising VCCOK 4.2 4.25 4.4 V VCC Quiescent Current EN high, no switching, PS0 EN high, no switching, PS1/PS2 ICC − − 9 9 15 15 mA mA VCC Shutdown Current EN low IsdCC − 30 50 mA PVCC Quiescent Supply Current EN high, no switching, PS0 EN high, no switching, PS1/PS2 IPCC − − 0.35 0.35 0.6 0.6 mA mA PVCC Shutdown Current EN low IsdPCC − − 2.0 mA (Note 8) FSW 200 800 kHz RFS = 39.2 kW VFS IREF = 1 mA VVREF Minimum On Time (Note 8) Ton_min 50 ns Minimum Off Time (Note 8) Toff_min 250 ns Maximum Duty Cycle (Note 8) Dmax Open−Loop DC Gain (Note 8) GAINEA 80 dB Unity Gain Bandwidth (Note 8) GBWEA 20 MHz Slew Rate (Note 8) SRCOMP 20 V/ms ICOMP(source) = 2 mA VmaxCOMP 3.2 3.4 − V ICOMP(sink) = 2 mA VminCOMP − 1.05 1.15 V VFB = VREFIN = 1.0 V IFB −400 400 nA VosEA = VREFIN − VFB (Note 8) VosEA −4 4 mV SUPPLY VOLTAGE PVCC Supply Voltage Range SUPPLY CURRENT SWITCHING FREQUENCY SETTING PS0 Switching Frequency Range FS Voltage 2.0 V VOLTAGE REFERENCE VREF Reference Voltage 1.98 2.0 2.02 V PWM MODULATION − 100 − % VOLTAGE ERROR AMPLIFIER COMP Voltage Swing FB, REFIN Bias Current Input Offset Voltage REFIN Discharge Switch ON−Resistance IREFIN (sink) = 2 mA 6.25 W GAINCA −5.5 V/V (Note 8) BWCA 10 MHz VosCS = VPH − VPGND (Note 8) VosCS −500 − EN High Threshold VhighEN 1.6 EN Low Threshold VlowEN − IbiasEN − CURRENT−SENSE AMPLIFIER Closed−Loop DC Gain −3dB Gain Bandwidth Input Offset Voltage 500 uV − − V − 0.8 V − 1.0 mA ENABLE EN Input Bias Current External 1k pull−up to 3.3 V 8. Guaranteed by design, not tested in production. http://onsemi.com 7 NCP81172 ELECTRICAL CHARACTERISTICS (continued) (VIN = 12 V, VVCC = VPVCC = 5 V, VREFIN = 1.0 V, VPSI = 3.3 V, typical values are referenced to TJ = 25C, Min and Max values are referenced to TJ from −40C to 100C. unless other noted) Characteristics Test Conditions Symbol Rising Falling VhighPSI Rising Falling VlowPSI Min Typ Max Unit 2.4 2.2 2.55 2.05 0.5 0.8 0.6 0.95 V − − 1.0 mA POWER SAVE INPUT PSI High Threshold PSI Low Threshold PSI Input Bias Current IbiasPSI V SOFT START AND PGOOD Vout Startup Delay Measured from EN to Vout Start up from 0 V Cout Startup Slew Rate PGOOD Startup Delay PGOOD Shutdown Delay PGOOD Low Voltage PGOOD Leakage Current 1.15 ms 3.0 V/ms Measured from EN to PGOOD assertion 2.0 Measured from EN to PGOOD de−assertion 125 ms ns IPGOOD= 4 mA (sink) VlPGOOD − − 0.3 V PGOOD = 5 V IlkgPGOOD − − 1.0 mA 110 122 134 PROTECTION RILMT is open Current Limit Threshold Measured from PGND to Phx (RILMT(1%) is connected from LG1 to GND) RILMT = 6.98 kW RILMT = 21.0 kW VOCTH RILMT = 35.7 kW 72 82 92 89 100 111 146 163 180 OCP is disabled RILMT = 49.9 kW Fast Under Voltage Protection (FUVP) Threshold Voltage from FB to GND Faster Under Voltage Protection (FUVP) Delay Slow Under Voltage Protection (SUVP) Threshold 0.2 0.25 − V (Note 8) 2.0 ms Voltage from COMP to GND 3.0 V 50 us Slow Under Voltage Protection (SUVP) Delay Over Voltage Protection (OVP) Threshold 0.15 mV (Note 8) Voltage from FB to GND Over Voltage Protection (OVP) Delay (Note 8) Over Temperature Protection (OTP) Threshold (Note 8) Recovery Temperature Threshold (Note 8) Over Temperature Protection (OTP) Delay 1.85 Tsd Trec (Note 8) 140 2.0 2.15 V 2.0 ms 150 C 125 C 125 ns 2 kW OUTPUT DISCHARGE Output Discharge Resistance per Phase Measured from PHx to PGND when EN is low (Note 8) 8. Guaranteed by design, not tested in production. http://onsemi.com 8 Rdischrg NCP81172 ELECTRICAL CHARACTERISTICS (continued) (VIN = 12 V, VVCC = VPVCC = 5 V, VREFIN = 1.0 V, VPSI = 3.3 V, typical values are referenced to TJ = 25C, Min and Max values are referenced to TJ from −40C to 100C. unless other noted) Characteristics Test Conditions Symbol Min Typ Max Unit VlowTSNS 0.99 1.00 1.01 V TSENSE and ALERT TALERT# Assert Threshold Measured at TSNS (Temperature Rising) TALERT# De−Assert Threshold Measured at TSNS (Temperature Falling) VhighTSNS − 1.05 − V IALERT= 4 mA (sink) VlowALERT − − 0.3 V TALERT# = 5 V IlkgALERT − − 1.0 mA TALERT# Low Voltage TALERT# Leakage Current PWM−VID BUFFER 1.4 V Buffer Output Rise Time Tr 3 ns Buffer Output Fall Time Tf 3 ns VID Input Threshold Rising and Falling Edge Delay Propagation Delay Propagation Delay Error T = | Tr − Tf | (Note 8) T Tpd = TpHL =TpLH Tpd Tpd = TpHL – TpLH (Note 8) Tpd 0.5 8 ns ns 0.5 ns INTERNAL HIGH−SIDE GATE DRIVE Pull−High Drive ON Resistance VBST – VPH = 5 V, IHG = 2 mA (source) Pull−Low Drive ON Resistance VBST – VPH = 5 V, IHG = 2 mA (sink) HG Propagation Delay Time From LG off to HG on RDRV_HH − 1.5 − W RDRV_HL − 1.0 − W TpdHG 16 ns INTERNAL LOW−SIDE GATE DRIVE Pull−High Drive ON Resistance VPVCC – VPGND = 5 V, ILG = 2 mA (source) Pull−Low Drive ON Resistance VPVCC – VPGND = 5 V, ILG = 2 mA (sink) LG Propagation Delay Time From HG off to LG on RDRV_LH − 1.0 − W RDRV_LL − 0.5 − W TpdLG 10 ns BOOTSTRAP On Resistance of Rectifier Switch Rectifier Switch Leakage Current VPVCC = 5 V, Id = 2 mA, TA = 25C VPVCC = 5 V, EN = 0 V 8. Guaranteed by design, not tested in production. http://onsemi.com 9 RBST 5.0 14 20 W IlkgBST − − 3 mA NCP81172 DETAILED DESCRIPTION General of multi−phase current−mode RPM control results in fast transient response and good dynamic current balance. It is able to support all−ceramic−capacitor applications. The NCP81172, a 2−phase synchronous buck controller, integrates gate drivers and PWM VID interface in a QFN−24 package and provides a compact−footprint power management solution for new generation computing processors. It receives power save input (PSI) from processors and operates in 1−phase diode emulation mode to obtain high efficiency in light−load condition. Operating in high switching frequency up to 800 kHz allows employing small size inductor and capacitors. Introduction Operation Modes The NCP81172 has three power operation modes responding to PSI levels as shown in Table 1. The operation mode can be changed on the fly. In 1−phase operation, no switching in phase 2. Table 1. POWER SAVING INTERFACE (PSI) CONFIGURATION PSI Level Power Mode Phase Configuration High (PSI 2.4 V) PS0 2−Phase, FCCM Intermediate (0.8 V < PSI < 2.4 V) PS1 1−Phase, FCCM Low (PSI 0.8 V) PS2 1−Phase, Auto CCM/DCM Switching Frequency The NCP81172 is also able to support pure single−phase applications without a need to stuff components for phase 2. In this configuration, the four pins including BST2, HG2, LG2, and PH2 can be float, but make sure the voltage at PSI pin is never in high level. Switching frequency is programmed by a resistor RFS applied from the FS pin to ground. The typical frequency range is from 200 kHz to 800 kHz. The FS pin provides approximately 2 V out and the source current is mirrored into the internal ramp generator. The switching frequency in 2−phase operation (PS0 mode) can be estimated by Remote Voltage Sense A high performance and high input impedance differential error amplifier, as shown in Figure 4, provides an accurate sense for the output voltage of the regulator. The output voltage and FBRTN inputs should be connected to the regulator’s output voltage sense points via a Kelvin−sense pair. The output voltage sense signal goes through a compensation network and into the inverting input (FB pin) of the error amplifier. The non−inverting input of the error amplifier is connected to the reference input (REFIN pin). 7 11 10 25 12 F SW(kHz) + 6603 @ R FS(kW) −0.766 (eq. 1) To reduce output ripple in 1−phase operation, the switching frequency in PS1 and PS2 modes is set to be higher than PS0 mode, which can be estimated by F SW(kHz) + 5226 @ R FS(kW) −0.665 (eq. 2) Figure 5 shows a measurement based on a typical application under condition of Vin = 20 V, Vout = 0.9 V, Iout = 10 A for PS1 mode operation and Iout = 20 A for PS0 mode operation. It can be also found that the higher RDS(on) of the low−side MOSFETs the smaller frequency difference between PS0 and PS1 mode. REFIN FB FBRTN GND COMP Figure 4. Differential Error Amplifier http://onsemi.com 10 NCP81172 Figure 5. Switching Frequency Programmed by Resistor RFS at FS Pin Soft Start voltage divider, consisting of a NTC thermistor R_NTC and a resistor R_TSNS, is employed to sense temperature and program alert level. Usually the thermistor is placed close to a hot spot like a power MOSFET. The NCP81172 monitors the voltage at TSNS pin and compares the voltage to an internal 1 V threshold by an internal comparator. Once the TSNS voltage drops below 1 V, the comparator turns on an open−drain switch at TALERT# pin and thus indicates a high temperature alert. The thermal alert can be de−asserted when TSNS voltage raises back to be higher than 1.05V. In an exemplary application where a 100 kW (B = 4250 at 25C) NTC thermistor is applied together with a 5.62 kW resistor, an low−valid thermal alert signal is asserted when the temperature of the NTC thermistor reaches 100C and de−asserted when the temperature drops down to 97C. The NCP81172 has a soft start function. The output starts to ramp up following a system reset period after the device is enabled. The device is able to start up smoothly under an output pre−biased condition without discharging the output before ramping up. REFIN Discharge An internal switch in REFIN pin starts to short REFIN to GND just after EN is pulled high and it turns off just before the beginning of the soft start. The typical on resistance of the switch is 6.25 W. Output Discharge in Shut Down The NCP81172 has an output discharge function when the device is in shutdown mode. The resistors (2 kW per phase) from PH node to PGND in both phases are active to discharge the output capacitors. Thermal Shutdown The NCP81172 has a thermal shutdown protection to protect the device from overheating when the die temperature exceeds 150C. Once the thermal protection is triggered, the fault state can be ended by re−applying VCC and/or EN if the temperature drops down below 125C. Temperature Sense and Thermal Alert The NCP81172 provides external temperature sense and thermal alert in the normal operation mode, and disables the function in the standby mode. The temperature sense and thermal alert circuit diagram is shown in . An external http://onsemi.com 11 NCP81172 8 VREF R_TSNS 2.0V R_NTC 13 1.0V 14 TALERT # R_TALERT TALERT# TSNS 3.3V Figure 6. Temperature Sense and Thermal Alert Circuit Diagram Over Current Protection Fast under voltage protection (FUVP) protects converters in case of an extreme short circuit in output by monitoring FB voltage. Once FB voltage drops below 0.2 V for more than 2 ms, the NCP81172 latches off, both the high−side MOSFETs and the low-side MOSFETs in all phases are turned off. The fault remains set until the system has either VCC or EN toggled state. The FUVP function is disabled in soft start. Slow under voltage protection (SUVP) of the NCP81172 is based on voltage detection at COMP pin. In normal operation, COMP level is below 2.5 V. When the output voltage drops below REFIN voltage for long time and COMP rises to be over 3 V, an internal UV fault timer will be triggered. If the fault still exists after 50 ms, the NCP81172 latches off, both the high-side MOSFETs and the low−side MOSFETs in all phases are turned off. The fault remains set until the system has either VCC or EN toggled state. The NCP81172 protects converters from over current. The current through each phase is monitored by voltage sensing from phase node PHx to power ground PGND. The sense signal is compared to an internal voltage threshold. Once over load happens, the inductor current is limited to an average current per phase, which can be estimated by I LMT(phase) + V thOC R DS(phase) (eq. 3) where RDS(phase) is a total on conduction resistance of low−side MOSFETs per phase. Normally, a continuous over load event leads to a voltage drop in the output voltage and possible to eventually trip under voltage protection. The over−current threshold can be externally programmed by adding a 1% tolerance resistor between LG1 pin and GND. The selectable thresholds can be found in the electrical table. Please note the maximum RC time constant formed by the resistor and the total input capacitance of the low−side MOSFETs should be smaller than 300 ms in order to make sure the detection voltage settles well. Over Voltage Protection Over voltage protection of the NCP81172 is based on voltage detection at FB pin. Once FB voltage is over 2 V for more than 2 ms, all the high−side MOSFETs are turned off and all the low−side MOSFETs are latched on. The NCP81172 latches off until the system has either VCC or EN has toggled state. Under Voltage Protection There are two under voltage protections implemented in the NCP81172, which are fast under voltage protection and slow under voltage protection. http://onsemi.com 12 NCP81172 LAYOUT GUIDELINES Electrical Layout Considerations Good electrical layout is a key to make sure proper operation, high efficiency, and noise reduction. Power Paths: Use wide and short traces for power paths to reduce parasitic inductance and high−frequency loop area. It is also good for efficiency improvement. Power Supply Decoupling: The power MOSFET bridges should be well decoupled by input capacitors and input loop area should be as small as possible to reduce parasitic inductance, input voltage spike, and noise emission. Place decoupling caps as close as possible to the controller VCC and VCCP pins. Output Decoupling: The output capacitors should be as close as possible to the load like a GPU. If the load is distributed, the capacitors should also be distributed and generally placed in greater proportion where the load is more dynamic. Switching Nodes: Switching nodes between HS and LS MOSFETs should be copper pours to carry high current and dissipate heat, but compact because they are also noise sources. Gate Drive: All the gate drive traces such as HGx, LGx, PHx, and BSTx should be short, straight as possible, and not too thin. The bootstrap cap and an option resistor need to be very close and directly connected between BSTx pin and PHx pin. Ground: It would be good to have separated ground planes for PGND and GND and connect the two planes at one point. PGND plane is an isolation plane between noisy power traces and all the sensitive control circuits. Directly connect the exposed pad (GND pin) to GND ground plane through vias. The analog control circuits should be surrounded by GND ground plane. GND ground plane is connected to PGND plane by single joint with low impedance. Voltage Sense: Use Kelvin sense pair and arrange a “quiet” path for the differential output voltage sense. Current Sense: The NCP81172 senses phase currents by monitoring voltages from phase nodes PHx to the common ground PGND pin. PGND ground plane should be well underneath PHx trances. To get better current balance between the two phases, try to make a layout as symmetrical as possible and balance the current flow in PGND plane for the two phases. Temperature Sense: A NTC thermistor is placed close to a hot spot like a power MOSFET, and a filter capacitor is placed close to TSNS pin of the controller. To avoid the traces from/to the NTC thermistor to cross over other sensitive control circuits. Compensation Network: The compensation network should be close to the controller. Keep FB trace short to minimize their capacitance to GND. PWM VID Circuit: The PWM VID is a high slew−rate digital signal from GPU to the controller. The trace routing of it should be done to avoid noise coupling from the switching node and to avoid coupling to other sensitive analog circuit as well. The RC network of the PWM VID circuit needs to be close to the controller. A 10 nF ceramic cap is connected from VREF pin to GND plane, and another small ceramic cap is connected from REFIN pin to GND plane. Thermal Layout Considerations Good thermal layout helps high power dissipation from a small−form factor VR with reduced temperature rise. The exposed pads of the controller and power MOSFETs must be well soldered on the board. A four or more layers PCB board with solid ground planes is preferred for better heat dissipation. More vias are welcome to be underneath the exposed pads and surrounding the power devices to connect the inner ground layers to reduce thermal resistances. Use large area copper pour to help thermal conduction and radiation. Try distributing multiple heat sources to reduce temperature rise in hot spots. http://onsemi.com 13 NCP81172 PACKAGE DIMENSIONS QFN24, 4x4, 0.5P CASE 485L ISSUE B D PIN 1 REFEENCE 2X ÉÉÉ ÉÉÉ 0.15 C DETAIL A E ALTERNATE CONSTRUCTIONS ÉÉ ÉÉ ÇÇ EXPOSED Cu TOP VIEW DETAIL B 0.10 C A3 NOTE 4 A1 SEATING PLANE L 24X 7 DIM A A1 A3 b D D2 E E2 e L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.30 0.50 0.05 0.15 RECOMMENDED SOLDERING FOOTPRINT* D2 DETAIL A ÉÉ ÇÇ ÇÇ A3 ALTERNATE TERMINAL CONSTRUCTIONS C A1 SIDE VIEW MOLD CMPD DETAIL B A 0.08 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 0.15 C 2X L L A B 4.30 13 24X 0.55 2.90 E2 1 1 24 19 e e/2 BOTTOM VIEW 24X b 0.10 C A B 0.05 C 4.30 2.90 NOTE 3 0.50 PITCH 24X 0.32 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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