Integrated
Circuit
Systems, Inc.
ICS9250-08
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Pin Configuration
VDDREF
*FS2/REF1
*PCI_STOP/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
BUFFERIN
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
2
I C
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
{
ICS9250-08
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
•
3 - CPUs @2.5V, up to 150MHz.
•
17 - SDRAM @ 3.3V, up to 150MHz.
•
7 - PCI @3.3V
•
2 - IOAPIC @ 2.5V
•
1 - 48MHz, @3.3V fixed.
•
1 - 24MHz @ 3.3V
•
2 - REF @3.3V, 14.318MHz.
Features:
•
Up to 150MHz frequency support
•
Support power management: CPU, PCI, stop and Power
down Mode form I2C programming.
•
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
•
Uses external 14.318MHz crystal
Key Specifications:
•
CPU – CPU: <175ps
•
CPU – PCI: min = 1ns max = 4ns
•
PCI – PCI: <250ps
•
SDRAM - SDRAM: <500ps
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDLIOAPIC
IOAPIC0
IOAPIC_F
GND
CPUCLK_F
CPUCLK1
VDDLCPU
CPUCLK2
GND
CPU_STOP#
SDRAM_F
VDDSDR
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
VDD48
24MHz/FS0*
48MHz/FS1*
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
** Internal Pull-down resistor of 240K to GND on indicated inputs.
Block Diagram
PLL2
48MHz
24MHz
÷2
IOAPIC_F
X1
X2
XTAL
OSC
IOAPIC0
STOP
2
PLL1
Spread
Spectrum
FS[3:0]
MODE
1
STOP
2
4
PCI
CLOCK
DIVDER
STOP
6
CPUCLK [2:1]
PCI_STOP#
SCLK
{ SDATA
BUFFERIN
PCICLK [5:0]
PCICLK_F
CPU_STOP#
2
CPUCLK_F
LATCH
POR
I C
REF [1:0]
Control
Logic
Config.
Reg.
STOP
16
SDRAM [15:0]
SDRAM_F
9250-08 Rev H 10/8/99
Third party brands and names are the property of their respective owners.
Functionality
FS3
FS2
FS1
FS0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CPU
(MHz)
133
124
150
140
105
110
115
120
100.3
133
112
103
66.8
83.3
75
124
PCICLK (MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.67 (CPU/3)
38.33 (CPU/3)
40.00 (CPU/3)
33.43 (CPU/3)
44.33 (CPU/3)
37.33 (CPU/3)
34.33 (CPU/2)
33.40 (CPU/2)
41.65 (CPU/2)
37.5 (CPU/2)
41.33 (CPU/2)
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9250-08
Pin Configuration
PIN NUMBER
2
3
P I N NA M E
REF1
FS21
REF0
P C I _ S TO P # 1
4, 10, 23, 26, 34, 42,
GND
48, 53
TYPE
OUT
IN
OUT
IN
PWR
5
X1
IN
6
X2
OUT
PCICLK_F
OUT
8
9
16, 14, 13, 12, 11
17
27
28
MODE1
IN
FS31
IN
DESCRIPTION
14.318 MHz reference clock output
L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D P C I
14.318MHz reference clock output
Halts PCICLK [5:0] at logic "0" level when low.
(in mobile, MODE=0)
Ground.
14.318MHz input. Has internal load cap, (nominal 33pF).
Crystal output. Has internal load cap (33pF) and feedback
resistor to X1
Free running BUS clock not affected by PCI_STOP#
Latched input for MODE select. Converts pin 3 to PCI_STOP# when
low for power management.
Latched frequency select input, pull-down
PCICLK0
OUT
Free running BUS clock not affected by PCI_STOP#
PCICLK [5:1]
OUT
PCI Clock Outputs.
BU F F E R I N
SDATA
SCLK
24MHz
IN
IN
IN
Input for Buffers
S e r i a l d a t a i n f o r s e r i a l c o n fi g p o r t . ( I 2 C )
Clock input for serial config port. (I2C)
OUT
24MHz clock output for Super I/O or FD.
30
FS01
IN
L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D 4 .
OUT
IN
48MHz clock output for USB.
L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D 2 .
PWR
Nominal 3.3V power supply, see power groups for function.
SDRAM [15:0]
OUT
SDRAM clocks
46
SDRAM_F
OUT
Free running SDRAM clock Not affected by CPU_STOP#
47
C P U _ S TO P #
29
1, 7, 15, 20,
31, 37, 45
24, 25, 32, 33, 18,
19, 21, 22, 35, 36,
38, 39, 40, 41, 43,
44
50, 56
55
51, 49
52
54
48MHz
FS11
VDDPCI, VDDREF,
VDDSDR, VDD48
VDDLCPU,
VDDLIOAPIC
I OA P I C 0
CPUCLK [2:1]
CPUCLK_F
I OA P I C _ F
IN
Halts CPUCLK [2:1], IOAPIC0, SDRAM [15:0]
clocks at logic "0" level when low.
PWR
CPU and IOAPIC clock buffer power supply, 2.5V nominal.
OUT
OUT
OUT
IOAPIC clock output. (14.318 MHz) Poweredby VDDLIOAPIC
CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)
Free running CPU output clock. Not affected ty the CPU_STOP#.
Freerunning IOAPIC clock output. Not affected by the CPU_STOP#
(14.31818 MHz) Powered by VDDLIOAPIC
OUT
Notes:
1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9250-08
General Description
Power Groups
The ICS9250-08 is the single chip clock solution for Desktop/
designs using BX, Appollo Pro 133 type of chip sets. It provides
all necessary clock signals for such a system.
VDDREF = REF [1:0], X1, X2
VDDPCI = PCICLK_F, PCICLK [5:0]
VDDSDR = SDRAM [15:0], supply for PLL core,
VDD48 = 48MHz, 24MHz
VDDLIOAPIC = IOAPIC_F
VDDLCPU = CPUCLK_F [2:1]
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9250-08
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
MODE
(Latched Input)
0
1
PCI_STOP#
(Input)
REF0
(Output)
Third party brands and names are the property of their respective owners.
3
ICS9250-08
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ICS (Slave/Receiver)
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
4
ICS9250-08
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Bit 2,
Bit 6:4
Bit 3
Bit 1
Bit 0
Description
0 - ±0.25% Spread Spectrum Modulation
1 - ±0.5% Spread Spectrum Modulation
Bit2 Bit6 Bit5 Bit4
CPU clock
PCI
0111
100.3
33.43 (CPU/3)
0110
133
44.33 (CPU/3)
0101
112
37.33 (CPU/3)
0100
103
34.3 (CPU/3)
0011
66.8
33.4 (CPU/2)
0010
83.3
41.65(CPU/2)
0001
75
37.5 (CPU/2)
0000
124
41.33 (CPU/3)
1111
133
33.25 (CPU/4)
1110
124
31.00 (CPU/4)
1101
150
37.50 (CPU/4)
1100
140
35.00 (CPU/4)
1011
105
35.00 (CPU/3)
1010
110
36.67 (CPU/3)
1001
115
38.33 (CPU/3)
1000
120
40.00 (CPU/3)
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 6:4 (above)
0 - Normal
1 - Spread Spectrum Enabled (Center Spread)
0 - Running
1- Tristate all outputs
PWD
0
Note1
0
0
0
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 2, 4, 5,
6 are default to 0000, and if bit 3 is written to a 1 to use Bits 2, 6:4, then these
should be defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
Third party brands and names are the property of their respective owners.
5
ICS9250-08
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
46
49
51
52
PWD
1
1
1
1
1
1
1
1
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
DESCRIPTION
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
SDRAM_F (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK_F (Act/Inact)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
30
29
33, 32,
25, 24
22, 21,
19, 18
39, 38,
36, 35
44, 43,
41, 40
PWD
1
1
1
1
BIT PIN# PWD
Bit 7
X
Bit 6
1
Bit 5
1
Bit 4
X
Bit 3
1
Bit 2
1
Bit 1
X
Bit 0
1
DESCRIPTION
R e s e r ve d
R e s e r ve d
24MHz (Act/Inact)
48MHz (Act/Inact)
1
SDRAM(12:15) (Act/Inact)
1
SDRAM (8:11) (Act/Inact)
1
SDRAM (4:7) (Act/Inact)
1
SDRAM0 (0:3) (Act/Inact)
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
R e s e r ve d
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
PIN#
8
16
14
13
12
11
9
DESCRIPTION
Latched FS0#
R e s e r ve d
R e s e r ve d
Latched FS1#
R e s e r ve d
R e s e r ve d
Latched FS3#
R e s e r ve d
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
Bit 7
1
Bit 6
X
Bit 5
54
1
Bit 4
55
1
Bit 3
1
Bit 2
1
Bit 1
2
1
Bit 0
3
1
DESCRIPTION
R e s e r ve d
Latched FS2#
IOAPIC_F (Act/Inact)
IOAPIC0 (Act/Inact)
R e s e r ve d
R e s e r ve d
REF1 (Act/Inact)
REF0 (Act/Inact)
Third party brands and names are the property of their respective owners.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
6
ICS9250-08
Shared Pin Operation Input/Output Pins
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
The I/O pins designated by (input/output) on the ICS925008 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 4-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
Third party brands and names are the property of their respective owners.
7
ICS9250-08
Fig. 2a
Fig. 2b
Third party brands and names are the property of their respective owners.
8
ICS9250-08
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9250-08. All other clocks will continue to run while the CPUCLKs are disabled. The
CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the
CPUCLKs inside the ICS9250-08.
3. IOAPIC output is stopped Glitch Free by CPUSTOP# going low.
4. PCI_STOP# is shown in a high (true) state.
5. All other clocks continue to run undisturbed.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9250-08. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9250-08 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full
high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK
clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the device.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
9
ICS9250-08
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .
7.0 V
GND 0.5 V to V DD +0.5 V
0°C to +70°C
115°C
65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
2
VDD+0.3
V
Input High Voltage
VIH
VSS-0.3
0.8
V
Input Low Voltage
VIL
µA
VIN = VDD
0.1
5
Input High Current
IIH
µA
Input Low Current
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
2.0
µA
VIN = 0 V; Inputs with pull-up resistors
-200
-100
Input Low Current
IIL2
IDD3.3OP66 Select @ 66MHz; Sdram running, unloaded
112
140
Operating Supply
mA
150
IDD3.3OP100 Select @ 100MHz; Sdram running, unloaded
180
Current
200
IDD3.3OP133 Select @ 133MHz; Sdram running, unloaded
250
VDD = 3.3 V
12
14.318
16
MHz
Input frequency
Fi
Logic Inputs
5
pF
CIN
Input Capacitance1
X1 & X2 pins
27
36
45
pF
CINX
Transition Time1
TTrans
To 1st crossing of target Freq.
3
ms
Settling Time1
TS
From 1st crossing to 1% target Freq.
1
3
ms
Clk Stabilization1
TStab
From VDD = 3.3 V to 1% target Freq.
3
ms
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
IDD2.5OP66 Select @ 66MHz; Max discrete cap loads
10
Operating
Operating
IDD2.5OP100 Select @ 100MHz; Max discrete cap loads
13
IDD2.5OP133 Select @ 133MHz; Max discrete cap loads
Supply Current
18
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
10
MAX
25
25
25
UNITS
mA
ICS9250-08
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
VOH2B
IOH = -12.0 mA
2
Output Low Voltage
VOL2B
IOL = 12 mA
Output High Current
IOH2B
VOH = 1.7 V
Output Low Current
IOL2B
VOL = 0.7 V
19
Rise Time
tr2B1
VOL = 0.4 V, VOH = 2.0 V
0.4
Fall Time
tf2B1
VOH = 2.0 V, VOL = 0.4 V
0.4
1
VT = 1.25 V; CPU < 120MHz
45
dt1B
Duty Cycle
dt2B1
VT = 1.25 V; CPU >= 124MHz
35
tsk2B1
VT = 1.25 V; CPU >= 100 MHz
Skew
tsk2B1
VT = 1.25 V; CPU < 100 MHz
1
Jitter, One Sigma
tj1σ2B
VT = 1.25 V
1
Jitter, Absolute
tjabs2B
VT = 1.25 V
-250
tjcyc-cyc2B1 VT = 1.25 V
Jitter, Cycle-to-cycle
TYP
2.3
0.3
-35
26
1.4
1.35
45
43
150
170
35
99
210
MAX UNITS
V
0.4
V
-19
mA
mA
1.8
ns
1.8
ns
55
%
50
175
ps
240
150
ps
+250
250
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
IOH = -18 mA
2.4
2.9
V
Output High Voltage
VOH1
IOL = 9.4 mA
0.2
0.4
V
Output Low Voltage
VOL1
Output High Current
IOH1
VOH = 2.0 V
-52
-22
mA
Output Low Current
IOL1
VOL = 0.8 V
25
41
mA
Rise Time1
tr1
VOL = 0.4 V, VOH = 2.4 V
0.5
2.2
2.6
ns
Fall Time1
tf1
VOH = 2.4 V, VOL = 0.4 V
0.5
1.8
2.2
ns
Duty Cycle1
dt1
tsk1
tsk1
VT = 1.5 V
VT = 1.5 V; All PCI clocks including PCI0
VT = 1.5 V; All PCI clocks except PCI0
46
50
400
250
56
850
500
%
tj1σ1
VT = 1.5 V
15
150
tjabs1
VT = 1.5 V
60
250
Skew1 window
Jitter, One Sigma1
Jitter, Absolute
1
1
-250
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
ps
ps
ICS9250-08
Electrical Characteristics - SDRAM
T A = 0 - 70º C; VDD = 3.3 V +/-5%, V DDL = 2.5 V +/-5%; C L =30 pF
PA RA M ETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Ris e Time
Fall Time
1
1
1
Duty Cycle
1
Skew W indow
Jitter, One Sigma
Jitter, A bs olute
1
1
1
SYM BOL
VO H 1
VO L 1
IO H 1
IO L 1
t r1
t r1
t f1
t f1
CONDITIONS
IO H = -28 mA
IO L = 19 mA
VO H = 2.0 V
VO L = 0.8 V
VOL = 0.4 V, VOH = 2.4 V; 66, 75, 83 M Hz
VO L = 0.4 V, VO H = 2.4 V; >= 100 M Hz
VO H = 2.4 V, VO L = 0.4 V; 66, 75, 83 M Hz
VO H = 2.4 V, VO L = 0.4 V; >= 100 M Hz
d t1
t sk 1
t sk 1
VT = 1.5 V; Input Duty Cycle at 50%
VT = 1.5 V; SD_F to 0:6, 8:10
VT = 1.5 VSD_F to 7, 12:15
t j1 σ1
VT = 1.5 V
t jab s 1
VT = 1.5 V
M IN
2.4
33
0.5
0.5
0.5
0.5
47
-250
TYP
2.8
0.34
-100
42
1.6
1.3
1.5
1.5
M A X UNITS
V
0.4
V
-42
mA
mA
2.2
1.6
ns
2.3
1.8
52
150
210
57
250
400
50
150
130
250
%
ps
Guaranteed by des ign, not 100% tes ted in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
VOH4B
IOH = -8 mA
2
IOL = 12 mA
Output Low Voltage
VOL4B
VOH = 1.7 V
Output High Current
IOH4B
VOL = 0.7 V
19
Output Low Current
IOL4B
Rise Time1
Fall Time
1
1
Duty Cycle
1
Jitter, One Sigma
Jitter, Absolute1
1
TYP
2.2
0.3
-24
26
MAX UNITS
V
0.4
V
-15
mA
mA
Tr4B
VOL = 0.4 V, VOH = 2.0 V
0.4
1.3
1.6
ns
Tf4B
VOH = 2.0 V, VOL = 0.4 V
0.4
2
2.6
ns
Dt4B
VT = 1.25 V
45
51
55
%
Tj1σ4B
VT = 1.25 V
240
300
ps
Tjabs4B
VT = 1.25 V
625
650
ps
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
ICS9250-08
Electrical Characteristics - 48M Hz, 24M Hz,REF0
T A = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; C L = 20 pF (unless otherwise stated)
PA RA METER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
Rise Time
Fall Time
1
1
1
Duty Cycle
1
1
Jitter, Cycle-to-cycle
Jitter, Cycle-to-cycle 1
1
SYMBOL
VO H 5
VO L5
IO H 5
IO L5
CONDITIONS
IO H = -12 mA
IO L = 12 mA
VO H = 2.0 V
VO L = 0.8 V
MIN
2.4
10
TYP
2.8
0.2
-33
32
MA X UNITS
V
0.4
V
-20
mA
mA
t r5
VO L = 0.4 V, VO H = 2.4 V, 48MHz
2
4
ns
t f5
VO H = 2.4 V, VO L = 0.4 V, 48MHz
1.8
4
ns
d t5
VT = 1.5 V, 48MHz
50
55
%
t r5
VOL = 0.4 V, VOH = 2.4 V, REF0
2.2
4
ns
t f5
VOH = 2.4 V, VOL = 0.4 V, REF0
1.8
4
ns
d t5
VT = 1.5 V, REF
52
55
%
700
1100
ps
500
800
ps
TYP
2.8
0.2
-28
22
MAX UNITS
V
0.4
V
-20
mA
mA
t jcyc-cyc5
t jcyc-cyc5
45
45
VT = 1.5 V, 24, 48MHz
VT = 1.5 V, REF0
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF1
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
IOH = -14 mA
2.4
Output High Voltage
VOH5
IOL = 6 mA
Output Low Voltage
VOL5
Output High Current
IOH5
VOH = 2.0 V
Output Low Current
IOL5
VOL = 0.8 V
10
Rise Time1
Fall Time
1
1
Duty Cycle
Jitter, Cycle-to-cycle1
1
tr5
VOL = 0.4 V, VOH = 2.4 V, REF1
2.5
4
ns
tf5
VOH = 2.4 V, VOL = 0.4 V, REF1
2.2
4
ns
50
600
55
800
%
ps
dt5
tjcyc-cyc5
VT = 1.5 V, REF1
VT = 1.5 V, REF1
45
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
ICS9250-08
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
Ferrite
Bead
VDD
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
Notes:
1) All clock outputs should have a
series terminating resistor, and a 20pF
capacitor to ground between the
resistor and clock pin. Not shown in
all places to improve readibility of
diagram.
2) Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
C1
C1
2
3.3V Power Route
Component Values:
C1 : Crystal load values determined by user
C2 : 22µF/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 100pF ceramic capacitor
C4 : 20pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01µF ceramic
Connections to VDD:
C2
22µF/20V
Tantalum
C2
22µF/20V
Tantalum
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
Ferrite
Bead
VDD
C3
2.5V Power Route
1
Clock Load
C3
3.3V Power Route
Ground
Ground
= Routed Power
= Ground Connection (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
Third party brands and names are the property of their respective owners.
14
ICS9250-08
SYMBOL
A
A1
A2
B
C
D
E
e
H
h
L
N
µ
X
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095
.101
.110
.008
.012
.016
.088
.090
.092
.008
.010
.0135
.005
.010
See Variations
.292
.296
.299
0.025 BSC
.400
.406
.410
.010
.013
.016
.024
.032
.040
See Variations
0°
5°
8°
.085
.093
.100
VARIATIONS
MIN.
.720
AD
D
NOM.
.725
N
MAX.
.730
56
SSOP Package
Ordering Information
ICS9250yF-08
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
15
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.