3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 FEATURES: • • • • • • • • • • • • • • 2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay Automatic identification of ST-BUS®/GCI interfaces Accept streams of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s Automatic frame offset delay measurement Per-stream frame delay offset programming Per-channel high impedance output control Per-channel Processor Mode Control interface compatible to Intel/Motorola CPUs Connection memory block programming IEEE-1149.1 (JTAG) Test Port Available in 84-pin Plastic Leaded Chip Carrier (PLCC), 100-pin Ball Grid Array (BGA), 100-pin Plastic Quad Flatpack IDT72V90823 (PQFP) and 100-pin Thin Quad Flatpack (TQFP) 3.3V Power Supply Operating Temperature Range -40°°C to +85°°C DESCRIPTION: The IDT72V90823 is a non-blocking digital switch that has a capacity of 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s, 1,024 x 1,024 channels at 4.096 Mb/s and 512 x 512 channels at 2.048 Mb/s. Some of the main features are: programmable stream and channel control, Processor Mode, input offset delay and high-impedance output control. Per-stream input delay control is provided for managing large multi-chip switches that transport both voice channel and concatenated data channels. In addition, input streams can be individually calibrated for input frame offset. FUNCTIONAL BLOCK DIAGRAM VCC GND RESET TMS TDI TDO TCK TRST ODE IC Test Port RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 Loopback Receive Serial Data Streams Output MUX Data Memory Connection Memory Internal Registers Timing Unit CLK F0i FE/ WFPS HCLK Transmit Serial Data Streams TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 TX8 TX9 TX10 TX11 TX12 TX13 TX14 TX15 Microprocessor Interface AS/ IM DS/ RD ALE CS R/W/ A0-A7 DTA D8-D15/ WR AD0-AD7 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp. CCO 5712 drw01 DECEMBER 2002 1 2002 Integrated Device Technology, Inc. All rights reserves. Product specifications subject to change without notice. DSC-5712/4 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATIONS A1 BALL PAD CORNER A RX0 TX13 TX11 TX10 TX8 TX7 TX4 TX3 TX0 CCO RX2 RX1 TX14 TX12 TX9 TX6 TX5 TX2 ODE D14 RX5 RX4 RX3 TX15 VCC VCC DNC TX1 D15 D12 RX7 RX8 RX6 VCC GND GND VCC DTA D13 D11 RX10 RX9 VCC GND GND GND GND VCC D10 D9 RX11 RX12 VCC GND GND GND GND VCC AD7 D8 RX13 RX15 VCC GND GND VCC AD4 AD6 AD5 CS AD1 AD2 AD3 AD0 B C D E F G CLK H J TCK RESET VCC RX14 FE/ HCLK FOI TDI TRST A0 A1 A4 A7 R/W/RW IM TMS TDO IC WFPS A2 A3 A5 A6 1 2 3 4 5 6 7 8 VCC K DS/RD AS/ALE 9 10 5712 drw02 RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 F0i FE/HCLK GND CLK VCC 12 13 14 15 GND ODE TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 GND VCC TX8 TX9 TX10 TX11 TX12 TX13 TX14 INDEX TX15 GND BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC) TOP VIEW 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 CCO DTA 69 68 67 66 65 D12 64 63 62 61 60 59 58 57 56 GND 55 54 AD0 D15 D14 D13 D11 D10 D9 D8 VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 GND NOTES: PLCC: 0.05in. pitch, 1.15in. x 1.15in. (PL84-1, order code: J) 1. DNC - Do Not Connect TOP VIEW 2. IC - Internal Connection, tie to GROUND for normal operation. 3. All I/O pins are 5V tolerant except for TMS, TDI and TRST. 2 IM AS/ALE R/W/RW CS DS/RD A7 A6 A5 A4 A3 A2 A1 A0 WFPS IC RESET TCK TRST TDO TDI TMS 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 5712 drw03 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE DNC 76 DNC 77 RX0 78 RX1 79 RX2 80 RX3 81 RX4 82 RX5 83 RX6 84 RX7 DNC GND TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 VCC GND TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 ODE GND DNC DNC 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DNC 74 75 PIN CONFIGURATIONS (CONTINUED) DNC 50 49 DNC 48 CCO 47 DTA 46 D15 45 D14 44 D13 43 D12 42 D11 85 41 D10 RX8 86 40 D9 30 AD1 CLK 97 29 AD0 VCC 98 28 GND DNC 99 27 DNC DNC 100 26 DNC 5712 drw04 DNC DNC IM CS AS/ALE R/W/RW DS/RD A7 A6 A5 A4 A3 A2 A1 WFPS A0 RESET IC TRST TCK TDI TDO TMS DNC DNC INDEX 25 AD2 96 24 31 23 95 GND 22 AD3 FE/HCLK 21 32 20 AD4 94 19 F0i 33 18 93 17 AD5 RX15 16 34 15 AD6 92 14 35 13 91 RX14 12 AD7 RX13 11 36 10 90 9 VCC RX12 8 37 7 89 6 GND RX11 5 38 4 D8 88 3 39 2 87 1 RX9 RX10 DNC DNC DNC 51 54 52 DNC 55 53 ODE GND CCO 57 TX0 58 56 TX1 59 TX4 62 60 TX5 63 TX3 TX6 64 TX2 TX7 65 61 GND 66 67 TX8 VCC TX10 TX9 70 68 TX11 71 69 TX13 TX12 73 72 TX15 TX14 75 GND 76 74 DNC DNC 78 77 DNC DNC 80 79 TQFP: 0.50mm pitch, 14mm x 14mm (PN100-1, order code: PF) TOP VIEW 94 37 AD5 RX14 95 36 AD4 RX15 96 35 AD3 FOi 97 34 AD2 FE/HCLK 98 33 AD1 GND 99 32 AD0 CLK 100 31 GND 13 14 15 16 17 18 19 A0 A1 A2 A3 A4 A5 11 8 RESET WFPS INDEX 30 RX13 DNC AD7 AD6 29 38 DNC 93 DNC RX12 28 39 27 92 DNC VCC RX11 24 40 25 26 91 CS AS/ALE IM GND RX10 23 D8 41 R/W/WR 42 90 22 89 RX9 DS/RD RX8 A7 D10 D9 20 43 21 88 A6 RX7 12 44 10 87 TRST IC D11 RX6 9 45 TCK 86 6 D12 RX5 7 46 TDI TDO 85 TMS D13 RX4 5 47 VCC 84 3 D14 RX3 4 48 DNC 83 DNC D15 RX2 1 DTA 49 2 50 82 DNC 81 RX1 DNC RX0 PQFP: 0.65mm pitch, 14mm x 20mm (PQ100-2, order code: PQF) TOP VIEW 3 5712 drw05 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION SYMBOL NAME GND Vcc TX0-15(1) O RX0-15(1) Ground. Vcc TX Output 0 to 15 (Three-state Outputs) RX Input 0 to 15 I/O F0i(1) Frame Pulse I I FE/HCLK(1) Frame Evaluation/ HCLK Clock CLK(1) Clock I TMS Test Mode Select I TDI Test Serial Data In I TDO Test Serial Data Out O TCK(1) TRST Test Clock Test Reset I I IC(1) Internal Connection I RESET(1) Device Reset (Schmitt Trigger Input) I WFPS(1) I A0-7(1) Wide Frame Pulse Select Address 0-7 DS/RD(1) Data Strobe/Read I R/W / WR(1) Read/Write / Write I CS(1) AS/ALE(1) I I Chip Select Address Strobe or Latch Enable I I DESCRIPTION Ground Rail. +3.3 Volt Power Supply. Serial data output stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0-1 in the IMS register. Serial data input stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0-1 in the IMS register. When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS® and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame pulse which conforms to WFPS formats. When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK (4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode. Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). Depending upon the value programmed at bits DR0-1 in the IMS register, this input accepts a 4.096, 8.192 or 16.384 MHz clock. JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pullup when not driven. JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up when not driven. JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when JTAG scan is not enabled. Provides the clock to the JTAG test logic. Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure that the IDT72V90823 is in the normal functional mode. Connect to GND for normal operation. This pin must be low for the IDT72V90823 to function normally and to comply with IEEE 1114 (JTAG) boundary scan requirements. This input (active LOW) puts the IDT72V90823 in its reset state that clears the device internal counters, registers and brings TX0-15 and microport data outputs to a high-impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held LOW for a minimum of 100ns to reset the device. When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in ST-BUS®/GCI mode. When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal memories. For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed bus operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs. In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs. Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V90823. This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed bus operation, connect this pin to ground. NOTE: 1. These pins are 5V tolerant. 4 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (CONTINUED) SYMBOL IM (1) AD0-7(1) NAME I/O CPU Interface Mode I Address/Data Bus 0 to 7 Data Bus 8-15 Data Transfer Acknowledgment I/O CCO(1) Control Output O ODE(1) Output Drive Enable I D8-15(1) DTA(1) I/O O DESCRIPTION When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor port is in non-multiplexed mode. These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins are also the input address bits of the microprocessor port. These pins are the eight most significant data bits of the microprocessor port. This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is in high-impedance. This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1,024 or 2.048 bits per frame respectively. The level of each bit is determined by the CCO bit in the connection memory. See External Drive Control Section. This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15 output drivers are enabled. However, each channel may still be put into a high-impedance state by using the per channel control bit in the connection memory. NOTE: 1. These pins are 5V tolerant. 5 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE By having the each location in the connection memory specify an input channel, multiple outputs can specify the same input address. This can be a powerful tool used for broadcasting data. In Processor Mode, the microprocessor writes data to the connection memory. Each location in the connection memory corresponds to a particular output stream and channel number and is transferred directly to the parallel-toserial converter one time-slot before it is to be output. This data will be output on the TX streams in every frame until the data is changed by the microprocessor. As the IDT72V90823 can be used in a wide variety of applications, the device also has memory locations to control the outputs based on operating mode. Specifically, the IDT72V90823 provides five per-channel control bits for the following functions: processor or connection mode, constant or variable delay, enables/three-state the TX output drivers and enables/disable the loopback function. In addition, one of these bits allows the user to control the CCO output. If an output channel is set to a high-impedance state through the connection memory, the TX output will be in a high-impedance state for the duration of that channel. In addition to the per-channel control, all channels on the ST-BUS® outputs can be placed in a high impedance state by either pulling the ODE input pin low or programming the Output Stand-By (OSB) bit in the interface mode selection register. This action overrides the per-channel programming in the connection memory bits. The connection memory data can be accessed via the microprocessor interface. The addressing of the devices internal registers, data and connection memories is performed through the address input pins and the Memory Select (MS) bit of the control register. For details on device addressing, see Software Control and Control Register bits description (Table 4, 6 and 7). FUNCTIONAL DESCRIPTION The IDT72V90823 is capable of switching up to 2,048 x 2,048, 64 Kbit/s PCM or N x 64 Kbit/s channel data. The device maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis. The serial input streams of the IDT72V90823 can have a bit rate of 2.048, 4.096 or 8.192 Mb/s and are arranged in 125µs wide frames, which contain 32, 64 or 128 channels respectively. The data rates on input and output streams are identical. In Processor Mode, the microprocessor can access input and output timeslots on a per channel basis allowing for transfer of control and status information. The IDT72V90823 automatically identifies the polarity of the frame synchronization input signal and configures the serial streams to either ST-BUS® or GCI formats. With the variety of different microprocessor interfaces, IDT72V90823 has provided an Input Mode pin (IM) to help integrate the device into different microprocessor based environments: Non-multiplexed or Multiplexed. These interfaces provide compatibility with multiplexed and Motorola non-multiplexed buses. The device can also resolve different control signals eliminating the use of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE). The frame offset calibration function allows users to measure the frame offset delay using a frame evaluation pin (FE). The input offset delay can be programmed for individual streams using internal frame input offset registers, see Table 11. The internal loopback allows the TX output data to be looped around to the RX inputs for diagnostic purposes. A functional Block Diagram of the IDT72V90823 is shown in Figure 1. DATA AND CONNECTION MEMORY The received serial data is converted to parallel format by internal serialto-parallel converters and stored sequentially in the data memory. The 8 KHz input frame pulse (F0i) is used to generate channel and frame boundaries of the input serial data. Depending on the interface mode select (IMS) register, the usable data memory may be as large as 2,048 bytes. Data to be output on the serial streams (TX0-15) may come from either the data memory or connection memory. For data output from data memory (connection mode), addresses in the connection memory are used. For data to be output from connection memory, the connection memory control bits must set the particular TX output in Processor Mode. One time-slot before the data is to be output, data from either connection memory or data memory is read internally. This allows enough time for memory access and parallel-to-serial conversion. SERIAL DATA INTERFACE TIMING The master clock frequency must always be twice the data rate. For serial data rates of 2.048, 4.096 or 8.192 Mb/s, the master clock (CLK) must be either at 4.096, 8.192 or 16.384 MHz respectively. The input and output stream data rates will always be identical. The IDT72V90823 provides two different interface timing modes ST-BUS®/ GCI and WFP (wide frame pulse). If the WFPS pin is high, the IDT72V90823 is in the wide frame pulse (WFP) frame alignment mode. In ST-BUS®/GCI mode, the input 8 KHz frame pulse can be in either ST-BUS® or GCI format. The IDT72V90823 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS® or GCI. In ST-BUS® format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of CLK, three quarters of the way into the bit cell, see Figure 7. In GCI format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell, see Figure 8. CONNECTION AND PROCESSOR MODES In the Connection Mode, the addresses of the input source data for all output channels are stored in the connection memory. The connection memory is mapped in such a way that each location corresponds to an output channel on the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 13 and Table 14. Once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto a TX output stream. WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING When the device is in WFP frame alignment mode, the CLK input must be at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 kHz frame pulse is in ST-BUS® format. The timing relationship between CLK, HCLK and the frame pulse is shown in Figure 9. When WFPS pin is high, the frame alignment evaluation feature is disabled. However, the frame input offset registers may still be programmed to compensate for the varying frame delays on the serial input streams. 6 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE from low to high, the evaluation starts. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register (FAR) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the FAR register. The SFE bit must be set to zero before a new measurement cycle started. In ST-BUS® mode, the falling edge of the frame measurement signal (FE) is evaluated against the falling edge of the ST-BUS® frame pulse. In GCI mode, the rising edge of FE is evaluated against the rising edge of the GCI frame pulse. See Table 10 & Figure 4 for the description of the frame alignment register. This feature is not available when the WFP Frame Alignment mode is enabled (i.e., when the WFPS pin is connected to VCC). SWITCHING CONFIGURATIONS The IDT72V90823 can operate at different speeds. To configure the maximum non-blocking switching data rate, the two DR bits in the IMS register are used. Following are the possible configurations: 2.048 Mb/s Serial Links (DR0=0, DR1=0) When the 2.048 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 32, 64 Kbit/s channels each. This mode requires a CLK of 4.096 MHz and allows a maximum non-blocking capacity of 512 x 512 channels. 4.096 Mb/s Serial Links (DR0=1, DR1=0) When the 4.096 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 64, 64 Kbit/s channels each. This mode requires a CLK of 8.192 MHz and allows a maximum non-blocking capacity of 1,024 x 1,024 channels. MEMORY BLOCK PROGRAMMING The IDT72V90823 provides users with the capability of initializing the entire connection memory block in two frames. To set bits 11 to 15 of every connection memory location, first program the desired pattern in bits 5 to 9 of the IMS register. The block programming mode is enabled by setting the memory block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data will be loaded into the bits 11 to 15 of every connection memory location. The other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero. 8.192 Mb/s Serial Links (DR0=0, DR1=1) When the 8.192 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 128, 64 Kbit/s channels each. This mode requires a CLK of 16.384 MHz and allows a maximum non-blocking capacity of 2,048 x 2,048 channels. Table 1 summarizes the switching configurations and the relationship between different serial data rates and the master clock frequencies. LOOPBACK CONTROL The loopback control (LPBK) bit of each connection memory location allows the TX output data to be looped backed internally to the RX input for diagnostic purposes. If the LPBK bit is high, the associated TX output channel data is internally looped back to the RX input channel (i.e., data from TX n channel m routes to the RX n channel m internally); if the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero. INPUT FRAME OFFSET SELECTION Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. F0i). Although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. Because data is often delayed, this feature is useful in compensating for the skew between clocks. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR). The maximum allowable skew is +4.5 master clock (CLK) periods forward with resolution of 1/2 clock period. The output frame offset cannot be offset or adjusted. See Figure 5, Table 11 and 12 for delay offset programming. DELAY THROUGH THE IDT72V90823 The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on the per-channel basis. For voice applications, variable throughput delay is best as it ensures minimum delay between input and output data. In wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. The delay through the device varies according to the type of throughput delay selected in the V/C bit of the connection memory. SERIAL INPUT FRAME ALIGNMENT EVALUATION The IDT72V90823 provides the frame evaluation (FE) input to determine different data input delays with respect to the frame pulse F0i. A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. When the SFE bit in the IMS register is changed VARIABLE DELAY MODE (V/C BIT = 0) In this mode, the delay is dependent only on the combination of source and destination channels and is independent of input and output streams. The minimum delay achievable in the IDT72V90823 is three time-slots. If the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame (channel n, frame p+1). The same is true if input channel n is switched to output channel n+1 or n+2. If the input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. Table 2 shows the possible delays for the IDT72V90823 in the variable delay mode. TABLE 1 — SWITCHING CONFIGURATION Serial Interface Data Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Master Clock Required (MHz) 4.096 8.192 16.384 Matrix Channel Capacity 512 x 512 1,024 x 1,024 2,048 x 2,048 7 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE entire connection memory block to be programmed. The memory select bit is used to designate the connection memory or the data Memory. The stream address bits select internal memory subsections corresponding to input or output serial streams. The data in the IMS register consists of block programming bits (BPD0BPD4), block programming enable bit (BPE), output stand by bit (OSB), start frame evaluation bit (SFE) and data rate selection bits (DR0-1). The block programming and the block programming enable bits allows users to program the entire connection memory (see Memory Block Programming section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-BUS® output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all TX output drivers are enabled. CONSTANT DELAY MODE (V/C BIT = 1) In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2. In the IDT72V90823, the minimum throughput delay achievable in the constant delay mode will be one frame. For example, in 2 Mb/s mode, when input timeslot 31 is switched to output time-slot 0. The maximum delay of 94 time-slots of delay occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 3. MICROPROCESSOR INTERFACE The IDT72V90823 provides a parallel microprocessor interface for multiplexed or non-multiplexed bus structures. This interface is compatible with Motorola non-multiplexed and multiplexed buses. If the IM pin is low a Motorola non-multiplexed bus should be connected to the device. If the IM pin is high, the device monitors the AS/ALE and DS/RD to determine what mode the IDT72V90823 should operate in. If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the mode 2 multiplexed bus timing is selected. For multiplexed operation, the required signals are the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch enable (AS/ ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR), Chip select (CS) and Data transfer acknowledge (DTA). See Figure 12 and Figure 13 for multiplexed parallel microport timing. For the Motorola non-multiplexed bus, the required signals are the 16-bit data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines (CS, DS, R/W and DTA). See Figure 14 and 15 for Motorola non-multiplexed microport timing. The IDT72V90823 microport provides access to the internal registers, connection and data memories. All locations provide read/write access except for the data memory and the frame alignment register which are read only. CONNECTION MEMORY CONTROL The CCO pin is a 4.096, 8.192 or 16.384 Mb/s output, which carries 512, 1,024 or 2,048 bits, respectively. The contents of the CCO bit of each connection memory location are output on the CCO pin once every frame. The contents of the CCO bits of the connection memory are transmitted sequentially on to the CCO pin and are synchronous with the data rates on the other serial streams. The CCO bit is output one channel before the corresponding channel on the serial streams. For example, in 2.048 Mb/s mode (32 channels per frame), the contents of the CCO bit in position 0 (TX0, CH0) of the connection memory is output on the first clock cycle of channel 31 through CCO pin. The contents of the CCO bit in position 32 (TX1, CH0) of the connection memory is output on the second clock cycle of channel 31 via CCO pin. If the ODE pin or the OSB bit is high, the OE bit of each connection memory location controls the output drivers-enables (if high) or disables (if low). See Table 5 for detail. The processor channel (PC) bit of the connection memory selects between Processor Mode and Connection Mode. If high, the contents of the connection memory are output on the TX streams. If low, the stream address bit (SAB) and the channel address bit (CAB) of the connection memory defines the source information (stream and channel) of the time-slot that will be switched to the output from data memory. The V/C (Variable/Constant Delay) bit in each connection memory location allows the per-channel selection between variable and constant throughput delay modes. If the LPBK bit is high, the associated TX output channel data is internally looped back to the RX input channel (i.e., RX n channel m data comes from the TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of the frame delay offset registers must be set to zero. MEMORY MAPPING The address bus on the microprocessor interface selects the internal registers and memories of the IDT72V90823. If the A7 address input is low, then A6 through A0 are used to address the interface mode selection (IMS), control (CR), frame alignment (FAR) and frame input offset (FOR) registers (Table 4). If the A7 is high, then A6 through A0 are used to select 32, 64, or 128 locations corresponding to data rate of the STBUS®. The address input lines and the stream address bits (STA) of the control register allow access to the entire data and connection memories. The control and IMS registers together control all the major functions of the device, see Figure 3. As explained in the Serial Data Interface Timing and Switching Configurations sections, after system power-up, the IMS register should be programmed immediately to establish the desired switching configuration. The data in the control register consists of the memory block programming bit (MBP), the memory select bit (MS) and the stream address bits (STA). As explained in the Memory Block Programming section, the MBP bit allows the INITIALIZATION OF THE IDT72V90823 After power up, the state of the connection memory is unknown. As such, the outputs should be put in high impedance by holding the ODE low. While the ODE is low, the microprocessor can initialize the device, program the active paths, and disable unused outputs by programming the OE bit in connection memory. Once the device is configured, the ODE pin (or OSB bit depending on initialization) can be switched. 8 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE Control Register CRb7 CRb6 CRb5 CRb4 CRb3 CRb2 CRb1 CRb0 CRb4 1 0 The Control Register is only accessed when A7-A0 are all zeroed. When A7 =1, up to 128 bytes are randomly accessable via A0-A6 at any one instant. Of which stream these bytes (channels) are accessed is determined by the state of CRb3 -CRb0. Connection Memory Data Memory Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 10000000 10000001 10000010 Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel CRb3 CRb2 CRb1 CRb0 Stream 0 0 0 0 0 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 11111111 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 0 1 0 1 0 7 8 1 0 0 1 9 1 0 1 0 1 0 1 1 10 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 External Address Bits A7-A0 5712 drw06 Figure 3. Addressing Internal Memories 9 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE TABLE 2 — VARIABLE THROUGHPUT DELAY VALUE Delay for Variable Throughput Delay Mode (m – output channel number) (n – input channel number) m = n, n+1, n+2 m-n + 32 time slots m-n + 64 time-slots m-n + 128 time-slots Input Rate m<n 32 – (n-m) time-slots 64 – (n-m) time-slots 128 – (n-m) time-slots 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s m > n+2 m-n time-slots m-n time slots m-n time-slots TABLE 3 — CONSTANT THROUGHPUT DELAY VALUE Delay for Constant Throughput Delay Mode (m – output channel number) (n – input channel number) 32 + (32 – n) + m time-slots 64 + (64 – n) + m time-slots 128 + (128 – n) + m time-slots Input Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s TABLE 4 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING A7(1) A6 A5 A4 A3 A2 A1 A0 Location 0 0 0 0 0 0 0 0 Control Register, CR 0 0 0 0 0 0 0 1 Interface Mode Selection Register, IMS 0 0 0 0 0 0 1 0 Frame Alignment Register, FAR 0 0 0 0 0 0 1 1 Frame Input Offset Register 0, FOR0 0 0 0 0 0 1 0 0 Frame Input Offset Register 1, FOR1 0 0 0 0 0 1 0 1 Frame Input Offset Register 2, FOR2 0 0 0 0 0 1 1 0 Frame Input Offset Register 3, FOR3 1 0 0 0 0 0 0 0 Ch0 1 0 0 0 0 0 0 1 Ch1 1 0 0 . . . . . . 1 0 0 1 1 1 1 0 Ch30 1 0 0 1 1 1 1 1 Ch31 1 0 1 0 0 0 0 0 Ch32 1 0 1 0 0 0 0 1 Ch33 1 0 1 . . . . . . 1 0 1 1 1 1 1 0 Ch62 1 0 1 1 1 1 1 1 Ch63 1 1 0 0 0 0 0 0 Ch64 1 1 0 0 0 0 0 1 Ch65 1 1 0 . . . . . . 1 1 1 1 1 1 1 0 Ch126 1 1 1 1 1 1 1 1 Ch127 Notes: 1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers. 2. Channels 0 to 31 are used when serial interface is at 2.048 Mb/s mode 3. Channels 0 to 63 are used when serial interface is at 4.096 Mb/s mode. 4. Channels 0 to 127 are used when serial interface is at 8.192 Mb/s mode. 10 (Note 2) (Note 3) (Note 4) IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE TABLE 5 — OUTPUT HIGH IMPEDANCE CONTROL OE bit in Connection Memory 0 ODE pin Don’t Care OSB bit in IMS Register Don’t Care 1 1 1 1 0 0 1 1 0 1 1 0 TX Output Driver Status Per Channel High-Impedance High-Impedance Enable Enable Enable TABLE 6 — CONTROL REGISTER (CR) BITS Read/Write Address: 00H, Reset Value: 0000H. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 MBP MS Bit 15-6 5 4 3-0 3 2 1 0 STA3 STA2 STA1 STA0 Name Unused MBP (Memory Block Program) Description Must be zero for normal operation. When 1, the connection memory block programming feature is ready for the programming of Connection Memory high bits, bit 11 to bit 15. When 0, this feature is disabled. MS (Memory Select) When 0, connection memory is selected for read or write operations. When 1, the data memory is selected for read operations and connection memory is selected for write operations. (No microprocessor write operation is allowed for the data memory.) STA3-0 (Stream Address Bits) The binary value expressed by these bits refers to the input or output data stream, which corresponds to the subsection of memory made accessible for subsequent operations. (STA3 = MSB, STA0 = LSB) TABLE 7 — VALID ADDRESS LINES FOR DIFFERENT BIT RATES Input/Output Data Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Valid Address Lines A4, A3, A2, A1, A0 A5, A4, A3, A2, A1, A0 A6, A5, A4, A3, A2, A1, A0 11 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE TABLE 8 — INTERFACE MODE SELECTION (IMS) REGISTER BITS Read/Write Address: Reset Value: 01H, 0000H. 15 14 13 12 11 10 0 0 0 0 0 0 Bit 15-10 9 8 7 6 5 BPD4 BPD3 BPD2 BPD1 BPD0 Name 4 3 2 1 0 BPE OSB SFE DR1 DR0 Description Unused Must be zero for normal operation. 9-5 BPD4-0 (Block Programming Data) These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD4-0 are loaded into bit 15 and 11 of the connection memory. Bit 10 to bit 0 of the connection memory are set to 0. 4 BPE (Begin Block Programming Enable) A zero to one transition of this bit enables the memory block programming function. The BPE and BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set HIGH, the device requires two frames to complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to ensure proper operation. When BPE = 1, the other bit in the IMS register must not be changed for two frames to ensure proper operation. 3 OSB (Output Stand By) When ODE = 0 and OSB = 0, the output drivers of TX0 to TX15 are in high impedance mode. When ODE= 0 and OSB = 1, the output driver of TX0 to TX15 function normally. When ODE = 1, TX0 to TX15 output drivers function normally. 2 SFE (Start Frame Evaluation) A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from zero to one, the evaluation procedure stops. To start another fame evaluation cycle, set this bit to zero for at least one frame. DR0-1 (Data Rate Select) Input/Output data rate selection. See Table 9 for detailed programming. 1-0 TABLE 9 — SERIAL DATA RATE SELECTION (16 INPUT X 16 OUTPUT) DR1 0 0 1 1 DR0 0 1 0 1 Data Rate Selected 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Reserved Master Clock Required 4.096 MHz 8.192 MHz 16.384 MHz Reserved 12 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE TABLE 10 — FRAME ALIGNMENT REGISTER (FAR) BITS Read/Write Address: Reset Value: 02H, 0000H. 15 14 13 12 0 0 0 CFE Bit 15-13 12 11 10-0 11 10 FD11 FD10 Name Unused CFE (Complete Frame Evaluation) FD11 (Frame Delay Bit 11) FD10-0 (Frame Delay Bits) 9 8 7 6 5 4 3 2 1 0 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 Description Must be zero for normal operation. When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0. The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle. The binary value expressed in these bits refers to the measured input offset value. These bits are rest to zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB) ST-BUS Frame CLK Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 13 14 15 FE Input (FD[10:0] = 06H) (FD11 = 0, sample at CLK LOW phase) GCI Frame CLK Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 FE Input (FD[10:0] = 09H) (FD11 = 1, sample at CLK HIGH phase) 5712 drw07 Figure 4. Example for Frame Alignment Measurement 13 16 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE TABLE 11 — FRAME INPUT OFFSET REGISTER (FOR) BITS Read/Write Address: Reset Value: 03H for FOR0 register, 04H for FOR1 register, 05H for FOR2 register, 06H for FOR3 register, 0000H for all FOR registers. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0 15 14 13 12 11 10 9 8 5 4 3 2 1 0 OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF50 DLE5 OF42 OF41 OF40 DLE4 15 14 13 12 11 10 9 8 5 4 3 2 1 0 OF90 DLE9 OF82 OF81 OF80 DLE8 5 4 3 2 1 0 FOR0 Register 7 6 14 13 12 11 10 9 OF51 FOR1 Register 7 6 OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 15 OF52 OF92 OF91 FOR2 Register 8 7 6 OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12 FOR3 Register Name(1) OFn2, OFn1, OFn0 (Offset Bits 2, 1 & 0) DLEn (Data Latch Edge) Description These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse input signal is applied to the F0i input of the device. See Figure 5. ST-BUS® mode: GCI mode: DLEn = 0, if clock rising edge is at the ¾ point of the bit cell. DLEn = 1, if when clock falling edge is at the ¾ of the bit cell. DLEn = 0, if clock falling edge is at the ¾ point of the bit cell. DLEn = 1, if when clock rising edge is at the ¾ of the bit cell. NOTE: 1. n denotes an input stream number from 0 to 15. 14 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE TABLE 12 — OFFSET BITS (OFN2, OFN1, OFN0, DLEN) & FRAME DELAY BITS (FD11, FD2-0) Measurement Result from Frame Delay Bits Input Stream Offset No clock period shift (Default) + 0.5 clock period shift + 1.0 clock period shift + 1.5 clock period shift + 2.0 clock period shift + 2.5 clock period shift + 3.0 clock period shift + 3.5 clock period shift + 4.0 clock period shift + 4.5 clock period shift FD11 1 0 1 0 1 0 1 0 1 0 FD2 0 0 0 0 0 0 0 0 1 1 FD1 0 0 0 0 1 1 1 1 0 0 Corresponding Offset Bits FD0 0 0 1 1 0 0 1 1 0 0 OFn2 0 0 0 0 0 0 0 0 1 1 OFn1 0 0 0 0 1 1 1 1 0 0 OFn0 0 0 1 1 0 0 1 1 0 0 DLEn 0 1 0 1 0 1 0 1 0 1 ST-BUS F0i CLK RX Stream Bit 7 RX Stream Bit 7 Bit 7 RX Stream DLE = 0 offset = 1, DLE = 0 offset = 0, DLE = 1 offset = 1, DLE = 1 Bit 7 RX Stream offset = 0, denotes the 3/4 point of the bit cell GCI F0i CLK RX Stream Bit 0 Bit 0 RX Stream RX Stream RX Stream Bit 0 DLE = 0 offset = 1, DLE = 0 offset = 0, DLE = 1 offset = 1, DLE = 1 Bit 0 denotes the 3/4 point of the bit cell Figure 5. Examples for Input Offset Delay Timing 15 offset = 0, 5712 drw 08 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE TABLE 13 — CONNECTION MEMORY BITS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LPBK V/C PC CCO OE SAB3 SAB2 SAB1 SAB0 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0 Bit 15 14 13 12 11 10-8,7(1) 6-0(1) Name LPBK (Per Channel Loopback) V/C (Variable/Constant Throughput Delay) PC (Processor Channel) CCO (Control Channel Output) OE (Output Enable) SAB3-0 (Source Stream Address Bits) CAB6-0 (Source Channel Address Bits) Description When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode. This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a per-channel basis. When 1, the contents of the connection memory are output on the corresponding output channel and stream. Only the lower byte (bit 7 – bit 0) will be output to the TX output pins. When 0, the contents of the connection memory are the data memory address of the switched input channel and stream. This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first. This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions normally. When 0, the output driver is in a high-impedance state. The binary value is the number of the data stream for the source of the connection. The binary value is the number of the channel for the source of the connection. NOTE: 1. If bit 13 (PC) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (SAB0, CAB6 - CAB0) are output on the output channel and stream associated with this location. TABLE 14 — CAB BIT PROGRAMMING FOR DIFFERENT DATA RATES Data Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s CAB Bits Used to Determine the Source Channel of the Connection CAB4 to CAB0 (32 channel/input stream) CAB5 to CAB0 (64 channel/input stream) CAB6 to CAB0 (128 channel/input stream) 16 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE JTAG SUPPORT INSTRUCTION REGISTER In accordance with the IEEE 1149.1 standard, the IDT72V90823 uses public instructions. The IDT72V90823 JTAG Interface contains a two-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. See Table below for Instruction decoding. The IDT72V90823 JTAG interface conforms to the Boundary-Scan standard IEEE-1149.1. This standard specifies a design-for-testability technique called Boundary-Scan Test (BST). The operation of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. TEST ACCESS PORT (TAP) The Test Access Port (TAP) provides access to the test functions of the IDT72V90823. It consists of three input pins and one output pin. •Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. •Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to Vcc when it is not driven from an external source. •Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to Vcc when it is not driven from an external source. •Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high impedance state. •Test Reset (TRST) Reset the JTAG scan structure. This pin is internally pulled to VCC. Value 000 001 010 011 100 101 110 111 Instruction EXTEST EXTEST Sample/preload Sample/preload Sample/preload Sample/preload Bypass Bypass Function Select Boundary Scan Register Select Boundary Scan Register Select Boundary Scan Register Select Boundary Scan Register Select Boundary Scan Register Select Boundary Scan Register Select Bypass Register Select Bypass Register JTAG Instruction Register Decoding TEST DATA REGISTER As specified in IEEE 1149.1, the IDT72V90823 JTAG Interface contains two test data registers: •The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the IDT72V90823 core logic. •The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO. The IDT72V90823 boundary scan register contains 118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit clocked out. All three-state enable bits are active high. 17 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE TABLE 15 — BOUNDARY SCAN REGISTER BITS Device Pin TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 ODE CCO DTA D15 D14 D13 D12 D11 D10 D9 D8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 IM AD/ALE CS R/W / WR DS/RD A7 A6 A5 Boundary Scan Bit 0 to bit 117 Three-State Output Input Control Scan Cell Scan Cell 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Device Pin A4 A3 A2 A1 A0 WFPS RESET CLK FE/HCLK F0i RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 18 Boundary Scan Bit 0 to bit 117 Three-State Output Input Control Scan Cell Scan Cell 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC Vi Parameter Min. Max. Unit Supply Voltage -0.3 5.0 V GND -0.3 VCC +0.3 V Voltage on Digital Inputs (3.3V) Vi Voltage on Digital Inputs (5.0V) IO Current at Digital Outputs GND -0.3 5.5 V 20 mA TS Storage Temperature -65 +125 °C PD Package Power Dissapation 1 W RECOMMENDED DC OPERATING CONDITIONS Symbol NOTE: 1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Parameter Min. Typ. Max. Units VCC Positive Supply 3.0 3.6 V VIH Input HIGH Voltage (3.3V) 2.0 VCC V VIH Input HIGH Voltage (5.0V) VIL Input LOW Voltage TOP Operating Temperature Commercial 2.0 5.5 V GND 0.8 V -40 +85 °C NOTE: 1. Voltages are with respect to ground unless other wise stated. DC ELECTRICAL CHARACTERISTICS Symbol Characteristics ICC(1) Min. Typ. Max. Units Supply Current 7 14 30 10 20 45 mA mA mA IIL(2) IBL Input Leakage (input pins) 15 µA Input Leakage (I/O pins) 50 µA @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s CI Input Pin Capacitance 10 pF IOZ High-impedance Leakage 5 µA VOH Output HIGH Voltage 2.4 V VOL Output LOW Voltage 0.4 V CO Output Pin Capacitance 10 pF NOTE: 1. Outputs Unloaded. 2. For TDI, TMS, and TRST pins, the maximum leakage current is 50µA. Test Point VCC S1 is open circuit except when testing output levels or high impedance states. RL Output Pin S1 S2 S2 is switched to VCC or GND when testing output levels or high impedance states. CL GND GND 5712 drw09 Figure 6. Output Load 19 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK Symbol Characteristics Min. Typ. Max. Units tFPW Frame Pulse Width (ST-BUS , GCI) 26 26 26 295 145 80 ns ns ns tFPS Frame Pulse Setup time before CLK falling (ST-BUS® or GCI) 5 ns tFPH Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI) 10 ns tCP CLK Period Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s 190 110 55 300 150 70 ns ns ns tCH CLK Pulse Width HIGH Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s 85 50 20 150 75 40 ns ns ns tCL CLK Pulse Width LOW Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s 85 50 20 150 75 40 ns ns ns tr, tf Clock Rise/Fall Time 10 ns tHFPW Wide Frame Pulse Width 195 295 ns tHFPS Frame Pulse Setup Time before HCLK falling 5 150 ns tHFPH Frame Pulse Hold Time from HCLK falling 10 150 ns tHCP HCLK (4.096 MHz) Period Bit rate = 8.192 Mb/s 190 300 ns tHCH HCLK (4.096 MHz) Pulse Width HIGH Bit rate = 8.192 Mb/s 85 150 ns tHCL HCLK (4.096 MHz) Pulse Width LOW Bit rate = 8.192 Mb/s 85 150 ns tHr, tHf HCLK Rise/Fall Time 10 ns tDIF Delay between falling edge of HCLK and falling edge of CLK -10 10 ns ® Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s Bit rate = 8.192 Mb/s AC ELECTRICAL CHARACTERISTICS - SERIAL STREAMS(1) Symbol Characteristics Min. Typ. Max. Unit tSIS tSIH RX Setup Time 0 ns RX Hold Time 10 ns tSOD TX Delay – Active to Active 30 40 ns ns CL = 30pF CL = 200pF tDZ TX Delay – Active to High-Z 32 ns RL = 1KΩ, CL = 200pF tZD TX Delay – High-Z to Active 32 ns RL = 1KΩ, CL = 200pF tODE Output Driver Enable (ODE) Delay 32 ns RL = 1KΩ, CL = 200pF tXCD CCO Output Delay 30 40 ns ns CL = 30pF CL = 200pF NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 20 Test Conditions IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE tFPW F0i tFPS tFPH tCH tCP tCL tr tf CLK tSOD TX Bit 0, Last Ch (1) Bit 7, Channel 0 tSIS RX Bit 0, Last Ch(1) Bit 6, Channel 0 Bit 5, Channel 0 tSIH Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 5712 drw10 NOTE: 1. 2.048 Mb/s mode, last channel = ch 31, 4.096 Mb/s mode, last channel = ch 63, 8.192 Mb/s mode, last channel = ch 127. Figure 7. ST-BUS® Timing for 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0. tFPW F0i tFPS tFPH tCH tCP tCL tr tf CLK tSOD TX Bit 7, Last Ch(1) Bit 0, Channel 0 tSIS RX Bit 7, Last Ch(1) Bit 1, Channel 0 Bit 2, Channel 0 tSIH Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0 5712 drw11 NOTE: 1. 2.048 Mb/s mode, last channel = ch 31, 4.096 Mb/s mode, last channel = ch 63, 8.192 Mb/s mode, last channel = ch 127. Figure 8. GCI Timing at 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0 21 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE tHFPW tHFPS tHFPH F0i tHCP tHCL tHCH HCLK 4.096 MHz tHr tHf tCP tDIF tCH tr tCL tf CLK 16.384 MHz tSOD TX Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0 tSIS RX Bit 1, Ch 127 Bit 0, Ch 127 Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0 tSIH Bit 7, Ch 0 Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0 5712 drw12 NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. Figure 9. WFP Bus Timing for High Speed Serial Interface (8.192 Mb/s), when WFPS pin = 1 CLK (ST-BUS or WFPS mode) CLK (GCI mode) tDZ TX VALID DATA tZD TX ODE VALID DATA tODE tODE tXCD TX CCO VALID DATA 5712 drw13 5712 drw14 Figure 11. Output Driver Enable (ODE) Figure 10. Serial Output and External Control 22 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (INTEL) Symbol Parameter Min. Typ. Max. Units tALW ALE Pulse Width 20 ns tADS Address Setup from ALE falling 3 ns tADH Address Hold from ALE falling 3 ns tALRD RD Active after ALE falling 3 ns tDDR Data Setup from DTA LOW on Read 5 ns tCSRW CS Hold after RD/WR 5 ns tRW RD Pulse Width (Fast Read) 45 ns tCSR CS Setup from RD 0 ns tDHR Data Hold after RD 10 tWW WR Pulse Width (Fast Write) 45 ns tALWR WR Delay after ALE falling 3 ns tCSW CS Setup from WR 0 ns tDSW Data Setup from WR (Fast Write) 20 ns tSWD Valid Data Delay on Write (Slow Write) tDHW Data Hold after WR Inactive tAKD Acknowledgment Delay: (1) 20 122 5 tAKH (1) CL = 150pF ns CL = 150pF, RL = 1K ns ns Reading/Writing Registers Reading/Writing Memory Test Conditions @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s Acknowledgment Hold Time 43/43 ns CL = 150pF 760/750 400/390 220/210 ns ns ns CL = 150pF CL = 150pF CL = 150pF 22 ns CL = 150pF, RL = 1K NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. tALW ALE tADS tADH AD0-AD7 D8-D15 DATA ADDRESS tALRD tCSRW CS tCSR tDHR tRW RD tCSW tWW tDHW tDSW WR tALWR tSWD tAKD tDDR DTA tAKH 5712 drw15 Figure 12. Multiplexed Bus Timing (Intel Mode) 23 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (MOTOROLA) Symbol Parameter tASW ALE Pulse Width Min. Typ. Max. Units tADS Address Setup from AS falling 3 ns tADH Address Hold from AS falling 3 ns tDDR Data Setup from DTA LOW on Read 5 ns tCSH CS Hold after DS falling 0 ns tCSS CS Setup from DS rising 0 ns 20 tDHW Data Hold after Write 5 ns tDWS Data Setup from DS – Write (Fast Write) 20 ns tSWD Valid Data Delay on Write (Slow Write) tRWS R/W Setup from DS Rising tRWH R/W Hold from DS Rising 5 tDHR(1) Data Hold after Read 10 tDSH DS Delay after AS falling 10 tAKD Acknowledgment Delay: 122 tAKH(1) CL = 150pF ns 60 ns ns 20 ns CL = 150pF, RL = 1K ns Reading/Writing Registers Reading/Writing Memory Test Conditions ns @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s Acknowledgment Hold Time 43/43 ns CL = 150pF 760/750 400/390 220/210 ns ns ns CL = 150pF CL = 150pF CL = 150pF 22 ns CL = 150pF, RL = 1K NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. DS tRWH tRWS R/W tASW tDSH AS tADS AD0-AD7, D8-D15 WR AD0-AD7, D8-D15 RD CS tADH tSWD ADDRESS tDHW tDWS DATA tDHR DATA ADDRESS tCSH tCSS tDDR tAKH tAKD DTA 5712 drw16 Figure 13. Multiplexed Bus Timing (Motorola Mode) 24 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS-MOTOROLA NON-MULTIPLEXED BUS MODE Symbol Parameter Min. Typ. Max. Units tCSS CS Setup from DS falling 0 ns tRWS R/W Setup from DS falling 10 ns tADS Address Setup from DS falling 2 ns tCSH CS Hold after DS rising 0 ns tRWH R/W Hold after DS Rising 2 ns tADH Address Hold after DS Rising 2 ns tDDR Data Setup from DTA LOW on Read 2 tDHR Data Hold on Read 10 tDSW Data Setup on Write (Fast Write) 5 tSWD Valid Data Delay on Write (Slow Write) tDHW Data Hold on Write tAKD Acknowledgment Delay: 20 122 CL = 150pF CL = 150pF, RL = 1K ns ns Reading/Writing Registers tAKH(1) ns ns ns 5 Reading/Writing Memory Test Conditions @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s Acknowledgment Hold Time 43/43 ns CL = 150pF 760/750 400/390 220/210 ns ns ns CL = 150pF CL = 150pF CL = 150pF 22 ns CL = 150pF, RL = 1K NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. DS tCSS tCSH tCSS tCSH CS tRWS tRWH tRWS tRWH R/W tADS A0-A7 tADH VALID READ ADDRESS VALID WRITE ADDRESS tSWD AD0-AD7/ D8-D15 tDSW tADH tADS tDHW tDHR VALID WRITE DATA VALID READ DATA tDDR tAKD tAKH tAKD tAKH DTA 5712 drw17 Figure 14. Motorola Non-Multiplexed Asyncronous Bus Timing 25 IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 COMMERCIAL TEMPERATURE RANGE CLK GCI CLK ST-BUS tDSS tDSPW tDSS DS tCSS tCSH tCSS tCSH tRWS tRWH tRWS tRWH tADS tADH tADS tADH CS R/W A0-A7 tSWD AD0-AD7/ D8-D15 VALID READ ADDRESS VALID WRITE ADDRESS tDHW tDHR VALID WRITE DATA VALID READ DATA tCKAK tDDR tCKAK tAKH tAKH DTA 5712 drw18 Figure 15. Motorola Non-Multiplexed Syncronous Bus Timing 26 ORDERING INFORMATION IDT XXXXXX XX Device Type Package X Process/ Temperature Range BLANK Commercial (-40°C to +85°C) J BC PQF PF Plastic Leaded Chip Carrier (PLCC, J84-1) Ball Grid Array (BGA, BC100-1) Plastic Quad Flatpack (PQFP, PQ100-2) Thin Quad Flat Pack (TQFP, PN100-1) 72V90823 2,048 x 2,048 3.3V Time Slot Interchange Digital Switch 5712 drw19 DATASHEET DOCUMENT HISTORY 5/19/2000 7/27/2000 8/14/2000 9/14/2000 1/02/2001 1/25/2001 5/16/2001 08/06/2001 12/18/2002 pgs. 1,3,18 and 25. pgs. 1, 2, 4, 5, 6, 7, 16 and 25. pg. 6. pgs. 2, 3, 12, 13 and 18. pgs. 7, 18, 21, 22, 23, and 24 pgs. 1, 16, 18 and 24. pg. 16 pgs. 4, 5, 12 and 25. pg. 3 CORPORATE HEADQUARTER 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 27 for Tech Support: 408-330-1753 email: [email protected]