STMicroelectronics M24M01-WMW6TP/A 1 mbit serial iâ²c bus eeprom Datasheet

M24M01-HR
M24M01-R, M24M01-W
1 Mbit serial I²C bus EEPROM
Features
■
Support I2C bus modes:
– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode
WLCSP (CS)
■
M24M01-HR:
1 MHz, 400 kHz, or 100 kHz I2C clock
frequency
■
M24M01-R, M24M01-W:
400 kHz, or 100 kHz I2C clock frequency
■
Single supply voltage:
– 1.8 V to 5.5 V
– 2.5 V to 5.5 V
■
Hardware write control
■
Byte and Page Write (up to 256 bytes)
■
Random and Sequential Read modes
■
Self-timed programming cycle
■
Automatic address incrementing
■
Enhanced ESD/Latch-Up protection
■
More than 1 million Write cycles
■
More than 40-year data retention
■
Packages
– ECOPACK® (RoHS compliant)
SO8 (MN)
150 mils width
SO8 (MW)
208 mils width
Wafer
June 2009
Doc ID 12943 Rev 7
1/37
www.st.com
1
Contents
M24M01-R, M24M01-W, M24M01-HR
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Chip Enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1
3
4
2/37
2.6.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9
ECC (error correction code) and Write cycling . . . . . . . . . . . . . . . . . . . . . 16
3.10
Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
3.11
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.15
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
Contents
5
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
M24M01-R die description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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List of tables
M24M01-R, M24M01-W, M24M01-HR
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
4/37
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating conditions (M24M01-R and M24M01-HR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating conditions (M24M01-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC characteristics (M24M01-R and M24M01-HR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC characteristics (M24M01-W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC characteristics at 400 kHz (M24M01-R and M24M01-W) . . . . . . . . . . . . . . . . . . . . . . . 24
AC characteristics at 1 MHz (M24M01-HR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 27
SO8W – 8-lead plastic small outline, 208 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
WLCSP8 – Wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . 29
Pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Ordering information scheme (M24M01-x products sold in packages). . . . . . . . . . . . . . . . 32
Ordering information scheme (M24M01-R sold as bare dice) . . . . . . . . . . . . . . . . . . . . . . 33
Available M24M01-x products (package, voltage range, frequency,
temperature grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WLCSP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
M24M01-R/M24M01-W – Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . 10
M24M01-HR – Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 27
SO8W – 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . 28
WLCSP8 – Wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
M24M01-R die plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Description
1
M24M01-R, M24M01-W, M24M01-HR
Description
The M24M01-HR, M24M01-R and M24M01-W are I2C-compatible electrically erasable
programmable memory (EEPROM) devices organized as 128 Kb × 8 bits.
The I2C bus is a two-wire serial interface, comprising a bidirectional data line and a clock
line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with
the I2C bus definition.
The M24M01-HR, M24M01-R and M24M01-W behave as slaves in the I2C protocol, with all
memory operations synchronized by the serial clock. Read and Write operations are
generated by the bus master and initiated by a Start condition, followed by the device select
code, address bytes and data bytes. Data transfers are terminated by a Stop condition after
an Ack for Write, and after a NoAck for Read.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way.
The M24M01-HR, M24M01-R and M24M01-W are delivered in SO8 packages and the
M24M01-R is also available in wafer form (see Table 21: Available M24M01-x products
(package, voltage range, frequency, temperature grade) for details).
Caution:
As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form by STMicroelectronics must never be
exposed to UV light.
Figure 1.
Logic diagram
VCC
2
E1-E2
SCL
SDA
M24M01-R
M24M01-HR
M24M01-W
WC
VSS
AI13415d
6/37
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
Table 1.
Description
Signal names
Signal name
Function
Direction
E1, E2
Chip Enable
Input
SDA
Serial Data
I/O
SCL
Serial Clock
Input
WC
Write Control
Input
VCC
Supply voltage
VSS
Ground
Figure 2.
SO connections
M24M01-R
M24M01-R
M24M01-HR
DU
E1
E2
VSS
8
7
6
5
1
2
3
4
VCC
WC
SCL
SDA
AI13416e
1. See Section 7: Package mechanical data for package dimensions, and how to identify pin-1.
2. DU = Don’t use.
Figure 3.
WLCSP8 connections
Orientation reference
VCC
SCL
VSS
WC
DU
SDA
E1
E2
Die orientation
ai15952b
1. NC = not connected internally.
2. DU = Don’t use.
Doc ID 12943 Rev 7
7/37
Signal description
M24M01-R, M24M01-W, M24M01-HR
2
Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 6 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 6 indicates how
the value of the pull-up resistor can be calculated).
2.3
Chip Enable (E1, E2)
These input signals are used to set the value that is to be looked for on the two bits (b3, b2)
of the 7-bit device select code. These inputs must be tied to VCC or VSS, to establish the
device select code as shown in Figure 4. When not connected (left floating), these inputs
are read as low (0,0).
Figure 4.
Device select code
VCC
VCC
M24xxx
M24xxx
Ei
Ei
VSS
VSS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
8/37
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
2.5
Signal description
VSS ground
VSS is the reference for the VCC supply voltage.
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 7). In order to
secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package
pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (tW).
2.6.2
Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Table 7 and the rise time must not vary faster than 1 V/µs.
2.6.3
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC has
reached the internal reset threshold voltage. This threshold is lower than the minimum VCC
operating voltage defined in Table 7, and Table 8). When VCC passes over the POR
threshold, the device is reset and enters the Standby Power mode. The device must not be
accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min),
VCC(max)] range defined in Table 7.
In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops
below the power-on-reset threshold voltage, the device stops responding to any instruction
sent to it.
2.6.4
Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that is there is no internal
write cycle in progress).
Doc ID 12943 Rev 7
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Signal description
M24M01-R, M24M01-W, M24M01-HR
Figure 5.
M24M01-R/M24M01-W – Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz
Bus line pull-up resistor
(k )
100
fC = 400 kHz, tLOW = 1.3 µs
Rbus x Cbus time
constant must be less than
500 ns
VCC
10
Rbus
I²C bus
master
SCL
M24xxx
SDA
1
10
100
Cbus
1000
Bus line capacitor (pF)
ai14796
Bus line pull-up resistor (k )
Figure 6.
M24M01-HR – Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 1MHz
100
VCC
fC = 1 MHz, tLOW = 700 ns
(max possible value)
time constant Rbus x Cbus
must be less than 270 ns
10
fC = 1 MHz, tLOW = 400 ns,
(min possible value)
time constant Rbus x Cbus
must be less than 100 ns
Rbus
I²C bus
master
SCL
M24xxx
SDA
Cbus
1
10
100
Bus line capacitor (pF)
ai14795c
10/37
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
Figure 7.
Signal description
I2C bus protocol
SCL
SDA
SDA
Input
START
Condition
SCL
1
2
SDA
MSB
SDA
Change
STOP
Condition
3
7
8
9
ACK
START
Condition
SCL
1
2
SDA
MSB
3
7
8
9
ACK
STOP
Condition
AI00792B
Table 2.
Device select code
Chip Enable
address(2)
Device type identifier(1)
A16
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
A16
RW
Device select code
1. The most significant bit, b7, is sent first.
2. E1 and E2 are compared against the respective external pins on the memory device.
Table 3.
b15
Table 4.
b7
Most significant address byte
b14
b13
b12
b11
b10
b9
b8
b3
b2
b1
b0
Least significant address byte
b6
b5
b4
Doc ID 12943 Rev 7
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Device operation
3
M24M01-R, M24M01-W, M24M01-HR
Device operation
The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The M24M01-R, M24M01-HR and
M24M01-W devices are always slaves in all communications.
3.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
3.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode. A Stop condition at the end of a Write
instruction triggers the internal EEPROM Write cycle.
3.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
3.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
12/37
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M24M01-R, M24M01-W, M24M01-HR
3.5
Device operation
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 2-bit Chip Enable
“Address” (E2, E1). To address the memory array, the 4-bit device type identifier is 1010b.
Up to four memory devices can be connected on a single I2C bus. Each one is given a
unique 2-bit code on the Chip Enable (E1, E2) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 5.
Operating modes
Mode
Current Address Read
RW bit
WC(1)
Bytes
1
X
1
0
X
Random Address Read
Initial sequence
Start, device select, RW = 1
Start, device select, RW = 0, Address
1
1
X
reStart, device select, RW = 1
Sequential Read
1
X
≥1
Byte Write
0
VIL
1
Start, device select, RW = 0
Page Write
0
VIL
≤ 256
Start, device select, RW = 0
Similar to Current or Random Address Read
1. X = VIH or VIL.
Doc ID 12943 Rev 7
13/37
Device operation
Figure 8.
M24M01-R, M24M01-W, M24M01-HR
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
Byte addr
ACK
Byte addr
NO ACK
Data in
Stop
Dev sel
Start
Byte Write
ACK
R/W
WC
ACK
Dev sel
Start
Page Write
ACK
Byte addr
ACK
Byte addr
NO ACK
Data in 1
Data in 2
R/W
WC (cont'd)
NO ACK
Data in N
Stop
Page Write (cont'd)
NO ACK
14/37
Doc ID 12943 Rev 7
AI01120d
M24M01-R, M24M01-W, M24M01-HR
3.6
Device operation
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write
instruction with Write Control (WC) driven high (during a period of time from the Start
condition until the end of the two address bytes) will not modify the memory contents, and
the accompanying data bytes are not acknowledged, as shown in Figure 8.
Each data byte in the memory has a 17-bit address (the most significant bit b16 is in the
device select code and the Least Significant Bits b15-b0 are defined in two address bytes).
The most significant byte (Table 3) is sent first, followed by the least significant byte
(Table 4).
When the bus master generates a Stop condition immediately after the Ack bit (in the “10th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write
cycle.
After the Stop condition, the delay tW, and the successful completion of a Write operation,
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
3.7
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 9.
3.8
Page Write
The Page Write mode allows up to 256 bytes to be written in a single Write cycle, provided
that they are all located in the same ’row’ in the memory: that is, the most significant
memory address bits, b16-b8, are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 256 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (the 8 least significant
address bits only) is incremented. The transfer is terminated by the bus master generating a
Stop condition.
Doc ID 12943 Rev 7
15/37
Device operation
Figure 9.
M24M01-R, M24M01-W, M24M01-HR
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
ACK
Byte addr
Byte addr
ACK
Data in
Stop
Dev sel
Start
Byte Write
ACK
R/W
WC
ACK
Dev sel
Start
Page Write
ACK
Byte addr
ACK
Byte addr
ACK
Data in 1
Data in 2
R/W
WC (cont'd)
ACK
Data in N
Stop
Page Write (cont'd)
ACK
3.9
AI01106d
ECC (error correction code) and Write cycling
The M24M01-R, M24M01-HR and M24M01-W devices offer an ECC (error correction code)
logic which compares each 4-byte word with its six associated EEPROM ECC bits. As a
result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation,
the ECC detects it and replaces it by the correct value. The read reliability is therefore much
improved by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC word), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write by packets of 4 bytes in order to
benefit from the larger amount of Write cycles.
The M24M01-R, M24M01-HR and M24M01-W devices are qualified at 1 million (1 000 000)
Write cycles, using a cycling routine that writes to the device by multiples of 4-byte words.
16/37
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
Device operation
Figure 10. Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
returned
YES
NO
Next
Operation is
addressing the
memory
YES
Send Address
and Receive ACK
ReStart
Stop
NO
StartCondition
YES
Data for the
Write cperation
Ddevice select
with RW = 1
Continue the
Write operation
Continue the
Random Read operation
AI01847d
Doc ID 12943 Rev 7
17/37
Device operation
3.10
M24M01-R, M24M01-W, M24M01-HR
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 13, but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 10, is:
●
Initial condition: a Write cycle is in progress.
●
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
●
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 11. Read mode sequences
ACK
Data out
Stop
Start
Dev sel
NO ACK
R/W
ACK
Random
Address
Read
Byte addr
Dev sel *
ACK
ACK
Data out 1
Data out
R/W
NO ACK
Data out N
R/W
ACK
ACK
Byte addr
ACK
Byte addr
ACK
Dev sel *
Start
Start
Dev sel *
R/W
ACK
NO ACK
Stop
Start
Dev sel
Sequention
Random
Read
ACK
Byte addr
R/W
ACK
Sequential
Current
Read
ACK
Start
Start
Dev sel *
ACK
Stop
Current
Address
Read
ACK
Data out1
R/W
NO ACK
Stop
Data out N
1. The seven most significant bits of the device select code of a Random Read (in the
be identical.
18/37
Doc ID 12943 Rev 7
AI01105d
1st
and
4th
bytes) must
M24M01-R, M24M01-W, M24M01-HR
3.11
Device operation
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
3.12
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 11) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
3.13
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 11, without acknowledging the byte.
3.14
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 11.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
3.15
Acknowledge in Read mode
For all Read instructions, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
Doc ID 12943 Rev 7
19/37
Initial delivery state
4
M24M01-R, M24M01-W, M24M01-HR
Initial delivery state
The device is delivered with all the memory array bits set to 1 (each byte contains FFh).
5
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 6.
Absolute maximum ratings
Symbol
TA
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
(1)
°C
–0.50
VCC + 0.6
V
-
5
mA
–0.50
6.5
V
–3000
3000
V
Lead temperature during soldering
VIO
Input or output range
IOL
DC output current (SDA = 0)
VCC
Supply voltage
VESD
Electrostatic discharge voltage (Human Body
see note
model)(2)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
20/37
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
6
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 7.
Operating conditions (M24M01-R and M24M01-HR)
Symbol
VCC
TA
Table 8.
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature
–40
125
°C
Operating conditions (M24M01-W)
Symbol
VCC
TA
Table 9.
Parameter
AC measurement conditions
Symbol
CL
Parameter
Min.
Load capacitance
Max.
100
Input rise and fall times
Unit
pF
50
ns
Input levels
0.2VCC to 0.8VCC
V
Input and output timing reference levels
0.3VCC to 0.7VCC
V
Figure 12. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 10.
Symbol
Input parameters
Parameter(1)
Test condition
Min.
Max.
Unit
CIN
Input capacitance (SDA)
8
pF
CIN
Input capacitance (other pins)
6
pF
ZL
ZH
Input impedance (WC)
VIN < 0.3 VCC
30
kΩ
VIN > 0.7VCC
400
kΩ
1. Sampled only, not 100% tested.
Doc ID 12943 Rev 7
21/37
DC and AC parameters
Table 11.
Symbol
M24M01-R, M24M01-W, M24M01-HR
DC characteristics (M24M01-R and M24M01-HR)
Test condition (in addition to
those in Table 7)
Parameter
ILI
Input leakage current
(E1, E2, SCL, SDA)
ILO
Output leakage current
ICC
ICC0(1)
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 1.8 V, fc= 400 kHz
(rise/fall time < 50 ns)
0.8
mA
VCC = 2.5 V, fc= 400 kHz
(rise/fall time < 50 ns)
1
mA
VCC = 5.5 V, fc= 400 kHz
(rise/fall time < 50 ns)
2
mA
1.8 V < VCC < 5.5 V, fc= 1 MHz
(rise/fall time < 50 ns)
2.5
mA
During tW, 1.8V < VCC < 5.5V
5
mA
Device not selected
VIN = VSS or VCC,
VCC = 1.8 V
1
µA
Device not selected(2),
VIN = VSS or VCC,
VCC = 2.5 V
2
µA
Device not selected(2),
VIN = VSS or VCC,
VCC = 5.5 V
3
µA
V
Supply current (Read)
Supply current (Write)
(2),
ICC1
Standby supply current
VIL
Input low voltage
(SCL, SDA, WC)
VIH
Input high voltage
(SCL, SDA, WC)
VOL
Output low voltage
1.8 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
2.5 V ≤ VCC ≤ 5.5 V
–0.45
0.3 VCC
1.8 V ≤ VCC < 2.5 V
0.75VCC
VCC+1
2.5 V ≤ VCC ≤ 5.5 V
0.7VCC
VCC+1
IOL = 1.0 mA, VCC = 1.8 V
0.2
V
IOL = 2.1 mA, VCC = 2.5 V
0.4
V
IOL = 3.0 mA, VCC = 5.5 V
0.4
V
1. Characterized value, not tested in production.
2. The device is not selected after a power-up, a Read instruction (after the Stop condition), or after the
completion of an internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
22/37
V
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
Table 12.
Symbol
DC and AC parameters
DC characteristics (M24M01-W)
Test condition (in addition to
those in Table 8)
Parameter
ILI
Input leakage current
(E1, E2, SCL, SDA)
ILO
Output leakage current
ICC
ICC0(1)
Supply current (Read)
Supply current (Write)
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 2.5 V, fc= 400 kHz
(rise/fall time < 50 ns)
1
mA
VCC = 5.5 V, fc= 400 kHz
(rise/fall time < 50 ns)
2
mA
2.5 V < VCC < 5.5 V, fc= 1 MHz
(rise/fall time < 50 ns)
2.5
mA
During tW, 2.5 V < VCC < 5.5 V
5
mA
Device not selected
VIN = VSS or VCC,
VCC = 2.5 V
5
µA
Device not selected(2),
VIN = VSS or VCC,
VCC = 5.5 V
5
µA
(2),
ICC1
Standby supply current
VIL
Input low voltage
(SCL, SDA, WC)
2.5 V ≤ VCC ≤ 5.5 V
–0.45
0.3 VCC
VIH
Input high voltage
(SCL, SDA, WC)
2.5 V ≤ VCC ≤ 5.5 V
0.7VCC
VCC+1
VOL
Output low voltage
IOL = 2.1 mA, VCC = 2.5 V
0.4
V
IOL = 3.0 mA, VCC = 5.5 V
0.4
V
1. Characterized value, not tested in production.
2. The device is not selected after a power-up, a Read instruction (after the Stop condition), or after the
completion of an internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 12943 Rev 7
23/37
DC and AC parameters
Table 13.
M24M01-R, M24M01-W, M24M01-HR
AC characteristics at 400 kHz (M24M01-R and M24M01-W)
Test conditions specified in Table 7 and Table 8
Symbol
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
Clock pulse width high
600
ns
tCLCH
tLOW
Clock pulse width low
1300
ns
tXH1XH2(1)
tR
Input signal rise time
300
ns
tXL1XL2(1)
tF
Input signal fall time
300
ns
(2)
tF
SDA (out) fall time
20
120
ns
tDXCH
tSU:DAT
Data in set up time
100
ns
tCLDX
tHD:DAT
Data in hold time
0
ns
tCLQX
tDH
Data out hold time
200
ns
tCLQV(3)(4)
tAA
Clock low to next data valid (access time)
200
tQL1QL2
Parameter
Min.
Max.
Unit
400
kHz
900
ns
tCHDL(5)
tSU:STA
Start condition setup time
600
ns
tDLCL
tHD:STA
Start condition hold time
600
ns
tCHDH
tSU:STO
Stop condition setup time
600
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
ns
tW
tWR
Write time
tNS(6)
Pulse width ignored (input filter on SCL and
SDA)
5
ms
100
ns
1. Input rise/fall time values recommended by the I²C-bus specification in Standard mode (100 kHz mode).
The M24xxx devices accept these maximum input rise/fall times when running at a higher clock frequency
provided that these rise/fall times are compatible with all the other timing conditions defined in this AC
table.
2. The SDA(out) rise time is not defined by the M24xxx, it is defined by the application pull-up resistor
(connected on the SDA line) and, therefore, it is not specified in this table.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a
compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus
× Cbus time constant is less than 500 ns (as specified in Figure 5).
5. For a reStart condition, or following a Write cycle.
6. Characterized only, not tested in production.
24/37
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
Table 14.
DC and AC parameters
AC characteristics at 1 MHz (M24M01-HR)
Test conditions specified in Table 7
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock frequency
0
1
MHz
tCHCL
tHIGH
Clock pulse width high
300
-
ns
tCLCH
tLOW
Clock pulse width low
400
-
ns
tXH1XH2(1)
tR
Input signal rise time
-
120
ns
tXL1XL2(1)
tF
Input signal fall time
-
120
ns
tQL1QL2(2)(3)
tF
SDA (out) fall time
-
120
ns
tDXCH
tSU:DAT
Data in setup time
80
-
ns
tCLDX
tHD:DAT Data in hold time
0
-
ns
tCLQX
tDH
Data out hold time
50
-
ns
tCLQV(4)(5)
tAA
Clock low to next data valid (access time)
50
500
ns
tCHDL(6)
tSU:STA
Start condition setup time
250
-
ns
tDLCL
tHD:STA
Start condition hold time
250
-
ns
tCHDH
tSU:STO
Stop condition setup time
250
-
ns
tDHDL
tBUF
Time between Stop condition and next
Start condition
500
-
ns
tW
tWR
Write time
-
5
ms
Pulse width ignored (input filter on SCL
and SDA)
-
50
ns
tNS(2)
1. Input rise/fall time values recommended by the Fast-mode Plus I²C-bus specification. The M24xxx devices
accept longer input rise/fall times provided that these rise/fall times are compatible with all other timing
conditions defined in this AC table.
2. Characterized only, not tested in production.
3. The SDA(out) rise time is not defined by the M24xxx, it is defined by the application pull-up resistor
(connected on the SDA line) and, therefore, it is not specified in this table.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC, assuming
that the Rbus × Cbus time constant is within the range defined in Figure 6.
6. For a reStart condition, or following a Write cycle.
Doc ID 12943 Rev 7
25/37
DC and AC parameters
M24M01-R, M24M01-W, M24M01-HR
Figure 13. AC waveforms
tXL1XL2
tCHCL
tXH1XH2
tCLCH
SCL
tDLCL
tXL1XL2
SDA In
tCHDL
tCLDX
tXH1XH2
Start
condition
SDA
Input
SDA tDXCH
Change
tCHDH tDHDL
Start
Stop
condition condition
SCL
SDA In
tW
tCHDH
tCHDL
Stop
condition
Write cycle
Start
condition
tCHCL
SCL
tCLQV
SDA Out
tCLQX
Data valid
tQL1QL2
Data valid
AI00795e
26/37
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
7
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
A1
L
L1
SO-A
1. Drawing is not to scale.
Table 15.
SO8N – 8-lead plastic small outline, 150 mils body width, package data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
Min
1.75
Max
0.0689
A1
0.1
A2
1.25
b
0.28
0.48
0.011
0.0189
c
0.17
0.23
0.0067
0.0091
ccc
0.25
0.0039
0.0098
0.0492
0.1
0.0039
D
4.9
4.8
5
0.1929
0.189
0.1969
E
6
5.8
6.2
0.2362
0.2283
0.2441
E1
3.9
3.8
4
0.1535
0.1496
0.1575
e
1.27
-
-
0.05
-
-
h
0.25
0.5
0.0098
0.0197
k
0°
8°
0°
8°
L
0.4
1.27
0.0157
0.05
L1
1.04
0.0409
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 12943 Rev 7
27/37
Package mechanical data
M24M01-R, M24M01-W, M24M01-HR
Figure 15. SO8W – 8-lead plastic small outline, 208 mils body width, package outline
A2
A
c
b
CP
e
D
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
2. The ‘1’ that appears in the top view of the package shows the position of pin 1 and the ‘N’ indicates the total
number of pins.
Table 16.
SO8W – 8-lead plastic small outline, 208 mils body width, package
mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
2.5
Max
0.0984
A1
0
0.25
0
0.0098
A2
1.51
2
0.0594
0.0787
b
0.4
0.35
0.51
0.0157
0.0138
0.0201
c
0.2
0.1
0.35
0.0079
0.0039
0.0138
CP
0.1
0.0039
D
6.05
0.2382
E
5.02
6.22
0.1976
0.2449
E1
7.62
8.89
0.3
0.35
-
-
-
-
k
0°
10°
0°
10°
L
0.5
0.8
0.0197
0.0315
N
8
e
1.27
0.05
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Min
Doc ID 12943 Rev 7
8
M24M01-R, M24M01-W, M24M01-HR
Package mechanical data
Figure 16. WLCSP8 – Wafer level chip scale package outline
e1
D
e2
e
Detail A
E
e2
Orientation
reference
aaa
(4X)
A2
G
F
Orientation reference
A
Wafer’s back side
Side view
Bump side
Bump
A1
eee Z
b(8X)(2)
Z
Seating plane(3)
Note 4
Detail A rotated by 90°
E1_ME
1. Drawing is not to scale and corresponds to preliminary data.
2. The dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. The primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
Table 17.
WLCSP8 – Wafer level chip scale package mechanical data(1)
inches(2)
millimeters
Symbol
Typ
Min
0.555
Max
0.605
Typ
0.0228
Min
0.0219
Max
A
0.580
0.0238
A1
0.230
0.0091
A2
0.350
0.0138
b
0.322
0.0127
D
3.570
3.685
0.1406
0.1451
E
2.050
2.165
0.0807
0.0852
e
0.600
0.0236
e1
2.400
0.0945
e2
1.200
0.0472
F
0.585
0.0230
G
0.424
0.0167
aaa
0.110
0.0043
bbb
0.110
0.0043
ccc
0.110
0.0043
ddd
0.060
0.0024
eee
0.060
0.0024
N (number of bumps) 8
1. Preliminary data.
2. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 12943 Rev 7
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M24M01-R die description
M24M01-R, M24M01-W, M24M01-HR
8
M24M01-R die description
Caution:
As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form by STMicroelectronics must never be
exposed to UV light.
Product M24M01-A
●
Wafer size
203 mm (8 inches)
●
Die identification
M24M01, processed in the Rousset fab
Die Layout
●
Die size (X × Y)
2085 × 3605 µm (including scribe line)
●
Scribe line
80.0 × 80.0 µm
●
Pad opening
90 × 90 µm
●
DI
Die identification (at the position shown in Figure 17)
●
Pads
Pad contacts (at the positions shown in Figure 17 and
Table 18)
Figure 17. M24M01-R die plot
VCC
E0
WC
E1
Y
X
SCL
E2
VSS
SDA
Die identification: M24M01
ai15446
1. Refer to Table 18: Pad coordinates for the pad locations.
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Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
Table 18.
M24M01-R die description
Pad coordinates(1)
Signal
X (µm)
Y (µm)
Pads
VCC
784.02
1683
8
WC
922
1383.1
7
SCL
922.78
–1171.22
6
SDA
922.78
–1450.14
5
VSS
–920.06
–1548.98
4
E2
–920.06
–1358.7
3
E1
–922.8
1270.7
2
E0
–922.8
1563.02
1
1. Pad locations are measured relative to the die center (where X and Y are the horizontal and vertical axis,
respectively, measured in µm). Refer to Figure 17.
Doc ID 12943 Rev 7
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Part numbering
9
M24M01-R, M24M01-W, M24M01-HR
Part numbering
Table 19.
Ordering information scheme (M24M01-x products sold in packages)
Example:
M24M01
–
H R MN 6
T
P
/A
Device type
M24 = I2C serial access EEPROM
Device function
M01 = 1 Mbit (256 Kb × 8 bits)
Clock frequency
Blank: fC max = 400 kHz
H: fC max = 1 MHz
Operating voltage
W = VCC = 2.5 V to 5.5 V
R = VCC = 1.8 V to 5.5 V
Package
MN = SO8 (150 mils width)
MW = SO8 (208 mils width)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Automotive: device tested with high reliability certified flow(1) over –40 to 125 °C
Option
blank = standard packing
T = tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process(2)
A = F8L
1. ST strongly recommends the use of automotive grade devices for use in automotive environments. The
high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest
ST sales office for a copy.
2. The Process letter only concerns grade 3 devices and WLCSP devices.
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Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
Table 20.
Part numbering
Ordering information scheme (M24M01-R sold as bare dice)
Example:
M24M01
–
R
A
W 21 /90
Device type
M24 = I2C serial access EEPROM
Device function
M01 = 1 Mbit (256 Kb × 8 bits)
Clock frequency
Blank: fC max = 400 kHz
Operating voltage
R = VCC = 1.8 V to 5.5 V
Process letter
A = F8L
Delivery form
W = unsawn wafer
Wafer thickness
21 = 280 µm
Temperature range
/90 = –40 to 85 °C
For a list of available options (speed, package, etc.) or for further information on any aspect
of the devices, please contact your nearest ST sales office.
Doc ID 12943 Rev 7
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Part numbering
M24M01-R, M24M01-W, M24M01-HR
Table 21.
M24M01-R
M24M01-HR
1.8 V to 5.5 V at 1 MHz
1.8 V to 5.5 V at 400 kHz
M24M01-W
2.5 V to 5.5 V at 400 kHz
SO8N (MN)
Range 6
Range 6
Range 3
SO8W (MW)
-
Range 6
-
Wafer
-
Range 6
-
WLCSP (CS)
-
Range 6
-
Package
34/37
Available M24M01-x products (package, voltage range, frequency,
temperature grade)
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
10
Revision history
Revision history
Table 22.
Document revision history
Date
Revision
07-Dec-2006
1
Initial release.
2
Document status promoted from Preliminary Data to full Datasheet.
Section 2.6: Supply voltage (VCC) updated.
Note 1 updated to latest standard revision below Table 6: Absolute
maximum ratings.
VIL, VIH modified and, rise/fall time corrected in Test conditions in
Table 11: DC characteristics (M24M01-R and M24M01-HR).
Package values in inches calculated from mm and rounded to 4
decimal digits (note added below package mechanical data tables in
Section 7: Package mechanical data.
3
1 MHz maximum clock frequency added:
– Figure 6: M24M01-HR – Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at maximum frequency fC =
1MHz
– Table 14: AC characteristics at 1 MHz (M24M01-HR) added.
tNS moved from Table 10: Input parameters to Table 13: AC
characteristics at 400 kHz (M24M01-R and M24M01-W). Note
removed below Table 10. In Table 13, tCH1CH2, tCL1CL2 and tDL1DL2
removed, tXH1XH2, tXL1XL2 added, tDL1DL2 max modified, notes
modified.
Figure 5: M24M01-R/M24M01-W – Maximum Rbus value versus bus
parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC
= 400 kHz modified.
Figure 13: AC waveforms modified. Small text changes.
4
M24M01-HR root part number added. Small text changes.
Figure 6: M24M01-HR – Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz
modified.
Most significant address bits modified in Section 3.8: Page Write on
page 15.
Test conditions modified for ILI, ICC and VOL in Table 11: DC
characteristics (M24M01-R and M24M01-HR).
TW and TNS values corrected in Table 13: AC characteristics at
400 kHz (M24M01-R and M24M01-W).
Cross-reference corrected in Note 5 below Table 14: AC
characteristics at 1 MHz (M24M01-HR).
02-Oct-2007
26-Nov-2007
18-Mar-2008
Changes
Doc ID 12943 Rev 7
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Revision history
M24M01-R, M24M01-W, M24M01-HR
Table 22.
Document revision history (continued)
Date
02-Sep-2008
12-Mar-2009
26-Jun-2009
36/37
Revision
Changes
5
Added: M24M01-W part number in device grade 3 temperature range
(see Table 8: Operating conditions (M24M01-W), Table 12: DC
characteristics (M24M01-W) and Table 19: Ordering information
scheme (M24M01-x products sold in packages)).
M24M01-R offered as a bare die (see Section 8: M24M01-R die
description and Table 20: Ordering information scheme (M24M01-R
sold as bare dice)).
In Table 13: AC characteristics at 400 kHz (M24M01-R and M24M01W), Note 1 modified, Note 2 added, tXH1XH2, tXL1XL2 and tDL1DL2
values modified.
In Table 14: AC characteristics at 1 MHz (M24M01-HR), Note 1
modified, Note 3 added, tXH1XH2, tXL1XL2 and tDL1DL2 values modified.
tCHDX, tDL1DL2 and tDXCX changed to tCHDL, tQL1QL2 and tDXCH,
respectively (see Table 13, Table 14 and Figure 13).
Table 21: Available M24M01-x products (package, voltage range,
frequency, temperature grade) added.
Small text changes.
6
WLCSP8 package added (see Figure 3: WLCSP8 connections and
Section 7: Package mechanical data).
Section 2.6: Supply voltage (VCC) updated.
IOL added to Table 6: Absolute maximum ratings.
VRES added to Table 11: DC characteristics (M24M01-R and
M24M01-HR) and Table 12: DC characteristics (M24M01-W).
ECOPACK text updated.
7
Section : Features updated.
NC pin changed to DU in Figure 2: SO connections.
Device select code Chip enable address bits updated in Section 2.3.
Internal reset threshold modified in Section 2.6.3: Device reset.
Figure 6: M24M01-HR – Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz
updated.
VRES removed, and ICC1 conditions modified in Table 11: DC
characteristics (M24M01-R and M24M01-HR), and Table 12: DC
characteristics (M24M01-W). VRES removed from Table 12: DC
characteristics (M24M01-W).
tXH1XH2 updated in Table 13: AC characteristics at 400 kHz (M24M01R and M24M01-W). tXH1XH2 updated, and Note 5 updated in Table 14:
AC characteristics at 1 MHz (M24M01-HR).
Command replaced by instruction in the whole document.
Doc ID 12943 Rev 7
M24M01-R, M24M01-W, M24M01-HR
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