Maxim MAX6620ATI Quad linear fan-speed controller Datasheet

19-4039; Rev 0; 3/08
KIT
ATION
EVALU
E
L
B
A
IL
AVA
Quad Linear Fan-Speed Controller
The MAX6620 controls the speeds of up to four fans
using four independent linear voltage outputs. The
drive voltages for the fans are controlled directly over
the I2C interface. Each output drives the base of an
external bipolar transistor or the gate of a FET in highside drive configuration. Voltage feedback at the fan’s
power-supply terminal is used to force the correct output voltage.
The MAX6620 offers two methods for fan control. In
RPM mode, the MAX6620 monitors four fan tachometer
logic outputs for precise (±1%) control of fan RPM and
detection of fan failure. In DAC mode, each fan is driven with a voltage resolution of 9 bits and the tachometer outputs of the fans are monitored for failure.
The DAC_START input selects the fan power-supply
voltage at startup to ensure appropriate fan drive when
power is first applied. A watchdog feature turns the
fans fully on to protect the system if there are no valid
I2C communications within a preset timeout period.
The MAX6620 operates from a 3.0V to 5.5V power supply with low 250µA supply current, and the I2C-compatible interface makes it ideal for fan control in a wide
range of cooling applications. The MAX6620 is available in a 28-pin TQFN package and operates over the
-40°C to +125°C automotive temperature range.
Features
♦ Controls Up to Four Independent Fans With
Linear (DC) Drive
♦ Uses Four External Low-Cost Pass Transistors
♦ 1% Accuracy Precision RPM Control
♦ Controlled Voltage Rate-Of-Change for Best
Acoustics
♦ I2C Bus Interface
♦ 3.0V to 5.5V Supply Voltage Range
♦ 250µA (typ) Operating Supply Current
♦ 3µA (typ) Shutdown Supply Current
♦ Small 5mm x 5mm Footprint
Ordering Information
PART
PINPACKAGE
TEMP RANGE
MAX6620ATI+
-40°C to +125°C
+Denotes a lead-free package.
*EP = Exposed paddle.
PKG
CODE
28 TQFN-EP*
T2855-8
Pin Configuration
Applications
Communications Equipment
TACH2
DACFB2
DACOUT2
GND
DACOUT3
DACFB3
TACH3
Consumer Products
Storage Equipment
21
20
19
18
17
16
15
TOP VIEW
Servers
14
TACH1 22
DACFB1 23
13
DACFB4
DACOUT1 24
12
DACOUT4
11
GND
FAN 26
10
GND
VCC 27
9
X2
8
X1
GND 25
MAX6620
GND
5
6
7
SPINUP_START
4
ADDR
3
DAC_START
2
SDA
SCL
1
WD_START
+
FAN_FAIL 28
Typical Application Circuit appears at end of data sheet.
TACH4
THIN QFN
(5mm × 5mm × 0.8mm)
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX6620
General Description
MAX6620
Quad Linear Fan-Speed Controller
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..........................................................-0.3V to +6.0V
FAN_FAIL, SDA, SCL to GND ...............................-0.3V to +6.0V
ADDR, SPINUP_START, DAC_START, WD_START,
X1, X2 to GND ........................................-0.3V to (VCC + 0.3V)
All Other Pins to GND..........................................-0.3V to +13.5V
Input Current at DACOUT_ Pins (Note 1) ...............+5mA/-50mA
Input Current at Any Pin (Note 1)..........................................5mA
ESD Protection (all pins, Human Body Model) (Note 2) ...±2000V
Continuous Power Dissipation (TA = +70°C)
28-Pin TQFN (derate 34.5mW/°C above +70°C) ....2758.6mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions.
Note 2: Human Body Model, 100pF discharged through a 1.5kΩ resistor.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40°C to +125°C, VCC = 3.0V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C, VCC = 3.3V.) (Note 3)
PARAMETER
SYMBOL
Operating Supply Voltage
VCC
Operating Supply Current
ICC
Quiescent Supply Current
VFAN Supply Voltage
DACOUT_ Output Current
DACOUT_ Output Voltage
CONDITION
MIN
DAC Feedback Voltage at Full
Scale
mA
I2C inactive
0.2
0.5
mA
3
20
µA
VFANHI
10
12
13.5
VFANLO
4.0
5.0
5.5
VGND + 10V < VDACOUT_ < 11.5V,
VFAN = 12V
-18
VGND + 3V < VDACOUT_ < 10V,
VFAN = 12V
-16
VDACOUT_
IDACOUT_ = 5mA
0.05
DACFBHS
At DACFB_,
code = 0x100,
IDACOUT_ = 5mA
DACFBFS
At DACFB_,
code = 0x1FF,
VDACFB511 IDACOUT_ = 5mA
TACH Count Accuracy (Note 4)
2
VFAN 0.1
V
256/535
VFAN = VFANLO
256/567
VFAN = 12V
5.54
VFAN = 5V
2.05
5.74
5.94
2.25
2.45
VFAN = VFANHI
511/535
VFAN = VFANLO
511/567
VFAN = 12V
11.25
11.45
11.65
VFAN = 5V
4.3
4.5
4.7
V
V
9
Bit
1
MΩ
25
(Note 4)
V
mA
RDACFB
TACH Minimum Input Pulse Width
Internal Reference Frequency
Accuracy
V
0.60
Shutdown mode
IDACOUT_
UNITS
5.5
0.25
Drive Voltage Resolution
DACFB_ Impedance
MAX
VCC = 5.5V
VFAN = VFANHI
DAC Feedback Voltage at Half
Scale
TYP
3.0
µs
-3
+3
Using 32.768kHz crystal
-0.1
+0.1
Using on-chip oscillator
-2
+2
_______________________________________________________________________________________
%
%
Quad Linear Fan-Speed Controller
(TA = -40°C to +125°C, VCC = 3.0V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C, VCC = 3.3V.) (Note 3)
PARAMETER
SYMBOL
Fan Control Accuracy (Note 4)
CONDITION
MIN
MAX
-1
+1
Using on-chip oscillator
-3
+3
XTAL Oscillator Startup Time
X1 Input Threshold
POR Threshold
TYP
Using 32.768kHz crystal, test at 850RPM
UNITS
%
2
s
0.7
V
VCC
2
VFAN
3.5
V
LOGIC (SDA, SCL, FAN_FAIL, WD_START, TACH_)
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
Input Low Current
VCC x
0.7
V
VCC x
0.3
V
IIH
1.0
µA
IIL
-1.0
µA
Input Capacitance
All digital inputs
6
Output High Current
Output Low Voltage
IOL = 3mA
pF
100
µA
0.4
V
LOGIC (DAC_START, SPIN_START, ADDR)
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
Input Low Current
V
0.5
V
IIH
1.0
µA
IIL
-1.0
µA
Input Capacitance
I2C-COMPATIBLE
VCC 0.5
All digital inputs
6
pF
TIMING (Notes 5, 6)
Serial Clock Frequency
fSCL
Bus Free Time Between STOP
and START Conditions
tBUF
400
kHz
1.3
µs
START Condition Hold Time
tHD:STA
0.6
µs
STOP Condition Setup Time
tSU:STO
600
ns
Clock Low Period
tLOW
1.3
µs
Clock High Period
tHIGH
0.6
µs
START Condition Setup Time
tSU:STA
600
ns
Data Setup Time
tSU:DAT
100
ns
tDH
100
Data Out Hold Time
Data In Hold Time
ns
tHD:DAT
(Note 6)
0
0.9
µs
Maximum Receive SCL/SDA Rise
Time
tR
(Note 8)
300
ns
Minimum Receive SCL/SDA Rise
Time
tR
(Note 7)
20 + 0.1
x CB
ns
_______________________________________________________________________________________
3
MAX6620
ELECTRICAL CHARACTERISTICS (continued)
MAX6620
Quad Linear Fan-Speed Controller
ELECTRICAL CHARACTERISTICS (continued)
(TA = -40°C to +125°C, VCC = 3.0V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C, VCC = 3.3V.) (Note 3)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Maximum Receive SCL/SDA Fall
Time
tF
Minimum Receive SCL/SDA Fall
Time
tF
(Note 7)
Transmit SDA Fall Time
tF
(Note 7)
20 + 0.1
x CB
250
ns
Pulse Width of Suppressed Spike
tSP
(Note 8)
0
50
ns
250
ns
50
ms
ns
20 + 0.1
x CB
ns
CL = 400pF, IOUT = 3mA
Output Fall Time
SDA Time Low for Reset of Serial
Interface
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
300
tTIMEOUT
(Note 9)
20
All parts will operate properly over the VCC supply voltage range of 3.0V to 5.5V.
Guaranteed by design and characterization.
All timing specifications are guaranteed by design.
A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling edge.
CB = total capacitance of one bus line in pF. Tested with CB = 400pF.
Input filters on SDA and SCL suppress noise spikes less than 50ns.
Holding the SDA line low for a time greater than tTIMEOUT will cause the devices to reset SDA to the idle state of the serial
bus communication (SDA set high).
tR
tF
SDA
tSU,DAT
tHD,DAT
tLOW
tBUF
tHD,STA
tSU,STA
tSU,STO
SCL
tHD,STA
tHIGH
tR
tF
S
Sr
A
Figure 1. I2C Serial Interface Timing
4
_______________________________________________________________________________________
P
S
Quad Linear Fan-Speed Controller
1.0
0.5
TA = 0°C
TA = +25°C
0
-0.5
-1.0
TA = +70°C
TA = +125°C
-1.5
-2.0
4.0
4.5
5.0
0
-0.5
TA = +25°C
-1.0
-1.5
MAX6620 toc03
1.0
0.5
VCC = 5.0V
0
-0.5
-1.0
VCC = 3.3V
-1.5
-2.0
3.0
3.5
4.0
4.5
5.0
-55
5.5
-10
35
80
DACFB_ VOLTAGE ACCURACY
vs. TEMPERATURE
DACFB_ VOLTAGE ACCURACY
vs. SUPPLY VOLTAGE
0
-0.5
-1.0
VFAN = 12V
1.5
VCC = 3.0V, 3.3V, 5.0V
1.0
0.5
0
-0.5
-1.0
2.0
DACFB VOLTAGE ACCURACY (%)
VCC = 3.3V, 5.0V
2.0
DACFB VOLTAGE ACCURACY (%)
VFAN = 12V
-10
35
80
-55
125
1.0
0.5
0
-0.5
-1.0
-2.0
-2.0
-10
35
80
3.0
125
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
DACFB_ VOLTAGE ACCURACY
vs. OUTPUT CURRENT
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OPERATING SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VCC = 3.0V, 3.3V
0.5
0
VCC = 5.5V
-1.0
-1.5
450
VFAN = 12V
400
350
300
INT CLK
250
200
150
100
OUTPUT CURRENT (mA)
0.5
0.4
0.3
INT CLK
0.2
0.1
EXT CLK
0
0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
VFAN = 12V
EXT CLK
50
-2.0
0.6
OPERATING SUPPLY CURRENT (mA)
1.5
500
STANDBY SUPPLY CURRENT (μA)
VFAN = 12V
5.5
MAX6620 toc09
TEMPERATURE (°C)
MAX6620 toc08
TEMPERATURE (°C)
MAX6620 toc07
-55
VFAN = 12V
1.5
-1.5
-1.5
-1.5
125
MAX6620 toc06
TACH COUNT ACCURACY WITH EXT CLK
vs. TEMPERATURE
MAX6620 toc05
TEMPERATURE (°C)
-2.0
DACFB VOLTAGE ACCURACY (%)
0.5
VFAN = 12V
1.5
SUPPLY VOLTAGE (V)
0.5
-0.5
TA = 0°C, +70°C, +125°C
2.0
SUPPLY VOLTAGE (V)
1.0
1.0
1.0
5.5
MAX6620 toc04
TACH COUNT ACCURACY WITH EXT CLK (%)
3.5
1.5
2.0
1.5
-2.0
3.0
2.0
VFAN = 12V
TACH COUNT ACCURACY WITH INT CLK (%)
1.5
2.0
MAX6620 toc02
VFAN = 12V
TACH COUNT ACCURACY WITH EXT CLK (%)
2.0
TACH COUNT ACCURACY WITH INT CLK
vs. TEMPERATURE
TACH COUNT ACCURACY WITH EXT CLK
vs. SUPPLY VOLTAGE
MAX6620 toc01
TACH COUNT ACCURACY WITH INT CLK (%)
TACH COUNT ACCURACY WITH INT CLK
vs. SUPPLY VOLTAGE
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
MAX6620
Typical Operating Characteristics
(VCC = 3.3V, VFAN = 12V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VCC = 3.3V, VFAN = 12V, TA = +25°C, unless otherwise noted.)
TA = +25°C
1.0
0.5
0
TA = +70°C
TA = +125°C
-0.5
-1.0
-1.5
-2.0
4.0
4.5
5.0
TA = +25°C
-1.0
-1.5
0
VCC = 5.0V
-0.5
-1.0
-1.5
-2.0
3.0
3.5
4.0
4.5
5.0
-55
5.5
-10
35
80
DACFB_ VOLTAGE ACCURACY
vs. SUPPLY VOLTAGE
-0.5
-1.0
3.5
-1.5
VFAN = 5.0V
VCC = 3.0V
2.5
1.5
0.5
-0.5
VCC = 5.5V
VCC = 3.3V
-1.5
-2.5
4.5
3.5
DACFB VOLTAGE ACCURACY (%)
0
4.5
DACFB VOLTAGE ACCURACY (%)
VFAN = 5.0V
-3.5
-10
35
80
125
VFAN = 5.0V
2.5
1.5
0.5
-0.5
-1.5
-2.5
-3.5
-4.5
-4.5
-55
-10
35
80
125
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
DACFB_ VOLTAGE ACCURACY
vs. OUTPUT CURRENT
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OPERATING SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VCC = 3.0V, 3.3V
0.5
-0.5
VCC = 5.5V
-2.5
450
400
350
300
200
150
100
50
-4.5
0
OUTPUT CURRENT (mA)
INT CLK
250
-3.5
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
VFAN = 5.0V
EXT CLK
0.6
OPERATING SUPPLY CURRENT (mA)
2.5
500
STANDBY SUPPLY CURRENT (μA)
VFAN = 5.0V
5.5
MAX6620 toc18
TEMPERATURE (°C)
MAX6620 toc17
TEMPERATURE (°C)
MAX6620 toc16
-55
125
MAX6620 toc15
DACFB_ VOLTAGE ACCURACY
vs. TEMPERATURE
MAX6620 toc14
TACH COUNT ACCURACY WITH EXT CLK
vs. TEMPERATURE
-2.0
6
-0.5
0.5
TEMPERATURE (°C)
0.5
-1.5
0
VCC = 3.3V
1.0
SUPPLY VOLTAGE (V)
VCC = 3.3V, 5.0V
1.5
0.5
VFAN = 5.0V
1.5
SUPPLY VOLTAGE (V)
1.0
3.5
TA = 0°C, +70°C, +125°C
5.5
MAX6620 toc13
TACH COUNT ACCURACY WITH EXT CLK (%)
3.5
1.5
4.5
1.0
2.0
-2.0
3.0
2.0
VFAN = 5.0V
1.5
TACH COUNT ACCURACY WITH INT CLK (%)
TA = 0°C
2.0
MAX6620 toc11
VFAN = 5.0V
1.5
TACH COUNT ACCURACY WITH EXT CLK (%)
MAX6620 toc10
TACH COUNT ACCURACY WITH INT CLK (%)
2.0
TACH COUNT ACCURACY WITH INT CLK
vs. TEMPERATURE
TACH COUNT ACCURACY WITH EXT CLK
vs. SUPPLY VOLTAGE
MAX6620 toc12
TACH COUNT ACCURACY WITH INT CLK
vs. SUPPLY VOLTAGE
DACFB VOLTAGE ACCURACY (%)
MAX6620
Quad Linear Fan-Speed Controller
VFAN = 5.0V
0.5
0.4
0.3
INT CLK
0.2
0.1
EXT CLK
0
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5.0
5.5
Quad Linear Fan-Speed Controller
PIN
NAME
1
SCL
I2C Serial-Clock Input. Can be pulled up to 5.5V regardless of VCC. Open circuit when VCC = 0V.
FUNCTION
2
SDA
Open-Drain, I2C Serial-Data Input/Output. Can be pulled up to 5.5V regardless of VCC. Open
circuit when VCC = 0V.
Startup Watchdog Set Input. This input is sampled when power is first applied and sets the initial
I2C watchdog behavior. When connected to GND, the watchdog function is disabled. When
connected to VCC, the MAX6620 monitors SDA. If 10s elapse without a valid I2C transaction, the
fan drive goes to 100%.
3
WD_START
4, 10, 11, 18,
25
GND
Ground
5
ADDR
I2C Address Set Input. This input is sampled when power is first applied and sets the I2C slave
address. When connected to GND, the slave address will be 0x50. When unconnected, the slave
address will be 0x52. When connected to VCC, the slave address will be 0x54.
DAC_START
Startup Fan Drive DAC Set Input. This input is sampled when power is first applied and sets the
power-up value for the fan drive voltage. When connected to GND, the fan drive voltage will be
0%. When unconnected, the fan drive voltage will be 75%. When connected to VCC, the fan drive
voltage will be 100%.
6
7
Startup Spin-Up Set Input. This input is sampled when power is first applied and sets the initial
spin-up behavior. When connected to GND, spin-up is disabled. When connected to VCC at
power-up, the fan is driven with a full-scale drive voltage until two tachometer pulses have been
SPINUP_START
detected, or 1s has elapsed. When unconnected, the fan is driven with a full-scale drive voltage
until two tachometer pulses have been detected, or 0.5s has elapsed. Spin-up behavior may be
modified by writing appropriate settings to the MAX6620’s registers.
8, 9
X1, X2
Crystal Oscillator Inputs. Connections for a standard 32.768kHz quartz crystal. The internal
oscillator circuitry is designed for operation with a crystal having a specified load capacitance
(CL) of 12pF. Connect an external 32.768kHz oscillator across X1 and X2 for operation with the
external oscillator. If no crystal or external oscillator is connected, the MAX6620 will use its
internal oscillator.
12, 17, 19, 24
DACOUT4–
DACOUT1
Fan Drive DAC Outputs. Connect to the gate of a p-channel MOSFET or base of a PNP bipolar
transistor.
13, 16, 20, 23
DACFB4–
DACFB1
14, 15, 21, 22
DAC Feedback Inputs. Connect a 0.1µF capacitor between these pins and GND. Connect to the
supply pin of the fan and to the drain of a p-channel MOSFET or collector of a PNP bipolar transistor.
TACH4–TACH1 Fan Tachometer Logic Inputs. These inputs accept input voltages up to VFAN.
26
FAN
Fan Power-Supply Voltage Input. Connect to the fan power supply (VFAN). Bypass with a 0.1µF
capacitor to GND.
27
VCC
Power-Supply Input. 3.3V nominal. Bypass VCC to GND with a 0.1µF capacitor.
28
FAN_FAIL
—
EP
Active-Low, Open-Drain Fan Failure Output. Active only when fault is present; open-circuit when
VCC = 0V. This pin can be pulled up to 5.5V regardless of VCC.
Exposed Paddle. Internally connected to GND. Connect to a large ground plane to maximize
thermal performance. Not intended as an electrical connection point.
_______________________________________________________________________________________
7
MAX6620
Pin Description
MAX6620
Quad Linear Fan-Speed Controller
whether lack of I2C activity will force the fans to full
speed. When the watchdog function is enabled, the
fans will be driven to full speed if there is no I2C activity
for a period of 2s, 6s, or 10s.
Detailed Description
The MAX6620 controls the speeds of up to four fans
using four independent linear voltage outputs. The
drive voltages for the fans are controlled directly over
the I 2 C interface. Each of the outputs (DACOUT1–
DACOUT4) drive the base of an external PNP or the
gate of a p-channel MOSFET. Voltage feedback at the
fan’s power-supply terminal is used to force the output
voltage.
The MAX6620 monitors fan tachometer logic outputs for
precise (1%) control of fan RPM and detection of fan
failure. When the MAX6620 is used with 2-wire fans,
these inputs are not used, and the fans can be driven
to the desired voltage without using tachometer feedback.
Three inputs set the fan drive status on application of
power. The DAC_START input selects the fan-supply
voltage (100%, 75%, or 0%) at startup to ensure appropriate fan drive when power is first applied. The
SPIN_START input selects whether spin-up will be
applied to the fans at power-up. WD_START selects
Digital Interface
The MAX6620 features an I2C-compatible, 2-wire serial
interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX6620
and the master at rates up to 400kHz. The master (typically a microcontroller) initiates data transfer on the bus
and generates SCL. SDA and SCL require 4.7kΩ (typ)
pullup resistors.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data into or out of the MAX6620. The data on SDA must
remain stable during the high period of the SCL clock
pulse, as changes in SDA while SCL is high are control
signals (see the START and STOP Conditions section).
Both SDA and SCL idle high.
Write Byte Format
S
ADDRESS
WR
A
COMMAND
7 bits
A
DATA
8 bits
Slave Address: equivalent to chip-select line of
a 3-wire interface
A
P
8 bits
Command Byte: selects which
register you are writing to
1
Data Byte: data goes into the register
set by the command byte (to set
thresholds, configuration masks, and
sampling rate)
Read Byte Format
S
ADDRESS
WR
A
7 bits
COMMAND
A
S
8 bits
Slave Address: equivalent to chip-select line
ADDRESS
WR
7 bits
Command Byte: selects
which register you are
reading from
A
DATA
P
Data Byte: reads from
the register set by the
command byte
Receive Byte Format
A
COMMAND
A
P
S
8 bits
SHADED = SLAVE TRANSMISSION
A = NOT ACKNOWLEDGED
ADDRESS
7 bits
RD
A
DATA
A
P
8 bits
Data Byte: reads data from
the register commanded
by the last read byte or
write byte transmission;
also used for SMBus alert
response return address
Figure 2. I2C Protocols
8
A
8 bits
Slave Address: repeated
due to change in dataflow direction
Command Byte: sends command with no data, usually
used for one-shot command
S = START CONDITION
P = STOP CONDITION
RD
7 bits
Send Byte Format
S
ADDRESS
_______________________________________________________________________________________
Quad Linear Fan-Speed Controller
tLOW
B
tHIGH
C
E
D
F
G
H
I
J
K
MAX6620
A
M
L
SCL
SDA
tSU:STA
tHD:STA
tSU:DAT
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
tHD:DAT
tSU:STO tBUF
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = MASTER PULLS DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
Figure 3. I2C Write Timing Diagram
A
B
tLOW
C
D
E
F
G
tHIGH
H
I
J
K
L
M
SCL
SDA
tSU:STA tHD:STA
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
tSU:STO
tSU:DAT
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
I = MASTER PULLS DATA LINE LOW
tBUF
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
Figure 4. I2C Read Timing Diagram
START and STOP Conditions
The master initiates a transmission with a START condition (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is high
(Figure 3). The STOP condition frees the bus and places
all devices in F/S mode (Figure 1). Use a repeated
START condition (Sr) in place of a STOP condition to
leave the bus active and in its current timing mode.
Acknowledge Bits
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX6620 (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (9th pulse), and keep it
low during the high period of the clock pulse (Figure 4).
To generate a not acknowledge, the receiver allows
SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse, and leaves it high
during the high period of the clock pulse. Monitoring
the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer
happens if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the master should reattempt communication at
a later time.
_______________________________________________________________________________________
9
MAX6620
Quad Linear Fan-Speed Controller
Slave Address
A master initiates communication with a slave device by
issuing a START condition followed by a slave address
byte. As shown in Figure 5, the slave address byte consists of 7 address bits and a read/write bit (R/W). When
idle, the MAX6620 continuously waits for a START condition followed by its slave address. The first four bits
(MSBs) of the slave address have been factory programmed and are always 0101 and the seventh bit is 0.
Connect ADDR to GND or VCC, or leave it unconnected
to program D2 and D1 of the slave address according
to Table 1.
Table 1. Slave Address Setting with
ADDR Pin
SLAVE ADDRESS
ADDR CONNECTION
HEX
BINARY
GND
0x50
0101 000
Unconnected
0x52
0101 010
VCC
0x54
0101 100
After receiving the address, the MAX6620 (slave)
issues an acknowledgement by pulling SDA low for one
clock cycle.
Data Byte (Read and Write)
Single Read and Burst Read. A single read begins
with the bus master issuing a START condition followed
by the seven slave ID address bits and a zero (WR,
Figure 2), which is followed by an acknowledge bit (A)
from the slave corresponding to the slave ID. Next, the
master sends out an 8-bit register address, which is
also followed by an acknowledge bit from the slave.
The bus master issues another START condition and
the same seven slave ID address bits followed by a one
(RD, Figure 2), with the slave producing an acknowledge bit. The slave then sends out the 8-bit data corresponding to the register address previously written by
the master. The bus master sends back a not-acknowledge bit (A). This completes the single read process
and a STOP condition is issued by the bus master.
In a burst read, the process is the same as a single
read except that the bus master issues an acknowledge bit after each byte transmitted by the slave. After
each acknowledge bit, the register address increments
by one, and the data from the next register is transmitted by the slave. The process continues, with data
reads followed by acknowledges. After the register with
the highest address is read, the register pointer rolls
over to point to the first register. To terminate a burst
read, the bus master issues a STOP condition.
Single Write and Burst Write. A single write begins
with the bus master issuing a START condition followed
by the seven slave ID address bits and a zero (WR,
Figure 2), which is followed by an acknowledge bit (A)
from the slave corresponding to the slave ID. Next, the
master sends out an 8-bit register address, which is
also followed by an acknowledge bit from the slave.
After the acknowledge bit, 8-bit data is written to the
register, and the slave issues a third acknowledgement.
A STOP condition is issued by the bus master to complete the single write process.
In a burst write, the process is similar to a single write
except that the master does not issue a STOP condition
immediately after the first byte has been written. After
the first write is completed, the slave issues an
acknowledge bit, the register address increments by
one, and the data to be written to the next register is
transmitted by the master. The process continues, with
data writes followed by acknowledges. After the register with the highest available address is written, the register pointer rolls over to point to the first register. To
terminate a burst write, the bus master issues a STOP
condition.
Fan Drive
The MAX6620 uses external pass transistors to power
the fans. DACOUT1–DACOUT4 adjust the powersupply voltage for each fan by driving the base of a
PNP bipolar transistor, or the gate of a p-MOSFET. The
resulting fan-supply voltage is fed back to DACFB_.
This closes the voltage feedback loop. The system
power supply for the output devices is VFAN. VFAN is
S
SDA
0
1
0
1
D2
D1
0
R/W
2
3
4
5
6
7
8
A
ACKNOWLEDGE
SCL
1
9
Figure 5. MAX6620 Slave Address Byte
10
______________________________________________________________________________________
______________________________________________________________________________________
S
0
AS
ACK BIT
0
AS
7-BIT SLAVE ID
0
AS
BIT 7…………….………… BIT 0 ACK BIT
BURST READ
7-BIT SLAVE ID
S: 2-WIRE BUS START CONDITION BY MASTER
P: 2-WIRE BUS STOP CONDITION BY MASTER
AS: ACKNOWLEDGE BY SLAVE
AM: ACKNOWLEDGE BY MASTER
AM: NO ACKNOWLEDGE BY MASTER
S
BURST WRITE
7-BIT SLAVE ID
BIT 7…………….…………BIT 0
S
ACK BIT
7-BIT SLAVE ID
BIT 7…………….……….BIT 0
SINGLE READ
S
AS
ACK BIT
AS
ACK BIT
AS
8-BIT REGISTER ADDRESS
AS
BIT 7…………….…………… BIT 0 ACK BIT
8-BIT REGISTER ADDRESS
BIT 7…………….………BIT 0
8-BIT REGISTER ADDRESS
7-BIT SLAVE ID
S
FIRST 8-BIT DATA
7-BIT SLAVE ID
AS
1
AS
1
8-BIT DATA
AS
P
AM
LAST 8-BIT DATA
AM
BIT 7……….……………BIT 0 ACK BIT
FIRST 8-BIT DATA
BIT 7……….…………………BIT 0 ACK BIT
LAST 8-BIT DATA
AM
BIT 7…….…………BIT 0 ACK BIT
AS
ACK BIT
BIT 7…………….…………BIT 0 ACK BIT
AS
8-BIT DATA
BIT 7…….…….…………BIT 0
BIT 7………….…………BIT 0 ACK BIT
AS
ACK BIT
BIT 7…………….……………BIT 0 ACK BIT
S
8-BIT REGISTER ADDRESS
BIT 7…………….…………………BIT
BIT 7…………….……………BIT 0 ACK BIT
0
BIT 7…………….……………… BIT 0
P
P
P
MAX6620
SINGLE WRITE
Quad Linear Fan-Speed Controller
Figure 6. Read and Write Summary
11
MAX6620
Quad Linear Fan-Speed Controller
nominally 12V or 5V. The drive to the fans is proportional to VFAN. See the Fan_ Target Drive Voltage Registers
and the Applications Information sections for more
details.
Fan-Speed Control
DAC (Voltage) Mode. In DAC mode, the MAX6620 simply sets the voltage that powers the fan. The fan’s
speed is related, but not precisely proportional to, the
drive voltage. The drive voltage is set by the Fan_
Target Drive Voltage registers and may be read from
the Fan_ Drive Voltage registers. Because the output
voltage can ramp to new values at a controlled rate, the
values in the two registers may be different. See the
Register Descriptions and Applications Information sections for details.
RPM Mode. In RPM mode, the MAX6620 monitors
tachometer output pulses from the fan and adjusts the
fan drive voltage to force the fan’s speed to the desired
value. Fan speed is measured by counting the number
of internal 8192Hz clock cycles that take place during a
selectable number of tachometer periods. The number
of clock cycles counted (11-bit value) is stored in the
Fan_ TACH Count registers, and the desired number of
cycles is stored in the Fan_ Target TACH Count registers. See the Register Descriptions and Applications
Information sections for details.
Rate-of-Change Control. Sudden changes in fan
speed can be easily heard by users. The MAX6620
helps reduce the audibility of fan-speed changes by
controlling the rate at which the drive to the fan is incremented. Four bits in the Fan_ Dynamics registers set
the rate at which the fan drive voltage is incremented.
This allows the time required for a change in fan speed
to be varied from 0 (in DAC mode only) to several minutes. See the Register Descriptions and Applications
Information sections for details.
Monitoring Tachometer Signals. The TACH_ inputs
accept tachometer or “locked-rotor” output signals from
3- or 4-wire fans. When measuring fan speed, the
MAX6620 counts the number of internal 8192Hz clock
cycles that occur during 1, 2, 4, 8, 16, or 32 tachometer
periods. The number of tachometer periods is selectable for each fan by using the appropriate Fan_
Dynamics register. Tachometer pulses <25µs in duration are ignored to minimize the effect of noise on the
tachometer lines.
12
The TACH count for a given RPM can be obtained from
the following equation:
TACH count =
60
491520 × SR
× SR × 8192 =
NP × RPM
NP × RPM
where:
NP = number of tachometer pulses per revolution. Most
general-purpose brushless DC fans produce two
tachometer pulses per revolution.
SR = 1, 2, 4, 8, 16, or 32. See the Fan_ Speed Range
information in the Fan_ Dynamics Registers (06h, 07h,
08h, 09h)—POR = 0100 1100 section.
The tachometer count consists of 11 bits in the Fan_
TACH Count registers and is available in RPM and DAC
modes. In RPM mode, the desired fan count is written
to the Fan_ Target TACH Count registers.
Fan Failure Detection
When enabled, the MAX6620 monitors the TACH_
inputs to determine when a fan has failed. For fans with
tachometer outputs, failure is detected in various ways
depending on the fan control mode. In every case, four
consecutive fault detections are required to decide
whether the fan has failed. In DAC mode, the Fan_
Target TACH Count registers hold the upper limit for
tachometer count values; a fault condition is identified
when a TACH count exceeds the value written to the
Fan_ Target TACH Count registers for more than 1s. In
RPM mode, a fault condition is identified when any of
the following three conditions occur for more than 1s: 1)
the TACH count exceeds the value of the Fan_ Target
TACH Count registers while the fan drive voltage is at
full-scale, 2) the TACH count exceeds two times the
Fan_ Target TACH Count value, or 3) the TACH count
reaches its full count of 7FF.
Some fans have locked rotor outputs that produce a
logic-level output to indicate that the fan has stopped
spinning. These signals can be monitored by setting
D2:D1 in the Fan_ Configuration registers. D2 selects
locked rotor or tachometer monitoring and D1 selects the
polarity of the locked rotor signal. A fan fault has occurred
when a locked rotor signal has been present for 1s.
Fan failure is indicated in the Fan Fault register and
also with the open-drain FAN_FAIL output. The
FAN_FAIL output may be masked using the mask bits
in the Fan Fault register. When a fan failure is detected,
drive to the affected fan is removed. Drive may be
restored by writing a new DAC or fan count target to the
fan’s control registers. The global configuration regis-
______________________________________________________________________________________
Quad Linear Fan-Speed Controller
Watchdog
The MAX6620 includes an optional I2C watchdog function that monitors the I2C bus for transactions. When the
watchdog function is enabled, all fans will be forced to
full speed if no I2C transactions occur within a selected
period (2s, 6s, or 10s).
Spin-Up
When a fan is not spinning, and a voltage less than the
nominal fan-supply voltage is applied to its powersupply terminals, it may fail to start spinning. To overcome this, the full nominal supply voltage may be
applied to the fan terminals for a short time before a
lower voltage is applied. This “spin-up” period allows
the fan to overcome inertia and begin operating. Spinup is controlled using the Fan_ Configuration registers.
Spin-up can be disabled, or it can cause the fan to be
driven with the full supply voltage until it produces two
tachometer pulses, up to a maximum of 0.5s, 1s, or 2s
when the fan is started.
POR Options
Three inputs allow set up of the MAX6620’s behavior at
power-up. These inputs are sampled when power is
first applied to the MAX6620:
• WD_START. Connect WD_START to VCC to enable,
or to ground to disable, the watchdog function. When
enabled using WD_START, the timeout period is 10s.
After power is applied, the watchdog function may be
enabled or disabled through the global configuration
register.
• SPINUP_START. At power-up, spin-up operation is
controlled by the SPINUP_START pin, which can be
connected to ground (spin-up disabled), VCC (spinup for a maximum of 1s), or unconnected (spin-up for
a maximum of 0.5s).
• DAC_START. This input controls the fan drive voltage (for all four fans) at power-up. When connected
to ground, the initial fan drive voltage will be 0V.
When connected to VCC, the initial fan drive voltage
will be full scale. When unconnected, the initial fan
drive voltage will be 75% of VFAN.
______________________________________________________________________________________
13
MAX6620
ter’s bit D4 can be used to cause a fan failure to force
the remaining fan speeds to 100%.
14
REGISTER
NO./ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
______________________________________________________________________________________
0100 1100
0100 1100
0100 1100
0100 1100
0XX0 0000
0XX0 0000
0XX0 0000
0XX0 0000
0000 1111
0000 0XXX
POR
STATE
D4
D3
Same as Fan 1 Dynamics
Same as Fan 1 Dynamics
Same as Fan 1 Dynamics
Fan 2
Dynamics
Fan 3
Dynamics
Fan 4
Dynamics
Fan 1
Dynamics
TACH/
Locked
Rotor:
0 = TACH
1 = locked
rotor
DAC Rate-of-Change:
000 = 0s per LSB (DAC mode)
0.0625s per LSB (RPM mode)
001 = 0.015625s per LSB
010 = 0.03125s per LSB
011 = 0.0625s per LSB
100 = 0.125s per LSB
101 = 0.25s per LSB
110 = 0.5s per LSB
111 = 1s per LSB
Same as Fan 1 Configuration
Fan 4
Configuration
Speed Range (TACH periods):
000 = 1
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 32
111 = 32
Same as Fan 1 Configuration
Fan 3
Configuration
Fan 1
Configuration
TACH
input
enable
Same as Fan 1 Configuration
Mode:
0 = DAC
1 = RPM
D1
I2C Watchdog:
00 = No watchdog
01 = 2s
10 = 6s
11 = 10s
D2
I2C
Watchdog
Status
(read only):
1=
elapsed
D0
Locked
Rotor
Polarity:
0 = low
1 = high
Fan 1 Fault Fan 4 Mask Fan 3 Mask Fan 2 Mask Fan 1 Mask
Fan 2
Configuration
Spin-Up:
00 = No spin-up
01 = two TACH counts
or 0.5s
10 = two TACH counts
or 1s
11 = two TACH counts
or 2s
Fan 2 Fault
Fan 3 Fault
Fan 4 Fault
Run:
0 = run
1 = standby
Global
Configuration
D5
Fans to
Bus
OSC:
POR:
100% on
Timeout
0 = internal
failure:
(35ms):
0 = normal
0 = enabled 0 = enabled 1 = XTAL
1 = reset
1 = disabled 1 = disabled
D6
Fan Fault
D7
FUNCTION
MAX6620
Quad Linear Fan-Speed Controller
Registers
Register Map
1110 0000
1111 1111
1110 0000
0000 0000
0000 0000
15h
16h
17h
18h
19h
0000 0000
0000 0000
0000 0000
0000 0000
0011 1100
0000 0000
0011 1100
0000 0000
0011 1100
0000 0000
0011 1100
0000 0000
XXXX XXXX
X000 0000
XXXX XXXX
X000 0000
XXXX XXXX
X000 0000
XXXX XXXX
X000 0000
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
0000 0000
1111 1111
14h
0000 0000
1110 0000
13h
1Ah
1111 1111
12h
1Bh
1110 0000
1111 1111
11h
10h
Fan 4 Target
Drive Voltage
Fan 3 Target
Drive Voltage
Fan 2 Target
Drive Voltage
Fan 1 Target
Drive Voltage
Fan 4 Target
TACH Count
Fan 3 Target
TACH Count
Fan 2 Target
TACH Count
Fan 1 Target
TACH Count
Fan 4 Drive
Voltage
Fan 3 Drive
Voltage
Fan 2 Drive
Voltage
Fan 1 Drive
Voltage
Fan 4 TACH
Count
Fan 3 TACH
Count
Fan 2 TACH
Count
Fan 1 TACH
Count
FUNCTION
X = Depends on input states at power-up.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
POR
STATE
REGISTER
NO./ADDRESS
D0
D8
D2
D10
D0
D8
D2
D10
D7
—
D7
D1
D9
—
D7
D1
D9
D6
—
D6
D0
D8
—
D6
D0
D8
D5
—
D6
D3
—
D4
—
D6
—
D4
Same as Fan 1 Target Drive Voltage
Same as Fan 1 Target Drive Voltage
Same as Fan 1 Target Drive Voltage
—
D5
Same as Fan 1 Target TACH Count
Same as Fan 1 Target TACH Count
Same as Fan 1 Target TACH Count
—
D7
Same as Fan 1 Drive Voltage
Same as Fan 1 Drive Voltage
Same as Fan 1 Drive Voltage
—
D5
Same as Fan 1 TACH Count
Same as Fan 1 TACH Count
Same as Fan 1 TACH Count
—
D7
D4
—
D3
—
D5
—
D3
—
D5
D2
—
D2
—
D4
—
D2
—
D4
D1
—
D1
—
D3
Full
D1
—
D3
D0
Register Map (continued)
______________________________________________________________________________________
15
MAX6620
R/W
Quad Linear Fan-Speed Controller
Quad Linear Fan-Speed Controller
MAX6620
Register Descriptions
Global Configuration Register (00h)—POR = 0000 0XXX
BIT
R/W
7
R/W
Run:
0 = run
1 = standby
R/W
POR:
0 = normal operation
1 = reset all registers to POR values
This bit automatically resets itself and will always return a 0 when read.
R/W
I2C Bus Timeout:
0 = enabled
1 = disabled
The I2C interface will reset if SDA is low for more than 35ms.
R/W
Fans to 100% on failure:
0 = if a fan failure is detected, all other fan channels immediately go to full-scale drive voltage to
ensure adequate cooling
1 = disabled
R/W
Oscillator Selection:
Selects on-chip oscillator or 32.768kHz crystal/ceramic resonator. Use crystal if 1% RPM accuracy is
required.
0 = internal oscillator (default at power-on)
1 = external 32.768kHz crystal
When switching from the internal oscillator to an external crystal, the MAX6620 operates from the internal
oscillator until the crystal oscillator has started up. If the crystal is damaged or the oscillator fails to start,
the MAX6620 will continue to operate from the internal oscillator.
6
5
4
3
16
FUNCTION
______________________________________________________________________________________
Quad Linear Fan-Speed Controller
R/W
FUNCTION
I2C Watchdog:
When active, the watchdog monitors SDA and SCL for valid I2C transactions. If there are no valid
transactions between the master and the MAX6620 within the watchdog period, all fan output voltages
will go to full-scale drive voltage.
2
If the watchdog times out and valid I2C transactions begin to occur again, operation will resume with the
previous DAC value. The master can then program the output voltages, target TACH counts, or other
functions in the normal manner.
R/W
When the watchdog function is active, ensure that the master communicates to the MAX6620
periodically, for example reading a status register.
The POR state is set by the state of the WD_START pin at power-up.
1
0
R
D2:D1
I2C WATCHDOG PERIOD (s)
POR CONDITION
00
Inactive (no watchdog)
WD_START = GND
01
2
—
10
6
—
11
10
WD_START = VCC
I2C Watchdog Status:
0 = I2C transactions occurred within watchdog period
1 = time between I2C transaction exceeds watchdog period
This bit is cleared by I2C read from this register.
______________________________________________________________________________________
17
MAX6620
Global Configuration Register (00h)—POR = 0000 0XXX (continued)
BIT
Quad Linear Fan-Speed Controller
MAX6620
Fan Fault Register (01h)—POR = 0000 1111
BIT
R/W
FUNCTION
Fan 4 Fault Status:
Indicates which fans have had faults detected. When a fan fault is detected, the drive to the fan is disabled and
the corresponding fault bit is set. The fault bits latch until they are cleared by reading, thus allowing short-term
faults to be identified. After a fault status bit is cleared by reading, the corresponding output voltage will
remain zero until a Fan_ Target Drive Voltage register or Fan_ Target TACH Register is written. Writing a
new target drive voltage or target TACH count will cause drive to be applied to the fan again, at which time a
new failure-detection cycle will begin.
Fault Conditions Are:
7
MODE
FAN_ DRIVE
VOLTAGE REGISTER
DAC
Any
R
CONDITION
TACH count exceeds value of Fan_ Target
TACH count
TIME
(s)
>1
Locked rotor asserts
1FF (full)
RPM
<1FF
TACH count exceeds value of Fan_ Target
TACH Count
TACH count exceeds two times of Fan_ Target
TACH Count value
>1
TACH count reaches it full count of 7FF
FAN_FAIL will be asserted when four consecutive faults are detected.
18
6
R
Fan 3 Fault Status
5
R
Fan 2 Fault Status
4
R
3
R/W
2
R/W
Fan 1 Fault Status
Fan 4 Fault Mask:
Masks faults on selected fans from asserting the FAN_FAIL output. Faults will still be indicated by the fault
status bits:
0 = not masked
1 = masked
Fan 3 Fault Mask
1
R/W
Fan 2 Fault Mask
0
R/W
Fan 1 Fault Mask
______________________________________________________________________________________
Quad Linear Fan-Speed Controller
BIT
7
R/W
R/W
FUNCTION
RPM/DAC:
0 = DAC mode. The fan drive voltage is set by the value in the Fan_ Target Drive Voltage register.
1 = RPM mode. The fan drive voltage is adjusted to produce the TACH count value in the Fan_ Target
TACH Count register.
When changing from DAC to RPM mode, if the current RPM value is different from the value selected in
the Fan_ Target TACH Count register, the drive voltage will start from the current value and increment/
decrement toward the desired value at the selected DAC rate-of-change.
Spin-Up:
When the fan drive voltage increases from 0V to a value less than the full-scale drive voltage, it may be
necessary to drive the fan with the full-scale drive voltage for a brief period to ensure that the fan is
spinning before reducing the drive to the selected value.
6
R/W
When spin-up is selected, the fan is driven at the full-scale drive voltage until two tachometer pulses
have been detected or locked rotor has been cleared. A maximum spin-up time is also selectable to
ensure that the spin-up time is not excessive. After two tachometer pulses have been detected, or locked
rotor has been cleared or the spin-up has timed out, the drive voltage goes to the value in the Fan_ Target
Drive Voltage register.
The POR state is set by the state of the SPINUP_START pin at power-up.
D6:D5
5
FUNCTION
POR CONDITION
00
No spin-up
SPIN_START pin = ground
01
Spin-up until two tachometer pulses or
clearing of locked rotor, or 0.5s (max)
SPIN_START pin = open
10
Spin-up until two tachometer pulses or
clearing of locked rotor, or 1s (max)
SPIN_START pin = VCC
11
Spin-up until two tachometer pulses or
clearing of locked rotor, or 2s (max)
—
R/W
4
Reserved
3
R/W
TACH Input Enable:
Enables TACH input function and fan fault detection (automatically enabled in RPM mode).
0 = disabled. When disabled and TACH input is not used, bit 1 and bit 2 are ignored.
1 = enabled
2
R/W
TACH/Locked Rotor:
Selects TACH input function as TACH count or locked rotor. In locked rotor mode, the TACH count stops
and assertion of the TACH input indicates that the fan has stopped.
0 = TACH count
1 = locked rotor
1
R/W
Locked Rotor Polarity:
0 = low locked rotor. TACH input low in locked rotor mode indicates fan is stopped.
1 = high locked rotor. TACH input high in locked rotor mode indicates fan is stopped.
0
—
Reserved
______________________________________________________________________________________
19
MAX6620
Fan_ Configuration Registers (02h, 03h, 04h, 05h)—POR = 0XX0 0000
Quad Linear Fan-Speed Controller
MAX6620
Fan_ Dynamics Registers (06h, 07h, 08h, 09h)—POR = 0100 1100
BIT
7
R/W
R/W
FUNCTION
Fan_ Speed Range:
The MAX6620 determines fan speed by counting the number of internal 8192Hz clock cycles (using an 11bit counter) during one or more fan tachometer periods. Three bits set the nominal RPM range for the fan, as
shown in the table below. As an example, a setting of 010 causes the MAX6620 to count the number of
8192Hz clock cycles that occur during four complete tachometer periods. If the fan has a nominal speed of
2000RPM and two tachometer pulses per revolution, one tachometer period will be nominally 15ms, and four
tachometer periods will be 60ms. With an 8192Hz clock, the TACH count will therefore be equal to 491. With
a fan speed of 1/3 the nominal value, the count will be 1474. If the fan’s nominal speed is 1000RPM, the fullspeed TACH count will be 983. At 1/3 the nominal speed, there will be 2948 clock cycles in four tachometer
periods. This is greater than the maximum 11-bit count of 2047, so four tachometer periods is too many for
this fan; a setting of 001 (two clock cycles) is recommended instead.
The table below shows the full-speed tachometer counts for several combinations of nominal fan speeds
and D7:D5 settings. The shaded combinations will provide the best results. When setting D7:D5, the goal is
to obtain the highest tachometer count without exceeding the maximum count of 2047 when the fan is at the
minimum speed of interest. For example, if the minimum speed of interest is 1/3 of full speed, the maximum
tachometer count will be three times the value shown in the table below:
Tachometer Counts/(Counting Period) (8192Hz Clock Used):
6
5
20
R/W
D7:D5
NUMBER OF
TACH PERIODS
COUNTED
000
RPM
500
1000
2000
4000
8000
16000
1
491
(60ms)
245
(30ms)
122
(15ms)
61
(7.5ms)
30
(3.75ms)
15
(1.875ms)
001
2
983
(120ms)
491
(60ms)
245
(30ms)
122
(15ms)
61
(7.5ms)
30
(3.75ms)
010
4
1966
(240ms)
983
(120ms)
491
(60ms)
245
(30ms)
122
(15ms)
61
(7.5ms
011
8
2047
(480ms)
1966
(240ms)
983
(120ms)
491
(60ms)
245
(30ms)
122
(15ms)
100
18
2047
(960ms)
2047
(480ms)
1966
(240ms)
983
(120ms
491
(60ms)
245
(30ms
101,
110,
111
32
2047
(1920ms)
2047
(960ms)
2047
(480ms)
1966
(240ms)
983
(120ms)
491
(60ms)
R/W
______________________________________________________________________________________
Quad Linear Fan-Speed Controller
BIT
R/W
FUNCTION
Fan_ DAC Rate-of-Change:
The fan drive voltage (at the DACFB_ inputs) varies from 0 to full scale in 512 increments. The rate-ofchange bits determine the time interval between output voltage increments/decrements. In RPM mode, a
setting of 0 would result in an unstable feedback loop, so a default value of 0.0625 is in effect when 0 is
selected.
4
R/W
3
R/W
Regardless of the settings, there are a few cases for which the rate-of-change is always 0:
• When a target TACH count of 2047 (7FF) is selected, the fan drive voltage immediately goes to 0V. A
full-scale target count is assumed to mean that the intent is to shut down the fan, and going directly to 0
drive avoids the possibility of loss of control-loop feedback at high TACH counts. If a slow- speed
decrease toward 0 is desired, a target TACH count at the slowest practical value for the fan should be
chosen. Once that count has been reached, selecting a count of 2047 (7FF) will then take the drive
immediately to 0V.
• When a target fan drive voltage of 0V is selected, the drive voltage immediately goes to 0V. Again, it is
assumed that the intent is to shut down the fan. If a slow-speed decrease toward 0 is desired, a target
fan drive voltage of the slowest practical value for the fan in question should be chosen. Once that drive
voltage has been reached, selecting a target value of 0 will then take the drive immediately to 0V.
• When the current drive level is 0 in DAC mode, selecting a new target fan drive voltage will immediately
take the voltage to that value. The fan will spin-up first if spin-up is enabled.
• When the current drive level is 0 in RPM mode, selecting a new target TACH count that is less than 2047
(7FF) will immediately take the drive voltage to the value in the Fan_ Target Drive Voltage register. From
this value, the drive voltage will increment as needed to achieve the desired TACH count. The fan will
spin-up first if spin-up is enabled.
D4:D2
000
2
R/W
TIME BETWEEN OUTPUT VOLTAGE
INCREMENTS (s)
DAC MODE
0
RPM MODE
0.0625
TIME FROM 33%
TO 100%
(s)
0
001
0.015625
10
010
0.03125
20
011
0.0625 (default)
40
100
0.125
80
101
0.25
160
110
0.5
320
111
1.0
640
1
—
Reserved
0
—
Reserved
______________________________________________________________________________________
21
MAX6620
Fan_ Dynamics Registers (06h, 07h, 08h, 09h)—POR = 0100 1100 (continued)
Quad Linear Fan-Speed Controller
MAX6620
Fan_ TACH Count Registers (10h, 12h, 14h, 16h)—POR = 1111 1111
BIT
R/W
FUNCTION
7
6
5
4
3
R
2
Fan_ TACH Count D10:D3:
Indicates the number of 8192Hz clock pulses counted during the counting period. The Fan_ TACH Count
consists of 11 bits contained in two bytes.
To minimize noise from spurious tachometer transitions, pulses less than 25µs are ignored.
1
0
Fan_ TACH Count Registers (11h, 13h, 15h, 17h)—POR = 1110 0000
BIT
R/W
FUNCTION
7
6
R
Fan_ TACH Count D7:D5
5
Fan_ Drive Voltage Registers (18h, 1Ah, 1Ch, 1Eh)—POR = 0000 0000
BIT
R/W
FUNCTION
7
6
Fan_ Drive Voltage D8:D1:
This is a 9-bit value that ranges from 0 to 511.
5
4
3
R
This register shows the actual fan drive voltage. When the value in this register is 480V, the nominal fan drive
voltage of VFAN is supplied to the fan, as shown in the table in the Fan_ Target Drive Voltage Registers section.
2
1
0
Fan_ Drive Voltage Registers (19h, 1Bh, 1Dh, 1Fh)—POR = 0000 0000
22
BIT
R/W
7
R
Fan_ Drive Voltage D0
FUNCTION
0
R
Full-Scale Status:
0 = DAC is driving with value of D8:D0 that is not at full scale
1 = DAC is driving with full scale voltage
______________________________________________________________________________________
Quad Linear Fan-Speed Controller
BIT
writes in between. These target registers are updated
internally at the same time when a second byte (LSB) is
written.
R/W
FUNCTION
Fan_ Target TACH Count D10:D3:
In RPM mode, write the desired tachometer count to this register. The MAX6620 will then adjust the fan drive
voltage to achieve this tachometer count.
7
6
In DAC mode, this register has no effect.
5
4
R/W
3
When changing from DAC mode to RPM mode, best results are obtained by loading this register with the
desired TACH count before changing to RPM mode. The target TACH count for a given RPM will be obtained
by the following equation:
TargetTACH =
2
60
× SR × 8192
NP × RPM
where:
NP = number of TACH pulses per revolution
SR = 1, 2, 4, 8, 16, or 32 (see the fan_ speed range information in the Fan_ Dynamics Registers (06h, 07h, 08h,
09h)—POR = 0100 1100 section)
1
0
Fan_ Target TACH Count Registers (21h, 23h, 25h, 27h)—POR = 0000 0000
BIT
R/W
FUNCTION
7
6
R
Fan_ Target TACH Count D2:D0
5
______________________________________________________________________________________
23
MAX6620
Fan_ Target TACH Count Registers (20h, 22h, 24h, 26h)—POR = 0011 1100
The Fan_ Target TACH Count consists of 11 bits contained in two bytes. The two bytes must be written in
order in one or two I2C transactions, with no other I2C
MAX6620
Quad Linear Fan-Speed Controller
Fan_ Target Drive Voltage Registers (28h, 2Ah, 2Ch, 2Eh)—POR = XXXX XXXX
The Fan_ Target Drive Voltage consists of 9 bits contained in two bytes. The two bytes must be written in
order in one or two I2C transactions with no other I2C
BIT
R/W
writes in between. These target registers are updated
internally at the same time when a second byte (LSB) is
written.
FUNCTION
Fan_ Target Drive Voltage D8:D1:
This is a 9-bit value that ranges from 0 to 511 and is contained in two bytes. In DAC mode, write the
desired fan drive voltage to these two registers. The MAX6620 will then ramp the fan drive voltage to
this value at a rate determined by the DAC rate-of-change bits.
7
In RPM mode, the value contained in this register will be the voltage applied to the fan immediately after
spin-up or after changing the Fan_ Target TACH Count from 2047 (7FF) to a value lower than 2047 (7FF).
For example, if the fan is currently stopped with spin-up disabled, and a new Fan_ Target TACH Count
corresponding to 60% of the full-scale fan speed is to be selected, the fan voltage can be programmed
to immediately go to 60% of the full-scale drive voltage when the new Fan_ Target TACH Count is
selected from 2047 (7FF), and then close the RPM control loop starting from that voltage.
6
5
The register value is converted to the drive voltage at the fan (or voltage at DACFB_) as follows:
D8:D0
4
DECIMAL
R/W
3
2
FAN_ DRIVE VOLTAGE (V)
HEX
5V RANGE
12V RANGE
0
000h
0.000
0.000
200
0C8h
1.764
4.486
300
12Ch
2.646
6.729
400
190h
3.527
8.972
480
1E0h
4.232
10.766
511
1FFh
4.506
11.462
The value of the Fan_ Target Drive Voltage at POR depends on state of the DAC_START pin, as shown
below:
1
D8:D0
0
DECIMAL
HEX
DAC_START
0
000h
GND
384
180h
Open
511
1FF
VCC
Fan_ Target Drive Voltage Registers (29h, 2Bh, 2Dh, 2Fh)—POR = X000 0000
24
Bit
R/W
7
R
FUNCTION
Fan_ Target Drive Voltage D0
______________________________________________________________________________________
Quad Linear Fan-Speed Controller
External Pass Transistors
Match external pass transistors to the fans being used.
Ensure that the pass transistor is capable of handling
the maximum fan current. For best results, the pass
transistor’s maximum current rating should be at least
50% greater than the fan’s nominal supply current.
The transistor should also be capable of dissipating the
worst-case power, which usually occurs when the fan is
being driven to approximately 50% of the nominal supply voltage. The maximum power dissipation will
depend on the thermal resistance of the transistor, its
case, and the printed-circuit board (PCB) to which it is
soldered. For example, if the worst-case transistor
power dissipation occurs when the fan current is
100mA, and the voltage across the fan is 6.5V, the
maximum power dissipation will be 650mW. A
BCP69T1-D in a SOT223-4 package is rated at 1.5W at
25°C (about 1W at 70°C) when soldered to a 0.93in2
(6cm2) copper PCB pad, and can easily handle this
power dissipation. Larger copper pads, packages with
lower thermal resistance, or different transistors can
give significantly different results.
The MAX6620 uses an advanced output driver design
that eliminates the large external capacitors often connected across the fan’s power-supply terminals. For
stability with a variety of fans, connect a 0.1µF capacitor from DACFB_ to ground.
Using a Low-Dropout Voltage Regulator
(LDO) as the Pass Device
Voltage regulators can be used instead of discrete transistors to drive the fans (Figure 7). The voltage feedback loop is closed around the regulator to provide the
desired output voltage. When using a voltage regulator,
note the following:
• Most regulators require relatively large capacitors at
their inputs and outputs for stability.
• Most regulators have a lower output voltage limit that
is >0V. If removing the drive from the fan is necessary when using a regulator, choose a regulator that
has an on/off control input and drive that input from
the system microcontroller.
Fan-Speed Control (DAC and RPM Modes)
The MAX6620 has two main modes for controlling fan
speeds. In DAC mode, the MAX6620 produces an output voltage that drives the fan. This voltage is proportional to the main fan power-supply voltage (VFAN).
Write the 9-bit desired voltage value in the Fan_ Target
Drive Voltage register.
In RPM mode, the MAX6620 monitors the tachometer
signals from the fans through the TACH_ inputs and
adjusts the drive voltage to yield the desire tachometer
count. The tachometer count is the number of internal
8192 clock cycles that are counted during the selected
number of tachometer pulses.
Controlling 2-Wire Fans (DAC Mode)
In DAC mode, the MAX6620 sets the fan’s supply voltage to the value selected in the Fan_ Target Drive
Voltage register. Tachometer monitoring is never done
when controlling a 2-wire fan, so the TACH input enable
bit in the Fan_ Configuration register should be set to 0.
Enabling the TACH input when using a 2-wire fan will
result in an erroneous fan failure detection.
Initial Settings:
• Begin with the POR settings. The POR value of the
fan_ DAC rate-of-change bits (4:2 of the Fan_
Dynamics Register) can yield slower fan speed
changes than desired. If this is the case, choose a
faster value, such as 001.
Starting the Fan:
• Write the desired drive voltage value to the Fan_
Target Drive Voltage register.
Changing Speeds:
• Write the new desired drive voltage value to the Fan_
Target Drive Voltage register.
Stopping the Fan:
• Write a voltage value of 0 to the Fan_ Target Drive
Voltage register.
Controlling 3-Wire Fans (DAC Mode)
In DAC mode, the MAX6620 sets the fan’s supply voltage to the value selected in the Fan_ Target Drive
Voltage register. 3-wire fans with tachometer outputs
allow monitoring of the fan’s speed to detect fan failure.
To monitor a fan’s speed, the TACH input should be
enabled.
______________________________________________________________________________________
25
MAX6620
Applications Information
MAX6620
Quad Linear Fan-Speed Controller
VFAN
+12V
0.33μF
VC
VIN
PQ20RX
VO
VADJ
DACOUT1
470Ω
47μF
2.4kΩ
27kΩ
DACFB1
VFAN
VCC
3.0V TO 5.5V
VFAN
+12V
TACH1
0.1μF
FAN1
0.1μF
VFAN
0.33μF
FAN_FAIL
VC
VIN
PQ20RX
VO
VADJ
DACOUT2
470Ω
SDA
47μF
2.4kΩ
27kΩ
TO I2C MASTER
DACFB2
SCL
VFAN
TACH2
FAN2
VCC
VFAN
ADDR
DAC_START
I2C INTERFACE,
REGISTERS, AND
CONTROL LOGIC
DAC OUTPUT
DRIVER
0.33μF
TACH MONITOR
VC
VIN
PQ20RX
VO
VADJ
SPINUP_START
DACOUT3
470Ω
47μF
2.4kΩ
27kΩ
WD_START
DACFB3
VFAN
X1
(OPTIONAL CRYSTAL)
X2
TACH3
FAN3
VFAN
0.33μF
VC
VIN
PQ20RX
VO
VADJ
DACOUT4
470Ω
47μF
2.4kΩ
27kΩ
DACFB4
VFAN
TACH4
FAN3
Figure 7. Using Low Dropout Voltage Regulators Instead of Discrete Transistors as the Pass Devices
26
______________________________________________________________________________________
Quad Linear Fan-Speed Controller
• Set the TACH input enable bit in the Fan_
Configuration register to 1.
Note: This bit can be set after the fan has been started, if desired. If the bit is set before writing a target
fan drive voltage, the target drive voltage should be
set immediately after enabling the TACH input to
avoid failure detection before the fan has started
spinning.
Starting the Fan:
• Write the desired drive voltage value to the Fan_
Target Drive Voltage register.
Changing Speeds:
• Write the new desired drive voltage value to the Fan_
Target Drive Voltage register.
Stopping the Fan:
• Write a 0 to the TACH input enable bit in the Fan_
Configuration register. This prevents the MAX6620
from deciding that the fan has failed after it has
stopped.
• Write a voltage value of 0V to the Fan_ Target Drive
Voltage register.
• If a gradual decrease in fan speed is desired, write
the lowest drive voltage at which the fan will reliably
operate. When the drive voltage reaches that value,
write 0V to the Fan_ Target Drive Voltage register.
Controlling 3-Wire Fans (RPM Mode)
Begin as in DAC mode and start the fan.
Changing from DAC Mode to RPM Mode:
• Write the desired tachometer count to the Fan_ TACH
Count registers.
• Set bit 7 of the Fan_ Configuration register to 1. This
selects RPM mode. The fan will go to the selected
speed.
Note: When the DAC rate-of-change is set to one of
the faster values, the fan drive voltage can, depending on the fan’s characteristics, undergo a slow oscillation. While this rarely has an audible impact, it can
be reduced or eliminated by selecting a slower rateof-change once the fan’s speed has reached or
approached its target value.
Changing Speeds:
• Write the desired tachometer count to the Fan_
Target TACH Count registers.
Stopping the Fan:
• Write the current drive voltage into the Fan_ Target
Drive Voltage register.
• Write a value greater than the current tachometer
count into the Fan_ Target TACH Count register.
• Write a 0 to bit 7 of the Fan_ Configuration register.
This selects DAC mode.
• Write a 0 to the TACH input enable bit in the Fan_
Configuration register. This prevents the MAX6620
from detecting a high TACH count and determining
that the fan has failed.
• Write a voltage value of 0V to the Fan_ Target Drive
Voltage register.
• If a gradual decrease in fan speed is desired, write
the lowest drive voltage at which the fan will reliably
operate. When the drive voltage reaches that value,
write 0 to the Fan_ Target Drive Voltage register.
______________________________________________________________________________________
27
MAX6620
Initial Settings:
• Begin with the POR settings. The POR value of the
fan_ DAC rate-of-change bits (4:2 of the Fan_
Dynamics register) can yield slower fan speed
changes than desired. If this is the case, choose a
faster value, such as 001.
• Write the desired number of tachometer periods to
be counted in the speed range bits (7:5 of the Fan_
Dynamics register).
• Write the maximum allowable tachometer count to the
Fan_ Target TACH Count registers. Tachometer
counts greater than this value will result in a fan fault
detection. Choose a value that will not be encountered during normal operation, accounting for normal
fan speed tolerances.
Note: Setting a full-scale target count (2047) will
result in the fan drive going to 0V.
Quad Linear Fan-Speed Controller
MAX6620
Typical Application Circuit
0.1μF
4.7kΩ
DACOUT1
VFAN
DACFB1
0.1μF
VCC
VFAN
4.7kΩ
TACH1
0.1μF
FAN1
0.1μF
FAN_FAIL
0.1μF
4.7kΩ
DACOUT2
VFAN
DACFB2
0.1μF
4.7kΩ
SDA
TACH2
FAN2
TO I2C MASTER
SCL
0.1μF
4.7kΩ
DACOUT3
ADDR
VCC
DAC OUTPUT
DRIVER
I2C INTERFACE,
REGISTERS, AND
CONTROL LOGIC
DACFB3
0.1μF
TACH MONITOR
DAC_START
VFAN
4.7kΩ
TACH3
FAN3
SPINUP_START
0.1μF
WD_START
4.7kΩ
DACOUT4
X1
VFAN
DACFB4
0.1μF
(OPTIONAL CRYSTAL)
4.7kΩ
TACH4
X2
GND
Chip Information
PROCESS: CMOS
28
______________________________________________________________________________________
FAN4
Quad Linear Fan-Speed Controller
QFN THIN.EPS
______________________________________________________________________________________
29
MAX6620
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX6620
Quad Linear Fan-Speed Controller
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.