Cypress CY14B256LA-SZ25XIT 256 kbit (32k x 8) nvsram Datasheet

CY14B256LA
256 Kbit (32K x 8) nvSRAM
Features
Functional Description
■
25 ns and 45 ns Access Times
■
Internally Organized as 32K x 8 (CY14B256LA)
■
Hands off Automatic STORE on Power Down with only a Small
Capacitor
■
STORE to QuantumTrap Nonvolatile Elements Initiated by
Software, Device Pin, or AutoStore on Power Down
■
RECALL to SRAM Initiated by Software or Power Up
■
Infinite Read, Write, and Recall Cycles
■
1 Million STORE Cycles to QuantumTrap
The Cypress CY14B256LA is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as
32K bytes of 8 bits each. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power down. On power
up, data is restored to the SRAM (the RECALL operation) from
the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
■
20 year Data Retention
■
Single 3V +20% to -10% Operation
■
Industrial Temperature
■
44-Pin TSOP - II, 48-Pin SSOP, and 32-Pin SOIC Packages
■
Pb-free and RoHS Compliance
Cypress Semiconductor Corporation
Document Number: 001-54707 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 08, 2009
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CY14B256LA
Contents
Features ...............................................................................1
Functional Description .......................................................1
Contents ..............................................................................2
Pinouts ................................................................................3
Device Operation ................................................................5
SRAM Read .........................................................................5
SRAM Write .........................................................................5
AutoStore Operation ..........................................................5
Hardware STORE Operation ..............................................5
Hardware RECALL (Power Up) ..........................................6
Software STORE .................................................................6
Software RECALL ...............................................................6
Preventing AutoStore .........................................................7
Data Protection ...................................................................7
Noise Considerations .........................................................7
Best Practices .....................................................................8
Maximum Ratings ...............................................................9
Operating Range .................................................................9
Document Number: 001-54707 Rev. *B
DC Electrical Characteristics ............................................ 9
AC Test Conditions ..........................................................10
Data Retention and Endurance .......................................10
Capacitance ......................................................................10
Thermal Resistance ..........................................................10
AC Switching Characteristics .........................................11
AutoStore/Power Up RECALL .........................................13
Software Controlled STORE/RECALL Cycle ..................14
Hardware STORE Cycle ...................................................15
Truth Table For SRAM Operations ..................................16
Part Numbering Nomenclature ........................................16
Ordering Information ........................................................17
Package Diagrams ............................................................18
Document History Page ...................................................20
Sales, Solutions, and Legal Information ........................20
Worldwide Sales and Design Support .........................20
Products ......................................................................20
Page 2
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CY14B256LA
Pinouts
Figure 1. Pin Diagram - 44 Pin TSOP II/48 Pin SSOP
NC
[5]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
44 - TSOP II
(x8)
Top View
(not to scale)
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
HSB
NC
[4]
NC
[3]
NC
[2]
NC
NC [1]
[1]
NC
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
30
29
28
27
26
25
24
23
VCAP
A14
A13
VCAP
NC
A14
A12
A7
A6
A5
NC
A4
NC
NC
NC
VSS
NC
NC
DQ0
A3
A2
A1
A0
A12
A11
A10
DQ1
DQ2
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 - SSOP
(x8)
Top View
(not to scale)
48
47
VCC
46
45
44
43
42
41
40
HSB
WE
A13
A8
A9
39
38
37
36
NC
NC
NC
VSS
NC
35
34
33
32
31
30
29
28
27
26
25
NC
NC
A11
NC
DQ6
OE
A10
CE
DQ7
DQ5
DQ4
DQ3
VCC
Figure 2. Pin Diagram - 32-Pin SOIC
32 - SOIC
(x8)
Top View
(not to scale)
Notes
1. Address expansion for 1 Mbit. NC pin not connected to die
2. Address expansion for 2 Mbit. NC pin not connected to die.
3. Address expansion for 4 Mbit. NC pin not connected to die.
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
Document Number: 001-54707 Rev. *B
Page 3
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CY14B256LA
Table 1. Pin Definitions
Pin Name
I/O Type
A0 – A14
Input
Description
Address Inputs Used to Select One of the 32,768 bytes of the nvSRAM.
DQ0 – DQ7 Input/Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
WE
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
VSS
Ground
Ground for the Device. Must be connected to the ground of the system.
VCC
Power
Supply
Power Supply Inputs to the Device. 3.0V +20%, –10%
HSB
VCAP
NC
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is
driven HIGH for short time with standard output high current.
Power
Supply
AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No Connect No Connect. This pin is not connected to the die.
Document Number: 001-54707 Rev. *B
Page 4
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CY14B256LA
The CY14B256LA nvSRAM is made up of two functional
components paired in the same physical cell. They are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B256LA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the nonvolatile cells and up to 1 million STORE operations.
Refer to the Truth Table For SRAM Operations on page 16 for a
complete description of read and write modes.
SRAM Read
The CY14B256LA performs a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A0-14 determines which of the 32,768 data bytes each are
accessed. When the read is initiated by an address transition,
the outputs are valid after a delay of tAA (read cycle 1). If the read
is initiated by CE or OE, the outputs are valid at tACE or at tDOE,
whichever is later (read cycle 2). The data output repeatedly
responds to address changes within the tAA access time without
the need for transitions on any control input pins. This remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–7 are
written into the memory if the data is valid tSD before the end of
a WE-controlled write or before the end of a CE-controlled write.
Keep OE HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B256LA stores data to the nvSRAM using one of the
following three storage operations: Hardware STORE activated
by HSB; Software STORE activated by an address sequence;
AutoStore on device power down. The AutoStore operation is a
unique feature of QuantumTrap technology and is enabled by
default on the CY14B256LA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 7. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
may corrupt the data stored in nvSRAM.
Document Number: 001-54707 Rev. *B
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 9 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. Place a
pull up on WE to hold it inactive during power up. This pull up is
only effective if the WE signal is tristate during power up. Many
MPUs tristate their controls on power up. This must be verified
when using the pull up. When the nvSRAM comes out of
power-on-recall, the MPU must be active or the WE held inactive
until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 3. AutoStore Mode
VCC
0.1uF
VCC
10kOhm
Device Operation
WE
VCAP
VSS
VCAP
Hardware STORE Operation
The CY14B256LA provides the HSB pin to control and
acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B256LA conditionally initiates a STORE
operation after tDELAY. An actual STORE cycle only begins if a
write to the SRAM has taken place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition when
the STORE (initiated by any means) is in progress.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B256LA. But any SRAM read and write cycles
are inhibited until HSB is returned HIGH by MPU or other
external source.
Page 5
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CY14B256LA
During any STORE operation, regardless of how it is initiated,
the CY14B256LA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the CY14B256LA remains disabled until the
HSB pin returns HIGH. Leave the HSB unconnected if it is not
used.
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Hardware RECALL (Power Up)
Software RECALL
During power up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven low by the HSB driver.
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0C63 Initiate RECALL Cycle
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14B256LA Software
STORE cycle is initiated by executing sequential CE controlled
read cycles from six specific address locations in exact order.
During the STORE cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the nonvolatile
elements. After a STORE cycle is initiated, further input and
output are disabled until the cycle is completed.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0FC0 Initiate STORE Cycle
Table 2. Mode Selection
CE
WE
OE
A14 - A0[6]
Mode
I/O
Power
H
X
X
X
Not Selected
Output High-Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[7]
Notes
6. While there are 15 address lines on the CY14B256LA, only the lower 14 are used to control software modes.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-54707 Rev. *B
Page 6
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CY14B256LA
Table 2. Mode Selection (continued)
CE
WE
OE
A14 - A0[6]
Mode
I/O
Power
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[7]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High-Z
Active ICC2[7]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High-Z
Active[7]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B45 AutoStore Disable
The AutoStore is reenabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B46 AutoStore Enable
Document Number: 001-54707 Rev. *B
If the AutoStore function is disabled or reenabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled.
Data Protection
The CY14B256LA protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and write operations. The low voltage condition is detected when
VCC is less than VSWITCH. If the CY14B256LA is in a write mode
(both CE and WE are LOW) at power up, after a RECALL or
STORE, the write is inhibited until the SRAM is enabled after
tLZHSB (HSB to output active). This protects against inadvertent
writes during power up or brown out conditions.
Noise Considerations
Refer to CY application note AN1064.
Page 7
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CY14B256LA
Best Practices
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, autostore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this max VCAP value. Customers that
want to use a larger VCAP value to make sure there is extra store
charge and store time should discuss their VCAP size selection
with Cypress to understand any impact on the VCAP voltage level
at the end of a tRECALL period.
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in this nvSRAM product are delivered from
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
Document Number: 001-54707 Rev. *B
Page 8
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CY14B256LA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Storage Temperature ................................. –65°C to +150°C
Surface Mount Pb Soldering
Temperature (3 Seconds) .......................................... +260°C
Maximum Accumulated Storage Time:
At 150°C Ambient Temperature........................ 1000h
DC Output Current (1 output at a time, 1s duration).... 15 mA
At 85°C Ambient Temperature..................... 20 Years
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with Power Applied.. –55°C to +150°C
Supply Voltage on VCC Relative to GND ..........–0.5V to 4.1V
Voltage Applied to Outputs in
Latch Up Current ................................................... > 200 mA
Operating Range
Range
High-Z State........................................... –0.5V to VCC + 0.5V
Input Voltage.............................................–0.5V to Vcc+0.5V
Ambient Temperature
VCC
–40°C to +85°C
2.7V to 3.6V
Industrial
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V)
Parameter
Description
Test Conditions
Min
Typ[8]
Max
2.7
3.0
Unit
VCC
Power Supply
3.6
V
ICC1
Average VCC Current
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads (IOUT = 0 mA)
70
52
mA
mA
ICC2
Average VCC Current
during STORE
All Inputs Don’t Care, VCC = Max
Average current for duration tSTORE
10
mA
ICC3
Average VCC Current at All I/P cycling at CMOS levels.
tRC= 200 ns,
Values obtained without output loads (IOUT = 0 mA).
VCC (Typ), 25°C
ICC4
Average VCAP Current All Inputs Don’t Care. Average current for duration tSTORE
during AutoStore Cycle
5
mA
ISB
VCC Standby Current
5
mA
IIX[9]
Input Leakage Current VCC = Max, VSS < VIN < VCC
(except HSB)
–1
+1
μA
Input Leakage Current VCC = Max, VSS < VIN < VCC
(for HSB)
–100
+1
μA
–1
+1
μA
35
CE > (VCC – 0.2V). VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
mA
IOZ
Off-State Output
Leakage Current
VIH
Input HIGH Voltage
2.0
VCC +
0.5
V
VIL
Input LOW Voltage
Vss – 0.5
0.8
V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOUT = 4 mA
VCAP
Storage Capacitor
Between VCAP pin and VSS, 5V Rated
VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or WE < VIL
IOUT = –2 mA
2.4
61
V
68
0.4
V
180
μF
Notes
8. Typical values are at 25°C, VCC= VCC (Typ). Not 100% tested.
9. The HSB pin has IOUT = -2 uA for VOH of 2.4V when both active high and low drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
Document Number: 001-54707 Rev. *B
Page 9
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CY14B256LA
Data Retention and Endurance
Parameter
Description
DATAR
Data Retention
NVC
Nonvolatile STORE Operations
Min
Unit
20
Years
1,000
K
Max
Unit
7
pF
7
pF
Capacitance
Parameter[10]
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC (Typ)
Thermal Resistance
Parameter[10]
ΘJA
Description
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
48-SSOP 44-TSOP II
Test conditions follow standard
test methods and procedures for
measuring thermal impedance, in
accordance with EIA/JESD51.
32-SOIC
Unit
37.47
31.11
41.55
°C/W
24.71
5.56
24.43
°C/W
Figure 4. AC Test Loads
577Ω
577Ω
3.0V
3.0V
R1
for tri-state specs
R1
OUTPUT
OUTPUT
30 pF
R2
789Ω
5 pF
R2
789Ω
AC Test Conditions
Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <3 ns
Input and Output Timing Reference Levels .................... 1.5V
Note
10. These parameters are guaranteed by design and are not tested.
Document Number: 001-54707 Rev. *B
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CY14B256LA
AC Switching Characteristics
Parameters
Cypress
Alt
Parameters
Parameters
SRAM Read Cycle
tACS
tACE
[11]
tRC
tRC
Chip Enable Access Time
Read Cycle Time
tAA[12]
tAA
Address Access Time
25
45
ns
tDOE
tOE
Output Enable to Data Valid
12
20
ns
tOHA[12]
25 ns
Description
Min
45 ns
Max
Min
25
25
Max
45
45
Unit
ns
ns
tOH
Output Hold After Address Change
3
3
ns
[10, 13]
tLZ
Chip Enable to Output Active
3
3
ns
tHZCE[10, 13]
tLZCE
tLZOE
tHZ
Chip Disable to Output Inactive
[10, 13]
tOLZ
Output Enable to Output Active
[10, 13]
tOHZ
Output Disable to Output Inactive
tPA
Chip Enable to Power Active
tPS
Chip Disable to Power Standby
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
25
20
20
10
0
20
0
0
tOW
Output Active after End of Write
3
tHZOE
tPU[10]
tPD[10]
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tHZWE[10, 13,14]
tLZWE
[10, 13]
Switching Waveforms
10
0
15
0
10
0
ns
15
0
25
3
ns
ns
45
ns
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
30
30
15
0
30
0
0
10
ns
ns
Figure 5. SRAM Read Cycle #1: Address Controlled [11, 12, 15]
tRC
Address
Address Valid
tAA
Data Output
Previous Data Valid
Output Data Valid
tOHA
Notes
11. WE must be HIGH during SRAM read cycles.
12. Device is continuously selected with CE and OE LOW.
13. Measured ±200 mV from steady state output voltage.
14. If WE is low when CE goes low, the outputs remain in the high impedance state.
15. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-54707 Rev. *B
Page 11
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CY14B256LA
Figure 6. SRAM Read Cycle #2: CE and OE Controlled [11, 15]
Address
Address Valid
tRC
tHZCE
tACE
CE
tAA
tLZCE
tHZOE
tDOE
OE
tLZOE
Data Output
ICC
High Impedance
Output Data Valid
tPU
tPD
Active
Standby
Figure 7. SRAM Write Cycle #1: WE Controlled [14, 15, 16]
tWC
Address
Address Valid
tSCE
tHA
CE
tAW
tPWE
WE
tSA
tHD
tSD
Data Input
Input Data Valid
tLZWE
tHZWE
Data Output
High Impedance
Previous Data
Figure 8. SRAM Write Cycle #2: CE Controlled [14, 15, 16]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tPWE
WE
tSD
Data Input
Data Output
tHD
Input Data Valid
High Impedance
Note
16. CE or WE must be > VIH during address transitions.
Document Number: 001-54707 Rev. *B
Page 12
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CY14B256LA
AutoStore/Power Up RECALL
Parameters
tHRECALL [17]
CY14B256LA
Min
Max
20
Description
Power Up RECALL Duration
tSTORE
[18]
STORE Cycle Duration
tDELAY
[19]
Time Allowed to Complete SRAM Write Cycle
VSWITCH
Low Voltage Trigger Level
tVCCRISE[10]
VCC Rise Time
[10]
VHDIS
tLZHSB[10]
tHHHD[10]
Unit
ms
8
ms
25
ns
2.65
V
150
µs
HSB Output Disable Voltage
1.9
V
HSB To Output Active Time
HSB High Active Time
5
500
µs
ns
Switching Waveforms
Figure 9. AutoStore or Power Up RECALL[20]
VCC
VSWITCH
VHDIS
VVCCRISE
Note
18
tSTORE
tHHHD
Note
tSTORE
Note
tHHHD
HSB OUT
18
21
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
Read & Write
Inhibited
(RWI)
tHRECALL
POWER-UP
RECALL
Read & Write
tHRECALL
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
17. tHRECALL starts from the time VCC rises above VSWITCH.
18. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
19. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
20. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
21. HSB pin is driven high to VCC only by internal 100 kΩ resistor, HSB driver is disabled.
Document Number: 001-54707 Rev. *B
Page 13
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CY14B256LA
Software Controlled STORE/RECALL Cycle
Parameters[22, 23]
25 ns
Description
Min
25
45 ns
Max
Min
45
Max
Unit
tRC
STORE/RECALL Initiation Cycle Time
tSA
Address Setup Time
0
0
ns
tCW
Clock Pulse Width
20
30
ns
tHA
Address Hold Time
0
tRECALL
RECALL Duration
ns
0
200
ns
200
µs
Switching Waveforms
Figure 10. CE and OE Controlled Software STORE/RECALL Cycle[23]
tRC
Address
tRC
Address #1
tSA
Address #6
tCW
tCW
CE
tHA
tSA
tHA
tHA
tHA
OE
tHHHD
HSB (STORE only)
tHZCE
tLZCE
t DELAY
24
Note
tLZHSB
High Impedance
tSTORE/tRECALL
DQ (DATA)
RWI
Figure 11. Autostore Enable / Disable Cycle
Address
tRC
tRC
Address #1
Address #6
tSA
CE
tCW
tCW
tHA
tSA
tHA
tHA
tHA
OE
tLZCE
tHZCE
tSS
24
Note
t DELAY
DQ (DATA)
Notes
22. The software sequence is clocked with CE controlled or OE controlled reads.
23. The six consecutive addresses must be read in the order listed in Table 2 on page 6. WE must be HIGH during all six consecutive cycles.
24. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
Document Number: 001-54707 Rev. *B
Page 14
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CY14B256LA
Hardware STORE Cycle
Parameters
CY14B256LA
Description
Min
tDHSB
HSB To Output Active Time when write latch not set
tPHSB
Hardware STORE Pulse Width
tSS [25, 26]
Soft Sequence Processing Time
Switching Waveforms
Max
Unit
25
ns
100
μs
15
ns
Figure 12. Hardware STORE Cycle[18]
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
tLZHSB
DQ (Data Out)
RWI
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100kOhm resistor,
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
HSB (IN)
HSB (OUT)
tDELAY
tDHSB
tDHSB
RWI
Figure 13. Soft Sequence Processing[25, 26]
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
tSS
Soft Sequence
Command
Address #1
tSS
Address #6
tCW
CE
VCC
Notes
25. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
26. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document Number: 001-54707 Rev. *B
Page 15
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CY14B256LA
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations.
Table 3. Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High-Z
Deselect/Power down
Standby
L
H
L
Data Out (DQ0–DQ7);
Read
Active
L
H
H
High-Z
Output Disabled
Active
L
L
X
Data in (DQ0–DQ7);
Write
Active
Part Numbering Nomenclature
CY 14 B 256 L A-ZS 25 X I T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
I - Industrial (-40 to 85oC)
Pb-Free
Die revision:
Blank - No Rev
A - 1st Rev
Voltage:
B - 3.0V
Package:
ZS - 44 TSOP II
SP - 48 SSOP
SZ - 32 SOIC
Speed:
25 - 25 ns
45 - 45 ns
Data Bus:
L - x8
Density:
256 - 256 Kb
14 - nvSRAM
Cypress
Document Number: 001-54707 Rev. *B
Page 16
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CY14B256LA
Ordering Information
Speed
(ns)
25
45
Ordering Code
Package
Diagram
Package Type
CY14B256LA-ZS25XIT
51-85087
44-pin TSOP II
CY14B256LA-ZS25XI
51-85087
44-pin TSOP II
CY14B256LA-SP25XIT
51-85061
48-pin SSOP
CY14B256LA-SP25XI
51-85061
48-pin SSOP
CY14B256LA-SZ25XIT
51-85127
32-pin SOIC
CY14B256LA-SZ25XI
51-85127
32-pin SOIC
CY14B256LA-ZS45XIT
51-85087
44-pin TSOP II
CY14B256LA-ZS45XI
51-85087
44-pin TSOP II
CY14B256LA-SP45XIT
51-85061
48-pin SSOP
CY14B256LA-SP45XI
51-85061
48-pin SSOP
CY14B256LA-SZ45XIT
51-85127
32-pin SOIC
CY14B256LA-SZ45XI
51-85127
32-pin SOIC
Operating
Range
Industrial
All the above parts are Pb-free.
Document Number: 001-54707 Rev. *B
Page 17
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CY14B256LA
Package Diagrams
Figure 14. 44-Pin TSOP II (51-85087)
51-85087 *B
Document Number: 001-54707 Rev. *B
Page 18
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CY14B256LA
Package Diagrams
(continued)
Figure 15. 48-Pin SSOP (51-85061)
51-85061 *C
Document Number: 001-54707 Rev. *B
Page 19
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CY14B256LA
Package Diagrams
(continued)
Figure 16. 32-Pin SOIC (51-85127)
PIN 1 ID
16
1
REFERENCE JEDEC MO-119
0.405[10.287]
0.419[10.642]
17
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
0.292[7.416]
0.299[7.594]
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
32
SEATING PLANE
0.810[20.574]
0.822[20.878]
0.090[2.286]
0.100[2.540]
0.004[0.101]
0.050[1.270]
TYP.
0.026[0.660]
0.032[0.812]
0.014[0.355]
0.020[0.508]
Document Number: 001-54707 Rev. *B
0.004[0.101]
0.0100[0.254]
0.021[0.533]
0.041[1.041]
0.006[0.152]
0.012[0.304]
51-85127 *B
Page 20
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CY14B256LA
Document History Page
Document Title: CY14B256LA 256 Kbit (32K x 8) nvSRAM
Document Number: 001- 54707
Orig. of
Submission
Rev. ECN No.
Description of Change
Change
Date
**
2746918 GVCH/AESA
07/31/2009
New Data Sheet
*A
2772059 GVCH/PYRS
09/30/2009
Updated Software STORE, RECALL and Autostore Enable, Disable soft sequence
*B
2829117
GVCH
12/16/09
Updated STORE cycles to QuantumTrap from 200K to 1 Million
Updtaed 48-pin SSOP package diagram
Added Contents. Moved to external web
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life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54707 Rev. *B
Revised December 08, 2009
Page 21
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