NBSG72A 2.5 V/3.3 V SiGe Differential 2 x 2 Crosspoint Switch with Output Level Select The NBSG72A is a high-bandwidth fully differential 2 × 2 crosspoint switch with Output Level Select (OLS) capabilities. This is a part of the GigaCommt family of high performance Silicon Germanium products. The device is housed in a low profile 3 × 3 mm 16-pin QFN package. Differential inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to program the peak-to-peak output amplitude between 0 mV and 800 mV in five discrete steps. The SELECT inputs are single-ended and can be driven with either LVECL or LVCMOS/LVTTL input levels. http://onsemi.com 1 QFN−16 MN SUFFIX CASE 485G MARKING DIAGRAM* ÇÇÇ ÇÇÇ 16 Features • • • • • • • 1 Maximum Input Clock Frequency > 7 GHz Typical Maximum Input Data Rate > 7 Gb/s Typical SG 72A ALYWG G 200 ps Typical Propagation Delay (OLS = FLOAT) 55/45 ps Typical Rise/Fall Times (OLS = FLOAT) Selectable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Selectable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V Selectable Output Levels (0 mV, 200 mV, 400 mV, 600 mV or 800 mV Peak-to-Peak Output) 50 W Internal Input Termination Resistors • • Single-Ended LVECL or LVCMOS/LVTTL Select Inputs • (SELA, SELB) These are Pb-Free Devices © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 8 A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. 1 Publication Order Number: NBSG72A/D NBSG72A Exposed Pad (EP) VTD0 1 D0 2 VCC Q0 Q0 OLS 16 15 14 13 12 VCC 11 Q1 NBSG72A D0 3 10 Q1 SELA 4 9 5 6 7 VEE D1 D1 SELB 8 VTD1 Figure 1. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin No. Name I/O 1 VTD0 − 2 D0 LVDS, CML, ECL, LVTTL, LVCMOS Input Inverted Differential Input 0. 3 D0 LVDS, CML, ECL, LVTTL, LVCMOS Input Noninverted Differential Input 0. 4 SELA LVECL, LVCMOS Input Select Logic Input A. Internal 75 kW Pulldown to VEE. ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ 5 VEE − 6 D1 LVDS, CML, ECL, LVTTL, LVCMOS Input 7 D1 LVDS, CML, ECL, LVTTL, LVCMOS Input 8 VTD1 − 9 SELB LVECL, LVCMOS Input 10 Q1 RSECL Output 11 Q1 RSECL Output 12 VCC − 13 OLS (Note 2) Input 14 Q0 RSECL Output 15 Q0 RSECL Output 16 VCC − − EP − Description Common Internal 50 W Termination Pin for D0 and D0 Input. See Table 4. (Note 1) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Negative Supply. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Inverted Differential Input 1. Noninverted Differential Input 1. Common Internal 50 W Termination Pin for D1 and D1 Input. See Table 4. (Note 1) Select Logic Input B. Internal 75 kW Pulldown to VEE. Noninverted Differential Output. Inverted Differential Output. Positive Supply. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Input Pin for Output Level Select (OLS) See Table 3. Noninverted Differential Output Typically Terminated with 50 W Resistor to VTT = VCC − 2.0 V. Inverted Differential Output Typically Terminated with 50 W Resistor to VTT = VCC − 2.0 V. Positive Supply. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die but may be electrically and thermally connected to VEE on the PC board. 1. In the differential configuration when the input termination pins (VTD0, VTD1) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation. 2. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2 kW resistor should be connected from OLS pin to VEE. http://onsemi.com 2 NBSG72A VTD0 50 W D0 50 W 2 2 D0 2 D1 2 Q0 2 Q0 D1 + 50 W VTD1 50 W VCC 2 SELA Table 2. TRUTH TABLE VEE 2 75 kW 2 Q1 2 Q1 SELA SELB Q0 Q1 LOW LOW D0 D0 HIGH LOW D1 D0 LOW HIGH D0 D1 HIGH HIGH D1 D1 2 SELB 75 kW OLS Figure 2. Logic/Block Diagram Table 3. OUTPUT LEVEL SELECT (OLS) OLS Output Amplitude (VOUTPP) OLS Sensitivity VCC 800 mV OLS − 75 mV VCC − 0.4 V 200 mV OLS ± 150 mV VCC − 0.8 V 600 mV OLS ± 100 mV VCC − 1.2 V 0 OLS ± 75 mV VEE (Note 3) 400 mV OLS ± 100 mV FLOAT 600 mV N/A 3. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. Table 4. INTERFACING OPTIONS Interfacing Options Connections CML Connect VTD0 and VTD1 to VCC LVDS VTD0 and VTD1 Should Be Left Floating. AC−COUPLED RSECL, PECL, NECL LVCMOS / LVTTL Bias VTD0 and VTD1 Inputs within Common Mode Range (VIHCMR) Standard ECL Termination Techniques The external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS Inputs. http://onsemi.com 3 NBSG72A Table 5. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (SELA, SELB) 75 kW ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 50 V > 1 kV Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Moisture Sensitivity (Note 4) Flammability Rating Level 1 Transistor Count 436 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 4. For additional information, see Application Note AND8003/D. Table 6. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Units VCC Positive Power Supply VEE = 0 V 3.6 V VEE Negative Power Supply VCC = 0 V −3.6 V Positive Input Negative Input VEE = 0 V VCC = 0 V 3.6 −3.6 V VEE − VCC ≥ 2.8 V VEE − VCC < 2.8 V 2.8 |VCC − VEE| V Continuous Surge 25 50 mA Static Surge 45 80 mA mA −40 to +85 °C VI VINPP Differential Input Voltage |DX − DX| VI ≤ VCC VI ≥ VEE Iout Output Current IIN Input Current Through RT (50 W Resistor) TA Operating Temperature Range Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) (Note 5) 0 lfpm 500 lfpm 42 35 °C/W qJC Thermal Resistance (Junction-to-Case) (Note 5) 4 °C/W Tsol Wave Solder < 3 sec @ 260°C 265 °C Pb-Free Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 5. JEDEC standard multilayer board − 1S2P (1 signal, 2 power). http://onsemi.com 4 NBSG72A Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT (VCC = 2.5 V; VEE = 0 V) (Note 6) −40°C Symbol 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 40 55 65 40 55 65 40 55 65 mA 1460 1510 1560 1490 1540 1590 1515 1565 1615 mV (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) 555 1235 775 1455 1005 705 1295 895 1505 1095 855 1385 1015 1585 1215 595 1270 810 1490 1040 745 1330 930 1540 1130 895 1420 1050 1620 1250 625 1295 840 1510 1065 775 1355 960 1560 1155 925 1445 1080 1640 1275 Output Voltage Amplitude (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) 670 125 510 0 325 800 215 615 5 415 660 120 505 0 320 795 210 610 0 410 655 120 500 0 320 790 210 605 0 410 Characteristic POWER SUPPLY CURRENT IEE Negative Power Supply Current PECL OUTPUTS (Note 7) VOH Output HIGH Voltage VOL Output LOW Voltage VOUTPP mV mV DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 12 & 14) (Note 8) VIH Input HIGH Voltage D0, inv-D0, D1, inv-D1, SELA, SELB 1200 VCC 1200 VCC 1200 VCC mV VIL Input LOW Voltage D0, inv-D0, D1, inv-D1, SELA, SELB 0 VIH − 150 0 VIH − 150 0 VIH − 150 mV Vth Input Threshold Reference Voltage Range (Note 9) 950 VCC – 75 950 VCC – 75 950 VCC – 75 mV Single-Ended Input Voltage (VIH – VIL) 150 2600 150 2600 150 260 mV VISE DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 13 & 15) (Note 10) VIHD Differential Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VILD Differential Input LOW Voltage 0 VIHD − 75 0 VIHD − 75 0 VIHD − 75 mV VID Differential Input Voltage (VIHD – VILD) 75 2600 75 2600 75 2600 mV 1200 2500 1200 2500 1200 2500 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 11) (Figure 16) IIH Input HIGH Current (@VIH) 35 100 35 100 35 100 mA IIL Input LOW Current (@VIL) 20 100 20 100 20 100 mA 50 55 50 55 50 55 W TERMINATION RESISTORS RTIN Internal Input Termination Resistor 45 45 45 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC. 7. All outputs loaded with 50 W to VCC − 2.0 V. 8. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 9. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2. 10. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 NBSG72A Table 8. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT (VCC = 3.3 V; VEE = 0 V) (Note 12) −40°C Symbol 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 40 55 65 40 55 65 40 55 65 mA 2260 2310 2360 2290 2340 2390 2315 2365 2415 mV (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) **(OLS = VEE) 1320 2030 1550 2260 1785 1470 2090 1670 2310 1875 1620 2180 1790 2390 1995 1360 2065 1585 2290 1820 1510 2125 1705 2340 2030 1660 2215 1825 2420 2030 1390 2090 1615 2315 1850 1540 2150 1735 2365 1940 1690 2240 1855 2445 2060 Output Voltage Amplitude (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) **(OLS = VEE) 705 130 535 0 345 815 220 640 0 435 695 125 530 0 340 805 215 635 0 430 590 125 525 0 335 800 215 630 0 425 Characteristic POWER SUPPLY CURRENT IEE Negative Power Supply Current PECL OUTPUTS (Note 13) VOH Output HIGH Voltage VOL Output LOW Voltage VOUTPP mV mV DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 12 & 14) (Note 14) VIH Input HIGH Voltage D0, inv-D0, D1, inv-D1, SELA, SELB 1200 VCC 1200 VCC 1200 VCC mV VIL Input LOW Voltage D0, inv-D0, D1, inv-D1, SELA, SELB 0 VIH − 150 0 VIH − 150 0 VIH − 150 mV Vth Input Threshold Reference Voltage Range (Note 15) 950 VCC – 75 950 VCC – 75 950 VCC – 75 mV Single-Ended Input Voltage (VIH – VIL) 150 2600 150 2600 150 2600 mV VISE DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 13 & 15) (Note 16) VIHD Differential Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VILD Differential Input LOW Voltage 0 VIHD − 75 0 VIHD − 75 0 VIHD − 75 mV VID Differential Input Voltage (VIHD – VILD) 75 2600 75 2600 75 2600 mV 1200 3300 1200 3300 1200 3300 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 17) (Figure 16) IIH Input HIGH Current (@VIH) 35 100 35 100 35 100 mA IIL Input LOW Current (@VIL) 20 100 20 100 20 100 mA 50 55 50 55 50 55 W TERMINATION RESISTORS RTIN Internal Input Termination Resistor 45 45 45 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. **When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. 12. Input and output parameters vary 1:1 with VCC. 13. All outputs loaded with 50 W to VCC − 2.0 V. 14. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 15. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2. 16. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 6 NBSG72A Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT (VCC = 0 V; VEE = −3.465 V to −2.375 V) (Note 18) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 40 55 65 40 55 65 40 55 65 mA −1040 −990 −940 −1010 −960 −910 −985 −935 −885 mV POWER SUPPLY CURRENT IEE Negative Power Supply Current NECL OUTPUTS (Note 19) VOH Output HIGH Voltage VOL Output LOW Voltage −3.465 V ≤ VEE ≤ −3.0 V (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) **(OLS = VEE) −3.0 V < VEE ≤ −2.375 V (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) VOUTPP mV −1980 −1270 −1750 −1040 −1515 −1830 −1210 −1630 −990 −1425 −1680 −1120 −1510 −910 −1305 −1940 −1235 −1715 −1010 −1480 −1790 −1175 −1595 −960 −1390 −1640 −1085 −1475 −880 −1270 −1910 −1210 −1685 −985 −1450 −1760 −1150 −1565 −935 −1360 −1610 −1060 −1445 −855 −1240 −1945 −1265 −1725 −1045 −1495 −1795 −1205 −1605 −995 −1405 −1645 −1115 −1485 −915 −1285 −1905 −1230 −1690 −1010 −1460 −1755 −1170 −1570 −960 −1370 −1605 −1080 −1450 −880 −1250 −1875 −1205 −1660 −900 −1435 −1725 −1145 −1540 −940 −1345 −1575 −1055 −1420 −860 −1225 Output Voltage Amplitude −3.465 V ≤ VEE ≤ −3.0 V (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) **(OLS = VEE) −3.0 V < VEE ≤ −2.375 V (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) (OLS = VEE) mV 705 130 535 0 345 815 220 640 0 435 695 125 530 0 340 805 215 635 0 430 690 125 525 0 335 800 215 630 0 425 670 125 510 0 325 800 215 615 5 415 660 120 505 0 320 795 210 610 0 410 655 120 500 0 320 790 210 605 5 410 DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 12 & 14) (Note 20) VIH Input HIGH Voltage (Single-Ended) D0, inv-D0, D1, inv-D1, SELA, SELB VEE + 1200 VCC VEE + 1200 VCC VEE + 1200 VCC mV VIL Input LOW Voltage (Single-Ended) D0, inv-D0, D1, inv-D1, SELA, SELB VEE VIH − 150 VEE VIH − 150 VEE VIH − 150 mV Vth Input Threshold Reference Voltage Range (Note 21) VEE + 950 VCC – 75 VEE + 950 VCC – 75 VEE + 950 VCC – 75 mV 150 2600 150 2600 150 260 mV VISE Single-Ended Input Voltage (VIH – VIL) DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 13 & 15) (Note 22) VIHD Differential Input HIGH Voltage VEE + 1200 VCC VEE + 1200 VCC VEE + 1200 VCC mV VILD Differential Input LOW Voltage VEE VIHD − 75 VEE VIHD − 75 VEE VIHD − 75 mV VID Differential Input Voltage (VIHD – VILD) 75 2600 75 2600 75 2600 mV VEE + 1200 0.0 VEE + 1200 0.0 VEE + 1200 0.0 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 23) (Figure 16) IIH Input HIGH Current (@VIH) 35 1000 35 1000 35 100 mA IIL Input LOW Current (@VIL) 20 100 20 100 20 1000 mA http://onsemi.com 7 NBSG72A Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT (continued) (VCC = 0 V; VEE = −3.465 V to −2.375 V) (Note 18) −40°C Symbol Characteristic Min 25°C Typ Max Min 85°C Typ Max 900 300 100 −300 300 100 5 −100 Min Typ Max 900 300 100 −300 300 100 5 −100 Unit DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 13 & 15) (Note 22) IOLS OLS Input Current (see Figure 10) (OLS = VCC) (OLS = VCC − 0.4 V) (OLS = VCC − 0.8 V, OLS = FLOAT) (OLS = VCC − 1.2 V) −3.465 V ≤ VEE ≤ −3.0 V *(OLS = VEE) −3.0 V < VEE ≤ −2.375 V (OLS = VEE) mA −300 300 100 5 −100 900 300 100 −1500 −600 −1500 −600 −1500 −600 −1000 −400 −1000 −400 −1000 −400 45 50 45 50 45 50 TERMINATION RESISTORS RTIN Internal Input Termination Resistor 55 55 55 W Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *Typicals used for testing purposes. **When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. 18. Input and output parameters vary 1:1 with VCC. 19. All outputs loaded with 50 W to VCC − 2.0 V. 20. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 21. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2. 22. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously. 23. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 8 NBSG72A Table 10. AC CHARACTERISTICS (VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V) (Note 24) −40°C Symbol VOUTPP tPLH tPHL Min Typ fin < 5 GHz fin v 7 GHz 400 200 590 250 Propagation Delay to Output Differential D0, D1 → Q0, Q1 SELA, SELB → Q0, Q1 170 190 205 265 Propagation Delay to Output Differential D0, D1 → Q0, Q1 SELA, SELB → Q0, Q1 170 150 Characteristic Output Voltage Amplitude tSKEW Duty Cycle Skew (Note 25) Within-Device Skew Device-to-Device Skew tJITTER RMS Random Clock Jitter (Note 26) v 1 GHz OLS = VCC v 5 GHz OLS = VCC v 6.5 GHz OLS = VCC v 1 GHz OLS = VCC − 400 mV v 5 GHz OLS = VCC − 400 mV v 6.5 GHz OLS = VCC − 400 mV v 1 GHz OLS = VCC − 800 mV v 5 GHz OLS = VCC − 800 mV v 6.5 GHz OLS = VCC − 800 mV v 1 GHz OLS = VEE v 5 GHz OLS = VEE v 6.5 GHz OLS = VEE Peak-to-Peak Data Dependent Jitter (Note 27) fin v 7 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 28) Output Rise/Fall Times (20% − 80%) @ 1 GHz (Q0, Q1) tr tf 25°C Max Min Typ 450 180 590 250 255 350 170 190 205 265 205 215 255 270 170 150 5.0 5.0 15 85°C Max Min Typ Max 440 130 590 250 255 350 170 190 210 265 260 350 205 215 255 270 170 150 210 215 260 270 25 25 50 5.0 5.0 15 25 25 50 5.0 5.0 15 25 25 50 0.16 0.14 0.21 0.23 0.18 0.2 0.17 0.14 0.2 0.18 0.16 0.18 0.3 0.4 0.5 0.4 0.5 0.5 0.3 0.4 0.5 0.3 0.6 0.5 0.17 0.16 0.31 0.23 0.19 0.25 0.18 0.16 0.27 0.19 0.17 0.24 0.3 0.4 0.7 0.4 0.5 0.6 0.3 0.3 0.7 0.3 0.4 0.6 0.18 0.19 0.44 0.25 0.23 0.32 0.19 0.2 0.38 0.2 0.2 0.34 0.4 0.4 0.9 0.4 0.5 0.7 0.3 0.3 0.9 0.3 0.4 0.8 12 18 12 18 12 18 Unit mV ps ps ps ps 75 2600 75 70 55 40 30 2600 75 70 55 40 30 2600 mV ps 40 30 55 45 55 45 55 45 70 55 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 24. Measured using a 75 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. OLS = FLOAT. Input edge rates 40 ps (20% − 80%). 25. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform. 26. Additive RMS jitter with 50% Duty Cycle clock signal. 27. Additive Peak-to-Peak data dependent jitter with NRZ PRBS 231−1 data at 7 Gb/s. 28. Input Voltage Swing is a single-ended measurement operating in differential mode. VINPP (max) cannot exceed VCC − VEE. http://onsemi.com 9 NBSG72A OUTPUT VOLTAGE AMPLITUDE (mV) 900 OLS = VCC 800 700 OLS = VCC − 0.8 V = FLOAT 600 500 *OLS = VEE 400 300 OLS = VCC − 0.4 V 200 100 0 1 2 3 4 5 6 7 8 9 INPUT FREQUENCY (GHz) Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Clock Frequency (fin) @ Ambient Temperature (Typical) *When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. Input Signal D0 Q0 D0 Selected Q0 Output Signal Path 20 0 dB 0 Non−Driven Input D1 Q1 D1 Measured Q1 Non−Driven Output (VNA) SELA Logic Low SELB Yscale = 10 dB/div NBSG72A Q Q Logic High −80 1 Xscale = 1 GHz/div 8 Figure 4. Channel-to-Channel Crosstalk Isolation at Ambient Temperature (D0 to Q0 Signal Path Selected; SelA = Low, SelB = High) D0 Non−Driven Input NBSG72A D0 Q0 20 Selected Q0 Output 0 Q1 D1 Input Signal SELA Logic High SELB 0 dB Yscale = 10 dB/div D1 Measured Non−Driven Output Q1 (VNA) Q Q Logic Low −80 1 Xscale = 1 GHz/div Figure 5. Channel-to-Channel Crosstalk Isolation at Ambient Temperature (D1 to Q0 Signal Path Selected; SelA = High, SelB = Low) http://onsemi.com 10 8 NBSG72A Signal Path D1 Input Signal D1 20 Q0 Non−Driven Q0 Selected Output Q1 NBSG72A SELA Logic Low 0dB 0 Yscale = 10 dB/div D0 Non−Driven Input D0 Measured Output Q1 (VNA) SELB Q Q Logic Low −80 1 Xscale = 1 GHz/div 8 Figure 6. Channel-to-Channel Crosstalk Isolation at Ambient Temperature (D0 to Q0 and Q1 Signal Path Selected; SelA = Low, SelB = Low) D0 Input Signal NBSG72A Q0 20 Measured Output Q0 (VNA) D0 0dB D1 Non−Driven Input D1 Yscale = 10 dB/div 0 Q1 Signal Path SELA Logic High Non−Driven Q1 Selected Output SELB Q Q Logic High −80 1 Xscale = 1 GHz/div Figure 7. Channel-to-Channel Crosstalk Isolation at Ambient Temperature (D1 to Q0 and Q1 Signal Path Selected; SelA = High, SelB = High) http://onsemi.com 11 8 NBSG72A Y = 75 mv/div Total System Jitter = 17.2 ps Input Generator Jitter = 10 ps Device Jitter = 6.8 ps X = 60 ps/div Y = 80 mV/div Figure 8. Eye Diagram at 3.2 Gb/s (VCC − VEE = 3.3 V, OLS = FLOAT @ 255C with input pattern of 231−1 PRBS, 5000 Waveforms) Total System Jitter = 17.2 ps Input Generator Jitter = 10 ps Device Jitter = 7.2 ps X = 21 ps/div Figure 9. Eye Diagram at 7 Gb/s/s (VCC − VEE = 3.3 V, OLS = FLOAT @ 255C with input pattern of 231−1 PRBS, 5000 Waveforms) http://onsemi.com 12 NBSG72A 300 200 100 IOLS (mA) 0 −100 −200 −300 −400 −500 −600 −700 VCC VCC − 400 VCC − 800 VCC − 1200 VEE VOLS (mV) Figure 10. Typical OLS Input Current vs. OLS Input Voltage (VCC − VEE = 3.3 V @ 255C) 1000 VCC − 75 VOUTPP (mV) 800 VCC − 700 VCC − 900 600 VEE + 100 400 VCC − 250 VCC − 550 200 VCC − 1125 VCC − 1275 0 VCC VCC − 400 VCC − 800 VCC − 1200 OLS (mV) Figure 11. OLS Operating Area http://onsemi.com 13 VEE NBSG72A IN VIH Vth IN VIL IN IN Vth Figure 12. Differential Input Driven Single-Ended VCC Vthmax Figure 13. Differential Inputs Driven Differentially VIHmax VILmax Vth IN Vthmin VEE VIH Vth VIL IN IN VID = |VIHD(IN) − VILD(IN)| VIHD VILD VIHmin VILmin Figure 14. Vth Diagram Figure 15. Differential Inputs Driven Differentially VCC VIHDmax VIHCMRmax VILDmax VIHCMR VIHDtyp VID = VIHD − VILD IN IN VILDtyp VIHDmin VIHCMRmin VILDmin VEE Figure 16. VIHCMR Diagram http://onsemi.com 14 NBSG72A D VINPP = VIH(D) − VIL(D) D Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 17. AC Reference Measurement Zo = 50 W Q D Receiver Device Driver Device Zo = 50 W Q D 50 W 50 W VTT VTT = VCC − 2.0 V Figure 18. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† NBSG72AMNG QFN-16 (Pb-Free / Halide-Free) 123 Units / Tube NBSG72AMNR2G QFN-16 (Pb-Free / Halide-Free) 3000 / Tape & Reel Device Board Description NBSG72AMNEVB NBSG72AMN Evaluation Board †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPICE Modeling Kit AN1504/D − Metastability and the ECLinPSt Family AN1568/D − Interfacing between LVDC and ECL AN1672/D − The ECL Translator Guide http://onsemi.com 15 NBSG72A PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE F D ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ PIN 1 LOCATION 0.10 C 2X L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E ÉÉÉ ÉÉÉ TOP VIEW DETAIL B 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L EXPOSED Cu 0.10 C 2X A B (A3) ÉÉ ÉÉ ÇÇ MOLD CMPD A3 A1 DETAIL B A 0.05 C ALTERNATE CONSTRUCTIONS NOTE 4 A1 SIDE VIEW C SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.03 0.05 0.20 REF 0.18 0.24 0.30 3.00 BSC 1.65 1.75 1.85 3.00 BSC 1.65 1.75 1.85 0.50 BSC 0.18 TYP 0.30 0.40 0.50 0.00 0.08 0.15 RECOMMENDED SOLDERING FOOTPRINT* 16X 0.10 C A B 16X L DETAIL A 0.58 PACKAGE OUTLINE D2 8 4 1 9 2X E2 16X 2X 1.84 3.30 K 1 16X 16 e e/2 BOTTOM VIEW 0.30 16X b 0.50 PITCH 0.10 C A B 0.05 C NOTE 3 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. GigaComm is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 16 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NBSG72A/D