Sharp LH28F008SCB-L12 Flash memory 8m (1mb ã 8) Datasheet

PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F008SCT-L85
Flash Memory
8M (1MB × 8)
(Model No.: LHF08CH1)
Spec No.: EL104027C
Issue Date: April 24, 2000
sharp
LHF08CH1
●Handle this document carefully for it contains material protected by international
copyright law. Any reproduction, full or in part, of this material is prohibited without the
express written permission of the company.
●When using the products covered herein, please observe the conditions written herein
and the precautions outlined in the following paragraphs. In no event shall the company
be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.
(1) The products covered herein are designed and manufactured for the following
application areas. When using the products covered herein for the equipment listed
in Paragraph (2), even for the following application areas, be sure to observe the
precautions given in Paragraph (2). Never use the products for the equipment listed
in Paragraph (3).
•Office electronics
•Instrumentation and measuring equipment
•Machine tools
•Audiovisual equipment
•Home appliance
•Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative of the
company and then accept responsibility for incorporating into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
safety of the equipment and the overall system.
•Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
•Mainframe computers
•Traffic control systems
•Gas leak detectors and automatic cutoff devices
•Rescue and security equipment
•Other safety devices and safety equipment,etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality, reliability, or accuracy.
•Aerospace equipment
•Communications equipment for trunk lines
•Control equipment for the nuclear power industry
•Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above
three Paragraphs to a sales representative of the company.
●Please direct all queries regarding the products covered herein to a sales representative
of the company.
Rev. 1.3
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LHF08CH1
1
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION ................................................... 3
5.0 DESIGN CONSIDERATIONS ..............................23
1.1 New Features...................................................... 3
5.1 Three-Line Output Control .................................23
1.2 Product Overview ................................................ 3
5.2 RY/BY# and Block Erase, Byte Write and Lock-Bit
2.0 PRINCIPLES OF OPERATION ............................. 7
5.3 Power Supply Decoupling ..................................23
2.1 Data Protection ................................................... 7
5.4 VPP Trace on Printed Circuit Boards ..................23
3.0 BUS OPERATION................................................. 8
5.6 Power-Up/Down Protection................................24
3.1 Read ................................................................... 8
5.7 Power Dissipation ..............................................24
Configuration Polling...........................................23
5.5 VCC, VPP, RP# Transitions.................................24
3.2 Output Disable .................................................... 8
3.3 Standby ............................................................... 8
6.0 ELECTRICAL SPECIFICATIONS........................25
3.4 Deep Power-Down .............................................. 8
6.1 Absolute Maximum Ratings ...............................25
3.5 Read Identifier Codes Operation ......................... 9
6.2 Operating Conditions .........................................25
3.6 Write.................................................................... 9
6.2.1 Capacitance .................................................25
6.2.2 AC Input/Output Test Conditions ..................26
4.0 COMMAND DEFINITIONS .................................... 9
6.2.3 DC Characteristics........................................27
4.1 Read Array Command....................................... 12
6.2.4 AC Characteristics - Read-Only Operations .29
4.2 Read Identifier Codes Command ...................... 12
6.2.5 AC Characteristics - Write Operations..........32
4.3 Read Status Register Command....................... 12
6.2.6 Alternative CE#-Controlled Writes ................35
4.4 Clear Status Register Command....................... 12
6.2.7 Reset Operations .........................................38
4.5 Block Erase Command...................................... 12
6.2.8 Block Erase, Byte Write and Lock-Bit
4.6 Byte Write Command ........................................ 13
Configuration Performance...........................39
4.7 Block Erase Suspend Command....................... 13
4.8 Byte Write Suspend Command ......................... 14
7.0 ADDITIONAL INFORMATION .............................40
4.9 Set Block and Master Lock-Bit Commands ....... 14
7.1 Ordering Information ..........................................40
4.10 Clear Block Lock-Bits Command..................... 15
8.0 PACKAGE AND PACKING SPECIFICATIONS ..41
Rev. 1.3
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LHF08CH1
2
LH28F008SCT-L85
8M-BIT (1MB x 8)
SmartVoltage Flash MEMORY
■ SmartVoltage Technology
2.7V(Read-Only), 3.3V or 5V VCC
3.3V, 5V or 12V VPP
■ Automated Byte Write and Block Erase
Command User Interface
Status Register
■ High-Performance Read Access Time
85ns(5V±0.25V), 90ns(5V±0.5V),
120ns(3.3V±0.3V), 150ns(2.7V-3.6V)
■ Enhanced Automated Suspend Options
Byte Write Suspend to Read
Block Erase Suspend to Byte Write
Block Erase Suspend to Read
■ Operating Temperature
0°C to +70°C
■ High-Density Symmetrically-Blocked
Architecture
Sixteen 64K-byte Erasable Blocks
■ Extended Cycling Capability
100,000 Block Erase Cycles
1.6 Million Block Erase Cycles/Chip
■ SRAM-Compatible Write Interface
■ Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
■ Industry-Standard Packaging
40-Lead TSOP
■ Enhanced Data Protection Features
Absolute Protection with VPP=GND
Flexible Block Locking
Block Erase/Byte Write Lockout
during Power Transitions
■ CMOS Process
(P-type silicon substrate)
■ ETOXTM* Nonvolatile Flash Technology
■ Not designed or rated as radiation
hardened
SHARP’s LH28F008SCT-L85 Flash memory with SmartVoltage technology is a high-density, low-cost, nonvolatile,
read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory
cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F008SCT-L85 offers three levels of protection: absolute protection with VPP at
GND, selective hardware block locking, or flexible software block locking. These alternatives give designers
ultimate control of their code security needs.
The LH28F008SCT-L85 is manufactured on SHARP’s 0.38µm ETOXTM process technology. It come in
industry-standard package: the 40-lead TSOP, ideal for board constrained applications. Based on the 28F008SA
architecture, the LH28F008SCT-L85 enables quick and easy upgrades for designs demanding the state-of-the-art.
*ETOX is a trademark of Intel Corporation.
Rev. 1.3
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LHF08CH1
1 INTRODUCTION
This
datasheet
contains
LH28F008SCT-L85
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F008SCT-L85
Flash memory documentation also includes
application notes and design tools which are
referenced in Section 7.
1.1 New Features
The LH28F008SCT-L85 SmartVoltage Flash memory
maintains backwards-compatibility with SHARP’s
28F008SA. Key enhancements over the 28F008SA
include:
•SmartVoltage Technology
•Enhanced Suspend Capabilities
•In-System Block Locking
Both devices share a compatible pinout, status
register, and software command set. These
similarities enable a clean upgrade from the
28F008SA to LH28F008SCT-L85. When upgrading, it
is important to note the following differences:
•Because of new feature support, the two devices
have different device codes. This allows for
software optimization.
•VPPLK has been lowered from 6.5V to 1.5V to
support 3.3V and 5V block erase, byte write, and
lock-bit configuration operations. The VPP voltage
transitions to GND is recommended for designs
that switch VPP off during read operation.
•To take advantage of SmartVoltage technology,
allow VPP connection to 3.3V or 5V.
1.2 Product Overview
The LH28F008SCT-L85 is a high-performance 8M-bit
SmartVoltage Flash memory organized as 1M-byte of
8 bits. The 1M-byte of data is arranged in sixteen
64K-byte blocks which are individually erasable,
lockable, and unlockable in-system. The memory
map is shown in Figure 3.
3
SmartVoltage technology provides a choice of VCC
and VPP combinations, as shown in Table 1, to meet
system performance and power expectations. 2.7V
VCC consumes approximately one-fifth the power of
5V VCC. But, 5V VCC provides the highest read
performance. VPP at 3.3V and 5V eliminates the need
for a separate 12V converter, while VPP=12V
maximizes block erase and byte write performance.
In addition to flexible erase and program voltages,
the dedicated VPP pin gives complete data protection
when VPP≤VPPLK.
Table 1. VCC and VPP Voltage Combinations
Offered by SmartVoltage Technology
VCC Voltage
VPP Voltage
2.7V(1)

3.3V
3.3V, 5V, 12V
5V
5V, 12V
NOTE:
1. Block erase, byte write and lock-bit configuration
operations with VCC<3.0V are not supported.
Internal
VCC and VPP detection Circuitry
automatically configures the device for optimized
read and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, byte write, and lock-bit configuration
operations.
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.3s (5V VCC, 12V
VPP) independent of other blocks. Each block can be
independently erased 100,000 times (1.6 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
Writing memory data is performed in byte increments
typically within 6µs (5V VCC, 12V VPP). Byte write
suspend mode enables the system to read data or
execute code from any other flash memory array
location.
Rev. 1.3
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LHF08CH1
Individual block locking uses a combination of bits,
sixteen block lock-bits and a master lock-bit, to lock
and unlock blocks. Block lock-bits gate block erase
and byte write operations, while the master lock-bit
gates
block
lock-bit
modification.
Lock-bit
configuration operations (Set Block Lock-Bit, Set
Master Lock-Bit, and Clear Block Lock-Bits
commands) set and cleared lock-bits.
The status register indicates when the WSM’s block
erase, byte write, or lock-bit configuration operation is
finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal of
status (versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using RY/BY# minimizes
both CPU overhead and system power consumption.
When low, RY/BY# indicates that the WSM is
performing a block erase, byte write, or lock-bit
configuration. RY/BY#-high indicates that the WSM is
ready for a new command, block erase is suspended
(and byte write is inactive), byte write is suspended,
or the device is in deep power-down mode.
4
The access time is 85ns (tAVQV) over the commercial
temperature range (0°C to +70°C) and VCC supply
voltage range of 4.75V-5.25V. At lower VCC voltages,
the access times are 90ns (4.5V-5.5V), 120ns
(3.0V-3.6V) and 150ns (2.7V-3.6V).
The Automatic Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical ICCR current is 1 mA at 5V VCC.
When CE# and RP# pins are at VCC, the ICC CMOS
standby mode is enabled. When the RP# pin is at
GND, deep power-down mode is enabled which
minimizes power consumption and provides write
protection during reset. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are recognized.
With RP# at GND, the WSM is reset and the status
register is cleared.
The device is available in 40-lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in
Figure 2.
Rev. 1.3
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LHF08CH1
5
DQ0-DQ7
Input
Buffer
I/O Logic
Identifier
Register
Status
Register
Data
Register
Output
Multiplexer
Output
Buffer
VCC
CE#
WE#
Command
Register
OE#
RP#
Data
Comparator
A0-A19
Input
Buffer
Y
Decoder
Address
Latch
X
Decoder
RY/BY#
Y Gating
Write State
Machine
Program/Erase
Voltage Switch
16
64KByte
Blocks
VPP
VCC
GND
Address
Counter
Figure 1. Block Diagram
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
VPP
RP#
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-LEAD TSOP
STANDARD PINOUT
10mm x 20mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
GND
GND
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
Figure 2. TSOP 40-Lead Pinout
Rev. 1.3
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LHF08CH1
Symbol
Type
A0-A19
INPUT
DQ0-DQ7
INPUT/
OUTPUT
CE#
INPUT
RP#
INPUT
OE#
INPUT
WE#
INPUT
RY/BY#
OUTPUT
VPP
SUPPLY
VCC
SUPPLY
GND
NC
SUPPLY
6
Table 2. Pin Descriptions
Name and Function
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins float
to high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP# at VHH enables setting of the
master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP#=VHH overrides block lock-bits thereby enabling block erase and byte write
operations to locked memory blocks. Block erase, byte write, or lock-bit configuration
with VIH<RP#<VHH produce spurious results and should not be attempted.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and byte write is inactive, byte write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.
BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY: For
erasing array blocks, writing bytes, or configuring lock-bits. With VPP≤VPPLK, memory
contents cannot be altered. Block erase, byte write, and lock-bit configuration with an
invalid VPP (see DC Characteristics) produce spurious results and should not be
attempted.
DEVICE POWER SUPPLY: Internal detection configures the device for 2.7V, 3.3V or 5V
operation. To switch from one voltage to another, ramp VCC down to GND and then ramp
VCC to the new voltage. Do not float any power pins. With VCC≤VLKO, all write attempts
to the flash memory are inhibited. Device operations at invalid VCC voltage (see DC
Characteristics) produce spurious results and should not be attempted. Block erase, byte
write and lock-bit configuration operations with VCC<3.0V are not supported.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Rev. 1.3
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LHF08CH1
7
2 PRINCIPLES OF OPERATION
The LH28F008SCT-L85 SmartVoltage Flash memory
includes an on-chip WSM to manage block erase,
byte write, and lock-bit configuration functions. It
allows for: 100% TTL-level control inputs, fixed power
supplies during block erasure, byte write, and lock-bit
configuration, and minimal processor overhead with
RAM-Like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the VPP voltage. High
voltage on VPP enables successful block erasure,
byte writing, and lock-bit configuration. All functions
associated with altering memory contents−block
erase, byte write, Lock-bit configuration, status, and
identifier codes−are accessed via the CUI and
verified through the status register.
Commands
are
written
using
standard
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
byte write, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification, and margining of data.
Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs
array data, accesses the identifier codes, or outputs
status register data.
Interface software that initiates and polls progress of
block erase, byte write, and lock-bit configuration can
be stored in any block. This code is copied to and
executed from system RAM during flash memory
updates. After successful completion, reads are
again possible via the Read Array command. Block
erase suspend allows system software to suspend a
block erase to read or write data from any other
block. Byte write suspend allows system software to
suspend a byte write to read data from any other
flash memory array location.
FFFFF
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
64K-byte Block
15
64K-byte Block
14
64K-byte Block
13
64K-byte Block
12
64K-byte Block
11
64K-byte Block
10
64K-byte Block
9
64K-byte Block
8
64K-byte Block
7
64K-byte Block
6
64K-byte Block
5
64K-byte Block
4
64K-byte Block
3
64K-byte Block
2
64K-byte Block
1
64K-byte Block
0
00000
Figure 3. Memory Map
2.1 Data Protection
Depending on the application, the system designer
may choose to make the VPP power supply
switchable (available only when memory block
erases, byte writes, or lock-bit configurations are
required) or hardwired to VPPH1/2/3. The device
accommodates
either
design
practice
and
encourages optimization of the processor-memory
interface.
When VPP≤VPPLK, memory contents cannot be
altered. The CUI, with two-step block erase, byte
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to VPP. All write
functions are disabled when VCC is below the write
lockout voltage VLKO or when RP# is at VIL. The
device’s block locking capability provides additional
protection from inadvertent code or data alteration by
gating erase and byte write operations.
Rev. 1.3
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LHF08CH1
8
3 BUS OPERATION
consuming
completes.
active
power
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.4 Deep Power-Down
until
the
operation
RP# at VIL initiates the deep power-down mode.
3.1 Read
Information can be read from any block, identifier
codes, or status register independent of the VPP
voltage. RP# can be at either VIH or VHH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from deep power-down mode,
the device automatically resets to read array mode.
Four control pins dictate the data flow in and out of
the component: CE#, OE#, WE#, and RP#. CE# and
OE# must be driven active to obtain data at the
outputs. CE# is the device selection control, and
when active enables the selected memory device.
OE# is the data output (DQ0-DQ7) control and when
active drives the selected memory data onto the I/O
bus. WE# must be at VIH and RP# must be at VIH or
VHH. Figure 15 illustrates a read cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0-DQ7 are
placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0-DQ7 outputs are placed in
a high-impedance state independent of OE#. If
deselected during block erase, byte write, or lock-bit
configuration, the device continues functioning, and
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low for
a minimum of 100 ns. Time tPHQV is required after
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During block erase, byte write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time tPHWL is required after RP#
goes to logic-high (VIH) before another command can
be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, byte
write, or lock-bit configuration modes. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array
data. SHARP’s flash memories allow proper CPU
initialization following a system reset through the use
of the RP# input. In this application, RP# is controlled
by the same RESET# signal that resets the system
CPU.
Rev. 1.3
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LHF08CH1
9
3.5 Read Identifier Codes Operation
3.6 Write
The read identifier codes operation outputs the
manufacturer code, device code, block lock
configuration codes for each block, and the master
lock configuration code (see Figure 4). Using the
manufacturer and device codes, the system CPU can
automatically match the device with its proper
algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
VPP=VPPH1/2/3, the CUI additionally controls block
erasure, byte write, and lock-bit configuration.
FFFFF
F0004
Reserved for
Future Implementation
F0003
F0002
Block 15 Lock Configuration Code
F0001
Reserved for
Future Implementation
F0000
Block 15
(Blocks 2 through 14)
When the VPP voltage ≤ VPPLK, Read operations
from the status register, identifier codes, or blocks
are enabled. Placing VPPH1/2/3 on VPP enables
successful block erase, byte write and lock-bit
configuration operations.
Reserved for
Future Implementation
10003
10002
Block 1 Lock Configuration Code
10001
Reserved for
Future Implementation
10000
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a command
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 16 and 17 illustrate
WE# and CE#-controlled write operations.
4 COMMAND DEFINITIONS
1FFFF
10004
The Block Erase command requires appropriate
command data and an address within the block to be
erased. The Byte Write command requires the
command and address of the location to be written.
Set Master and Block Lock-Bit commands require the
command and address within the device (Master
Lock) or block within the device (Block Lock) to be
locked. The Clear Block Lock-Bits command requires
the command and address within the device.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
Block 1
0FFFF
Reserved for
Future Implementation
00004
00003
Master Lock Configuration Code
00002
Block 0 Lock Configuration Code
00001
Device Code
00000
Manufacturer Code
Block 0
Figure 4. Device Identifier Code Memory Map
Rev. 1.3
sharp
LHF08CH1
Mode
Read
Notes
1,2,3,8
Output Disable
3
Standby
3
Deep Power-Down
4
Read Identifier Codes
8
Write
3,6,7,8
RP#
VIH or
VHH
VIH or
VHH
VIH or
VHH
VIL
VIH or
VHH
VIH or
VHH
10
Table 3. Bus Operations
CE#
OE#
WE#
Address
VPP
DQ0-7
RY/BY#
VIL
VIL
VIH
X
X
DOUT
X
VIL
VIH
VIH
X
X
High Z
X
VIH
X
X
X
X
High Z
X
X
X
X
X
High Z
VOH
VIL
VIL
VIH
X
See
Figure 4
X
Note 5
VOH
VIL
VIH
VIL
X
X
DIN
X
NOTES:
1. Refer to DC Characteristics. When VPP≤VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2/3 for VPP. See DC Characteristics for
VPPLK and VPPH1/2/3 voltages.
3. RY/BY# is VOL when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms.
It is VOH during when the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write
suspend mode, or deep power-down mode.
4. RP# at GND±0.2V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when VPP=VPPH1/2/3
and VCC=VCC2/3/4. Block erase, byte write, or lock-bit configuration with VCC<3.0V or VIH<RP#<VHH produce
spurious results and should not be attempted.
7. Refer to Table 4 for valid DIN during a write operation.
8. Don’t use the timing both OE# and WE# are VIL.
Rev. 1.3
sharp
LHF08CH1
Command
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Byte Write
Table 4. Command Definitions(9)
Bus Cycles
First Bus Cycle
Req’d.
Notes Oper(1)
Addr(2)
Data(3)
1
Write
X
FFH
4
Write
X
90H
≥2
2
Write
X
70H
1
Write
X
50H
2
5
Write
BA
20H
40H
2
5,6
Write
WA
or
10H
11
Second Bus Cycle
Oper(1)
Addr(2)
Data(3)
Read
Read
IA
X
ID
SRD
Write
BA
D0H
Write
WA
WD
Block Erase and Byte Write
1
5
Write
X
B0H
Suspend
Block Erase and Byte Write
1
5
Write
X
D0H
Resume
Set Block Lock-Bit
2
7
Write
BA
60H
Write
BA
01H
Set Master Lock-Bit
2
7
Write
X
60H
Write
X
F1H
Clear Block Lock-Bits
2
8
Write
X
60H
Write
X
D0H
NOTES:
1. BUS operations are defined in Table 3.
2. X=Any valid address within the device.
IA=Identifier Code Address: see Figure 4.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 7 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and
master lock codes. See Section 4.2 for read identifier code data.
5. If the block is locked, RP# must be at VHH to enable block erase or byte write operations. Attempts to issue a
block erase or byte write to a locked block while RP# is VIH.
6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master
lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VIH.
8. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation
simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can
be done while RP# is VIH.
9. Commands other than those shown above are reserved by SHARP for future device implementations and
should not be used.
Rev. 1.3
sharp
LHF08CH1
12
4.1 Read Array Command
4.3 Read Status Register Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array
mode. This operation is also initiated by writing the
Read Array command. The device remains enabled
for reads until another command is written. Once the
internal WSM has started a block erase, byte write or
lock-bit configuration, the device will not recognize
the Read Array command until the WSM completes
its operation unless the WSM is suspended via an
Erase Suspend or Byte Write Suspend command.
The Read Array command functions independently of
the VPP voltage and RP# can be VIH or VHH.
The status register may be read to determine when a
block erase, byte write, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing the
Read Status Register command. After writing this
command, all subsequent read operations output
data from the status register until another valid
command is written. The status register contents are
latched on the falling edge of OE# or CE#, whichever
occurs. OE# or CE# must toggle to VIH before further
reads to update the status register latch. The Read
Status Register command functions independently of
the VPP voltage. RP# can be VIH or VHH.
4.2 Read Identifier Codes Command
4.4 Clear Status Register Command
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the
command write, read cycles from addresses shown in
Figure 4 retrieve the manufacturer, device, block lock
configuration and master lock configuration codes
(see Table 5 for identifier code values). To terminate
the operation, write another valid command. Like the
Read Array command, the Read Identifier Codes
command functions independently of the VPP voltage
and RP# can be VIH or VHH. Following the Read
Identifier Codes command, the following information
can be read:
Table 5. Identifier Codes
Code
Address
Data
Manufacture Code
00000
89
Device Code
00001
A6
Block Lock Configuration
X0002(1)
DQ0=0
•Block is Unlocked
DQ0=1
•Block is Locked
DQ1-7
•Reserved for Future Use
Master Lock Configuration
00003
DQ0=0
•Device is Unlocked
DQ0=1
•Device is Locked
DQ1-7
•Reserved for Future Use
NOTE:
1. X selects the specific block lock configuration
code to be read. See Figure 4 for the device
identifier code memory map.
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to "1"s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate
various failure conditions (see Table 7). By allowing
system software to reset these bits, several
operations (such as cumulatively erasing or locking
multiple blocks or writing several bytes in sequence)
may be performed. The status register may be polled
to determine if an error occurre during the sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently
of the applied VPP Voltage. RP# can be VIH or VHH.
This command is not functional during block erase or
byte write suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated by
a two-cycle command. A block erase setup is first
written, followed by an block erase confirm. This
command sequence requires appropriate sequencing
and an address within the block to be erased (erase
changes
all block data to FFH). Block
preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system). After
the two-cycle block erase sequence is written, the
device automatically outputs status register data
when read (see Figure 5). The CPU can detect block
erase completion by analyzing the output data of the
RY/BY# pin or status register bit SR.7.
Rev. 1.3
sharp
LHF08CH1
13
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued.
corresponding block lock-bit be cleared or, if set, that
RP#=VHH. If byte write is attempted when the
corresponding block lock-bit is set and RP#=VIH,
SR.1 and SR.4 will be set to "1". Byte write
operations with VIH<RP#<VHH produce spurious
results and should not be attempted.
This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to "1". Also, reliable block erasure
can
only
occur
when
VCC=VCC2/3/4
and
VPP=VPPH1/2/3. In the absence of this high voltage,
block contents are protected against erasure. If block
erase is attempted while VPP≤VPPLK, SR.3 and SR.5
will be set to "1". Successful block erase requires that
the corresponding block lock-bit be cleared or, if set,
that RP#=VHH. If block erase is attempted when the
corresponding block lock-bit is set and RP#=VIH,
SR.1 and SR.5 will be set to "1". Block erase
operations with VIH<RP#<VHH produce spurious
results and should not be attempted.
4.7 Block Erase Suspend Command
4.6 Byte Write Command
Byte write is executed by a two-cycle command
sequence. Byte write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the byte write and write verify algorithms
internally. After the byte write sequence is written, the
device automatically outputs status register data
when read (see Figure 6). The CPU can detect the
completion of the byte write event by analyzing the
RY/BY# pin or status register bit SR.7.
When byte write is complete, status register bit SR.4
should be checked. If byte write error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for "1"s that do not
successfully write to "0"s. The CUI remains in read
status register mode until it receives another
command.
Reliable byte writes can only occur when
VCC=VCC2/3/4 and VPP=VPPH1/2/3. In the absence of
this high voltage, memory contents are protected
against byte writes. If byte write is attempted while
VPP≤VPPLK, status register bits SR.3 and SR.4 will be
set to "1". Successful byte write requires that the
The Block Erase Suspend command allows
block-erase interruption to read or byte-write data in
another block of memory. Once the block-erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block
erase sequence at a predetermined point in the
algorithm. The device outputs status register data
when read after the Block Erase Suspend command
is written. Polling status register bits SR.7 and SR.6
can determine when the block erase operation has
been suspended (both will be set to "1"). RY/BY# will
also transition to VOH. Specification tWHRH2 defines
the block erase suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A Byte Write command sequence can
also be issued during erase suspend to program data
in other blocks. Using the Byte Write Suspend
command (see Section 4.8), a byte write operation
can also be suspended. During a byte write operation
with block erase suspended, status register bit SR.7
will return to "0" and the RY/BY# output will transition
to VOL. However, SR.6 will remain "1" to indicate
block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status register
bits SR.6 and SR.7 will automatically clear and
RY/BY# will return to VOL. After the Erase Resume
command is written, the device automatically outputs
status register data when read (see Figure 7). VPP
must remain at VPPH1/2/3 (the same VPP level used
for block erase) while block erase is suspended. RP#
must also remain at VIH or VHH (the same RP# level
used for block erase). Block erase cannot resume
until byte write operations initiated during block erase
suspend have completed.
Rev. 1.3
sharp
LHF08CH1
4.8 Byte Write Suspend Command
The Byte Write Suspend command allows byte write
interruption to read data in other flash memory
locations. Once the byte write process starts, writing
the Byte Write Suspend command requests that the
WSM suspend the byte write sequence at a
predetermined point in the algorithm. The device
continues to output status register data when read
after the Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the byte write operation has been
suspended (both will be set to "1"). RY/BY# will also
transition to VOH. Specification tWHRH1 defines the
byte write suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
byte write is suspended are Read Status Register
and Byte Write Resume. After Byte Write Resume
command is written to the flash memory, the WSM
will continue the byte write process. Status register
bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to VOL. After the Byte Write
Resume
command is written, the device
automatically outputs status register data when read
(see Figure 8). VPP must remain at VPPH1/2/3 (the
same VPP level used for byte write) while in byte write
suspend mode. RP# must also remain at VIH or VHH
(the same RP# level used for byte write).
4.9 Set Block and Master Lock-Bit
Commands
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
master lock-bit. The block lock-bits gate program and
erase operations while the master lock-bit gates
block-lock bit modification. With the master lock-bit
not set, individual block lock-bits can be set using the
Set Block Lock-Bit command. The Set Master
Lock-Bit command, in conjunction with RP#=VHH,
sets the master lock-bit. After the master lock-bit is
set, subsequent setting of block lock-bits requires
both the Set Block Lock-Bit command and VHH on
14
the RP# pin. See Table 6 for a summary of hardware
and software write protection options.
Set block lock-bit and master lock-bit are executed by
a two-cycle command sequence. The set block or
master lock-bit setup along with appropriate block or
device address is written followed by either the set
block lock-bit confirm (and an address within the
block to be locked) or the set master lock-bit confirm
(and any device address). The WSM then controls
the set lock-bit algorithm. After the sequence is
written, the device automatically outputs status
register data when read (see Figure 9). The CPU can
detect the completion of the set lock-bit event by
analyzing the RY/BY# pin output or status register bit
SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Master Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations occur
only when VCC=VCC2/3/4 and VPP=VPPH1/2/3. In the
absence of this high voltage, lock-bit contents are
protected against alteration.
A successful set block lock-bit operation requires that
the master lock-bit be cleared or, if the master
lock-bit is set, that RP#=VHH. If it is attempted with
the master lock-bit set and RP#=VIH, SR.1 and SR.4
will be set to "1" and the operation will fail. Set block
lock-bit operations while VIH<RP#<VHH produce
spurious results and should not be attempted. A
successful set master lock-bit operation requires that
RP#=VHH. If it is attempted with RP#=VIH, SR.1 and
SR.4 will be set to "1" and the operation will fail. Set
master lock-bit operations with VIH<RP#<VHH
produce spurious results and should not be
attempted.
Rev. 1.3
sharp
LHF08CH1
4.10 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits command. If the
master lock-bit is set, clearing block lock-bits requires
both the Clear Block Lock-Bits command and VHH on
the RP# pin. See Table 6 for a summary of hardware
and software write protection options.
Clear block lock-bits operation is executed by a
two-cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the
device automatically outputs status register data
when read (see Figure 10). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# Pin output or status register bit
SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
another command is issued.
Operation
Block Erase or
Byte Write
Master
Lock-Bit
X
Set Block
Lock-Bit
0
1
Set Master
Lock-Bit
Clear Block
Lock-Bits
X
0
1
15
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR.5 being set to "1". Also, a reliable clear
block lock-bits operation can only occur when
VCC=VCC2/3/4 and VPP=VPPH1/2/3. If a clear block
lock-bits operation is attempted while VPP≤VPPLK,
SR.3 and SR.5 will be set to "1". In the absence of
this high voltage, the block lock-bits content are
protected against alteration. A successful clear block
lock-bits operation requires that the master lock-bit is
not set or, if the master lock-bit is set, that RP#=VHH.
If it is attempted with the master lock-bit set and
RP#=VIH, SR.1 and SR.5 will be set to "1" and the
operation will fail. A clear block lock-bits operation
with VIH<RP#<VHH produce spurious results and
should not be attempted.
If a clear block lock-bits operation is aborted due to
VPP or VCC transitioning out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values. Once the master lock-bit is set, it
cannot be cleared.
Table 6. Write Protection Alternatives
Block
Lock-Bit
RP#
Effect
0
VIH or VHH Block Erase and Byte Write Enabled
1
VIH
Block is Locked. Block Erase and Byte Write Disabled
Block Lock-Bit Override. Block Erase and Byte Write
VHH
Enabled
X
VIH or VHH Set Block Lock-Bit Enabled
X
VIH
Master Lock-Bit is Set. Set Block Lock-Bit Disabled
VHH
Master Lock-Bit Override. Set Block Lock-Bit Enabled
X
VIH
Set Master Lock-Bit Disabled
VHH
Set Master Lock-Bit Enabled
X
VIH or VHH Clear Block Lock-Bits Enabled
X
VIH
Master Lock-Bit is Set. Clear Block Lock-Bits Disabled
Master Lock-Bit Override. Clear Block Lock-Bits
VHH
Enabled
Rev. 1.3
sharp
LHF08CH1
WSMS
ESS
7
6
16
Table 7. Status Register Definition
ECLBS
BWSLBS
VPPS
BWSS
5
4
3
2
DPS
R
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
Check RY/BY# or SR.7 to determine block erase, byte
write, or lock-bit configuration completion.
SR.6-0 are invalid while SR.7="0".
SR.6 = ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
If both SR.5 and SR.4 are "1"s after a block erase or
lock-bit configuration attempt, an improper command
sequence was entered.
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.3 does not provide a continuous indication of VPP
level. The WSM interrogates and indicates the VPP level
only after Block Erase, Byte Write, Set Block/Master
Lock-Bit, or Clear Block Lock-Bits command sequences.
SR.3 is not guaranteed to reports accurate feedback
only when VPP≠VPPH1/2/3.
SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS
1 = Error in Byte Write or Set Master/Block Lock-Bit
0 = Successful Byte Write or Set Master/Block
Lock-Bit
SR.3 = VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = BYTE WRITE SUSPEND STATUS
1 = Byte Write Suspended
0 = Byte Write in Progress/Completed
SR.1 does not provide a continuous indication of master
and block lock-bit values. The WSM interrogates the
master lock-bit, block lock-bit, and RP# only after Block
Erase, Byte Write, or Lock-Bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set, master
lock-bit is set, and/or RP# is not VHH. Reading the block
lock and master lock configuration codes after writing
the Read Identifier Codes command indicates master
and block lock-bit status.
SR.1 = DEVICE PROTECT STATUS
1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock SR.0 is reserved for future use and should be masked
Detected, Operation Abort
out when polling the status register.
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
Rev. 1.3
sharp
LHF08CH1
17
Start
Bus
Operation
Command
Write 20H,
Block Address
Write
Erase Setup
Data=20H
Addr=Within Block to be Erased
Write
Erase
Confirm
Data=D0H
Addr=Within Block to be Erased
Write D0H,
Comments
Block Address
Status Register Data
Read
Read Status
Register
Suspend Block
Erase Loop
No
SR.7=
0
Suspend
Block Erase
Yes
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after a sequence of
block erasures.
1
Write FFH after the last operation to place device in read array mode.
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Bus
Read Status Register
Data(See Above)
Operation
Command
Standby
Comments
Check SR.3
1=VPP Error Detect
1
VPP Range Error
SR.3=
0
Check SR.1
1=Device Protect Detect
Standby
RP#=VIH,Block Lock-Bit is Set
Only required for systems
implementing lock-bit configuration
1
Device Protect Error
SR.1=
Standby
Check SR.4,5
Both 1=Command Sequence Error
0
Standby
1
SR.4,5=
Check SR.5
1=Block Erase Error
Command Sequence
Error
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
0
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
1
SR.5=
Block Erase Error
0
Block Erase Successful
Figure 5. Automated Block Erase Flowchart
Rev. 1.3
sharp
LHF08CH1
18
Start
Bus
Operation
Command
Write 40H,
Address
Write
Setup Byte Write
Data=40H
Addr=Location to Be Written
Write
Byte Write
Data=Data to Be Written
Addr=Location to Be Written
Write Byte
Comments
Data and Address
Status Register Data
Read
Read
Status Register
Suspend Byte
Write Loop
No
SR.7=
0
Suspend
Byte Write
Yes
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
Repeat for subsequent byte writes.
SR full status check can be done after each byte write, or after a sequence of
byte writes.
1
Write FFH after the last byte write operation to place device in
read array mode.
Full Status
Check if Desired
Byte Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Operation
Command
Standby
1
Comments
Check SR.3
1=VPP Error Detect
VPP Range Error
SR.3=
Check SR.1
1=Device Protect Detect
0
Standby
RP#=VIH,Block Lock-Bit is Set
Only required for systems
implementing lock-bit configuration
1
Device Protect Error
SR.1=
Standby
0
Check SR.4
1=Data Write Error
SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are written before
1
SR.4=
0
Byte Write Error
full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Byte Write Successful
Figure 6. Automated Byte Write Flowchart
Rev. 1.3
sharp
LHF08CH1
Start
Bus
Operation
Write
Write B0H
19
Command
Erase
Suspend
Comments
Data=B0H
Addr=X
Status Register Data
Read
Addr=X
Read
Status Register
Check SR.7
1=WSM Ready
Standby
0=WSM Busy
SR.7=
0
Check SR.6
1=Block Erase Suspended
Standby
0=Block Erase Completed
1
Write
SR.6=
0
Erase
Resume
Data=D0H
Addr=X
Block Erase Completed
1
Read or
Read
Byte Write
Byte Write ?
Read Array Data
Byte Write Loop
No
Done?
Yes
Write D0H
Write FFH
Block Erase Resumed
Read Array Data
Figure 7. Block Erase Suspend/Resume Flowchart
Rev. 1.3
sharp
LHF08CH1
Start
Bus
Operation
Write
Write B0H
20
Command
Byte Write
Suspend
Comments
Data=B0H
Addr=X
Status Register Data
Read
Addr=X
Read
Status Register
Check SR.7
1=WSM Ready
Standby
0=WSM Busy
SR.7=
0
Check SR.2
1=Byte Write Suspended
Standby
0=Byte Write Completed
1
Write
SR.2=
0
Read Array
Data=FFH
Addr=X
Byte Write Completed
Read Array locations other
Read
than that being written.
1
Write
Write FFH
Byte Write
Resume
Data=D0H
Addr=X
Read Array Data
Done
No
Reading
Yes
Write D0H
Write FFH
Byte Write Resumed
Read Array Data
Figure 8. Byte Write Suspend/Resume Flowchart
Rev. 1.3
sharp
LHF08CH1
Start
Write 60H,
Block/Device Address
21
Bus
Operation
Command
Write
Set
Block/Master
Lock-Bit Setup
Set
Write 01H/F1H,
Block/Device Address
Write
Block or Master
Lock-Bit Confirm
Comments
Data=60H
Addr=Block Address(Block),
Device Address(Master)
Data=01H(Block),
F1H(Master)
Addr=Block Address(Block),
Device Address(Master)
Read
Status Register
SR.7=
Status Register Data
Read
Check SR.7
0
Standby
1=WSM Ready
0=WSM Busy
1
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation
Full Status
Check if Desired
or after a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
read array mode.
Set Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Operation
Standby
1
Command
Comments
Check SR.3
1=VPP Error Detect
VPP Range Error
SR.3=
0
Standby
RP#=VIH, Master Lock-Bit is Set
1
Device Protect Error
SR.1=
Check SR.1
1=Device Protect Detect
RP#=VIH
(Set Master Lock-BIt Operation)
(Set Block Lock-BIt Operation)
Check SR.4,5
0
Standby
Both 1=Command
Sequence Error
1
SR.4,5=
Command Sequence
Error
Standby
Check SR.4
1=Set Lock-Bit Error
0
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set before
full status is checked.
1
SR.4=
Set Lock-Bit Error
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0
Set Lock-Bit Successful
Figure 9. Set Block and Master Lock-Bit Flowchart
Rev. 1.3
sharp
LHF08CH1
Start
Write 60H
22
Bus
Operation
Command
Write
Clear Block
Lock-Bits Setup
Data=60H
Addr=X
Clear Block
Data=D0H
Addr=X
Write
Lock-Bits Confirm
Comments
Write D0H
Read
Status Register Data
Read
Status Register
Check SR.7
Standby
SR.7=
0
1=WSM Ready
0=WSM Busy
Write FFH after the Clear Block Lock-Bits operation to
place device in read array mode.
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Operation
Command
Standby
1
Comments
Check SR.3
1=VPP Error Detect
VPP Range Error
SR.3=
Standby
0
Check SR.1
1=Device Protect Detect
RP#=VIH, Master Lock-Bit is Set
Check SR.4,5
1
Device Protect Error
SR.1=
Standby
Both 1=Command
Sequence Error
0
Standby
1
SR.4,5=
Command Sequence
Error
Check SR.5
1=Clear Block Lock-Bits Error
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If error is detected, clear the Status Register before attempting
0
retry or other error recovery.
1
SR.5=
Clear Block Lock-Bits
Error
0
Clear Block Lock-Bits
Successful
Figure 10. Clear Block Lock-Bits Flowchart
Rev. 1.3
sharp
LHF08CH1
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP
provides
three
control
inputs
to
accommodate
multiple
memory
connections.
Three-line control provides for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will
not occur.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
23
RY/BY# is also VOH when the device is in block erase
suspend (with byte write inactive), byte write suspend
or deep power-down modes.
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are
interested in three supply current issues; standby
current levels, active current levels and transient
peaks produced by falling and rising edges of CE#
and OE#. Transient current magnitudes depend on
the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. Each
device should have a 0.1µF ceramic capacitor
connected between its VCC and GND and between its
VPP and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7µF electrolytic capacitor should be placed at the
array’s power supply connection between VCC and
GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.2 RY/BY# and Block Erase, Byte Write,
and Lock-Bit Configuration Polling
5.4 VPP Trace on Printed Circuit Boards
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, byte write
and lock-bit configuration completion. It transitions
low after block erase, byte write, or lock-bit
configuration commands and returns to VOH when
the WSM has finished executing the internal
algorithm.
Updating flash memories that reside in the target
system requires that the printed circuit board
designer pay attention to the VPP Power supply trace.
The VPP pin supplies the memory cell current for byte
writing and block erasing. Use similar trace widths
and layout considerations given to the VCC power
bus. Adequate VPP supply traces and decoupling will
decrease VPP voltage spikes and overshoots.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
Rev. 1.3
sharp
LHF08CH1
5.5 VCC, VPP, RP# Transitions
Block erase, byte write and lock-bit configuration are
not guaranteed if VPP falls outside of a valid VPPH1/2/3
range, VCC falls outside of a valid VCC2/3/4 range, or
RP#≠VIH or VHH. If VPP error is detected, status
register bit SR.3 is set to "1" along with SR.4 or SR.5,
depending on the attempted operation. If RP#
transitions to VIL during block erase, byte write, or
lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation
will abort and the device will enter deep power-down.
The aborted operation may leave data partially
altered. Therefore, the command sequence must be
repeated after normal operation is restored. Device
power-off or RP# transitions to VIL clear the status
register.
The CUI latches commands issued by system
software and is not altered by VPP or CE# transitions
or WSM actions. Its state is read array mode upon
power-up, after exit from deep power-down or after
VCC transitions below VLKO.
After block erase, byte write, or lock-bit configuration,
even after VPP transitions down to VPPLK, the CUI
must be placed in read array mode via the Read
Array command if subsequent access to the memory
array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, byte writing, or lock-bit
configuration during power transitions. Upon
power-up, the device is indifferent as to which power
24
supply (VPP or VCC) powers-up first. Internal circuitry
resets the CUI to read array mode at power-up.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and CE# must be low for a
command write, driving either to VIH will inhibit writes.
The CUI’s two-step command sequence architecture
provides added level of protection against data
alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP#=VIL regardless of its control inputs state.
5.7 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is retained
when system power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when system
power is applied. For example, portable computing
products and other power sensitive applications that
use an array of devices for solid-state storage can
consume negligible power by lowering RP# to VIL
standby or sleep modes. If access is again needed,
the devices can be read following the tPHQV and
tPHWL wake-up cycles required after RP# is first
raised to VIH. See AC Characteristics− Read Only
and Write Operations and Figures 15, 16 and 17 for
more information.
Rev. 1.3
sharp
LHF08CH1
6 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Block Erase, Byte Write
and Lock-Bit Configuration ...........0°C to +70°C(1)
Temperature under Bias............... -10°C to +80°C
Storage Temperature........................ -65°C to +125°C
Voltage On Any Pin
(except VCC, VPP, and RP#).......-2.0V to +7.0V(2)
VCC Supply Voltage ..........................-2.0V to +7.0V(2)
VPP Update Voltage during
Block Erase, Byte Write and
Lock-Bit Configuration ........... -2.0V to +14.0V(2,3)
RP# Voltage with Respect to
GND during Lock-Bit
Configuration Operations ...... -2.0V to +14.0V(2,3)
25
*WARNING: Stressing the device beyond the
"Absolute Maximum Ratings" may cause permanent
damage. These are stress ratings only. Operation
beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device reliability.
NOTES:
1. Operating temperature is for commercial
temperature product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on VCC and VPP pins. During
transitions, this level may undershoot to -2.0V for
periods <20ns. Maximum DC voltage on
input/output pins and VCC is VCC+0.5V which,
during transitions, may overshoot to VCC+2.0V for
periods <20ns.
3. Maximum DC voltage on VPP and RP# may
overshoot to +14.0V for periods <20ns.
4. Output shorted for no more than one second. No
more than one output shorted at a time.
Output Short Circuit Current ........................ 100mA(4)
6.2 Operating Conditions
Temperature and VCC Operating Conditions
Symbol
Parameter
Notes
Min.
Max.
Unit
Test Condition
TA
Operating Temperature
0
+70
°C
Ambient Temperature
VCC1
VCC Supply Voltage (2.7V-3.6V)
1
2.7
3.6
V
VCC2
VCC Supply Voltage (3.3V±0.3V)
3.0
3.6
V
VCC3
VCC Supply Voltage (5V±0.25V)
4.75
5.25
V
VCC4
VCC Supply Voltage (5V±0.5V)
4.50
5.50
V
NOTE:
1. Block erase, byte write and lock-bit configuration operations with VCC<3.0V should not be attempted.
6.2.1 CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
NOTE:
1. Sampled, not 100% tested.
TA=+25°C, f=1MHz
Typ.
Max.
6
8
8
12
Unit
pF
pF
Condition
VIN=0.0V
VOUT=0.0V
Rev. 1.3
sharp
LHF08CH1
26
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
2.7
1.35
INPUT
TEST POINTS
1.35
OUTPUT
0.0
AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 11. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V
3.0
INPUT
TEST POINTS
1.5
1.5
OUTPUT
0.0
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 12. Transient Input/Output Reference Waveform for VCC=3.3V±0.3V and VCC=5V±0.25V
(High Speed Testing Configuration)
2.4
2.0
2.0
TEST POINTS
INPUT
0.8
0.45
OUTPUT
0.8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for VCC=5V±0.5V
(Standard Testing Configuration)
Test Configuration Capacitance Loading Value
Test Configuration
CL(pF)
VCC=3.3V±0.3V, 2.7V-3.6V
50
VCC=5V±0.25V
30
VCC=5V±0.5V
100
1.3V
1N914
RL=3.3kΩ
DEVICE
UNDER
TEST
CL Includes Jig
Capacitance
OUT
CL
Figure 14. Transient Equivalent Testing
Load Circuit
Rev. 1.3
sharp
LHF08CH1
27
6.2.3 DC CHARACTERISTICS
Sym.
Parameter
ILI
Input Load Current
ILO
Output Leakage Current
ICCS
VCC Standby Current
ICCD
ICCR
VCC Deep Power-Down
Current
VCC Read Current
DC Characteristics
VCC=2.7V
VCC=3.3V
Notes Typ. Max. Typ. Max.
1
±0.5
±0.5
6
12
7
12
17
35
mA
7
18
8
18
20
50
mA












17
17
12
17
17
12


35
30

30
25
mA
mA
mA
mA
mA
mA
Test
Conditions
VCC=VCCMax.
VIN=VCC or GND
VCC=VCCMax.
VOUT=VCC or GND
CMOS Inputs
VCC=VCCMax.
CE#=RP#=VCC±0.2V
TTL Inputs
VCC=VCCMax.
CE#=RP#=VIH
RP#=GND±0.2V
IOUT(RY/BY#)=0mA
CMOS Inputs
VCC=VCCMax.
CE#=GND
f=5MHz(3.3V, 2.7V),
8MHz(5V)
IOUT=0mA
TTL Inputs
VCC=VCCMax.
CE#=GND
f=5MHz(3.3V, 2.7V),
8MHz(5V)
IOUT=0mA
VPP=3.3V±0.3V
VPP=5.0V±0.5V
VPP=12.0V±0.6V
VPP=3.3V±0.3V
VPP=5.0V±0.5V
VPP=12.0V±0.6V
1,2


1
6
1
10
mA
CE#=VIH
1
±2
10
±15
200
±2
10
±15
200
±2
10
±15
200
µA
µA
VPP≤VCC
VPP>VCC
0.1
5
0.1
5
0.1
5
µA
RP#=GND±0.2V












40
40
15
20
20
15


40
15

20
15
mA
mA
mA
mA
mA
mA
VPP=3.3V±0.3V
VPP=5.0V±0.5V
VPP=12.0V±0.6V
VPP=3.3V±0.3V
VPP=5.0V±0.5V
VPP=12.0V±0.6V


200
10
200
µA
VPP=VPPH1/2/3
1
ICCE
VCC Block Erase or
Clear Block Lock-Bits
Current
VCC Byte Write or Block
Erase Suspend Current
VPP Standby or Read
Current
VPP Deep Power-Down
Current
VPP Byte Write or Set
Lock-Bit Current
1,7
VPP Block Erase or
Clear Lock-Bit Current
1,7
IPPWS VPP Byte Write or Block
IPPES Erase Suspend Current
±10
µA
100
20
100
25
100
µA
0.1
2
0.2
2
0.4
2
mA
10
µA
10
10
1,5,6
1,7
IPPE
µA
20
1
VCC Byte Write or
Set Lock-Bit Current
IPPW
±0.5
±1
1,3,6
ICCW
ICCWS
ICCES
IPPS
IPPR
IPPD
±0.5
VCC=5V
Typ. Max. Unit
1
1,7
1
10


Rev. 1.3
sharp
LHF08CH1
Sym.
Parameter
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH1
Output High Voltage
(TTL)
VOH2
Output High Voltage
(CMOS)
VPPLK VPP Lockout during
Normal Operations
VPPH1 VPP during Byte Write,
Block Erase or
Lock-Bit Operations
VPPH2 VPP during Byte Write,
Block Erase or
Lock-Bit Operations
VPPH3 VPP during Byte Write,
Block Erase or
Lock-Bit Operations
VLKO VCC Lockout Voltage
VHH
RP# Unlock Voltage
28
DC Characteristics (Continued)
VCC=2.7V
VCC=3.3V
VCC=5V
Test
Notes Min. Max. Min. Max. Min. Max. Unit
Conditions
7
-0.5
0.8
-0.5
0.8
-0.5
0.8
V
7
VCC
VCC
VCC
2.0
2.0
2.0
V
+0.5
+0.5
+0.5
3,7
VCC=VCCMin.
IOL=5.8mA(VCC=5V)
0.4
0.4
0.45
V
IOL=2.0mA
(VCC=3.3V, 2.7V)
3,7
VCC=VCCMin.
IOH=-2.5mA(VCC=5V)
2.4
2.4
2.4
V
IOH=-2.0mA(VCC=3.3V)
IOH=-1.5mA(VCC=2.7V)
3,7
0.85
0.85
0.85
VCC=VCCMin.
V
VCC
VCC
VCC
IOH=-2.0mA
VCC
VCC
VCC
VCC=VCCMin.
V
-0.4
-0.4
-0.4
IOH=-100µA
4,7
1.5
1.5
1.5
V


3.0
3.6


V


4.5
5.5
4.5
5.5
V


11.4
12.6
11.4
12.6
V
2.0
8,9

2.0

11.4
2.0
12.6
11.4
V
12.6
V
Set master lock-bit
Override master and
block lock-bit
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA=+25°C.
2. ICCWS and ICCES are specified with the device de-selected. If read or byte written while in erase suspend mode,
the device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.
3. Includes RY/BY#.
4. Block erases, byte writes, and lock-bit configurations are inhibited when VPP≤VPPLK, and not guaranteed in the
range between VPPLK(max.) and VPPH1(min.), between VPPH1(max.) and VPPH2(min.), between VPPH2(max.)
and VPPH3(min.), and above VPPH3(max.).
5. Automatic Power Savings (APS) reduces typical ICCR to 1mA at 5V VCC and 3mA at 2.7V and 3.3V VCC in static
operation.
6. CMOS inputs are either VCC±0.2V or GND±0.2V. TTL inputs are either VIL or VIH.
7. Sampled, not 100% tested.
8. Master lock-bit set operations are inhibited when RP#=VIH. Block lock-bit configuration operations are inhibited
when the master lock-bit is set and RP#=VIH. Block erases and byte writes are inhibited when the corresponding
block-lock bit is set and RP#=VIH. Block erase, byte write, and lock-bit configuration operations are not
guaranteed with VCC<3.0V or VIH<RP#<VHH and should not be attempted.
9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
Rev. 1.3
sharp
LHF08CH1
29
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS(1)
Sym.
tAVAV
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
VCC=2.7V-3.6V, TA=0°C to +70°C
Versions(4)
Parameter
Notes
Read Cycle Time
Address to Output Delay
CE# to Output Delay
RP# High to Output Delay
OE# to Output Delay
CE# to Output in Low Z
CE# High to Output in High Z
OE# to Output in Low Z
OE# High to Output in High Z
Output Hold from Address, CE# or OE# Change,
Whichever Occurs First
2
2
3
3
3
3
3
LH28F008SC-L150
Min.
Max.
150
150
150
600
50
0
55
0
20
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
See 5.0V VCC Read-Only Operations for notes 1 through 4.
Sym.
tAVAV
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
VCC=3.3V±0.3V, TA=0°C to +70°C
Versions(4)
Parameter
Notes
Read Cycle Time
Address to Output Delay
CE# to Output Delay
RP# High to Output Delay
OE# to Output Delay
CE# to Output in Low Z
CE# High to Output in High Z
OE# to Output in Low Z
OE# High to Output in High Z
Output Hold from Address, CE# or OE# Change,
Whichever Occurs First
2
2
3
3
3
3
3
LH28F008SC-L120
Min.
Max.
120
120
120
600
50
0
55
0
20
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
See 5.0V VCC Read-Only Operations for notes 1 through 4.
Rev. 1.3
sharp
LHF08CH1
Sym.
tAVAV
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
VCC=5V±0.5V, 5V±0.25V, TA=0°C to +70°C
VCC=5V±0.25V LH28F008SC-L85(5)
(4)
Versions
VCC=5V±0.5V
LH28F008SC-L90(6)
Parameter
Notes
Min.
Max.
Min.
Max.
Read Cycle Time
85
90
Address to Output Delay
85
90
CE# to Output Delay
2
85
90
RP# High to Output Delay
400
400
OE# to Output Delay
2
40
45
CE# to Output in Low Z
3
0
0
CE# High to Output in High Z
3
55
55
OE# to Output in Low Z
3
0
0
OE# High to Output in High Z
3
10
10
Output Hold from Address, CE# or OE#
3
0
0
Change, Whichever Occurs First
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
3. Sampled, not 100% tested.
4. See Ordering Information for device speeds (valid operational combinations).
5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed
Configuration) for testing characteristics.
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.
Rev. 1.3
sharp
LHF08CH1
VIH
Standby
Device
Address Selection
ADDRESSES(A)
31
Data Valid
Address Stable
VIL
tAVAV
VIH
CE#(E)
tEHQZ
VIL
VIH
OE#(G)
tGHQZ
VIL
VIH
WE#(W)
tGLQV
VIL
tELQV
tGLQX
tELQX
tOH
VOH
DATA(D/Q)
(DQ0-DQ7)
HIGH Z
Valid Output
VOL
HIGH Z
tAVQV
VCC
tPHQV
VIH
RP#(P)
VIL
Figure 15. AC Waveform for Read Operations
Rev. 1.3
sharp
LHF08CH1
32
6.2.5 AC CHARACTERISTICS - WRITE OPERATION(1)
Sym.
VCC=2.7V-3.6V, TA=0°C to +70°C
Versions(5)
Parameter
Notes
tAVAV
Write Cycle Time
tPHWL
RP# High Recovery to WE# Going Low
tELWL
CE# Setup to WE# Going Low
tWLWH
WE# Pulse Width
tAVWH
Address Setup to WE# Going High
tDVWH
Data Setup to WE# Going High
tWHDX
Data Hold from WE# High
tWHAX
Address Hold from WE# High
tWHEH
CE# Hold from WE# High
tWHWL
WE# Pulse Width High
tWHGL
Write Recovery before Read
NOTE:
See 5.0V VCC WE#-Controlled Writes for notes 1 through 5.
Sym.
2
3
3
VCC=3.3V±0.3V, TA=0°C to +70°C
Versions(5)
Parameter
Notes
tAVAV
Write Cycle Time
tPHWL
RP# High Recovery to WE# Going Low
2
tELWL
CE# Setup to WE# Going Low
tWLWH
WE# Pulse Width
tPHHWH RP# VHH Setup to WE# Going High
2
tVPWH
VPP Setup to WE# Going High
2
tAVWH
Address Setup to WE# Going High
3
tDVWH
Data Setup to WE# Going High
3
tWHDX
Data Hold from WE# High
tWHAX
Address Hold from WE# High
tWHEH
CE# Hold from WE# High
tWHWL
WE# Pulse Width High
tWHRL
WE# High to RY/BY# Going Low
tWHGL
Write Recovery before Read
tQVVL
VPP Hold from Valid SRD, RY/BY# High
2,4
tQVPH
RP# VHH Hold from Valid SRD, RY/BY# High
2,4
NOTE:
See 5V VCC AC Characteristics - Write Operations for Notes 1 through 5.
LH28F008SC-L150
Min.
Max.
150
1
0
70
50
50
5
5
0
25
0
Unit
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
LH28F008SC-L120
Min.
Max.
120
1
0
70
100
100
50
50
5
5
0
25
100
0
0
0
Unit
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 1.3
sharp
LHF08CH1
Sym.
tAVAV
tPHWL
tELWL
tWLWH
tPHHWH
tVPWH
tAVWH
tDVWH
tWHDX
tWHAX
tWHEH
tWHWL
tWHRL
tWHGL
tQVVL
tQVPH
VCC=5V±0.5V, 5V±0.25V, TA=0°C to +70°C
VCC=5V±0.25V LH28F008SC-L85(6)
(5)
Versions
VCC=5V±0.5V
LH28F008SC-L90(7)
Parameter
Notes
Min.
Max.
Min.
Max.
Write Cycle Time
85
90
RP# High Recovery to WE# Going Low
2
1
1
CE# Setup to WE# Going Low
0
0
WE# Pulse Width
50
50
RP# VHH Setup to WE# Going High
2
100
100
VPP Setup to WE# Going High
2
100
100
Address Setup to WE# Going High
3
40
40
Data Setup to WE# Going High
3
40
40
Data Hold from WE# High
5
5
Address Hold from WE# High
5
5
CE# Hold from WE# High
0
0
WE# Pulse Width High
25
25
WE# High to RY/BY# Going Low
90
90
Write Recovery before Read
0
0
VPP Hold from Valid SRD, RY/BY# High
2,4
0
0
RP# VHH Hold from Valid SRD, RY/BY#
2,4
0
0
High
33
Unit
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as
during read-onry operations. Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase, byte write, or lock-bit configuration.
4. VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase,
byte write, or lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed
Configuration) for testing characteristics.
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.
Rev. 1.3
sharp
LHF08CH1
AIN
AIN
4
5
6
Valid
SRD
DIN
}
}
3
}
2
}
}
}
1
34
VIH
ADDRESSES(A)
VIL
tWHAX
tAVWH
tAVAV
VIH
CE#(E)
VIL
tWHEH
tELWL
tWHGL
VIH
OE#(G)
VIL
tWHWL
tWHQV1,2,3,4
VIH
WE#(W)
VIL
VIH
DATA(D/Q)
High Z
tWLWH
tDVWH
tWHDX
DIN
DIN
VIL
tPHWL
tWHRL
VOH
RY/BY#(R)
VOL
tPHHWH
tQVPH
VHH
RP#(P)
VIH
VIL
tVPWH
VPPH3,2,1
VPP(V)
tQVVL
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or byte write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 16. AC Waveform for WE#-Controlled Write Operations
Rev. 1.3
sharp
LHF08CH1
35
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES(1)
Sym.
VCC=2.7V-3.6V, TA=0°C to +70°C
Versions(5)
Parameter
Notes
tAVAV
Write Cycle Time
tPHEL
RP# High Recovery to CE# Going Low
2
tWLEL
WE# Setup to CE# Going Low
tELEH
CE# Pulse Width
tAVEH
Address Setup to CE# Going High
3
tDVEH
Data Setup to CE# Going High
3
tEHDX
Data Hold from CE# High
tEHAX
Address Hold from CE# High
tEHWH
WE# Hold from CE# High
tEHEL
CE# Pulse Width High
tEHGL
Write Recovery before Read
NOTE:
See 5.0V VCC Alternative CE#-Controlled Writes for notes 1 through 5.
Sym.
VCC=3.3V±0.3V, TA=0°C to +70°C
Versions(5)
Parameter
Notes
tAVAV
Write Cycle Time
tPHEL
RP# High Recovery to CE# Going Low
2
tWLEL
WE# Setup to CE# Going Low
tELEH
CE# Pulse Width
tPHHEH RP# VHH Setup to CE# Going High
2
tVPEH
VPP Setup to CE# Going High
2
tAVEH
Address Setup to CE# Going High
3
tDVEH
Data Setup to CE# Going High
3
tEHDX
Data Hold from CE# High
tEHAX
Address Hold from CE# High
tEHWH
WE# Hold from CE# High
tEHEL
CE# Pulse Width High
tEHRL
CE# High to RY/BY# Going Low
tEHGL
Write Recovery before Read
tQVVL
VPP Hold from Valid SRD, RY/BY# High
2,4
tQVPH
RP# VHH Hold from Valid SRD, RY/BY# High
2,4
NOTE:
See 5V VCC Alternative CE#-Controlled Writes for Notes 1 through 5.
LH28F008SC-L150
Min.
Max.
150
1
0
70
50
50
5
5
0
25
0
Unit
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
LH28F008SC-L120
Min.
Max.
120
1
0
70
100
100
50
50
5
5
0
25
100
0
0
0
Unit
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 1.3
sharp
LHF08CH1
Sym.
tAVAV
tPHEL
tWLEL
tELEH
tPHHEH
tVPEH
tAVEH
tDVEH
tEHDX
tEHAX
tEHWH
tEHEL
tEHRL
tEHGL
tQVVL
tQVPH
VCC=5V±0.5V, 5V±0.25V, TA=0°C to +70°C
VCC=5V±0.25V LH28F008SC-L85(6)
(5)
Versions
VCC=5V±0.5V
LH28F008SC-L90(7)
Parameter
Notes
Min.
Max.
Min.
Max.
Write Cycle Time
85
90
RP# High Recovery to CE# Going Low
2
1
1
WE# Setup to CE# Going Low
0
0
CE# Pulse Width
50
50
RP# VHH Setup to CE# Going High
2
100
100
VPP Setup to CE# Going High
2
100
100
Address Setup to CE# Going High
3
40
40
Data Setup to CE# Going High
3
40
40
Data Hold from CE# High
5
5
Address Hold from CE# High
5
5
WE# Hold from CE# High
0
0
CE# Pulse Width High
25
25
CE# High to RY/BY# Going Low
90
90
Write Recovery before Read
0
0
VPP Hold from Valid SRD, RY/BY# High
2,4
0
0
RP# VHH Hold from Valid SRD, RY/BY#
2,4
0
0
High
36
Unit
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and
inactive WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase, byte write, or lock-bit configuration.
4. VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase,
byte write, or lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed
Configuration) for testing characteristics.
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.
Rev. 1.3
sharp
LHF08CH1
AIN
AIN
4
5
6
Valid
SRD
DIN
}
}
3
}
2
}
}
}
1
37
VIH
ADDRESSES(A)
VIL
tEHAX
tAVEH
tAVAV
VIH
WE#(W)
VIL
tEHWH
tWLEL
tEHGL
VIH
OE#(G)
VIL
tEHEL
tEHQV1,2,3,4
VIH
CE#(E)
VIL
VIH
DATA(D/Q)
High Z
tELEH
tDVEH
tEHDX
DIN
DIN
VIL
tPHEL
tEHRL
VOH
RY/BY#(R)
VOL
tPHHEH
tQVPH
VHH
RP#(P)
VIH
VIL
tVPEH
VPPH3,2,1
VPP(V)
tQVVL
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or byte write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 17. AC Waveform for CE#-Controlled Write Operations
Rev. 1.3
sharp
LHF08CH1
38
6.2.7 RESET OPERATIONS
VOH
RY/BY#(R)
VOL
VIH
RP#(P)
VIL
tPLPH
(A)Reset During Read Array Mode
VOH
RY/BY#(R)
VOL
tPLRH
VIH
RP#(P)
VIL
tPLPH
(B)Reset During Block Erase, Byte Write, or Lock-Bit Configuretion
2.7V/3.3V/5V
VCC
VIL
t235VPH
VIH
RP#(P)
VIL
(C)RP# rising Timing
Figure 18. AC Waveform for Reset Operation
Sym.
tPLPH
tPLRH
t235VPH
Parameter
RP# Pulse Low Time
(If RP# is tied to VCC, this
specification is not applicable)
RP# Low to Reset during
Block Erase, Byte Write or
Lock-Bit Configuration
VCC 2.7V to RP# High
VCC 3.0V to RP# High
VCC 4.5V to RP# High
Reset AC Specifications
VCC=2.7V
VCC=3.3V
Notes Min.
Max.
Min.
Max.
100

1,2
3
100
100
VCC=5V
Min.
Max.
100
20
100
ns
12
100
Unit
µs
ns
NOTES:
1. If RP# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset
will complete within 100ns.
2. A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid.
3. When the device power-up, holding RP# low minimum 100ns is required after VCC has been in predefined range
and also has been in stable there.
Rev. 1.3
sharp
LHF08CH1
39
6.2.8 BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE(3,4)
Sym.
tWHQV1
tEHQV1
tWHQV2
tEHQV2
tWHQV3
tEHQV3
tWHQV4
tEHQV4
tWHRH1
tEHRH1
tWHRH2
tEHRH2
Sym.
tWHQV1
tEHQV1
Parameter
VCC=3.3V±0.3V, TA=0°C to +70°C
VPP=3.3V
VPP=5V
Notes Typ.(1)
Max.
Typ.(1)
Max.
VPP=12V
Typ.(1)
Max.
Unit
Byte Write Time
2
19
300
10
150
7
125
µs
Block Write Time
2
1.2
4
0.7
2
0.5
1.5
s
Block Erase Time
2
0.8
6
0.4
5
0.3
4
s
Set Lock-Bit Time
2
21
300
13.3
150
11.6
125
µs
Clear Block Lock-Bits Time
2
1.8
6
1.2
5
1.1
4
s
7.1
10
6.6
9.3
7.4
10.4
µs
15.2
21.1
12.3
17.2
12.3
17.2
µs
Byte Write Suspend Latency
Time to Read
Erase Suspend Latency
Time to Read
VCC=5V±0.5V, 5V±0.25V, TA=0°C to +70°C
VPP=5V
Parameter
Notes Typ.(1)
Max.
Byte Write Time
2
8
150
VPP=12V
Typ.(1)
Max.
6
100
Unit
µs
Block Write Time
2
0.5
1.5
0.4
1
s
tWHQV2
Block Erase Time
2
0.4
5
0.3
4
s
tEHQV2
tWHQV3
Set Lock-Bit Time
2
12
150
10
100
µs
tEHQV3
tWHQV4
Clear Block Lock-Bits Time
2
1.1
5
1
4
s
tEHQV4
tWHRH1 Byte Write Suspend Latency Time to
5.6
7
5.2
7.5
µs
tEHRH1 Read
tWHRH2
Erase Suspend Latency Time to Read
9.4
13.1
9.8
12.6
µs
tEHRH2
NOTES:
1. Typical values measured at TA=+25°C and nominal voltages. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
4. Block erase, byte write and lock-bit configuration operations with VCC<3.0V and/or VPP<3.0V are not
guaranteed.
Rev. 1.3
sharp
LHF08CH1
40
7 ADDITIONAL INFORMATION
7.1 Ordering Information
Product line designator for all SHARP Flash products
L H 2 8 F 0 0 8 S C (H) T - L 8 5
Device Density
008 = 8-Mbit
Architecture
S = Regular Block
Power Supply Type
C = SmartVoltage Technology
Operating Temperature
Blank = 0°C ~ +70°C
H = -40°C ~ +85°C
Access Speed (ns)
85:85ns(5V,30pF), 90ns(5V),
120ns(3.3V), 150ns(2.7V)
12:120ns(5V), 150ns(3.3V)
170ns(2.7V)
Package
T = 40-Lead TSOP
R = 40-Lead TSOP(Reverse Bend)
N = 44-Lead PSOP
B = 42 or 48-Ball CSP
Valid Operational Combinations
VCC=2.7-3.6V
VCC=3.3±0.3V
VCC=5.0±0.5V
50pF load,
50pF load,
100pF load,
Option
Order Code
1.35V I/O Levels
1.5V I/O Levels
TTL I/O Levels
1
LH28F008SCT-L85 LH28F008SC-L150 LH28F008SC-L120 LH28F008SC-L90
VCC=5.0±0.25V
30pF load,
1.5V I/O Levels
LH28F008SC-L85
Rev. 1.3
sharp
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tVR
t2VPH *1
tR
tPHQV
VIH
RP# (P)
(RST#)
VCCW *2 (V)
VIL
VCCWH1/2
(VPPH1/2)
GND
(VPP)
tR or tF
tR or tF
tAVQV
VIH
Valid
Address
ADDRESS (A)
VIL
tF
tR
tELQV
VIH
CE#
(E)
VIL
VIH
WE# (W)
VIL
tF
tR
tGLQV
VIH
OE#
(G)
VIL
VIH
WP#
(S)
VIL
VOH
DATA (D/Q)
VOL
High Z
Valid
Output
*1 t5VPH for the device in 5V operations.
*2 To prevent the unwanted writes, system designers should consider the VCCW (VPP) switch, which connects VCCW (VPP)
to GND during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations.
See the application note AP-007-SW-E for details.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
Rev. 1.10
sharp
ii
A-1.1.1 Rise and Fall Time
Symbol
Parameter
Notes
Min.
Max.
Unit
1
0.5
30000
µs/V
tVR
VCC Rise Time
tR
Input Signal Rise Time
1, 2
1
µs/V
tF
Input Signal Fall Time
1, 2
1
µs/V
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
tR(Max.) and tF(Max.) for RP# (RST#) are 100µs/V.
Rev. 1.10
sharp
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal
Input Signal
VIH (Min.)
VIH (Min.)
VIL (Max.)
VIL (Max.)
Input Signal
Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for VIH (Min.) and VIL (Max.).
Rev. 1.10
sharp
iv
A-2 RELATED DOCUMENT INFORMATION(1)
Document No.
Document Name
AP-001-SD-E
Flash Memory Family Software Drivers
AP-006-PT-E
Data Protection Method of SHARP Flash Memory
AP-007-SW-E
RP#, VPP Electric Potential Switching Circuit
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Rev. 1.10
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
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Phone: (65) 271-3566
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Phone: (82) 2-711-5813 ~ 8
Fax: (82) 2-711-5819
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(Shanghai) Co., Ltd.
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Head Office:
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Email: [email protected]
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3rd Business Division,
17/F, Admiralty Centre, Tower 1
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Phone: (852) 28229311
Fax: (852) 28660779
www.sharp.com.hk
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Phone: (86) 755-3273731
Fax: (86) 755-3273735